Method for creating interconnections

Abstract

Title: Method for Creating Interconnections The invention relates to a method for manufacturing an interconnection level comprising: • forming, on a substrate (S), a first metallic layer (21), • forming, on the first metallic layer (21), an etching stop layer (30), • structuring the etching stop layer (30), • forming, on the structured etching stop layer comprising a via opening (30v), a second metallic layer (22), • forming, on the second metallic layer (22), a second mask defining a via pattern (40v) above the via opening (30v), • etching the second metallic layer (22), configured to form a via (61) under the second mask, then • etching the first metallic layer (21), configured to form a line (62) under the structured etching stop layer, the line (62) being connected to the via (61) through via the opening (30v).Figure for the abridged version: Fig.14.

Description

Title of the invention: Method for creating interconnections technical field

[0001] The present invention relates to the technical field of interconnections for microelectronics. Its particularly advantageous application is the formation of radio frequency (RF) compatible vias and interconnect lines. PRIORITY OF THE TECHNOLOGY

[0002] The development of microelectronic devices based on "quantum bits" or "qubits," for example spin qubits or superconducting qubits, requires the fabrication of specific interconnect routing. These interconnects are notably based on metallic materials other than the copper generally used in the line and via levels associated with the fabrication of field-effect transistor-based devices.

[0003] Document EP3577700 discloses various methods for fabricating vias and metallic lines suitable for manufacturing superconducting circuits. In this document, a niobium and / or aluminum-based via is formed on a first layer of semiconducting metal, typically niobium-based, by interposing a stop-etching layer between the via and the first metal layer. This stop-etching layer typically allows for better detection of the end of etching of the superconducting layer that primarily forms the via. According to this document, this stop-etching layer can be aluminum-based and exhibit superconducting properties within a certain temperature range. It thus participates in the conduction between the via and the underlying superconducting line. According to another possibility disclosed in document EP3577700, the stop-etching layer can be based on a dielectric material.An opening is then created within this etching stop layer to connect the via to the underlying superconducting line. This approach requires multiple lithography / etching and polishing steps. This increases the dimensional variability, particularly in thickness, of the devices at the wafer scale.

[0004] Another solution for forming the different levels of metallic lines and vias is based on adapting Damascus-type processes. This approach introduces other problems, particularly for etching the dielectric matrix with a low dielectric constant. An increase in the dielectric constant is typically observed during the etching of the dielectric matrix. RF compatibility is degraded.

[0005] An object of the present invention is to propose a method for forming interconnection lines and vias which at least partially overcomes the disadvantages mentioned above.

[0006] In particular, an object of the present invention is to propose an alternative method for forming interconnection lines and vias, exhibiting improved reproducibility. SUMMARY

[0007] To achieve this objective, according to one embodiment, a manufacturing process for an interconnection level is provided, comprising at least one line based on a first metallic material A and at least one via based on a second metallic material B, said process comprising: • the supply of a substrate, • the formation, on the substrate, of a first metallic layer based on the first metallic material A, • the formation, on the first metallic layer, of an etching stop layer based on a dielectric material C exhibiting an etching selectivity SA: c with respect to the first material A typically greater than or equal to 5:1, • a structuring of the etching stop layer, by means of at least one first mask, such that the structured etching stop layer has at least one line pattern, said at least one line pattern comprising at least one via opening, • the formation, on the structured etching stop layer comprising at least one via opening, of a second metallic layer based on the second metallic material, • the formation, on the second metallic layer, of a second mask defining at least one via pattern directly above at least one via opening, • an etching of the second metallic layer, said etching being configured to form at least one via under the second mask, then • an etching of the first metallic layer, said etching being configured to form at least one line below at least one line pattern of the structured etching stop layer, said at least one line being connected to said at least one via through at least one via opening.

[0008] Advantageously, the first and second masks are formed on planar layers, respectively on the etching stop layer and on the second layer metallic. This helps to limit the dimensional variability associated with the formation of these masks, typically by lithography.

[0009] Advantageously, the etching stop layer is structured so as to expose the first metallic layer outside of at least one line pattern. This allows the etching of the second metallic layer and the first metallic layer to be performed sequentially. The formation of at least one line from the first metallic layer is carried out at the end of the process. The at least one line is aligned vertically with at least one line pattern. The at least one via is aligned vertically with at least one via pattern. This avoids the need for alignment between the two etches, unlike the solution disclosed in document EP3577700. This limits the dimensional variability associated with such alignment.

[0010] The invention also provides, according to a second aspect, a device comprising, stacked along a direction z: • a substrate, • an interconnection level comprising • at least one connecting line based on a first metallic material A, • an etching stop layer based on a dielectric material C exhibiting an etching selectivity SA:c with respect to the first material typically greater than or equal to 5:1, • at least one connection via based on a second metallic material B.

[0011] The etching stop layer has at least one line pattern comprising at least one via opening configured to connect at least one connection via and at least one connection line.

[0012] Advantageously, the etching stop layer covers at least one connection line along the z direction, without extending outside of said at least one connection line, in projection along the z direction.

[0013] The advantages described above with regard to the method apply mutatis mutandis to the device according to the invention. BRIEF DESCRIPTION OF THE FIGURES

[0014] The aims, objects, features and advantages of the invention will become clearer from the detailed description of embodiments thereof, which are illustrated by the following accompanying drawings in which:

[0015] [Fig.1] [Fig.2] [Fig.3] [Fig.4] [Fig.5] [Fig.6] [Fig.7] [Fig.8] [Fig.9] [Fig.10] [Fig.12] [Fig.13] [Fig.14] Figures 1 to 10 and 12 to 14 illustrate in an xz plane, cross-sections representing different stages of the manufacturing process of an interconnection level according to an embodiment of the present invention.

[0016] [Fig. 11] The [Fig. 11] schematically illustrates in top view a step of the manufacturing process corresponding to the [Fig. 10], according to an embodiment of the present invention.

[0017] [Fig.15] [Fig.17] [Fig.19] Figures 15, 17, 19 schematically illustrate in an xz plane, cross-sections representing different stages of structuring the etching stop layer according to another embodiment of the present invention.

[0018] [Fig. 16] [Fig. 18] Figures 16 and 18 schematically illustrate, in top view, the steps of the manufacturing process corresponding to Figures 15 and 17, respectively.

[0019] [Fig.20] [Fig.21] [Fig.22] [Fig.23] [Fig.24] [Fig.25] Figures 20 to 25 schematically illustrate in an xz plane, cross-sections representing different stages of structuring the etching stop layer according to another embodiment of the present invention.

[0020] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the thicknesses and / or dimensions of the different layers and patterns are not representative of reality. For clarity, all alphanumeric references are not systematically repeated from one figure to another. It is understood that elements already described and referenced, when reproduced in another figure, typically bear the same alphanumeric references, even if these are not explicitly mentioned. A person skilled in the art will easily identify the same element reproduced in different figures. DETAILED DESCRIPTION

[0021] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in association or alternatively are stated below.

[0022] The structuring of the etching stop layer can be done in various ways.

[0023] According to one example, the structuring of the etching stop layer comprises the following sub-steps: • the formation of the first mask on the etching stop layer, said first mask directly defining at least one line pattern comprising at least one via opening, • a partial removal of the etching stop layer, only in areas of the etching stop layer not covered by the first mask, of in order to expose the first metallic layer outside the areas covered by the first mask, • the removal of the first mask.

[0024] The formation of the first mask takes place here on the etching stop layer, and covers the parts of the etching stop layer that will be retained: the first mask therefore "directly" defines at least one line pattern comprising at least one via opening. The at least one line pattern is located below the first mask, directly above the first mask.

[0025] According to one example, the formation of the first mask is done by double lithography. This makes it possible to obtain patterns with resolution exceeding the performance of the lithography equipment.

[0026] According to one example, the structuring of the etching stop layer comprises the following sub-steps: • before formation of the etching stop layer, formation of the first mask on the first metallic layer, said first mask indirectly defining at least one line pattern including at least one via opening, • the formation of the etching stop layer by selective deposition of the dielectric material on areas of the first metallic layer not covered by the first mask, • the removal of the first mask.

[0027] The formation of the first mask occurs here before the formation of the etching stop layer, and covers the parts of the first metallic layer that will not be covered by the etching stop layer: the first mask therefore "indirectly" defines at least one line pattern comprising at least one via opening. The at least one line pattern is located on the parts of the first metallic layer not covered by the first mask.

[0028] According to one example, the selective deposition of the dielectric material is carried out by atomic layer deposition (ALD). According to another example, the selective deposition of the dielectric material is carried out by chemical vapor deposition (CVD).

[0029] According to one example, the at least one via pattern has a critical dimension CD2, taken along an x-axis, greater than a dimension CDopen of the at least one via aperture taken along the x-axis. This allows for a certain tolerance in the alignment between the first and second masks, particularly for defining the first and second masks by lithography. The second mask can thus partially overlap the edges of the via aperture of the first mask, in projection along a stacking direction z. According to another example, the at least one via pattern via presents a critical dimension CD2, taken along an x-axis, substantially equal to a dimension CDopen of at least one via opening taken along the x-axis.

[0030] According to an example, the at least one via pattern has a critical dimension CD2, taken along an x-axis, less than a dimension CDi of the at least one line pattern taken along the x-axis.

[0031] According to one example, the etching of the second metallic layer and the etching of the first metallic layer are linked together in a single etching sequence. This etching sequence may include several sub-steps with different plasma conditions, for example.

[0032] According to one example, the etching of the second metallic layer and the etching of the first metallic layer are carried out in a single etching operation, during a single step. The etching conditions remain substantially identical during the etching of the second and first metallic layers. This makes it possible to reduce the time and / or costs of the process.

[0033] According to one example, the first metallic material A and / or the second metallic material B are based on at least one of: TiN, TaN, W, Ru, Ti, Ta, V3Si, CoSi2, Nb3Ge, Al, NbN, and their alloys.

[0034] According to an example, the first metallic material A and the second metallic material B are based on the same material.

[0035] According to an example, the first metallic material A and / or the second metallic material B are different from copper.

[0036] According to an example, the etching stop layer based on a dielectric material C has an etching selectivity SA:c with respect to the first material A greater than or equal to 5:1.

[0037] According to one example, the etching stop layer is based on a dielectric material C chosen from: SiO2, TiO2, HfO2, HfN, ZrN, SiN, SiCN. This makes it possible to obtain an SA:c etching selectivity between the first metallic material A and the dielectric material C greater than or equal to 5:1. The etching speed of the etching stop layer is at least five times lower than the etching speed of the first and second metallic layers. According to one example, the SA:B etching selectivity between the first metallic material A and the dielectric material C is greater than 10:1.

[0038] According to one example, the at least one connecting via has a critical dimension CDvia, taken along an x-axis, greater than a dimension CDopen of the at least one via opening taken along the x-axis, and less than a dimension CDiigne of the at least one connecting line taken along the x-axis, so that the burn stop layer is partially intercalated between the at least one connecting via and the at least one connecting line.

[0039] According to another example, the at least one connection via has a critical dimension CDvia, taken along an x-axis, substantially equal to a dimension CDiigne of the at least one connection line taken along the x-axis, so that the burn stop layer is sandwiched between the at least one connection via and the at least one connection line.

[0040] According to one example, at least one connecting line has a critical dimension CDiigne, taken along an x-axis, substantially equal to a dimension CDi, taken along the x-axis, of at least one line pattern of the etching stop layer.

[0041] According to one example, the at least one connecting line has a critical dimension CDiigne, taken along an x-axis, substantially equal to a critical dimension CDvia, taken along the x-axis, of the at least one connecting via.

[0042] Except in cases of incompatibility, it is understood that all the above optional features and / or the indicated variants may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.

[0043] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0044] A substrate, film, or layer "based" on a material A is understood to mean a substrate, film, or layer comprising only that material A or that material A and possibly other materials, for example, dopant elements or alloying elements. Thus, a spacer based on silicon nitride (SiN) may, for example, comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even silicon oxynitride (SiON).

[0045] The term "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant less than 20, and preferably less than 10.

[0046] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated, the adjective "successive" does not necessarily imply, even though this is generally preferred, that the steps follow each other immediately, with intermediate steps potentially separating them.

[0047] Furthermore, the term "step" refers to the execution of a part of the process, and can designate a set of sub-steps.

[0048] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may, in particular, be followed by actions related to a different step, and other actions of the first step may be repeated subsequently. Thus, the term "step" does not necessarily imply unitary actions that are inseparable in time and in the sequence of the process phases. The etching of the first and second metallic layers, in particular, may be linked together or considered as part of a single etching step.

[0049] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" refers to etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting an etching speed of material A greater than the etching speed of material B. Selectivity is the ratio of the etching speed of material A to the etching speed of material B. It is denoted SA:B. A selectivity SA:B of 10:1 means that the etching speed of material A is 10 times greater than the etching speed of material B.

[0050] A preferably orthonormal coordinate system, comprising the x, y, z axes, is shown in the attached figures.

[0051] In this patent application, the term thickness will preferably be used for a layer or film, and height for a device or structure. Thickness is measured along a direction normal to the principal plane of extension of the layer or film. Thus, a metallic layer typically has a thickness along the z-axis. A via formed from such a metallic layer has a height along the z-axis. The relative terms "on," "overhangs," "above," "below," "underlying," and "below" refer to positions measured along the z-direction. A "lateral" dimension corresponds to a dimension along a direction in the xy-plane. A "lateral" or "lateral" extension is understood to be an extension along one or more directions in the xy-plane.

[0052] An element located "in line with" or "directly above" another element means that these two elements are both located on the same line perpendicular to a plane in which extends mainly a lower or upper face of a substrate, that is to say on the same line oriented vertically on the cross-sectional figures.

[0053] The terms "approximately", "around", "in the order of" mean to the nearest 10%, and preferably to the nearest 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the bounds are inclusive, unless otherwise stated.

[0054] The manufacturing steps of an interconnection level according to a first embodiment of the invention are illustrated in Figures 1 to 14.

[0055] As illustrated in [Fig. 1], the method comprises providing a substrate S typically including a silicon-based support layer 10 carrying components, for example, spin qubit transistors or superconducting qubit transistors. The substrate S may also include connecting pads 12 integrated into a first silicon oxide-based layer 11, above the support layer 10. An objective of the method according to the invention is to form lines connecting the pads 12, and vias above and connecting these lines.

[0056] A first metallic layer 21 is first formed on the substrate S. The first metallic layer 21 can be formed from one or more of the following materials: Ti, TiN, Ta, TaN, W, Ru, V3Si, CoSi2, Nb3Ge, Al, NbN. The first metallic layer 21 can, in particular, be formed by physical vapor deposition (PVD). This metallic layer 21 typically has a thickness e2i on the order of a few tens of nanometers, for example, on the order of 40 nm. After deposition, the first metallic layer 21 is typically planarized, for example, conventionally by chemical polishing (CMP).

[0057] As illustrated in [Fig. 2], an etching stop layer 30 is then directly formed on the first metallic layer 21. This etching stop layer 30 typically has a thickness on the order of a few nanometers, for example less than 5 nm. It is preferably based on a dielectric chosen from among SiO2, TiO2, HfO2, HfN, ZrN, SiN, SiCN. The formation of the etching stop layer 30 can in particular be carried out by one of the following techniques: physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD).

[0058] A color layer 31, intended to form a first etching mask, is deposited on the etching stop layer 30. This color layer 31 is, for example, SiON-based. It typically has a thickness e31 on the order of a few nanometers to a few tens of nanometers, for example, on the order of 5 nm to 10 nm. The color layer 31 is then patterned by lithography / etching to form the first etching mask. This patterning can be done by simple lithography, for example under extreme UV exposure, or by double lithography known as "double patterning".

[0059] Figures 3 to 8 illustrate a structuring of the colouring layer 31 by “double patterning”.

[0060] As illustrated in [Fig.3], a first lithography can be carried out so as to define line patterns 32 in a first layer of photosensitive resin, preferably in line with the pads 12.

[0061] As illustrated in [Fig. 4], a first engraving can then be carried out so as to transfer the line patterns 32 into the coloring layer 31. The coloring layer is thus partially structured. This first partial structuring makes it possible to obtain line patterns 311 in the coloring layer.

[0062] As illustrated in [Fig. 5], the line patterns 32 of the first resin layer are then removed, for example by oxygen-based plasma, so as to re-expose the line patterns 311 of the partially structured color layer. In the case of structuring by "double patterning", the line patterns 311 typically have a CDi dimension, along x, of between 70 nm and 100 nm, for example on the order of 80 nm.

[0063] As illustrated in [Fig.6], a second lithography can be carried out so as to define aperture patterns via 33v in a second layer 33 of photosensitive resin, on the line patterns 311 of the partially structured colouring layer.

[0064] As illustrated in [Fig. 7], a second etching can be performed to complete the structuring of the coloring layer. The opening patterns of via 33v are transferred into the coloring layer. This second structuring makes it possible to obtain opening patterns of via 31v within the line patterns 311 of the coloring layer.

[0065] As illustrated in [Fig.8], after removal of the second layer 33 of resin, a first etching mask 31m comprising line patterns 311 and via opening patterns 31v is formed on the etching stop layer 30.

[0066] The first etching mask is not necessarily based on a color layer, nor is it necessarily produced by "double patterning". When the first etching mask is produced by simple lithography, the CDi dimension of the line patterns 311 is typically between 100 nm and 200 nm, for example, on the order of 130 nm. When the first etching mask is produced by extreme UV lithography, the CDi dimension of the line patterns 311 is typically between 20 nm and 50 nm, for example, on the order of 26 nm. This first etching mask 31m is used here to directly transfer the line patterns 311 and the aperture patterns of via 31v into the etching stop layer 30.

[0067] As illustrated in [Fig. 9], an anisotropic etching of the etching stop layer 30, along z, is carried out so as to form the line patterns 301 under the patterns of line 311, and the opening patterns of via 30v under the opening patterns of via 31v. This etching may feature a halogenated etching chemistry based on chlorine or fluorine, depending on the type of mask 31m and the nature of the etching stop layer 30. For a hafnium-based etching stop layer 30, the etching may be performed using BC13 etching chemistry. For a silicon-based etching stop layer 30, the etching may be performed using a fluorocarbon etching chemistry, for example CF4.

[0068] As illustrated in Figures 10 and 11, in transverse and top views respectively, after removal of the first etching mask 31m, a structured etching stop layer, comprising line patterns 301 and via opening patterns 30v, is obtained on the first metallic layer 21. The line patterns 301 typically have the dimension CDi along x, and the via opening patterns 30v typically have the dimension CDopen along x. When the first etching mask is produced by single lithography or by "double patterning", the CDopen dimension of the via opening patterns 30v is typically between 30 nm and 70 nm, for example on the order of 50 nm. When the first etching mask is made by extreme UV lithography, the CDopen dimension of the aperture patterns via 30v can be between 8 nm and 20 nm, for example on the order of 10 nm.

[0069] As illustrated in [Fig. 12], after structuring the etching stop layer, a second metallic layer 22, typically based on the same metal(s) as the first metallic layer 21, is then formed on the first metallic layer 21 and on the structured etching stop layer 301. This metallic layer 22 typically has a thickness e22 on the order of a few tens of nanometers, for example, on the order of 40 nm. The thicknesses e21 and e22 are preferably chosen so that the total thickness e21 + e22 of the metallic layers 21, 22 is between 90 nm and 110 nm. After deposition, the second metallic layer 22 is typically planarized, for example, conventionally by chemical mechano-polishing (CMP).

[0070] As illustrated in [Fig.13], a second etching mask 40 comprising via patterns 40v is formed on the second metallic layer 22. This second etching mask 40 is preferably based on organic layers, for example in the form of a stack known as "trilayer", typically comprising an organic planarization layer, an anti-reflective layer and a photosensitive resin layer.

[0071] The 40v via patterns of this second etching mask 40 are aligned with the 30v via opening patterns of the etching stop layer, so that the 40v via patterns are vertically aligned with the 30v via opening patterns. The patterns of 40v patterns typically have a CD2 dimension along x that is slightly larger, for example 10% larger, than the CDopen dimension along x of 30v patterns. This facilitates the alignment of 40v and 30v patterns with each other. A certain tolerance in alignment accuracy is thus achieved.

[0072] As illustrated in [Fig. 14], the first and second metal layers 21, 22 are then etched through their entire thickness, along z, outside the via patterns 40v. The second metal layer 22 is first etched to form the connecting vias 61, and then the first metal layer 21 is etched to form the connecting lines 62. The etchings of the first and second metal layers 21, 22 are preferably linked. According to one possibility, particularly when the first and second metal layers 21, 22 are of the same type, the etchings of these metal layers 21, 22 are carried out in a single step, with the same etching chemistry.

[0073] The etchings are chosen here so as to selectively etch the first and second metals of the first and second metallic layers 21, 22 with respect to the etching stop layer material. In particular, the etching selectivity SA:c, that is to say the ratio between the etching speed of the metallic material(s) to the etching speed of the etching stop layer material, is greater than or equal to 5:1, preferably greater than or equal to 10:1.

[0074] The etching of the metallic material(s) can be carried out using chlorinated chemistry. In this case, good selectivity is achieved with respect to the etching arrest layer. In particular, when the arrest layer is based on HfO2 or SiO2, the etching speed of the arrest layer is less than 20 nm / min. Alternatively, the etching of the metallic material(s) can be carried out using fluorinated or fluorocarbon chemistry. In this case, it is preferable to avoid SiN and SiO2 as the dielectric material for the arrest layer.

[0075] After etching, metallic vias 61 with a critical dimension CDvia along x are obtained. The critical dimension CDvia along x is substantially equal to the dimension CD2 of the 40v via patterns. Metallic lines 62 with a critical dimension CDiigne along x are obtained. The critical dimension CDiigne along x is substantially equal to the dimension CDi of the line patterns 301. The metallic vias 61 are connected to the metallic lines 62 by continuity of material through the openings of the 30v via.

[0076] Figures 15 to 19 illustrate a structuring of the etching stop layer according to another embodiment of the invention.

[0077] As illustrated in figures 15, 16, a first mask 31b based on reverse polarity resin is first formed directly on the first metallic layer 21. It comprises pads 31v,b of dimension CDopen along x, defining the via openings, and openings 311,b of dimension CDi along x, defining the line patterns.

[0078] As illustrated in Figures 17, 18, a selective deposition of the dielectric material B is carried out in the openings 311,b, on the first metallic layer 21. This deposition can typically be carried out by atomic layer deposition (ALD). This makes it possible to form a directly structured etching stop layer 301. The structuring of the etching stop layer by lithography / etching is thus avoided. This makes it possible to preserve the surface of the first metallic layer 21, in particular under the pads 31v,b. The quality of the interface subsequently obtained between the via and the underlying line is thus preserved.

[0079] As illustrated in [Fig. 19], the first resin-based mask 31b is then removed, typically by O2 / N2 plasma. A directly structured etching stop layer 30 is thus obtained. The subsequent via and line formation steps are identical to those described previously.

[0080] Figures 20 to 25 illustrate a structuring of the etching stop layer according to another embodiment of the invention.

[0081] As illustrated in [Fig.20], a resin-based mask 31c is formed on the etching stop layer 30. It comprises only openings 31v,b of CDopen dimension along x, defining the via openings.

[0082] As illustrated in [Fig.21], etching through the openings 31v,b allows the via 30v openings to be formed in the etching stop layer 30. The etching stop layer 30 is here partially structured and at this stage only includes the via 30v openings.

[0083] As illustrated in [Fig. 22], the second metallic layer 22 is then formed on the partially structured etching stop layer and in the 30v via openings. An etching mask comprising 40v via patterns is formed on the second metallic layer 22, as before. The 40v via patterns have a CD2 dimension.

[0084] As illustrated in [Fig.23], the second metallic layer 22 is then etched with a stop on the etching stop layer, in order to form the connecting vias 61.

[0085] As illustrated in [Fig.24], an engraving mask comprising line patterns 401 is formed on and around the connecting vias 61, preferably in line with the connecting pads 12. The line patterns 401 have a dimension CDi.

[0086] As illustrated in [Fig. 25], one or more engravings are then made to remove the etching stop layer 30 and then the first metallic layer 21 outside the areas covered by the line patterns 401. Connecting lines 62 are thus formed. This variant allows us to consider pairs of materials A, C exhibiting a lower SA:c etching selectivity.

[0087] In view of the preceding description, it is clear that the proposed method and device offer a particularly efficient and versatile solution for forming interconnection levels based on vias and metallic lines suitable for the manufacture of radio frequency and / or superconducting circuits.

[0088] The invention is not limited to the embodiments previously described.

Claims

1. Demands A method for manufacturing an interconnection level comprising at least one line (62) based on a first metallic material (A) and at least one via (61) based on a second metallic material (B), said method comprising: • a supply of a substrate (S), • the formation, on the substrate (S), of a first metallic layer (21) based on the first metallic material (A), • the formation, on the first metallic layer (21), of an etching stop layer (30) based on a dielectric material (C) exhibiting a selectivity SA: c to etching with respect to the first material (A), • a structuring of the etching stop layer (30), by means of at least one first mask (31m, 31b, 31c), such that the structured etching stop layer has at least one line pattern (301), said line pattern (301) comprising at least one via opening (30v), • a formation, on the structured etching stop layer comprising at least one via opening (30v), of a second metallic layer (22) based on the second metallic material (B), • a formation, on the second metallic layer (22), of a second mask defining at least one via pattern (40v) directly above at least one via opening (30v), • an etching of the second metallic layer (22), said etching being configured to form at least one via (61) under the second mask, then • an etching of the first metallic layer (21), said etching being configured to form at least one line (62) under at least one line pattern (301) of the structured etching stop layer, said at least one line (62) being connected to said at least one via (61) through at least one via opening (30v).

2. A method according to the preceding claim, wherein the structuring of the etching stop layer (30) comprises the following substeps: • a formation of the first mask (31m) on the etching stop layer, said first mask (31m) directly defining at least one line pattern (311, 301) comprising at least one via opening (31v, 30v), • a partial removal of the etching stop layer (30), only at the level of areas of the etching stop layer (30) not covered by the first mask (31m), so as to expose the first metallic layer (21) outside the areas covered by the first mask (31m), • a removal of the first mask (31m).

3. Method according to the preceding claim, wherein the formation of the first mask (31m) is done by double lithography.

4. A method according to claim 1, wherein the structuring of the etching stop layer (30) comprises the following substeps: • prior to formation of the etching stop layer (30), a formation of the first mask (31b) on the first metal layer (21), said first mask (31b) indirectly defining at least one line pattern (311,b, 301) comprising at least one via opening (31v,b, 30v), • the formation of the etching stop layer (30, 301) by selective deposition of the dielectric material (C) on areas of the first metal layer (21) not covered by the first mask (31b), • a removal of the first mask (31b).

5. A method according to the preceding claim, wherein the selective deposition of the dielectric material (C) is carried out by atomic layer deposition (ALD) or by chemical vapor deposition (CVD).

6. A method according to any one of the preceding claims, wherein at least one via pattern (40v) has a critical dimension CD2, taken along an x-axis, greater than a CDopen dimension of at least one via opening (30v) taken along the x-axis, and less than a CDi dimension of at least one line pattern (301) taken along the x-axis.

7. A method according to any one of the preceding claims, wherein the etching of the second metallic layer (22) and the etching of the first metallic layer (21) are linked according to a single sequence of etchings.

8. A method according to any one of the preceding claims, wherein the first metallic material (A) and / or the second metallic material (B) are based on at least one of: TiN, TaN, W, Ru, Ti, Ta, V3Si, CoSi2, Nb3Ge, Al, NbN.

9. A method according to any one of the preceding claims, wherein the first metallic material (A) and the second metallic material (B) are based on the same material.

10. A method according to any one of the preceding claims, wherein the etching stop layer (30) is based on a dielectric material (C) taken from: SiO2, TiO2, HfO2, HfN, ZrN, SiN, SiCN.

11. A device comprising, stacked along a z-direction: • a substrate (S), • an interconnection level comprising • at least one connecting line (62) based on a first metallic material (A), • an etch arrest layer (30) based on a second dielectric material (C) having an etch selectivity SA:c with respect to the first material (A), • at least one connecting via (61) based on a second metallic material (B), said etch arrest layer (30) having at least one line pattern (301) comprising at least one via opening (30v) configured to connect the at least one connecting via (61) and the at least one connecting line (62), said device being characterized in that the etch arrest layer (30, 301) covers the at least one connecting line (62) along the z-direction, without extending beyond said at least one connecting line (62), in projection along the z direction.

12. Device according to the preceding claim, wherein the at least one connection via (61) has a critical dimension CDvia, taken along an x-axis, greater than a CDopen dimension of the at least an opening of via (30v) taken along the x-axis, and less than a dimension CDiigne of at least one connection line (62) taken along the x-axis, so that the burn-stop layer (30, 301) is partially intercalated between the at least one connection via (61) and the at least one connection line (62).

13. Device according to any one of claims 11 to 12, wherein the at least one connecting line (62) has a critical dimension CDiigne, taken along an x-axis, substantially equal to a critical dimension CDvia, taken along the x-axis, of the at least one connecting via (61).

14. Device according to any one of claims 11 to 13, wherein the first metallic material (A) is based on at least one of: TiN, TaN, W, Ru, Ti, Ta, V3Si, CoSi2, Nb3Ge, Al, NbN, and their alloys.

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