Control of boost converter current limit

Abstract

An input current limit of boost converter circuitry is controlled based on a received power dissipation value for the boost converter circuitry. The power dissipation value may be based on an input po

Description

Field of the Invention 5 The present disclosure relates to a system and method for controlling an input current limit of boost converter circuitry. Background 10 Ina packaged integrated circuit (IC) device, circuitry is implemented on a semiconductor (e.g. silicon) die encased in a protective package. The package is provided with external connectors such as conductive pins, pads or balls which are internally coupled to the semiconductor die to permit connection of the semiconductor die to external components. 15 In operation, power is dissipated by the circuitry, which causes a junction temperature of the semiconductor die to increase. The degree to which the junction temperature increases is dependent upon the junction to ambient thermal resistance Theta JA (0JA) of the package. The junction to ambient thermal resistance 0jA is defined as the 20 temperature differential between a junction of an IC and the ambient temperature per Watt of power dissipated. Summary 25 According to a first aspect, the invention provides a method for controlling an input current limit of boost converter circuitry, the method comprising: receiving a power dissipation value for the boost converter circuitry, wherein the power dissipation value is representative of power dissipated by the boost converter circuitry in operation of the boost converter circuitry; and 30 controlling an input current limit of the boost converter circuitry based on the power dissipation value. The method may further comprise determining the power dissipation value based on an input power value of the boost converter circuitry and an efficiency value for the boost converter circuitry at the determined input power value. 5 Determining the input power value of the boost converter circuitry may comprise: receiving an input current value and an input voltage value and determining the input power value based on the input current value and the input voltage value. The input current value may be based on a signal received from input current monitor 10 circuitry and the input voltage value may be based on a signal received from input voltage monitor circuitry. Controlling the input current limit of the boost converter circuitry based on the power dissipation value may comprise: 15 comparing the power dissipation value to a threshold power dissipation value; and if the power dissipation value exceeds the threshold power dissipation value, reducing the input current limit; and if the power dissipation value is equal to or lower than the threshold power dissipation value, maintaining the input current limit at an existing level. 20 Controlling the input current limit of the boost converter circuitry based on the power dissipation value may comprise: determining a change in a junction temperature of a semiconductor die on which the boost converter circuitry is implemented; 25 comparing the change in the junction temperature to a threshold temperature change value; and if the change in the junction temperature exceeds the threshold temperature change value, reducing the input current limit; and if the change in the junction temperature is equal to or lower than the 30 threshold temperature change value, maintaining the input current limit at an existing level. Controlling the input current limit of the boost converter circuitry based on the power dissipation value may comprise: xt CM CM CM CM determining a final junction temperature value of a semiconductor die on which the boost converter circuitry is implemented resulting from power dissipation; comparing the final junction temperature value to a threshold junction temperature value; and 5 if the final junction temperature value exceeds the threshold temperature change value, reducing the input current limit; and if the final junction temperature value is equal to or lower than the threshold junction temperature value, maintaining the input current limit at an existing level. 10 Controlling the input current limit of the boost converter circuitry based on the power dissipation value may comprise: determining a duration for which the boost converter circuitry is permitted to dissipate power at the power dissipation value; and 15 controlling the input current limit of the boost converter circuitry based on the determined duration. Determining the duration for which the boost converter is permitted to dissipate power at the power dissipation value may comprise comparing the power dissipation value to a 20 predefined power dissipation vs duration function. The efficiency value may be dynamically calculated or dynamically measured during operation of the boost converter circuitry. 25 The efficiency value may be determined based on a polynomial defining a relationship between an input power of the boost converter circuitry, a boost ratio of the boost converter circuitry and an efficiency of the boost converter circuitry. The efficiency value may be determined based on a lookup table defining input power 30 values, boost ratio values and corresponding efficiency values for the boost converter circuitry. The input current limit of the boost converter circuitry may be controlled to limit a die temperature increase or a rate of die temperature increase of a semiconductor die on which the boost converter circuitry is implemented. 5 According to a second aspect, the invention provides a computer-readable medium storing instructions which, when executed by processing circuitry, cause the processing circuitry to perform the method of any of the first to third aspects. According to a third aspect, the invention provides a system for controlling an input 10 current limit of boost converter circuitry, the system comprising a controller configured to carry out the method of the first aspect. xt CM CM CM CM According to a fourth aspect, the invention provides an integrated circuit comprising a system according to the third aspect. 15 According to a fifth aspect, the invention provides a host device comprising a system according to the third aspect The host device may comprise a laptop, notebook, netbook or tablet computer, a gaming 20 device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device. 25 Brief Description of the Drawings Embodiments of the invention will now be described, strictly by way of example only, with reference to the accompanying drawings, of which: 30 Figure 1 is a schematic representation of a packaged integrated circuit device comprising boost converter circuitry; Figure 2 is a schematic representation of a system for controlling an input current limit of boost converter circuitry according to the present disclosure; Figure 3 is a flow diagram illustrating an example method for controlling the input current 5 limit of boost converter circuitry in the system of Figure 2; Figure 4 is a flow diagram illustrating steps in one example approach to determining a power dissipation value in the method of Figure 3; 10 Figure 5 is a flow diagram illustrating steps in one example approach to controlling the input current limit of boost converter circuitry in the system of Figure 2; Figure 6 is a flow diagram illustrating steps in an alternative example approach to controlling the input current limit of boost converter circuitry in the system of Figure 2; xt CM CM CM CM 15 Figure 7 is a flow diagram illustrating steps in a further alternative example approach to controlling the input current limit of boost converter circuitry in the system of Figure 2; Figure 8 is a graphical representation of a function defining a duration for which boost 20 converter circuitry is permitted to supply different output power levels; and Figure 9 is a flow diagram illustrating steps in an example approach to controlling the input current limit of boost converter circuitry 230 in the system of Figure 2, based on a power vs duration function of the kind shown in Figure 8. 25 Detailed Description Figure 1 is a schematic representation of a packaged integrated circuit (IC) comprising boost converter circuitry. As shown in Figure 1, the packaged IC 100 includes a 30 protective package 110 that house a semiconductor die 120 on which boost converter circuitry 130 is implemented. The package 110 includes a plurality of external connectors 140 (e.g. conductive pins, pads or balls) which are internally coupled to the semiconductor die 120 to permit connection of the semiconductor die 120 to external components. As the boost converter circuitry 130 cannot operate with 100% efficiency, in operation of the boost converter circuitry 130, power is dissipated as heat, causing the temperature of the semiconductor die 120 to increase. The power Pdiss dissipated as heat into the 5 semiconductor is the difference between the power Pin supplied to the IC 100 and the power Pout output by the IC 100, i.e. Pdiss = Pin - Pout. Thus, assuming that the power efficiency of the boost converter circuitry 130 remains constant, the temperature of the semiconductor die 120 will increase as the input power Pin and / or output power Pout increases. 10 xt CM O CM CM As will be appreciated by those of ordinary skill in the art, the boost converter circuitry 130 is the dominant source of power dissipated as heat into the semiconductor die 120, but other elements of the IC 100 will also dissipate some power as heat, particularly if the IC 100 includes other circuitry in addition to the boost converter circuitry 130. Thus, 15 the value Pdiss is representative of the total power dissipated as heat into the semiconductor die 120, i.e. the power dissipation of the whole IC, rather than just the boost converter circuitry 130. For clarity and brevity, the power dissipation value Pdiss is referred to herein as being indicative of the power dissipation of the boost converter circuitry, but it is to be appreciated that references to the power dissipation of the boost 20 converter circuitry should be interpreted as references to the power dissipation of the whole IC. The boost converter circuitry 130 may be designed with a plurality of different specification ranges, each intended for a different use case. For example, the boost 25 converter circuitry 130 may have an input voltage range of 3 to 12VDC, an output voltage range of 5 to 15VDC and a maximum input current limit of 2A, so that the input power Pin can be approximately 6Wwhen the input voltage is 3V. In voltage regulated boost converter circuitry, the boost converter circuitry 130 is 30 operative to maintain the output voltage at a predefined level, and so the boost converter circuitry will attempt to draw the input power (current) required to satisfy an output power (current) demand. Because of the inherent inefficiency of the boost converter circuitry 130 (i.e. because the output power Pout cannot be equal to the input power Pin because the boost converter circuitry 130 cannot operate at 100% efficiency), in order to support 6 a given output power demand, the input power to the boost converter circuitry 130 must be greater than the output power demand. For example, if the boost converter circuitry 130 is operating in a configuration or mode 5 in which it converts an input voltage of 5VDC to an output voltage of 10VDC, then if a current demand of a load coupled to an output of the boost converter circuitry is 400mA, the required output power Pout is 10V x 400mA = 4W. If the boost converter circuitry 130 were able to operate with 100% efficiency, the input current required to support this output power Pout at the 5V input voltage would be 800mA (because 5Vx 800mA = 4W). 10 However, as the boost converter circuitry 130 cannot operate with 100% efficiency, the input power Pin must be greater than the required output power Pout, and so the boost converter circuitry 130 will draw more than 800mA of input current. Thus, assuming that the input voltage to the boost converter circuitry 130, the output 15 voltage supplied by the boost converter circuitry 130 to the load, and the efficiency of the boost converter circuitry 130 are substantially constant, in operation of the boost converter circuitry 130 the input current Is determined by load conditions (which affect the load current demand). CM CM 20 The boost converter circuitry 130 may be designed to provide a predefined maximum output power, However, if there are no limitations on the input current it is possible that in some circumstances the output power of the boost converter circuitry 130 may exceed the predefined maximum output power. 25 For example, if the boost converter is operating in a configuration or mode in which it converts an input voltage of 10VDC to an output voltage of 15VDC with a fixed input current limit of 2A, then if the load draws a current of more than 667mA, the maximum output power of 10W is exceeded (because the output voltage of 15V x the load current of 667mA = 10W). This corresponds to an input current of around 1 A, which is well below 30 the 2A input current limit. As demonstrated by the above example, in certain circumstances (which may not have been foreseen when deciding on the specifications for the boost converter circuitry 130), it is possible that the boost converter circuitry 130 may be made to operate outside of its 7 intended or specified operational parameters. This may lead to excessively increased die junction temperature and / or electrical overstress conditions and associated damage and / or other problems. 5 The present disclosure proposes method and system for controlling an input current limit of boost converter circuitry 130 of the kind described above with reference to Figure 1 to reduce the risk of damage or other problems that may arise as a result of excessive increases or rates of increase in die junction temperature. 10 Figure 2 is a schematic representation of a system for controlling an input current limit of boost converter circuitry according to the present disclosure. As shown generally at 200 in Figure 2, the system 200 comprises a controller 210 configured to provide a signal Him indicative of an input current limit to boost converter 15 circuitry 230 which supplies an output voltage Vout and an output current lout to a load 240. The boost converter circuitry 230 may be implemented as a packaged IC of the kind described above with refence to Figure 1, and thus may comprise a semiconductor die on which the boost converter circuitry 230 is implemented, encased in a protective package. 20 The controller 210 may be implemented in circuitry (e.g. integrated circuitry implemented on one or more integrated circuits, or discrete circuitry), or may alternatively be implemented in processing hardware such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a microprocessor or microcontroller 25 executing suitable instructions, software or program code. The controller 210 is configured to receive a signal linmon indicative of an input current lin to the boost converter circuitry 230. The signal linmon may be supplied, for example, by input current monitor circuitry (shown schematically at 250 in Figure 2), which may 30 comprise, for example, for example, a current sense resistor of known resistance coupled in series between an output terminal of a power supply that supplies the input voltage Vin to the boost converter circuitry 230 and an power supply input terminal of the boost converter circuitry 230 and analog to digital converter (ADC) circuitry coupled across the current sense resistor such that a digital signal output by the ADC circuitry is 8 representative of a voltage across the current sense resistor, which is in turn indicative of a current through the resistor and thus the input current to the boost converter circuitry 230. 5 The controller 210 is further configured to receive a signal Vinmon indicative of an input voltage Vin to the boost converter circuitry 230. The signal Vinmon may be supplied, for example, by input voltage monitor circuitry 260 which may comprise, for example, ADC circuitry having an input coupled to the power supply input terminal of the boost converter circuitry 230 and an output coupled to an input of the controller 210, such that a digital 10 ADC output signal representing the magnitude of the input voltage Vin is provided by the ADC circuitry to the controller 210 as the signal Vinmon indicative of the input voltage Vin. The controller 210 is further configured to receive a signal indicative of an efficiency value , 15 Eff for the boost converter circuitry 230. CM The efficiency value may be dynamically calculated or estimated (e.g. by processing C\J circuitry external to the controller 210, or by the controller 210 itself) during operation of the boost converter circuitry 230, e.g. based on measured or otherwise determined input CM 20 and output currents and voltages, or may alternatively be a fixed value indicative of an estimated efficiency of the boost converter circuitry 230. The controller 210 is further configured to receive predefined package characteristics or parameters (e.g. a package junction to ambient thermal resistance Oja of a package of 25 the boost converter circuitry 230). In some examples these predefined package characteristics are stored in a memory 220, which in the illustrated example is external to the controller 210, but which could equally be internal to the controller 210 (e.g. the memory 220 could be on-chip memory of a DSP IC). 30 The controller 210 is configured to dynamically adjust an input current limit for the boost converter circuitry 230 based on the input voltage Vin, the input current I in, and the efficiency value Eff. Figure 3 is a flow diagram illustrating an example method 300 performed by the controller 210 to control the input current limit of the boost converter circuitry 230 in the system 200 of Figure 2. 5 Ina first step 310 of the method 300, the controller 210 determines a power dissipation value Pdiss indicative of the on-chip power dissipation of the boost converter circuitry 230. In a subsequent step 320, the controller 210 controls the input current limit of the boost 10 converter circuitry 230 based on the determined power dissipation value Pdiss. Figure 4 is a flow diagram illustrating steps that may be performed by the controller 210 in one example approach to determining the power dissipation value Pdiss in the first CM CM step 310 of the method 300. 15 In a step 312, the controller 210 determines an input power value Pin, based on the input voltage Vin and the input current lin, by multiplying the input voltage Vin by the input current lin. 20 Ina subsequent 314, the controller 210 determines the power dissipation value Pdiss for an on-chip power dissipation, based on the determined input power value Pin and the efficiency value Eff. In some examples, the controller 210 may determine the power dissipation value Pdiss 25 based on the determined input power value Pin and the efficiency value Eff alone. In such examples, the controller 210 may first calculate an estimated output power value Pout as the product of the efficiency value Eff (expressed as a decimal value less than 1) and the determined input power value Pin, i.e. Pout = Pin x Eff. The controller 210 may then calculate the power dissipation value Pdiss by subtracting the estimated output 30 power value Pout from the determined input power value Pin, i.e. Pdiss = Pin - Pout. In other examples, the controller 210 may be programmed or otherwise provided with a relationship between the determined input power Pin, the efficiency value Eff and a currently selected boost ratio for the boost converter circuitry 230. This relationship may be defined by a polynomial which allows the efficiency value Eff to be calculated based on the determined input power value Pin and the currently selected boost ratio. 5 Alternatively, the controller 210 may be programmed or otherwise provided with a lookup table populated with input power values, boost ratio values and the corresponding efficiency values. Table 1 below shows an example of such a lookup table. The controller 210 may select the appropriate efficiency value Eff for the determined input power value 10 Pin and currently selected boost ratio from the lookup table. Input power value Pin Boost ratio Efficiency value Eff 100mW 1.2 90% 100mW 2 91% 100mW 4 92% CM 500mW 1.2 91% CM 500mW 2 92% 500mW 4 93% CM 2W 1.2 92% CM 2W 2 93% 2W 4 94% Table 1 In a further alternative, the controller may receive the power dissipation value Pdiss (or 15 a signal indicative of the power dissipation value Pdiss) from a system, apparatus or circuitry that measures the real-time power dissipation or efficiency of the boost converter circuitry 230 (e.g. the system described in the applicant’s co-pending US provisional patent application no. 63 / 440,942, filed on 25 January 2023, which is incorporated by reference in its entirety herein). 20 As described above, having determined or received the power dissipation value Pdiss, the controller 210 subsequently (at step 330) controls the input current limit of the boost converter circuitry 230 based on the determined power dissipation value Pdiss. Figure 5 is a flow diagram illustrating steps that may be performed by the controller 210 in one example approach to controlling the input current limit of the boost converter circuitry 230. As shown generally at 500 in Figure 5, in a first step 510, the controller 210 compares the determined power dissipation value Pdiss with one or more threshold 5 power dissipation values. If the determined power dissipation value exceeds a threshold power dissipation value, the controller 210 reduces the input current limit (step 520), to reduce the risk that the on-chip power dissipation could cause excessive heating of the semiconductor die on 10 which the boost converter circuitry 230 is implemented. If the determined power dissipation value Pdiss subsequently falls below the threshold, the controller 210 may increase the input current limit. 15 If the determined power dissipation value is equal to or lower than the threshold power dissipation value, the controller may maintain the input current limit at its existing level (step 530). Figure 6 is a flow diagram illustrating steps that may be performed by the controller 210 20 in an alternative example approach to controlling the input current limit of the boost converter circuitry 230 based on a change in a junction temperature of the semiconductor die. As shown generally at 600 in Figure 6, in a first step 610, the controller 210 may 25 dynamically calculate a change ATj in a junction temperature of the semiconductor die, based on the determined power dissipation value Pdiss and the package junction to ambient thermal resistance value 0ja, by multiplying the determined power dissipation value Pdiss by the junction to ambient thermal resistance value Oja, i.e. ATj = Pdiss x Oja- 30 Alternatively, the change ATj in junction temperature may be estimated, determined or predicted by the controller 210 using a Foster thermal model of the semiconductor die that is stored in or otherwise provided to the controller 210. The controller 210 may compare the calculated change ATj in junction temperature of the semiconductor die to a predefined threshold temperature change value (step 620) to detect if there is a risk that the junction temperature will exceed a safe limit. 5 If the calculated change ATj in junction temperature exceeds the predefined threshold temperature change value (indicating a risk that the junction temperature will exceed the safe limit), the controller 210 may reduce the input current limit of the boost converter circuitry 230 (step 630). 10 If the calculated change ATj in junction temperature subsequently falls below the predefined threshold temperature change value, the controller 210 may increase the input current limit. If the calculated change ATj in junction temperature is equal to or lower than the 15 predefined threshold temperature change value (indicating no risk or a low risk that the junction temperature will exceed the safe limit), the controller 210 may maintain the input current limit of the boost converter circuitry 230 at its current level (step 640). Additionally or alternatively, if an initial junction temperature TjO is known (e.g. from an 20 on-chip sensor measurement), a final junction temperature resulting from the on-chip power dissipation can be estimated, determined or predicted by the controller 210 by adding the change in junction temperature ATj to the initial junction temperature TjO, i.e. Tjfinal = TjO + ATj. Alternatively, the final junction temperature may be estimated, determined or predicted by the controller 210 using a Foster thermal model of the 25 semiconductor die that is stored in or otherwise provided to the controller 210. Figure 7 is a flow diagram illustrating steps that may be performed by the controller 210 in an alternative example approach to controlling the input current limit of the boost converter circuitry 230 based on an estimated, determined or predicted final junction 30 temperature of the semiconductor die. As shown generally at 700 in Figure 7, in a first step 710, the controller 210 may estimate, determine or predict a final junction temperature value resulting from the on-chip power dissipation, as described above. The controller 210 may subsequently compare the estimated, predicted or determined final junction temperature value to a predefined threshold junction temperature value (step 720) to detect if there is a risk that the junction temperature will exceed a safe limit. 5 If the estimated, predicted or determined final junction temperature exceeds the predefined threshold junction temperature value (indicating a risk that the junction temperature will exceed the safe limit), the controller 210 may reduce the input current limit of the boost converter circuitry 230 (step 730). 10 If the estimated, predicted or determined final junction temperature subsequently falls below the predefined threshold junction temperature value, the controller 210 may increase the input current limit. CM CM 15 If the estimated, predicted or determined final junction temperature is less than the predefined threshold junction temperature value (indicating no risk, or a low risk that the junction temperature will exceed the safe limit), the controller 210 may maintain the input current limit of the boost converter circuitry 230 at its current level (step 740). 20 In some examples, the controller 210 may be operative to adjust the input current limit of the boost converter circuitry 230 to permit the boost converter circuitry 230 to dissipate different levels of power for different durations, in order to maintain on-chip power dissipation within safe limits, e.g. below a level that could lead to damage or other problems due to excessive junction temperature, junction temperature increase or rate 25 of junction temperature increase. Figure 8 is a graphical representation of a function defining a duration for which the boost converter circuitry 230 is permitted to dissipate power at different levels. Such a function may be implemented by the controller 210 to permit the boost converter circuitry 30 230 to supply sufficient power to support fast transient high output voltages (such as may arise, for example, in Class D audio amplifier circuitry) while still providing a safety mechanism against possible damage caused by excessive die temperatures or die temperature increases arising due to increased power dissipation as the output power supplied by the boost converter circuitry increases. According to the function illustrated in Figure 8, for boost converter circuitry 230 designed or configured to be able to dissipate a power of 5W indefinitely, the boost converter circuitry 230 may be permitted to dissipate a power of 7.5W for only 100ms, to dissipate 5 a power of 10Wfor only 10ms, and to dissipate a power of 15Wfor only 1ms, in order to maintain the on-chip power dissipation and thus the die temperature, die temperature change and / or rate of die temperature change within safe limits. Figure 9 is a flow diagram illustrating steps that may be performed by the controller 210 10 in an example approach to controlling the input current limit of the boost converter circuitry 230 based on a power dissipation vs duration function of the kind described above with reference to Figure 8. In a first step 910, the controller 210 receives a power dissipation value Pdiss. The output CM CM 15 power dissipation value Pdiss may be determined as described above as the difference between an input power value Pin and an output power value Pout, for example. In a second step 920, the controller 210 compares the received power dissipation value Pdiss to a predefined power dissipation vs duration function to determine a duration (e.g. 20 a maximum allowable duration) for which the boost converter circuitry 230 can dissipate power at the received power dissipation value Pdiss. Subsequently, at step 930, the controller 210 adjusts the input current limit of the boost converter circuitry 230 after a time period equal to the duration determined in the second 25 step 920, if necessary. For example, if the controller 210 implements the function described above with reference to Figure 8, if the power dissipation value Pdiss is than 5W, the controller 210 need not adjust the input current limit. However, if the power dissipation value Pout rises 30 to 7.5W (e.g. due to an increase in input power caused by an increase in output power demand), the controller 210 will reduce the input current limit of the boost converter circuitry 230 after a period of 100ms has elapsed, to reduce the risk of damage resulting from an excessive die temperature or die temperature increase arising because of the increased on-chip power dissipation. Similarly, if the power dissipation value Pdiss rises to 10W, the controller 210 will reduce the input current limit of the boost converter circuitry 230 after a period of 10ms has elapsed, and if the power dissipation value Pdiss rises to 15W, the controller 210 will reduce the input current limit of the boost converter circuitry 230 after a period of 1 ms has elapsed. In this way the boost converter circuitry 230 is permitted to supply sufficient output power to downstream circuitry (e.g. amplifier) to support transient increases in power (e.g. load current) demand, while reducing the risk of potentially damaging increases in die temperature. 15 As will be apparent from the foregoing description and the accompanying drawings, the system and methods of the present disclosure provide different approaches to controlling the input current limit of boost converter circuitry, which all reduce the risk of damage and / or other problems that could arise as a result of excessive temperatures, temperature increases or rates of temperature increase resulting from increased power dissipation by the boost converter circuitry. CM CM The circuitry described above with reference to the accompanying drawings may be incorporated in a host device such as a laptop, notebook, netbook or tablet computer, a 20 gaming device such as a games console or a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player or some other portable device, or may be incorporated in an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a VR or AR device, a mobile telephone, a portable audio player or other portable device. 25 The skilled person will recognise that some aspects of the above-described apparatus and methods may be embodied as processor control code, for example on a non-volatile carrier medium such as a disk, CD- or DVD-ROM, programmed memory such as read only memory (Firmware), or on a data carrier such as an optical or electrical signal 30 carrier. For many applications, embodiments will be implemented on a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array). Thus the code may comprise conventional program code or microcode or, for example code for setting up or controlling an ASIC or FPGA. The code may also comprise code for dynamically configuring re-configurable apparatus such as re-programmable logic gate arrays. Similarly the code may comprise code for a hardware description language such as Verilog™ or VHDL (Very high speed integrated circuit Hardware Description Language). As the skilled person will appreciate, the code may be distributed between a plurality of coupled components in communication with one 5 another. Where appropriate, the embodiments may also be implemented using code running on a field-(re)programmable analogue array or similar device in order to configure analogue hardware. It should be noted that the above-mentioned embodiments illustrate rather than limit the 10 invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single feature or other unit may fulfil the functions of several units recited in the claims. Any reference numerals or labels , 15 in the claims shall not be construed so as to limit their scope. "‘T CM CM CM CM

Claims

1. A method for controlling an input current limit of boost converter circuitry, the method comprising:5 receiving a power dissipation value for the boost converter circuitry, wherein thepower dissipation value is representative of power dissipated by the boost converter circuitry in operation of the boost converter circuitry; andcontrolling an input current limit of the boost converter circuitry based on the power dissipation value.

102. A method according to claim 1, wherein the method further comprises determining the power dissipation value based on an input power value of the boost converter circuitry and an efficiency value for the boost converter circuitry at the determined inputxt CMCMCM CMpower value.

153. A method according to claim 2, wherein determining the input power value of the boost converter circuitry comprises:receiving an input current value and an input voltage value and determining the input power value based on the input current value and the input voltage value.

204. A method according to claim 3, wherein the input current value is based on a signal received from input current monitor circuitry and the input voltage value is based on a signal received from input voltage monitor circuitry.25 5. A method according to any of the preceding claims, wherein controlling the inputcurrent limit of the boost converter circuitry based on the power dissipation value comprises:comparing the power dissipation value to a threshold power dissipation value; and if the power dissipation value exceeds the threshold power dissipation30 value, reducing the input current limit; andif the power dissipation value is equal to or lower than the threshold power dissipation value, maintaining the input current limit at an existing level.

6. A method according to any of claims 1—4, wherein controlling the input current limit of the boost converter circuitry based on the power dissipation value comprises: determining a change in a junction temperature of a semiconductor die on which the boost converter circuitry is implemented;5 comparing the change in the junction temperature to a threshold temperature change value; andif the change in the junction temperature exceeds the threshold temperature change value, reducing the input current limit; andif the change in the junction temperature is equal to or lower than the 10 threshold temperature change value, maintaining the input current limit at anexisting level.

7. A method according to any of claims 1—4, wherein controlling the input currentxt CMOCM CMlimit of the boost converter circuitry based on the power dissipation value comprises:15 determining a final junction temperature value of a semiconductor die on which theboost converter circuitry is implemented resulting from power dissipation;comparing the final junction temperature value to a threshold junction temperature value; andif the final junction temperature value exceeds the threshold temperature20 change value, reducing the input current limit; andif the final junction temperature value is equal to or lower than the threshold junction temperature value, maintaining the input current limit at an existing level.25 8. A method according to any of the preceding claims, wherein controlling the inputcurrent limit of the boost converter circuitry based on the power dissipation value comprises:determining a duration for which the boost converter circuitry is permitted to dissipate power at the power dissipation value; and30 controlling the input current limit of the boost converter circuitry based on thedetermined duration.

9. A method according to claim 8, wherein determining the duration for which the boost converter is permitted to dissipate power at the power dissipation value comprises 19comparing the power dissipation value to a predefined power dissipation vs duration function.

10. A method according to any of claims 2-9, wherein the efficiency value is 5 dynamically calculated or dynamically measured during operation of the boost converter circuitry.

11. A method according to any of claims 2-7, wherein the efficiency value is determined based on a polynomial defining a relationship between an input power of the 10 boost converter circuitry, a boost ratio of the boost converter circuitry and an efficiency of the boost converter circuitry.

12. A method according to any of claims 2-7, wherein the efficiency value isdetermined based on a lookup table defining input power values, boost ratio values and 15 corresponding efficiency values for the boost converter circuitry.

13. A method according to any of the preceding claims, wherein the input current limit of the boost converter circuitry is controlled to limit a die temperature increase or a rate of die temperature increase of a semiconductor die on which the boost converter circuitry 20 is implemented.

14. A computer-readable medium storing instructions which, when executed by processing circuitry, cause the processing circuitry to perform the method of any of the preceding claims.2515. A system for controlling an input current limit of boost converter circuitry, the system comprising a controller configured to carry out the method of any of claims 1 to 13.30 16. An integrated circuit comprising a system according to claim 15.

17. A host device comprising a system according to claim 15.xt CMCMCM CM18. A host device according to claim 17, wherein the host device comprises a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with5 a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device.

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