Display device

Abstract

A multi-panel display apparatus comprises at least a first panel (B1, figure 12) and a second panel (B2, figure 12). A control circuit (FPGA, figure 12) is arranged to control each of the panels and is configured to output a reference gate signal to the first panel B1 and to output a timing-delayed gate clock signal to the second panel B2. At least one of the panels comprises an upper substrate 10 having a micro-LED 12 mounted thereon and a lower substrate 20 connected to the upper substrate via routing 60. The arrangement is designed to cancel electromagnetic interference *(EMI) caused by the gate clock signal of the upper substrate and allows provision of a phase compensation signal through the lower substrate to prevent screen discontinuities due to timing dispersion. Additional panels (B3,B4, figure 12) may be included in the multi-panel display.

Images