Pixel circuit and display device including the same

Abstract

A pixel circuit comprising a first and second light emitting element (EL1, EL2), a driving transistor (DT) to drive the two light emitting elements, a compensation voltage line (PL4) for applying a compensation voltage, a first switch element (T1) comprising a first electrode connected between the driving element and the EL1 and driven by the first mode selection signal, a second switch element (T2) including a first electrode and connected between the driving element and EL2, a third switch element (T3) that applies a predetermined compensation voltage to at least one anode electrode of the EL1 and EL2 where the first electrode of the T3 is connected to the first electrode of T1 and the first electrode of the T2, and a second electrode of T3 is connected to the PL4. The pixel circuit is driven in the order of an initialisation period, a sensing period, a data wire period, a pre-change period, and an emission period. Where during initialisation a reference voltage is applied to the first electrode, EL1 and EL2, during the pre-charge period the compensation voltage is applied to one of EL1 or EL2.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0193956, filed December, 28, 2023. BACKGROUND 1. Field

[0002] The present disclosure relates to a pixel circuit and a display device including the same. 2. Discussion of Related Art

[0003] Variable viewing angle technology is being applied to display devices. Variable viewing angle technology may present video content or visual information reproduced on a display device only to a user within a narrow viewing angle range, or to multiple users within a wide viewing angle range.

[0004] As the market for future vehicles such as electric vehicles and selfdriving cars expands, demand for vehicle display devices is rapidly increasing. Research is being conducted on a method of dividing the screen of a vehicle display device and controlling one part of the screen to have a narrow viewing angle and the other part to have a wide viewing angle. This technology may drive pixels with a narrow viewing angle arranged in one area of the screen to display personal contents or information that only a specific user may view, and simultaneously drive pixels with a wide viewing angle arranged in the other area of the screen to display shared contents that multiple users may view together.

[0005] In vehicle display devices, display panels for organic light emitting display devices are attracting attention. An organic light emitting display device includes an organic light emitting diode (hereinafter, referred to as "OLED") that emits light by itself, and has an advantage in that the response speed is fast, the luminous efficiency and luminance are good, and the viewing angle is wide. The organic light emitting display device has a fast response speed, is excellent in terms of luminous efficiency, luminance and viewing angle, and provides an excellent contrast ratio and color reproducibility since it may express the black grayscale in complete black. Because the display panel of an organic light emitting display device may be flexibly bent, it may easily implement a curved surface. Due to these advantages, the share of organic light emitting display devices in the vehicle display device market is rapidly increasing. SUMMARY

[0006] However, due to a deviation in the panel fabrication process, a difference in the capacitance of parasitic capacitors formed in the light emitting elements occurs at each in-plane position. This results in a difference in charging time between the anode voltage of the first light emitting element and the anode voltage of the second light emitting element in a low grayscale with a small amount of current, leading to a deviation in luminance uniformity in a low grayscale.

[0007] The present disclosure is directed to solving all the above-described necessity and problems.

[0008] The present disclosure provides a pixel circuit and a display device including the same.

[0009] It should be noted that objects of the present disclosure are not limited to the above-described objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following descriptions.

[0010] A pixel circuit according to embodiments of the present disclosure may include a first light emitting element; a second light emitting element; a driving element transistor configured to drive the first and second light emitting elements; a compensation voltage line for applying a compensation voltage; a first switch element comprising a first electrode and connected between the driving element and the first light emitting element and driven by a first mode selection signal; a second switch element comprising a first electrode and connected between the driving element and the second light emitting element and driven by a second mode selection signal; and a third switch element configured to apply a predetermined compensation voltage to at least one of anode electrodes of the first light emitting element and the second light emitting element, wherein a first electrode of the third switch element is connected to the first electrode of the first switch element and the first electrode of the second switch element, and a second electrode of the third switch element is connected to the compensation voltage line.

[0011] A display device according to embodiments of the present disclosure may include the above-described pixel circuit; a data driver; a gate driver; and a power supply configured to supply the pixel base voltage and the compensation voltage.

[0012] According to the present disclosure, by initializing the anode electrode of the light emitting element to a reference voltage and then applying a compensation voltage of a predetermined voltage level before the emission period, the initial voltage of the anode electrode may be increased, thereby compensating for a luminance deviation in a low grayscale region with a small amount of current.

[0013] According to the present disclosure, low power driving may be possible by compensating for a luminance deviation in a low grayscale region.

[0014] The effects of the present specification are not limited to the above-mentioned effects, and other effects that are not mentioned will be apparently understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the attached drawings, in which:

[0016] FIG. 1 is a block diagram illustrating a display device according to one embodiment of the present disclosure;

[0017] FIG. 2 is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure;

[0018] FIG. 3 is a diagram illustrating lenses disposed on first and second light emitting elements shown in FIG. 2;

[0019] FIG. 4 is a diagram illustrating waveforms for driving the pixel circuit shown in FIG. 2 in a first mode;

[0020] FIGS. 5A to 5F are diagrams illustrating an operation of a pixel circuit driven in a first mode;

[0021] FIG. 6 is a diagram illustrating different waveforms for driving the pixel circuit shown in FIG. 2 in a first mode;

[0022] FIGS. 7A and 7B are diagrams comparing luminance deviations between a comparative example and an embodiment;

[0023] FIG. 8 is a diagram illustrating waveforms for driving the pixel circuit shown in FIG. 2 in a second mode;

[0024] FIGS. 9A to 9F are diagrams illustrating an operation of a pixel circuit driven in a second mode;

[0025] FIG. 10 is a diagram illustrating different waveforms for driving the pixel circuit shown in FIG. 2 in a second mode;

[0026] FIG. 11 is a diagram illustrating waveforms for simultaneously driving the pixel circuit shown in FIG. 2 in first and second modes; and

[0027] FIGS. 12A to 12E are diagrams illustrating an operation of the pixel circuit driven by the waveforms of FIG. 11. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0028] Advantages and features of the present specification and methods of achieving them will become apparent with reference to preferable embodiments, which are described in detail, in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments to be described below and may be implemented in different forms, the embodiments are only provided to completely disclose the present disclosure and completely convey the scope of the present disclosure to those skilled in the art, and the present specification is defined by the disclosed claims.

[0029] Since the shapes, sizes, proportions, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present disclosure are only exemplary, the present disclosure is not limited to the illustrated items. The same reference numerals indicate the same components throughout the specification. Further, in describing the present disclosure, when it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present disclosure, the detailed description thereof will be omitted.

[0030] When ‘including,’ ‘having,’ ‘consisting,’ and the like mentioned in the present specification are used, other parts may be added unless ‘only’ is used. A case in which a component is expressed in a singular form includes a plural form unless explicitly stated otherwise.

[0031] In interpreting the components, it should be understood that an error range is included even when there is no separate explicit description.

[0032] In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as ‘on,’ ‘at an upper portion,’ ‘at a lower portion,’ ‘next to, and the like, one or more other parts may be located between the two parts unless ‘immediately’ or ‘directly’ is used.

[0033] Although first, second, and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, a first component, which is mentioned, below may also be a second component within the technical spirit of the present disclosure.

[0034] The same reference numerals may refer to substantially the same elements throughout the present disclosure.

[0035] The following embodiments can be partially or entirely bonded to or combined with each other and can be linked and operated in technically various ways. The embodiments can be carried out independently of or in association with each other.

[0036] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] In a display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. Transistors may be implemented as oxide thin film transistors (oxide TFTs) including an oxide semiconductor, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, or the like.

[0038] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In the transistor, carriers start to flow from the source. The drain is an electrode through which carriers exit from the transistor. In a transistor, carriers flow from a source to a drain. In the case of an n-channel transistor, since carriers are electrons, a source voltage is a voltage lower than a drain voltage such that electrons may flow from a source to a drain. The n-channel transistor has a direction of a current flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide semiconductor (PMOS), since carriers are holes, a source voltage is higher than a drain voltage such that holes may flow from a source to a drain. In the p-channel transistor, since holes flow from the source to the drain, a current flows from the source to the drain. It should be noted that a source and a drain of a transistor are not fixed. For example, a source and a drain may be changed according to an applied voltage. Therefore, the disclosure is not limited due to a source and a drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0039] A gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than a threshold voltage of a transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0040] The transistor is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage. In the case of the n-channel transistor, a gate-on voltage may be a gate high voltage, and a gate-off voltage may be a gate low voltage. In the case of the p-channel transistor, a gate-on voltage may be a gate low voltage, and a gate-off voltage may be a gate high voltage.

[0041] FIG. 1 is a block diagram illustrating a display device according to one embodiment of the present disclosure.

[0042] Referring to FIG. 1, the display device according to an embodiment of the present disclosure includes a display panel 100, and a display panel driving circuit for writing pixel data to pixels of the display panel 100. Additionally, the display device includes a power supply 150.

[0043] The display panel 100 may be, but not limited to, a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be a heterogeneous panel of which at least a portion is curved or elliptical.

[0044] The display area AA of the display panel 100 includes a pixel array to display an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels. The power lines may be commonly connected to pixel circuits to supply a voltage required for driving pixels 101 to the pixels 101.

[0045] Each of the pixels 101 may be divided into a red sub-pixel, a green subpixel, and a blue sub-pixel for color implementation. Each pixel may further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light emitting element. The light emitting element may include an OLED or an inorganic light emitting diode (LED). Each pixel circuit is connected to the data lines, the gate lines, and the power lines. In the following description, a pixel may be interpreted as a sub-pixel.

[0046] The pixels may be arranged as real color pixels and pentile pixels. A pentile pixel may realize a higher resolution than a real color pixel by driving two sub-pixels with different colors as one pixel 101 and using a preset pixel rendering algorithm. This pixel rendering algorithm may compensate for insufficient color representation in each pixel with the color of light emitted from adjacent pixels.

[0047] Each of the pixels may include at least one first light-emitting element that emits light in first mode, and a second light-emitting element that emits light in second mode. Each of the pixels 101 emits light from the first light-emitting element at a wide viewing angle in first mode, while emitting light from the second light-emitting element at a narrow viewing angle in second mode.

[0048] The display area AA includes a plurality of pixel lines LI to Ln. Each of the pixel lines LI to Ln includes one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. Those pixels arranged in one pixel line share the gate lines 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of pixel lines LI to Ln.

[0049] The display panel 100 may be implemented with a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on the screen and a real object in the background is visible. The display panel 100 may be made of a flexible display panel.

[0050] The power supply 150 receives an input voltage applied from the host system 200 and outputs a voltage needed to drive the pixels 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 150 may include a direct current to direct current converter (DC-DC converter). The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply 150 may output a constant voltage (or direct current voltage), such as gate-on voltage, gate-off voltage, pixel driving voltage, cathode voltage, reference voltage, IC driving voltage of the display panel driving circuit, through the DC-DC converter. The gate-on voltage and the gate-off voltage may be supplied to the level shifter 140 and the gate driver 120. Voltages such as pixel driving voltage, cathode voltage, and reference voltage may be supplied to the pixels 101 through the power lines commonly connected to the pixels 101.

[0051] The power supply 150 may further include a gamma voltage generator. The gamma voltage generator receives a high-potential reference voltage and a low-potential reference voltage and outputs a plurality of gamma reference voltages divided at specific intervals on a preset gamma curve, for example, a 2.2 gamma curve. The gamma reference voltages are supplied to the data driver 110. In the data driver 110, the gamma reference voltages are subdivided by a voltage dividing circuit into grayscale voltages. The gamma voltage generator may be implemented with a programmable gamma circuit that may adjust the voltage of each of the gamma reference voltages according to digital data. The timing controller 130, the host system 200, or a separate external device may update digital data stored in a register of the programmable gamma circuit through a communication interface.

[0052] The display panel driving circuit writes pixel data of the input image to the pixels 101 of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0053] The display panel driving circuit may further include a touch sensor driver for driving touch sensors. The touch sensor driver is not shown in FIG. 1. The data driver 110 and the touch sensor driver may be integrated into one source drive IC.

[0054] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 may receive gamma reference voltages and generate gamma compensation voltages for each grayscale through a voltage dividing circuit. The per-grayscale gamma compensation voltages are supplied to a digital to analog converter (hereinafter referred to as “DAC”) disposed in each channel of the data driver 110.

[0055] The data driver 110 samples and latches digital data received from the timing controller 130 and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting first mode and second mode. The DAC converts the pixel data into a gamma compensation voltage and outputs a data voltage of the pixel data.

[0056] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wiring lines of the display area AA. The gate driver 120 may be disposed in at least one of left and right non-display areas NA outside the display area AA in the display panel 100 or at least a part thereof may be disposed within the display area AA.

[0057] The gate driver 120 may be disposed in the non-display areas NA on both sides of the display panel 100 with the display area AA of the display panel interposed therebetween to supply gate pulses on both sides of the gate lines 103 in a double feeding method. In another embodiment, the gate driver 120 may be disposed in at least one of the left and right non-display areas NA of the display panel 100 to supply gate signals to the gate lines 103 in a single feeding method. The gate driver 120 sequentially outputs pulses of the gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the pulses of the gate signals using shift registers. When a plurality of gate signals are applied to each pixel, the gate driver 120 may include a plurality of shift registers. The gate signal may include a scan signal being input to the pixel circuit through a plurality of gate lines, and an emission signal (or EM signal).

[0058] The timing controller 130 receives digital video data of an input image and a timing signal synchronized with this data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and horizontal period may be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of 1 horizontal period (1H).

[0059] The timing controller 130 may control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, DE received from the host system 200. The timing controller 130 may synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0060] The gate timing control signal output from the timing controller 130 may be input to the shift register of the gate driver 120 through the level shifter 140. The level shifter 140 may convert a voltage of the gate timing control signal received from the timing controller 130 to a swing width between the gate-on voltage and the gate-off voltage and supply it to the gate driver 120.

[0061] The timing controller 130 may supply first and second mode selection signals S sel and Psel to a pixel circuit. For example, the timing controller 130 may generate the first and second mode selection signals S sel and P sel of a first voltage level and supply them to a level shifter, and the level shifter may convert the first and second mode selection signals S sel and P sel of the first voltage level into the first and second mode selection signals S sel and P sel of a second voltage level and supply them to the pixel circuit.

[0062] The host system 200 may include a main board of one of a television system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, and a wearable terminal. The host system 200 may scale an image signal from a video source according to the resolution of the display panel 100, and may transmit it to the timing controller 130 together with the timing signals.

[0063] The host system 200 may transmit a mode signal having different logic values in first mode and second mode together with an image signal to the timing controller 130 at least once per frame.

[0064] FIG. 2 is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating lenses disposed on first and second light emitting elements shown in FIG. 2.

[0065] Referring to FIGS. 2 and 3, the pixel circuit according to an embodiment includes a first light emitting element ELI that emits light in a first mode SMODE, a second light emitting element EL2 that emits light in a second mode PMODE, a driving element DT that drives the first and second light emitting elements ELI and EL2, a compensation circuit 10 connected to the driving element, a first switch element Tl, a second switch element T2, and a third switch element T3. The compensation circuit includes a plurality of switch elements T4 to T9 and a capacitor Cst. The driving element DT and the switch elements Tl to T9 may be implemented as p-channel transistors, but are not limited thereto.

[0066] The pixel circuit is connected to power lines through which DC voltages or constant voltages are applied, such as a pixel driving voltage line (or a first power line) PL1 for applying a pixel driving voltage VDD, a pixel base voltage line (or a second power line) PL2 for applying a pixel base voltage VSS, a reference voltage line (or a third power line) PL3 for applying a reference voltage Vref, and a compensation voltage line (or a fourth power line) PL4 for applying a compensation voltage Vdc. The power lines on the display panel 100 may be connected in common to all pixels.

[0067] The pixel driving voltage VDD is set to a voltage higher than the maximum voltage of the data voltage Vdata and allows the driving element DT to operate in a saturation region. The pixel driving voltage VDD is a voltage higher than the pixel base voltage VSS. The reference voltage Vref may be set to a voltage that is lower than the pixel driving voltage VDD and higher than the pixel base voltage VSS. A gate-on voltage VGL may be set to a voltage higher than the pixel driving voltage VDD and a gate-off voltage VGH may be set to a voltage lower than the pixel base voltage VSS.

[0068] The driving element DT drives the first and second light-emitting elements ELI and EL2 by generating a current according to a gate-source voltage Vgs. The driving element DT includes a first electrode connected to the first power line PL1 to which the pixel driving voltage VDD is applied, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0069] The first and second light-emitting elements ELI and EL2 may be implemented as organic light-emitting diodes (OLEDs). Each of the light-emitting elements ELI and EL2 includes an anode (or first electrode), a cathode (or second electrode), and an organic compound layer formed between the anode and the cathode. The anode of the first light-emitting element ELI is connected to a fifth node n5, and the cathode thereof is connected to the second power line PL2 to which the pixel base voltage VSS is applied. The anode of the second light-emitting element EL2 is connected to a sixth node n6, and the cathode thereof is connected to the second power line PL2. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL, but the present disclosure is not limited thereto. Each of the light-emitting elements ELI and EL2 may be implemented in a tandem structure in which a plurality of light-emitting layers are stacked. The light-emitting elements ELI and EL2 of the tandem structure may improve the luminance and lifetime of the pixel.

[0070] The first switch element T1 is connected between a fourth node n4 and a fifth node n5. The first switch element T1 is turned on in response to a gate-on voltage VGL of the first mode selection signal S sel to connect the fourth node n4 to the fifth node n5. The first switch element T1 includes a first electrode connected to the fourth node n4, a gate electrode to which the first mode selection signal S sel is applied, and a second electrode connected to the fifth node n5.

[0071] The second switching element T2 is connected between the fourth node n4 and a sixth node n6. The second switching element T2 is turned on in response to the gate-on voltage VGL of the second mode selection signal Psel to connect the fourth node n4 to the sixth node n6. The second switch element T2 includes a first electrode connected to the fourth node n4, a gate electrode to which the second mode selection signal P sel is applied, and a second electrode connected to the sixth node n6.

[0072] The third switch element T3 is connected between the fourth node n4 and the fourth power line PL4. The third switch element T3 is turned on in response to the gate-on voltage VGL of a third gate signal SCAN3 to connect the fourth node n4 to the fourth power line PL4 through which the compensation voltage Vdc is applied. The third switch element T3 includes a first electrode connected to the fourth node n4, a gate electrode to which the third gate signal SCAN3 is applied, and a second electrode connected to the fourth power line PL4.

[0073] The compensation circuit 10 may initialize the pixel circuit and compensate a data voltage Vdata inputted through a data line DL by a threshold voltage Vth of the driving element DT.

[0074] The capacitor Cst is connected between a first node nl and a second node n2. During a sensing period Tsen, the data voltage Vdata that has been compensated by the threshold voltage Vth of the driving element DT is stored in the capacitor Cst. The capacitor Cst maintains a gate-source voltage Vgs of the driving element DT during an emission period Tem.

[0075] The fourth switch element T4 is connected between the data line DL and the first node nl. The fourth switch element T4 is turned on in response to the gate-on voltage VGL of a first gate signal SCAN1 to apply the data voltage Vdata of pixel data to the capacitor Cst. The fourth switch element T4 includes a first electrode connected to the data line DL, a gate electrode to which the first gate signal SCAN1 is applied, and a second electrode connected to the first node nl.

[0076] The fifth switch element T5 is connected between the second node n2 and a third node n3. The fifth switch element T5 is turned on in response to the gate-on voltage VGL of a second gate signal SCAN2 to connect the gate electrode of the driving element DT to the second electrode thereof. The fifth switch element T5 includes a first electrode connected to the second node n2, a gate electrode to which the second gate signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0077] The sixth switch element T6 is connected between the first node nl and the third power line PL3. The sixth switch element T6 is turned on in response to the gate-on voltage VGL of a fourth gate signal EM to connect the first node nl to the third power line PL3. The sixth switch element T6 includes a first electrode connected to the first node nl, a gate electrode to which the fourth gate signal EM is applied, and a second electrode connected to the third power line PL3.

[0078] The seventh switch element T7 is connected between the third node n3 and the fourth node n4. The seventh switch element T7 is turned on in response to the gate-on voltage VGL of the fourth gate signal EM to connect the third node n3 to the fourth node n4. The seventh switch element T7 includes a first electrode connected to the third node n3, a gate electrode to which the fourth gate signal EM is applied, and a second electrode connected to the fourth node n4.

[0079] The eighth switch element T8 is connected between the fifth node n5 and the third power line PL3. The eighth switch element T8 is turned on in response to the gate-on voltage VGL of the second gate signal SCAN2 to connect the fifth node n5 to the third power line PL3 through which the reference voltage Vref is applied. The eighth switch element T8 includes a first electrode connected to the third power line PL3, a gate electrode to which the second gate signal SCAN2 is applied, and a second electrode connected to the fifth node n5.

[0080] The ninth switch element T9 is connected between the sixth node n6 and the third power line PL3. The ninth switch element T9 is turned on in response to the gate-on voltage VGL of the second gate signal SCAN2 to connect the sixth node n6 to the third power line PL3 through which the reference voltage Vref is applied. The ninth switch element T9 includes a first electrode connected to the third power line PL3, a gate electrode to which the second gate signal SCAN2 is applied, and a second electrode connected to the sixth node n6.

[0081] Referring to FIG. 3, a first lens LENS1 shown in FIG. 3 may be disposed on the first light-emitting element ELI. The first lens LENS1 may be a semi-cylindrical lens in order to limit a vertical viewing angle and widen a horizontal viewing angle. The first lens LENS1 is long in a horizontal direction (or the X-axis direction) of the display panel 100 and narrow in a vertical direction thereof. The first lens LENS1 may have a hemispherical cross section. The first lens condenses light traveling in the vertical direction among light of the first light-emitting element ELI emitted in the first mode to narrow the vertical viewing angle and widen the horizontal viewing angle. By the first lens LENS1, the vertical viewing angle of the first light-emitting element ELI is comparable to that of the second light-emitting element EL2, and the horizontal viewing angle thereof is larger than that of the second light-emitting element EL2. In FIG. 3, “R” indicates a red sub-pixel that emits light, “G” indicates a green sub-pixel that emits light, and “B” indicates a blue sub-pixel that emits light. The sub-pixels darkly expressed in FIG. 3 are nondriving sub-pixels that do not emit light.

[0082] Light emitted from a screen of a vehicle display disposed on a dashboard of a vehicle may travel to a front-facing camera disposed in front of an upper end of a room in the vehicle, and the screen of the vehicle display may be seen in an image captured by the front-facing camera. The first lens LENS1 limits the vertical viewing angle of the first light-emitting element ELI that emits light in the first mode to prevent a ghost image of the screen of the vehicle display, which is captured by the front-facing camera.

[0083] A second lens LENS2 shown in FIG. 3 may be disposed on the second light-emitting element EL2. The second lens LENS2 may be a semi-spherical lens whose thickness is larger at the center and smaller toward an edge thereof. The second lens LENS2 may condense light of the second light-emitting element EL2 emitted in the second mode to narrow an up-down and left-right viewing angles of the second light-emitting element EL2.

[0084] The first and second lenses LENS1 and LENS2 may be implemented as transparent media or transparent insulating layer patterns disposed in the display panel 100, but the present disclosure is not limited thereto.

[0085] The first light-emitting element ELI emits light at a first viewing angle by the first lens LENS1, and the second light-emitting element EL2 emits light at a second viewing angle smaller than the first viewing angle by the second lens LENS2.

[0086] This pixel circuit may be driven in a first mode in which the first lightemitting device ELI with a narrow viewing angle emits light, or in a second mode in which the second light-emitting device EL2 in a wide viewing angle emits light.

[0087] FIG. 4 is a diagram illustrating waveforms for driving the pixel circuit shown in FIG. 2 in a first mode. FIGS. 5A to 5F are diagrams illustrating an operation of a pixel circuit driven in a first mode.

[0088] Referring to FIG. 4, in the first mode, the pixel circuit is driven in the order of an initialization period Tini s, a sensing period Tsens. a data write period Tw_s, a pre-charging period Tp_s, a charge share period Tc_s, and an emission period Tern s.

[0089] Referring to FIG. 5A, during the initialization period Tini s, the second to fourth switch elements T2 to T4 are turned off, while the first switch element T1 and the fifth to ninth switch elements T5 to T9 are turned on, so that the reference voltage Vref is applied to both ends of the capacitor Cst, i.e., the first node nl and the second node n2, and to the anode electrodes of the first and second light emitting elements, i.e., the fifth node n5 and the sixth node n6, to initialize them.

[0090] Referring to FIG. 5B, during the sensing period Tsen s, the first to fourth switch elements T1 to T4 and the sixth and seventh switch elements T6 and T7 are turned off, while the fifth, eighth, and ninth switch elements T5, T8, and T9 are turned on, so that the pixel driving voltage is applied to the second node n2 to sense the threshold voltage Vth of the driving element DT. As a result, the voltage at the second node n2 becomes VDD+Vth.

[0091] Referring to FIG. 5C, during the data write period Tw_s, the first to third switch elements T1 to T3 and the sixth and seventh switch elements T6 and T7 are turned off, while the fourth, fifth, eighth, and ninth switch elements T4, T5, T8, and T9 are turned on to apply the data voltage Vdata to the first node nl. As a result, the voltage at the first node nl becomes Vdata, and the voltage at the second node n2 becomes VDD+Vth.

[0092] Referring to FIG. 5D, during the pre-charging period Tp s, the first switch element T1 and the fourth to ninth switch elements T4 to T9 are turned off, while the second and third switch elements T2 and T3 are turned on to pre-charge the sixth node n6 with the compensation voltage Vdc. As a result, the voltage at the sixth node n6 becomes Vref+Vdc, and a second parasitic capacitor Cel2 is charged with a charge +Q.

[0093] In this case, the compensation voltage Vdc may be higher than the reference voltage Vref to precharge the sixth node n6, which has been initialized to the reference voltage Vref, and may satisfy Vref <Vdc<VELi, Vel2 to prevent the light emitting elements from emitting light before the emission period. Here, Veli represents a voltage across both ends of the first light emitting element ELI, and Vel2 represents a voltage across both ends of the second light emitting element EL2.

[0094] Referring to FIG. 5E, during the charge share period Tc_s, the third to ninth switch elements T3 to T9 are turned off, while the first and second switch elements T1 and T2 are turned on to short the anode electrode of the first light emitting element, i.e., the fifth node n5, and the anode electrode of the second light emitting element, i.e., the sixth node n6, by connecting them to each other. As a result, the voltages at the fifth node n5 and the sixth node n6 are charge-shared, each becoming (Vref+Vdc) / 2, and the second parasitic capacitor Cel2 is discharged with a charge +Q / 2, while a first parasitic capacitor Celi is charged with an equal amount of charge +Q / 2.

[0095] Referring to FIG. 5F, during the emission period Tern s, the second to fifth switch elements T2 to T5 and the eighth and ninth switch elements T8 and T9 are turned off, while the first, sixth, and seventh switch elements Tl, T6, and T7 are turned on, so that a current flows through the driving element DT, causing the first light emitting element ELI to emit light.

[0096] In this case, since the voltage at the fifth node n5 is (Vref+Vdc) / 2 rather than the reference voltage Vref, the time to rise to the threshold voltage of the first light emitting element may be reduced, thereby reducing the luminance deviation.

[0097] FIG. 6 is a diagram illustrating different waveforms for driving the pixel circuit shown in FIG. 2 in a first mode.

[0098] Referring to FIG. 6, in the first mode, the pixel circuit is driven in the order of the initialization period Tini s, the sensing period Tsen s, the data write period Tw_s, the pre-charging period Tp_s, and the emission period Tern s.

[0099] Here, since the compensation voltage is directly applied to the anode electrode of the first light emitting element, unlike in FIG. 4, the charge share period may not be required and a voltage lower than the compensation voltage Vdc may be used.

[00100] FIGS. 7A and 7B are diagrams comparing luminance deviations between a comparative example and an embodiment.

[00101] Referring to FIG. 7A, the pixel circuit according to a comparative example is a circuit to which a separate compensation voltage is not applied, unlike the embodiment shown in FIG. 2. In this case, due to a deviation in the panel fabrication process, a difference in the capacitance of the parasitic capacitors formed in the light emitting elements occurs at each in-plane position. This results in a difference in charging time of the anode voltages of the light emitting elements in a low grayscale with a small amount of current, leading to a deviation in luminance uniformity in a low grayscale.

[00102] For example, when the capacitance of the parasitic capacitor is large, the charging time of the anode voltage of the light emitting element is short, so the luminance becomes relatively high, and when the capacitance of the parasitic capacitor is small, the charging time of the anode voltage of the light emitting element is long, so the luminance becomes relatively low.

[00103] Referring to FIG. 7B, the pixel circuit according to an embodiment is a circuit to which the compensation voltage shown in FIG. 2 is applied. In this case, even if a difference in the capacitance of the parasitic capacitors formed in the light emitting elements occurs at each in-plane position due to a deviation in the panel fabrication process, the deviation in luminance uniformity is compensated by precharging the anode voltage of the light emitting element with a separate compensation voltage higher than the reference voltage during the driving process, and driving the precharged voltage to be charge-shared between two adjacent light emitting elements to increase the initial anode voltage of the light emitting element.

[00104] For example, when the capacitance of the parasitic capacitor is small, the initial anode voltage of the light emitting element is increased, so the charging time is shortened, resulting in higher luminance. The luminance deviation is compensated through such charge sharing between the anode voltages of the light emitting elements.

[00105] FIG. 8 is a diagram illustrating waveforms for driving the pixel circuit shown in FIG. 2 in a second mode. FIGS. 9A to 9F are diagrams illustrating an operation of a pixel circuit driven in a second mode.

[00106] Referring to FIG. 8, in the second mode, the pixel circuit is driven in the order of an initialization period Tini_p, a sensing period Tsen_p, a data write period Tw_p, a pre-charging period Tp_p, a charge share period Tc_p, and an emission period Tem _p.

[00107] Referring to FIG. 9A, during the initialization period Tini_p, the first, third, and fourth switch elements Tl, T3, and T4 are turned off, while the second switch element T2 and the fifth to ninth switch elements T5 to T9 are turned on, so that the reference voltage Vref is applied to both ends of the capacitor Cst, i.e., the first node nl and the second node n2, and to the anode electrodes of the first and second light emitting elements, i.e., the fifth node n5 and the sixth node n6, to initialize them.

[00108] Referring to FIG. 9B, during the sensing period Tsenj, the first to fourth switch elements Tl to T4 and the sixth and seventh switch elements T6 and T7 are turned off, while the fifth, eighth, and ninth switch elements T5, T8, and T9 are turned on, so that the pixel driving voltage is applied to the second node n2 to sense the threshold voltage Vth of the driving element DT. As a result, the voltage at the second node n2 becomes VDD+Vth.

[00109] Referring to FIG. 9C, during the data write period Tw_p, the first to third switch elements Tl to T3 and the sixth and seventh switch elements T6 and T7 are turned off, while the fourth, fifth, eighth, and ninth switch elements T4, T5, T8, and T9 are turned on to apply the data voltage Vdata to the first node nl. As a result, the voltage at the first node nl becomes Vdata, and the voltage at the second node n2 becomes VDD+Vth.

[00110] Referring to FIG. 9D, during the pre-charging period Tpj, the second switch element T2 and the fourth to ninth switch elements T4 to T9 are turned off, while the first and third switch elements T1 and T3 are turned on to pre-charge the fifth node n5 with the compensation voltage Vdc. As a result, the voltage at the fifth node n5 becomes Vref+Vdc, and the first parasitic capacitor Celi is charged with a charge +Q.

[00111] In this case, the compensation voltage Vdc may be higher than the reference voltage Vref to precharge the fifth node n5, which has been initialized to the reference voltage Vref, and may satisfy Vref<Vdc<VELi, Vel2 to prevent the light emitting elements from emitting light before the emission period. Here, Veli represents a voltage across both ends of the first light emitting element ELI, and Vel2 represents a voltage across both ends of the second light emitting element EL2.

[00112] Referring to FIG. 9E, during the charge share period Tc_p, the third to ninth switch elements T3 to T9 are turned off, while the first and second switch elements T1 and T2 are turned on to short the anode electrode of the first light emitting element, i.e., the fifth node n5, and the anode electrode of the second light emitting element, i.e., the sixth node n6, by connecting them to each other. As a result, the voltages at the fifth node n5 and the sixth node n6 are charge-shared, each becoming (Vref+Vdc) / 2, and the first parasitic capacitor Celi is discharged with a charge +Q / 2, while the second parasitic capacitor Cel2 is charged with a charge +Q / 2.

[00113] Referring to FIG. 9F, during the emission period Tem_p, the first switch element Tl, the third to fifth switch elements T3 to T5, and the eighth and ninth switch elements T8 and T9 are turned off, while the second, sixth, and seventh switch elements T2, T6, and T7 are turned on, so that a current flows through the driving element DT, causing the second light emitting element EL2 to emit light.

[00114] In this case, since the voltage at the sixth node n6 is (Vref+Vdc) / 2 rather than the reference voltage Vref, the time to rise to the threshold voltage of the second light emitting element may be reduced, thereby reducing the luminance deviation.

[00115] FIG. 10 is a diagram illustrating different waveforms for driving the pixel circuit shown in FIG. 2 in a second mode.

[00116] Referring to FIG. 10, in the second mode, the pixel circuit is driven in the order of the initialization period Tini_p, the sensing period Tsen_p, the data write period Twp. the pre-charging period Tpp. and the emission period Temp

[00117] Here, since the compensation voltage is directly applied to the anode electrode of the second light emitting element, unlike in FIG. 8, the charge share period may not be required and a voltage lower than the compensation voltage Vdc may be used.

[00118] The pixel circuit according to an embodiment may allow the first light emitting element or the second light emitting element to selectively emit light, but is not limited thereto. That is, in the pixel circuit according to an embodiment, both the first light emitting element and the second light emitting element may emit light. When both the first and second light emitting elements emit light, it is possible to reproduce a high dynamic range (HDR) image with high luminance and high contrast ratio.

[00119] FIG. 11 is a diagram illustrating waveforms for simultaneously driving the pixel circuit shown in FIG. 2 in first and second modes. FIGS. 12Ato 12E are diagrams illustrating an operation of the pixel circuit driven by the waveforms of FIG. 11.

[00120] Referring to FIG. 11, in simultaneous operation of the first and second modes, the pixel circuit is driven in the order of an initialization period Tini sp, a sensing period Tsensp, a data write period Tw sp, a pre-charging period Tpsp, and an emission period Temsp.

[00121] Referring to FIG. 12A, during the initialization period Tinisp, the third and fourth switch elements T3 and T4 are turned off, while the first and second switch elements T1 and T2 and the fifth to ninth switch elements T5 to T9 are turned on, so that the reference voltage Vref is applied to both ends of the capacitor Cst, i.e., the first node nl and the second node n2, and to the anode electrodes of the first and second light emitting elements, i.e., the fifth node n5 and the sixth node n6, to initialize them.

[00122] Referring to FIG. 12B, during the sensing period Tsen sp, the first to fourth switch elements T1 to T4 and the sixth and seventh switch elements T6 and T7 are turned off, while the fifth, eighth, and ninth switch elements T5, T8, and T9 are turned on, so that the pixel driving voltage is applied to the second node n2 to sense the threshold voltage Vth of the driving element DT. As a result, the voltage at the second node n2 becomes VDD+Vth.

[00123] Referring to FIG. 12C, during the data write period Tw^sp, the first to third switch elements T1 to T3 and the sixth and seventh switch elements T6 and T7 are turned off, while the fourth, fifth, eighth, and ninth switch elements T4, T5, T8, and T9 are turned on to apply the data voltage Vdata to the first node nl. As a result, the voltage at the first node nl becomes Vdata, and the voltage at the second node n2 becomes VDD+Vth.

[00124] Referring to FIG. 12D, during the pre-charging period Tp sp, the fourth to ninth switch elements T4 to T9 are turned off, while the first to third switch elements TI to T3 are turned on to apply a compensation voltage Vdc' to the fifth and sixth nodes n5 and n6. As a result, the voltages at the fifth node n5 and the sixth node n6 both become Vref+Vdc', and the first parasitic capacitor Celi and the second parasitic capacitor Cel2 are each charged with a charge +Q.

[00125] In this case, the compensation voltage Vdc' may be a voltage lower than that in the first mode or the second mode operation, satisfying Vref<Vdc'<VELi, Vel2. Here, Veli represents a voltage across both ends of the first light emitting element ELI, and Vel2 represents a voltage across both ends of the second light emitting element EL2.

[00126] In simultaneous operation of the first mode and the second mode, a separate charge share period is not required since the compensation voltage Vdc' is simultaneously applied to the fifth node n5 and the sixth node n6.

[00127] Referring to FIG. 12E, in the emission period Tem sp, the third to fifth switch elements T3 to T5 and the eighth and ninth switch elements T8 and T9 are turned off, while the first, second, sixth, and seventh switch elements Tl, T2, T6, and T7 are turned on, so that a current flows through the driving element DT, causing both the first light emitting element ELI and the second light emitting element EL2 to emit light.

[00128] In this case, since the voltages at the fifth and sixth nodes are the compensation voltage Vdc' rather than the reference voltage Vref, the time to rise to the threshold voltage of the light emitting element may be reduced, thereby reducing the luminance deviation.

[00129] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and do not limit the present disclosure.

[00130] Also disclosed are the following numbered clauses:

[00131] 1. A pixel circuit comprising: a first light emitting element; a second light emitting element; a driving element configured to drive the first and second light emitting elements; a first switch element connected between the driving element and the first light emitting element and driven by a first mode selection signal; a second switch element connected between the driving element and the second light emitting element and driven by a second mode selection signal; and a third switch element configured to apply a predetermined compensation voltage to at least one of anode electrodes of the first light emitting element and the second light emitting element.

[00132] 2. The pixel circuit of clause 1, wherein the pixel circuit is driven in the order of an initialization period, a sensing period, a data write period, a precharging period, and an emission period, wherein during the initialization period, a reference voltage is applied to the anode electrodes of the first light emitting element and the second light emitting element to initialize them, and during the pre-charging period, the compensation voltage is applied to one of the anode electrodes of the first light emitting element and the second light emitting element which have been initialized to the reference voltage.

[00133] 3. The pixel circuit of clause 2, wherein the compensation voltage is set to be greater than the reference voltage and less than a voltage across both ends of each of the first light emitting element and the second light emitting element. charge share period after the pre-charging period, and during the charge share period, the anode electrode of the first light emitting element and the anode electrode of the second light emitting element are connected to each other to share the applied compensation voltage.

[00135] 5. The pixel circuit of clause 4, further comprising a compensation circuit, which includes: a capacitor connected between a first node and a second node to which a gate electrode of the driving element is connected; a fourth switch element including a first electrode connected to a data line, a second electrode connected to the first node, and a gate electrode to which a first gate signal is applied; a fifth switch element including a first electrode connected to the second node, a second electrode connected to a third node to which a source electrode of the driving element is connected, and a gate electrode to which a second gate signal is applied; a sixth switch element including a first electrode connected to the first node, a second electrode connected to a reference voltage line, and a gate electrode to which a fourth gate signal is applied; a seventh switch element including a first electrode connected to the third node, a second electrode connected to a fourth node, and a gate electrode to which the fourth gate signal is applied; an eighth switch element including a first electrode connected to the reference voltage line, a second electrode connected to a fifth node to which the anode electrode of the first light emitting element is connected, a gate electrode to which the second gate signal is applied; and a ninth switch element including a first electrode connected to the reference voltage line, a second electrode connected to a sixth node connected to which the anode electrode of the second light emitting element is connected, and a gate electrode to which the second gate signal is applied.

[00136] 6. The pixel circuit of clause 5, wherein the first switch element includes a first electrode connected to the fourth node, a second electrode connected to the fifth node, and a gate electrode to which the first mode selection signal is applied, the second switch element includes a first electrode connected to the fourth node, a second electrode connected to the sixth node, and a gate electrode to which the second mode selection signal is applied, and the third switch element includes a first electrode connected to the fourth node, a second electrode connected to a power line through which the compensation voltage is applied, and a gate electrode to which a third gate signal is applied.

[00137] 7. The pixel circuit of clause 6, wherein during the pre-charging period, at least one of the first switch element and the second switch element, and the third switch element are turned on, while all the other switch elements are turned off.

[00138] 8. The pixel circuit of clause 7, wherein during the charge share period, the first switch element and the second switch element are turned on, while all the other switch elements are turned off.

[00139] 9. A display device comprising: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are disposed; a data driver configured to output a data voltage to the plurality of data lines; and a gate driver configured to output a gate signal to the plurality of gate lines, wherein each of the pixel circuits includes: a first light emitting element; a second light emitting element; a driving element configured to drive the first and second light emitting elements; a first switch element connected between the driving element and the first light emitting element and driven by a first mode selection signal; a second switch element connected between the driving element and the second light emitting element and driven by a second mode selection signal; and a third switch element configured to apply a predetermined compensation voltage to at least one of anode electrodes of the first light emitting element and the second light emitting element.

[00140] 10. The display device of clause 9, wherein the pixel circuit is driven in the order of an initialization period, a sensing period, a data write period, a precharging period, and an emission period, wherein during the initialization period, a reference voltage is applied to the anode electrodes of the first light emitting element and the second light emitting element to initialize them, and during the pre-charging period, the compensation voltage is applied to one of the anode electrodes of the first light emitting element and the second light emitting element which have been initialized to the reference voltage.

[00141] 11 The display device of clause 10, wherein the pixel circuit is driven in a charge share period after the pre-charging period, and during the charge share period, the anode electrode of the first light emitting element and the anode electrode of the second light emitting element are connected to each other to share the applied compensation voltage.

[00142] 12. The display device of clause 11, wherein the compensation circuit includes: a capacitor connected between a first node and a second node to which a gate electrode of the driving element is connected; a fourth switch element including a first electrode connected to a data line, a second electrode connected to the first node, and a gate electrode to which a first gate signal is applied; a fifth switch element including a first electrode connected to the second node, a second electrode connected to a third node to which a source electrode of the driving element is connected, and a gate electrode to which a second gate signal is applied; a sixth switch element including a first electrode connected to the first node, a second electrode connected to a reference voltage line, and a gate electrode to which a fourth gate signal is applied; a seventh switch element including a first electrode connected to the third node, a second electrode connected to a fourth node, and a gate electrode to which the fourth gate signal is applied; an eighth switch element including a first electrode connected to the reference voltage line, a second electrode connected to a fifth node to which the anode electrode of the first light emitting element is connected, a gate electrode to which the second gate signal is applied; and a ninth switch element including a first electrode connected to the reference voltage line, a second electrode connected to a sixth node connected to which the anode electrode of the second light emitting element is connected, and a gate electrode to which the second gate signal is applied.

[00143] 13 The display device of clause 12, wherein the first switch element includes a first electrode connected to the fourth node, a second electrode connected to the fifth node, and a gate electrode to which the first mode selection signal is applied, the second switch element includes a first electrode connected to the fourth node, a second electrode connected to the sixth node, and a gate electrode to which the second mode selection signal is applied, and the third switch element includes a first electrode connected to the fourth node, a second electrode connected to a power line through which the compensation voltage is applied, and a gate electrode to which a third gate signal is applied.

[00144] 14. The display device of clause 9, wherein the first and second mode selection signals are received from a timing controller.

Claims

1. A pixel circuit comprising:a first light emitting element;a second light emitting element;a driving element transistor configured to drive the first and second light emitting elements;a compensation voltage line for applying a compensation voltage;a first switch element comprising a first electrode and connected between the driving element and the first light emitting element and driven by a first mode selection signal;a second switch element comprising a first electrode and connected between the driving element and the second light emitting element and driven by a second mode selection signal; anda third switch element configured to apply a predetermined compensation voltage to at least one of anode electrodes of the first light emitting element and the second light emitting element,wherein a first electrode of the third switch element is connected to the first electrode of the first switch element and the first electrode of the second switch element, and a second electrode of the third switch element is connected to the compensation voltage line.

2. The pixel circuit of claim 1, wherein the third switch element is for receiving a scan signal.

3. The pixel circuit of claim 1 or 2, further comprising:a pixel driving voltage line; anda pixel base voltage line for applying a pixel base voltage;wherein the driving element transistor is configured to connect the pixel driving voltage line to the first electrode of the first switch element and the first electrode of the second switch element.

4. The pixel circuit of claim 3, wherein a first electrode of the first light emitting element is connected to a second electrode of the first switch element and a second electrode of the first light emitting element is connected to the pixel base voltage line; andwherein a first electrode of the second light emitting element is connected to a second electrode of the second switch element and a second electrode of the second light emitting element is connected to the pixel base voltage line.

5. The pixel circuit of any preceding claim, wherein the pixel circuit is for being driven in the order of an initialization period, a sensing period, a data write period, a pre-charging period, and an emission period,wherein during the initialization period, a reference voltage is applied to the first electrodes of the first light emitting element and the second light emitting element to initialize them, andduring the pre-charging period, the compensation voltage is applied to one of the first electrodes of the first light emitting element and the second light emitting element which have been initialized to the reference voltage.

6. The pixel circuit of claim 5, wherein the compensation voltage is set to be greater than the reference voltage and less than a voltage across both ends of each of the first light emitting element and the second light emitting element.

7. The pixel circuit of claim 5 or 6, wherein the pixel circuit is for being driven in a charge share period after the pre-charging period, andduring the charge share period, the first electrode of the first light emitting element and the first electrode of the second light emitting element are connected to each other to share the applied compensation voltage.

8. The pixel circuit of any of claims 5 to 7, further comprising a compensation circuit, which includes:a capacitor connected between a first node and a second node to which a gate electrode of the driving element transistor is connected;a fourth switch element including a first electrode connected to a data line, a second electrode connected to the first node, and a gate electrode for receiving a first gate signal;a fifth switch element including a first electrode connected to the second node, a second electrode connected to a third node to which a source electrode of the driving element transistor is connected, and a gate electrode for receiving a second gate signal;a sixth switch element including a first electrode connected to the first node, a second electrode connected to a reference voltage line, and a gate electrode for receiving a fourth gate signal;a seventh switch element including a first electrode connected to the third node,a second electrode connected to a fourth node, and a gate electrode for receiving the fourth gate signal;an eighth switch element including a first electrode connected to the reference voltage line, a second electrode connected to a fifth node to which the first electrode of the first light emitting element is connected, a gate electrode for receiving the second gate signal; anda ninth switch element including a first electrode connected to the reference voltage line, a second electrode connected to a sixth node to which the first electrode of the second light emitting element is connected, and a gate electrode for receiving the second gate signal.

9. The pixel circuit of claim 8, whereinthe first electrode of the first switch element is connected to the fourth node, the second electrode of the first switch element is connected to the fifth node, and a gate electrode of the first switch element is for receiving the first mode selection signal,the first electrode of the second switch element is connected to the fourth node, the second electrode of the second switch element is connected to the sixth node, and a gate electrode of the second switch element is for receiving the second mode selection signal, andthe first electrode of the third switch element is connected to the fourth node, and a gate electrode of the third switch element is for receiving a third gate signal.

10. The pixel circuit of claim 9, wherein during the pre-charging period, at least one of the first switch element and the second switch element, and the thirdswitch element are turned on, while all the other switch elements are turned off.

11. The pixel circuit of claim 10, wherein during the charge share period, the first switch element and the second switch element are turned on, while all the other switch elements are turned off.

12. The pixel circuit of any preceding claim, wherein the first and second light-emitting elements are organic light-emitting diodes.

13. The pixel circuit of any preceding claim, wherein a viewing angle of the first light emitting element is greater than a viewing angle of the second light emitting element.

14. A display device comprising:the pixel circuit of claim 1;a data driver;a gate driver; anda power supply configured to supply the pixel base voltage and the compensation voltage.

15. The display device of claim 14, wherein the pixel circuit is configured to be driven in the order of an initialization period, a sensing period, a data write period, a pre-charging period, and an emission period,wherein during the initialization period, a reference voltage is applied to the first electrodes of the first light emitting element and the second light emittingelement to initialize them, andduring the pre-charging period, the compensation voltage is applied to one of the first electrodes of the first light emitting element and the second light emitting element which have been initialized to the reference voltage,wherein the power supply is configured to supply the reference voltage.

16. The display device of claim 15, wherein the pixel circuit is configured to be driven in a charge share period after the pre-charging period, andduring the charge share period, the first electrode of the first light emitting element and the first electrode of the second light emitting element are connected to each other to share the applied compensation voltage.

17. The display device of claim 16, wherein the compensation circuit includes:a capacitor connected between a first node and a second node to which a gate electrode of the driving element transistor is connected;a fourth switch element including a first electrode connected to a data line, a second electrode connected to the first node, and a gate electrode to which a first gate signal is applied;a fifth switch element including a first electrode connected to the second node, a second electrode connected to a third node to which a source electrode of the driving element transistor is connected, and a gate electrode to which a second gate signal is applied;a sixth switch element including a first electrode connected to the first node, a second electrode connected to a reference voltage line, and a gate electrode to whicha fourth gate signal is applied;a seventh switch element including a first electrode connected to the third node, a second electrode connected to a fourth node, and a gate electrode to which the fourth gate signal is applied;an eighth switch element including a first electrode connected to the reference voltage line, a second electrode connected to a fifth node to which the first electrode of the first light emitting element is connected, a gate electrode to which the second gate signal is applied; anda ninth switch element including a first electrode connected to the reference voltage line, a second electrode connected to a sixth node to which the first electrode of the second light emitting element is connected, and a gate electrode to which the second gate signal is applied,wherein the data driver is connected to the data line and the gate driver is configured to supply the gates signals.

18. The display device of claim 17, wherein:the first electrode of the first switch element is connected to the fourth node, the second electrode of the first switch element is connected to the fifth node, and the first mode selection signal is applied to a gate electrode of the first switch element,the first electrode of the second switch element is connected to the fourth node, the second electrode of the second switch element is connected to the sixth node, and the second mode selection signal is applied to a gate electrode of the second switch element, andthe first electrode of the third switch element is connected to the fourth node, and a third gate signal is applied to a gate electrode of the third switch element.

19. The display device of any of claims 14 to 18, wherein the display device further comprises a timing controller and the first and second mode selection signals are received from the timing controller.

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