Controlled oscillators

Abstract

The disclosed voltage-controlled oscillator (VCO) 500 has a ring oscillator 210 with an output frequency that depends on a bias current IB. A voltage-to-current circuit 203 generates the bias current and comprises a first current source 204 for generating a first current that varies with the VCO drive voltage, VD, and a second current source 205 that generates a second current that does not vary with the VCO drive voltage. The first and second currents are combined to provide the bias current supplied to the ring oscillator. A mode controller 501 selectively operates the VCO in a plurality of different modes wherein the second current is different in each mode. The resulting range of output frequency of the VCO is different in each mode. A wide range of output frequency is thus possible while avoiding the problem of high gain in the VCO transfer function (figures 3 and 4).

Description

The field of representative embodiments of this disclosure relates to methods, apparatus and / or implementations concerning or relating to controlled oscillators, in particular to voltage-controlled oscillators with a wide operating range of frequency. Controlled oscillators, for example voltage-controlled oscillators (VCOs), are used in a variety of applications. For instance, VCOs are routinely used as part of phase-locked loops (PLLs) for clock generation or frequency synthesis. Figure 1 illustrates one example of a known PLL which includes a VCO 101. A VCO drive voltage VD is supplied to the VCO 101, which generates an output clock signal CLK_OUT with a frequency that depends on VCO drive voltage VD. The output clock signal CLK_OUT is fed-back, possibly via a frequency divider 102 with a controllable divide value N, to a PLL controller 103 which also receives an input clock signal CLK_IN and which adjusts the VCO drive voltage to ensure that the feedback signal has phase and frequency lock with the input clock signal CLK_IN. In the example of figure 1, the PLL controller comprises a phase-and-frequency detector (PFD) 104, which compares the feedback signal with the input clock signal CLK_IN to determine whether clock edges of the feedback signal lead or lag the corresponding clock edges of the input clock signal CLK_IN and which generates down or up control signals for a charge pump 105 to decease or increase an output voltage, which is filtered by filter 106 to provide the VCO drive voltage VD. In this way the PLL 100 provides a stable output clock CLK_OUT with a frequency of N times the input clock signal CLK_IN. In some applications it may be desirable for such a PLL to be able to provide the output clock signal CLK_OUT over a wide range of possible operating frequencies, which consequently requires the VCO to be operable over a wide range of output frequencies for a given range of VCO drive voltage. This can be achieved by providing the VCO with a relatively high voltage-to-frequency transfer function gain, referred to as KVCO. However, a high KVCO can lead to lead to problems of noise and / or impact loop stability for the PLL. Embodiments of the present disclosure relate to methods and apparatus for controlled oscillators that at least mitigate at least some of above-mentioned issues. According to an aspect of the disclosure there is provided a voltage-controlled oscillator circuit comprising a ring oscillator with a plurality of delay elements, wherein an output frequency of the ring oscillator depends on a bias current supplied to the ring oscillator. A voltage-to-current circuit is configured to generate the bias current with a dependence on a VCO drive voltage. The voltage-to-current circuit comprises a first current source arrangement configured to generate a first current that varies with the VCO drive voltage and a second current source arrangement configured to generate a second current that does not vary with the VCO drive voltage; wherein the first and second currents are combined to provide the bias current supplied to the ring oscillator. A mode controller is configured to control the voltage-controlled oscillator circuit to selectively operate in one of a plurality of different modes, wherein the second current is different in each of said different modes such that an output range of frequency of the voltage-controlled oscillator circuit is different in each of said different modes. In some implementations, the mode controller may be configured to control a trim setting for the second current source arrangement to be different in the different modes to provide the different second current in the different modes. The different trim settings for the different modes may be predetermined and stored in a memory accessible by the mode controller. The different trim settings for the different modes may be settings determined in a manufacturing calibration process and written to said memory accessible by the mode controller. In some implementations, the variation in the first current with the VCO drive voltage may be the same in each of the different modes. In some implementations, the output ranges of frequency in the different modes may overlap in frequency. In some implementations, the voltage controlled oscillator circuit may be configured such that, at any operating temperature within a defined range of operating temperatures, upper and lower limits of the frequency range of a first mode are lower than respective upper and lower limits of the frequency range of a second mode corresponding to a higher frequency range and the upper limit of the frequency range of the first mode is higher than the lower limit of the frequency range of the second mode. In some implementations, the mode controller may be configured to control operation in a selected mode based on an indication of expected output frequency for the voltage-controlled oscillator circuit. The mode controller may be configured to operate in a first mode for an expected output frequency in a range between lower and upper values F0 and F1 respectively and to operate in a second mode for an expected output frequency in a range between lower and upper values F1 and F2 respectively, and the voltage controlled oscillator circuit may be configured such that an upper limit of the frequency range for the first mode is no lower than F1 across a defined range of operating temperatures and a lower limit of the frequency range for the second mode is no higher than F1 across the defined range of operating temperatures. In another aspect, a phase-locked-loop circuit may comprise the voltage-controlled oscillator circuit of any of the embodiments described herein configured to output an output clock signal and a PLL control arrangement configured to receive an input clock signal and a feedback signal derived from the output clock signal and to control the VCO drive voltage to achieve phase and frequency lock between the input clock signal and the clock signal. The phase-locked-loop circuit may comprise a frequency divider in a feedback path between an output for the output clock signal and the PLL control arrangement. The frequency divider may be configured to divide the frequency of the output clock signal by a controllably variable divide value to provide the feedback signal, wherein the mode controller is configured to control the mode of operation of the voltage-controlled oscillator circuit based on the variable divide value. Aspects also relate to an integrated circuit comprising the voltage-controlled oscillator circuit of any of the embodiments described herein or the phase-locked-loop circuit of any of the embodiments described herein. In another aspect there is provided a method of determining trim settings for a voltage-controlled oscillator circuit according to any of the embodiments described herein, the method comprising: setting the VCO drive voltage to a minimum drive value and adjusting the trim setting until an output frequency of the voltage-controlled oscillator circuit is less than a defined minimum frequency and storing the relevant trim setting as a minimum trim setting corresponding to a lowest frequency mode; setting the VCO drive voltage to a maximum drive value and adjusting the trim setting until an output frequency of the voltage-controlled oscillator circuit is more than a defined maximum frequency and storing the relevant trim setting as a maximum trim setting corresponding to a highest frequency mode; and interpolating between the maximum and minimum trim settings to determine one or more intermediate trim setting, each trim setting corresponding to a respective intermediate frequency mode. The method may be performed by test equipment as part of a manufacturing calibration process for an integrated circuit comprising the voltage-controlled oscillator circuit. The method may comprise writing the determined maximum, minimum and intermediate trim settings to the memory by the mode controller. It should be noted that, unless expressly indicated to the contrary herein or otherwise clearly incompatible, then any feature described herein may be implemented in combination with any one or more other described features. For a better understanding of examples of the present disclosure, and to show more clearly how the examples may be carried into effect, reference will now be made, by way of example only, to the following drawings in which: Figure 1 illustrates an example of a PLL including a VCO; Figure 2 illustrates the principles of one example of a VCO; Figure 3 illustrates an example of how output frequency may vary with voltage for the VCO of figure 2; Figure 4 illustrates an example how output frequency may vary with voltage across a plurality of frequency sub-ranges; Figure 5 illustrates an example of a VCO according to an embodiment which is operable with a plurality of frequency sub-ranges; and Figure 6 illustrates one method of determining trim settings for the VCO of figure 5. The description below sets forth example embodiments according to this disclosure. Further example embodiments and implementations will be apparent to those having ordinary skill in the art. Further, those having ordinary skill in the art will recognize that various equivalent techniques may be applied in lieu of, or in conjunction with, the embodiments discussed below, and all such equivalents should be deemed as being encompassed by the present disclosure. As noted above, in some applications there is a desire for a controlled oscillator, such as a voltage-controlled oscillator (VCO) to be operable over a wide range of possible output frequencies. Figure 2 illustrates the principles of operation of one known example of a VCO 200. The VCO 200 comprises a ring-oscillator 201, which comprises an odd number of inverters 202 series connected in a ring arrangement to provide an output clock signal CLK_OUT. As will be understood by one skilled in the art, the output clock signal CLK_OUT will be an oscillation signal with a frequency that depends on the number of inverters 202 and a propagation delay for each of the inverters. The propagation delay of the inverters depends on a bias current IB supplied to the ring oscillator 201. To provide a variable output frequency, the bias current IB is variable and is generated by voltage-to-current circuit 203 with a dependence on the VCO drive voltage VD. The voltage-to-current circuit 203 of the example of figure 2 is an analog circuit that has a first current source arrangement 204 for generating a variable current Ivar that varies with the VCO drive voltage VD. The voltage-to-current circuit 203 also comprises a second current source arrangement 205 that generates a nominally fixed, i.e. nonvariable current, Inx. These currents Ivar and lFix are combined to provide the bias current IB for the ring oscillator 201. The variable current Ivar effectively defines how the bias current IB varies with the VCO drive voltage, and thus effectively sets the voltage-to-frequency transfer function gain KVCO and extent of the operating frequency range, whilst the fixed current I fix effectively provides a fixed offset and thus defines the centre frequency of the operating range. To account for part-to-part process variations, the first and second current source arrangements 204 and 205 are configurable to ensure the desired bias current is generated in use, for a given value of VCO drive voltage (at defined operating conditions of supply voltage and temperature). Thus a range trim setting TR may provide configurability of the variable current Ivar. This is represented in figure 2 as the range trim setting TR controlling a multiplier, although it will be appreciated that the actual implementation may not involve a multiplier as such and may, for instance, involve enabling or disabling elements of the current source arrangement. Likewise a centre frequency trim setting TC may similarly provide configurability of the fixed current Ifix. These trim settings may be determined as part of a calibration process, e.g. as part of a start-up self-calibration, so that the VCO 200 operates over the desired frequency range. To provide a suitably wide operating range of frequency for the VCO, the first current source arrangement 204 could be configured to have a relatively large range for the variable current Ivar. That is, to achieve a desired operating range in frequency for the VCO 200, from a minimum frequency fmin to a maximum frequency fmax (at a defined temperature), the first current source arrangement 204 could be tuned so that a variation in VCO drive voltage from a minimum value, VDmin, to a maximum value, VDmax, provides a sufficient change in bias current to provide the required frequency excursion. The second current source arrangement 205 would then be tuned to set the centre frequency such that the minimum and maximum frequencies fmin and fmax have the desired values. Figure 3 illustrates a plot of the variation in output frequency with drive voltage for such operation (note, one skilled in the art will understand that the plot of figure 3 is an idealised plot and the variation in frequency with drive voltage may, in practice, not be linear over the whole of the operating range). For a wide operating range in output frequency, i.e. a large difference in the maximum and minimum frequency values, fmax and fmin, the KVCO gain of the VCO 200 needs to be relatively high, which as noted previously, can lead to undesirable issues with noise and / or negatively impact loop stability, when the VCO is used in a control loop such as a PLL discussed with reference to figure 1. Embodiments of the present disclosure implement a controlled oscillator, which may, in particular, be a VCO, which avoids the problem of an unduly high transfer function gain, e.g. KVCO gain. In embodiments of the disclosure, the VCO is operable with a plurality of different frequency sub-ranges, where the plurality of frequency sub-ranges collectively extend over the whole required frequency operating range, but each frequency sub-range extends over only part of this overall range. The VCO is configured such that the same VCO drive frequency will lead to a different VCO output frequency for the different frequency sub-ranges. The VCO drive voltage can be varied over the majority, or substantially all, of the range of VCO drive voltage but this only results in a variation of frequency of the VCO within the relevant frequency sub-range. This reduces the KVCO compared to operating over a single larger range. Figure 4 illustrates this principle. Figure 4 illustrates lines 401,402 and 403 representing how frequency may vary with VCO drive voltage VD over three different frequency subranges (for a given operating temperature). Line 401 illustrates a first frequency subrange, where a variation in drive voltage from VDmin to VDmax results in a variation in VCO output frequency from frlmin to frlmax, and line 402 illustrates a second frequency sub-range, where the same variation in drive voltage from VDmin to VDmax instead results in a variation in VCO output frequency from fr2min to fr2max, where fr2min and fr2max are higher than frlmin to frlmax respectively. Likewise, line 403 represents a third frequency sub-range with a frequency extent from fr3min to fr3max, where fr3min and fr3max are higher than fr2min to fr2max respectively. By selectively operating in the different frequency sub-ranges, the output frequency of the VCO can be selectively controlled to be any frequency within the overall frequency range between frlmin and fr3max, but with a reduced KVCO gain compared to that of line 404, which illustrates how frequency would vary with VCO drive voltage VD for a single operating frequency range of equivalent overall extent. The VCO can thus be considered to be operable in a selected one of a plurality of different modes, where the frequency output range of the VCO is different in each mode and the frequency output range in a given mode is only part of the overall operating range of the VCO. Figure 5 illustrates one example of a VCO 500 operable in different modes with different frequency sub-ranges according to an embodiment, in which similar components as discussed with reference to figure 2 are identified by the same references. Like VCO 200 discussed with reference to figure 2, the VCO 500 comprises a ring oscillator 201 with delay elements 202 driven by a bias current IB, the bias current IB being generated by voltage-to-current circuitry 203 with a dependence on the VCO drive voltage VD. To provide the variation in bias current IB with VCO drive voltage VD, a first current source arrangement 204 provides a variable current Ivar which varies with the VCO drive voltage VD. For the VCO 500, the bias current IB also has a dependence on a selected operating mode, as controlled by mode controller 501, so as to provide different frequency subranges. In the example of figure 5, the mode controller 501 controls the current generated by second current source arrangement 205, such that the current from the second current source arrangement 205, referred to Imode, is different for the different frequency sub-ranges. That is, the current Imode from the second current source arrangement 205 has a first value when operating in a first mode to provide the first frequency sub-range, a second, different, value when operating in a second mode to provide the second frequency sub-range, and a third value, different again, when operating in a third mode to provide the third frequency sub-range. Conveniently, the mode controller 501 may control the current Imode from the second current source arrangement 205 by controlling the trim settings TC for the second current source arrangement 205 such that the trim settings TC are different in the different modes. In a selected mode, the current Imode from the second current source arrangement 205 has a nominally fixed value, but the value of the current Imode differs in the different modes. In any given mode, the variable current Ivar from the first current source arrangement 204 effectively defines how the bias current IB varies with the VCO drive voltage and thus effectively sets the voltage-to-frequency transfer function gain KVCO and extent of the operating frequency sub-range, whilst the current Imode effectively provides a fixed offset and thus effectively defines the centre frequency of the relevant frequency sub-range. In at least some embodiments, the extent of the variation of the variable current Ivar may be the same in each mode, i.e. the range trim settings TR may not vary between the different modes, which can advantageously mean that the KVCO gain is the same in each mode. However, if desired it would be possible to provide different range trim settings in the different modes. The mode controller 501 controls the mode of operation of the VCO based on an indication of an expected output frequency of the VCO, i.e. an indication of the output frequency that the VCO is expected to be operated to provide. In at least some applications, the system in which the VCO 501 is used may effectively provide an indication of the expected output frequency for the VCO which can be used by the mode controller 501. For instance, for use in a PLL such as discussed with reference to figure 1, the output frequency of the PLL, and hence the VCO, is determined by the frequency of the input clock signal CLK_IN and the division value N. The nominal value of the input clock signal CLK_IN may be fixed and the output frequency of the PLL varied by changing the division value N. In which case, an indication of the division value N can be used as an indication of the expected output frequency of the VCO in use, and hence the mode controller 501 may control the mode of operation of the VCO based on an indication of the division value N. In some implementations, there could be a plurality of different frequency clock signals selectively used for the input clock signal CLKJN for the PLL, in which case the indication of the expected VCO output frequency may additionally or alternatively comprise an indication of the relevant clock signal selected as the PLL input clock signal CLKJN. The example of figure 3 illustrates three frequency sub-ranges, but it will be understood that different implementations may use different numbers of sub-ranges, for instance a greater number of sub-ranges. The number and spacing of the sub-ranges, and corresponding modes of operation, may be selected to provide a desired overall operating range of frequency with a desired KVCO gain in each individual mode and / or a desired degree of overlap in frequency between the sub-ranges. As illustrated in figure 3, the frequency sub-ranges may be configured to overlap, that is, at any given operating temperature, the upper frequency frlmax of the first frequency sub-range is greater than the lower frequency fr2min of the second frequency sub-range and similarly the upper frequency fr2max of the second frequency sub-range is greater than the lower frequency fr3min of the third frequency sub-range and so on for any additional sub-ranges. Providing an overlap between the frequency ranges can be advantageous in accounting for variations arising due to changes in operating conditions, such as temperature and supply voltage. It will be understood that the relationship between frequency and drive voltage VD illustrated in figure 4 will be valid for a given set of operating conditions and that a change in such conditions, e.g. a change in temperature, will result in a frequency shift of each of the sub-ranges, i.e. the value of the frequency frlmax that is generated by a drive voltage of VDmax when operating in the first mode has a dependence on temperature. Advantageously, the mode controller 501 may be configured to operate the VCO 500 in the first mode, with the first frequency sub-range, for an expected output frequency in a defined range, say from a defined frequency value F0 up to a certain frequency value F1, and to operate in the second mode, with the second frequency sub-range, for an expected output frequency in a range above the frequency value F1, up to a value F2 and may be configured to operate in this fashion across the whole expected range of operating conditions, i.e. so that mode controller 501 does not need to take conditions such as operating temperature into account. The first frequency sub-range may therefore be defined such that the upper limit of frequency frlmax that results from the drive voltage VDmax is no lower than F1 across the range of expected operating conditions and that the lower limit of frequency fr2min that results from the drive voltage VDmin is no higher than F1 across the range of expected operating conditions. In other words, at a temperature T1 that leads to the worst case expected decrease in output frequency, the frequency frlmax is F1 or higher and at a temperature T2 that leads to the worst case expected increase in output frequency, the frequency frlmax is F1 or lower. The limits of the other frequency ranges may be defined in a similar way, which means that at any given operating temperature, the respective frequency sub-ranges overlap. In addition, it may be desirable to allow for some frequency drift in use, i.e. to allow the expected frequency value to drift by a certain amount in use, e.g. by ±X%. In this case, it may be advantageous to ensure that the frequency frlmax that results from the drive voltage VDmax is no lower than F1+X% across the range of expected operating conditions and that the frequency fr2min that results from the drive voltage VDmin is no higher than F1-X% across the range of expected operating conditions. The mode controller 501 may thus controllably vary the trim settings TC for the second current source arrangement 205 based on the indication of expected output frequency for the VCO, e.g. based on the selected division value N in a PLL. The relevant trim settings TC are predetermined and may be selected from some suitable memory, e.g. as a look-up table or the like. To account for part-to-part variations, the relevant trim settings to implement the different frequency sub-ranges may be determined in a calibration process that may be performed as part of a factory calibration during device fabrication. Figure 6 illustrates one example of a suitable calibration process, which may be implemented by production test equipment (PTE), to determine the trim settings TC. Prior to determining the trim settings TC for the centre frequencies of the different frequency sub-ranges, the range trim settings may be calibrated to provide a desired KVCO gain based on the conventional process for calibrating the range trim setting TR, e.g. the VCO drive voltage may be varied between VDmin and VDmax and the change in output frequency Fout determined. Once suitable range trim settings have been applied, the process illustrated in figure 6 may be performed. In a first step 601 the VCO drive voltage may be set to the minimum setting VDmin and the trim setting TC reduced in step 602 until the output frequency Fout is less than a defined minimum frequency Fmin for the overall frequency range. This trim setting is stored as the minimum trim setting, which defines the lowest frequency sub-range. The VCO drive voltage may then be set to the maximum setting VDmax in step 603 and the trim setting TC increased in step 604 until the output frequency Fout is greater than a defined maximum frequency Fmax for the overall frequency range. This trim setting is stored as the maximum trim setting, which defines the highest frequency sub-range. In the example of figure 6 the trim setting values for any intermediate frequency sub-range are then determined by interpolation between the maximum and minimum trim settings to provide the required number of frequency subranges with the desired degree of overlap. Interpolation of these additional trim settings avoids the need for additional trimming process steps and can be performed by the PTE. The determined trim values for the different frequency sub-ranges, i.e. the different operating modes of the VCO, can then be written to suitable storage which forms part of the VCO circuit. It will, of course, be understood that the order of determining the minimum and maximum trim settings could be swapped, i.e. steps 603 and 604 could be performed before steps 601 and 602. As mentioned, this method of determining the suitable trim settings TC for the different modes of the VCO may be performed as part of a calibration step during device manufacture. However, in some applications if suitable clocks are available to the circuit to determine whether Fout is greater than Fmax or lower than Fmin to a sufficient accuracy, the calibration could be performed as part of a self-calibration on start-up or reset of the VCO. As noted above, a full set of trim settings for each of the different operating ranges may be determined, e.g. by interpolation from determined minimum and maximum trim settings, and the full set of trim settings stored in memory. In some cases, however, at least some trim settings could be calculated in use, e.g. by some logic associated with the mode controller. Thus, the maximum and minimum settings could be determined in a similar manner as discussed above, either as part of a factory calibration process and stored in memory or determined as part of a self-calibration process, but the trim settings for other intermediate operating modes may not be stored and may be calculated as needed. For example, based on the indication of expected output frequency a relevant trim setting could be interpolated from between the maximum and minimum values, which may reduce the amount of memory required compared to storing all the different trim settings. Embodiments of the present disclosure thus enable a VCO to be implemented based on a known VCO design but operated to provide different operating modes with different output frequency ranges. This enables the VCO to provide a wide operating range of frequency but without issues associated with a relatively high KVCO gain. Embodiments have been described with reference to VCOs, but the principles are applicable to other type of controlled oscillator. Controlling the trim settings of the VCO is a convenient way to provide the different frequency sub-ranges but other means of the implementing different frequency sub-ranges could be used in some implementations. Embodiments may be implemented as an integrated circuit. Embodiments may be implemented in a host device, which may be a portable and / or battery powered host device such as a mobile computing device for example a laptop, notebook or tablet computer, or a mobile communication device such as a mobile telephone, for example a smartphone, or an image capture device, such as a scanner. The device could be a wearable device such as a smartwatch. The host device could be a games console, a remote-control device, a home automation controller or a domestic appliance, a toy, a machine such as a robot, an audio player, a video player. It will be understood that embodiments may be implemented as part of a system provided in a home appliance or in a vehicle. There is further provided a host device incorporating the above-described embodiments. The skilled person will recognise that some aspects of the above-described apparatus and methods may be embodied as processor control code, for example on a non-volatile carrier medium such as a disk, CD- or DVD-ROM, programmed memory such as read only memory (Firmware), or on a data carrier such as an optical or electrical signal carrier. For some applications, embodiments may be implemented on a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array). Thus, the code may comprise conventional program code or microcode or, for example code for setting up or controlling an ASIC or FPGA. The code may also comprise code for dynamically configuring re-configurable apparatus such as re-programmable logic gate arrays. Similarly, the code may comprise code for a hardware description language such as Verilog ™ or VHDL (Very high-speed integrated circuit Hardware Description Language). As the skilled person will appreciate, the code may be distributed between a plurality of coupled components in communication with one another. Where appropriate, the embodiments may also be 5 implemented using code running on a field-(re)programmable analogue array or similar device in order to configure analogue hardware. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative 10 embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single feature or other unit may fulfil the functions of several units recited in the claims. Any reference numerals or labels in the claims shall not be construed so as to limit their scope. 15

Claims

1. A voltage-controlled oscillator circuit comprising:a ring oscillator comprising a plurality of delay elements wherein an output frequency of the ring oscillator depends on a bias current supplied to the ring oscillator;a voltage-to-current circuit configured to generate said bias current with a dependence on a VCO drive voltage, wherein the voltage-to-current circuit comprises:a first current source arrangement configured to generate a first current that varies with the VCO drive voltage; anda second current source arrangement configured to generate a second current that does not vary with the VCO drive voltage;wherein said first and second currents are combined to provide the bias current supplied to the ring oscillator; anda mode controller configured to control the voltage-controlled oscillator circuit to selectively operate in one of a plurality of different modes, wherein the second current is different in each of said different modes such that an output range of frequency of the voltage-controlled oscillator circuit is different in each of said different modes.

2. The voltage-controlled oscillator circuit of claim 1 wherein the mode controller is configured to control a trim setting for the second current source arrangement to be different in the different modes to provide the different second current in the different modes.

3. The voltage-controlled oscillator circuit of claim 2 where the different trim settings for the different modes are predetermined and stored in a memory accessible by the mode controller.

4. The voltage-controlled oscillator circuit of claim 3 wherein the different trim settings for the different modes are settings determined in a manufacturing calibration process and written to said memory accessible by the mode controller.

5. The voltage-controlled oscillator circuit of any preceding claim wherein the variation in the first current with the VCO drive voltage is the same in each of the different modes.

6. The voltage-controlled oscillator circuit of any preceding claim wherein the output ranges of frequency in the different modes overlap in frequency.

7. The voltage controlled oscillator circuit of any preceding claim configured such that, at any operating temperature within a defined range of operating temperatures, upper and lower limits of the frequency range of a first mode are lower than respective upper and lower limits of the frequency range of a second mode corresponding to a higher frequency range and the upper limit of the frequency range of the first mode is higher than the lower limit of the frequency range of the second mode.

8. The voltage-controlled oscillator circuit of any preceding claim wherein the mode controller is configured to control operation in a selected mode based on an indication of expected output frequency for the voltage-controlled oscillator circuit.

9. The voltage controlled oscillator circuit of claim 8 wherein the mode controller is configured to operate in a first mode for an expected output frequency in a range between lower and upper values F0 and F1 respectively and to operate in a second mode for an expected output frequency in a range between lower and upper values F1 and F2 respectively, and the voltage controlled oscillator circuit is configured such that an upper limit of the frequency range for the first mode is no lower than F1 across a defined range of operating temperatures and a lower limit of the frequency range for the second mode is no higher than F1 across the defined range of operating temperatures.

10. A phase-locked-loop circuit comprising:the voltage-controlled oscillator circuit of any preceding claim configured to output an output clock signal; anda PLL control arrangement configured to receive an input clock signal and a feedback signal derived from the output clock signal and to control the VCO drive voltage to achieve phase and frequency lock between the input clock signal and the clock signal.

11. The phase-locked-loop circuit of claim 10 comprising a frequency divider in a feedback path between an output for the output clock signal and the PLL control arrangement, wherein the frequency divider is configured to divide the frequency of the output clock signal by a controllably variable divide value to provide the feedback signal, wherein the mode controller is configured to control the mode of operation of the voltage-controlled oscillator circuit based on the variable divide value.

12. An integrated circuit comprising the voltage-controlled oscillator circuit of any of claims 1 to 8 or the phase-locked-loop circuit of any of claims 9 to 11.

13. A method of determining trim settings for a voltage-controlled oscillator circuit as claimed in claim 3 or any of claims 4 to 8 when dependent on claim 3, the method comprising:setting the VCO drive voltage to a minimum drive value and adjusting the trim setting until an output frequency of the voltage-controlled oscillator circuit is less than a defined minimum frequency and storing the relevant trim setting as a minimum trim setting corresponding to a lowest frequency mode;setting the VCO drive voltage to a maximum drive value and adjusting the trim setting until an output frequency of the voltage-controlled oscillator circuit is more than a defined maximum frequency and storing the relevant trim setting as a maximum trim setting corresponding to a highest frequency mode; andinterpolating between the maximum and minimum trim settings to determine one or more intermediate trim setting, each trim setting corresponding to a respective intermediate frequency mode.

14. The method of claim 13 wherein the method is performed by test equipment as part of a manufacturing calibration process for an integrated circuit comprising the voltage-controlled oscillator circuit.5 15. The method of claim 14 comprising writing the determined maximum, minimumand intermediate trim settings to the memory by the mode controller.19

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