High electron mobility transistors

Abstract

A high electron mobility transistor (HEMT) comprising: a channel layer 130; a barrier layer 140 configured to induce a two-dimensional electron gas (2DEG) 132 in the channel layer; a gate dielectric 480; and a gate electrode 470. The gate electrode comprises a work function configured to interrupt formation of the 2DEG in the channel layer, when a zero bias voltage is applied to the gate electrode by having the conduction band of the channel layer above the fermi level. This allows the HEMT to be used in enhancement mode operation.

Description

Technical field The present application relates to a high electron mobility transistor (HEMT). The present application also relates to a RF module, an electronic device and a method of forming a HEMT. Background Forming semiconductor devices from lll-N semiconductor materials is becoming increasingly desirable. Si has dominated the semiconductor industry for many decades. However, lll-N semiconductor materials, such as GaN, possess desirable electronic and photonic properties, outperforming Si in many aspects. The high electron mobility transistor (HEMT) is a semiconductor device commonly formed from lll-N materials. lll-N HEMTs typically exhibit a higher breakdown voltage and greater electron mobility than Si MOSFETs. The use of lll-N HEMTs has therefore found use in power and radio frequency (RF) communications applications. HEMTs exhibit high electron mobility due to the formation of a two-dimensional electron gas (2DEG) in the channel layer of the HEMT. Typically, an AIGaN barrier layer is formed over a GaN channel layer. The AIGaN barrier layer induces the formation of a 2DEG in the GaN channel layer. Whilst the formation of the 2DEG is a desirable property it commonly results in HEMTs exhibiting depletion mode (D-mode) behaviour where a negative bias voltage is applied to the HEMT in order to turn the HEMT to the ‘off’ state. The D-mode behaviour of a HEMT is typically not as desirable as an enhancement mode (E-mode) operation, where a transistor is normally in the ‘off’ state and a positive bias voltage is applied to turn the transistor to the ‘on’ state. For D-mode operation, a driver circuit or negative bias generator is typically added to a circuit to appropriately control the HEMT. Such circuitry is not commonly used for E-mode operation. Summary It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques. According to a first aspect there is provided a high electron mobility transistor (HEMT) for enhancement mode operation. The HEMT comprising: a channel layer; a barrier layer configured to induce a two-dimensional electron gas, 2DEG, in the channel layer; a gate dielectric; and a gate electrode. The gate electrode comprises a work function configured to interrupt formation of the 2DEG in the channel layer, when a zero bias voltage is applied to the gate electrode. According to a second aspect there is provided a semiconductor wafer comprising the HEMT according to the first aspect. According to a third aspect there is provided a radio frequency, RF, module comprising the HEMT according to the first aspect. According to a fourth aspect there is provided an electronic device comprising the RF module according to the third aspect. According to a fifth aspect there is provided a method for forming a HEMT. The method comprises forming a channel layer and a barrier layer, wherein the barrier layer is configured to induce a two-dimensional electron gas, 2DEG, in the channel layer; forming a gate dielectric; and forming a gate electrode, wherein the gate electrode comprises a work function configured to interrupt formation of the 2DEG in the channel layer when a zero bias voltage is applied to the gate electrode. According to a sixth aspect there is provided a method of forming a plurality of HEMTs comprising forming the HEMT according to the fifth aspect. Brief description of the drawings For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is an example of a HEMT; Figures 2a and 2b are examples of energy band diagrams; Figures 3a and 3b are examples of energy band diagrams; Figure 4 is another example of a HEMT; Figures 5a and 5b are examples of energy band diagrams; Figures 6a-c are process steps in a method for forming a HEMT; Figure 7 is an example of a semiconductor wafer; Figure 8 is another example of a semiconductor wafer; Figure 9 is another example of a semiconductor wafer; Figure 10 is another example of a HEMT; Figure 11 another example of a HEMT; Figure 12 is an energy band diagram; Figure 13 is another energy band diagram; Figure 14 is a block diagram illustrating a method of forming a HEMT. Detailed Description Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metalorganic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition. Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer. A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Alo.25Gao.75As means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As. Crystalline means a material or layer with a single crystal orientation. In epitaxial growth or deposition subsequent layers with the same or similar lattice constant follow the registry of the previous crystalline layer and therefore grow with the same crystal orientation. In-plane is used herein to mean parallel to the surface of the substrate; out-of-plane is used to mean perpendicular to the surface of the substrate. Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb). A substrate may be on-axis, that is where the growth surface aligns with a crystal plane. For example it has <100> crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane. Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction. Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type. A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and / or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function. A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided. A fully depleted porous layer means a layer in which there are no charge carriers. Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer. To provide additional context to the description of the examples according to the present disclosure, there now follows a further discussion of the drawbacks, which conventional techniques suffer from. Figure 1 is an example of a conventional HEMT 100. HEMT 100 comprises a substrate 110 and a buffer layer 120, a channel layer 130 and a barrier layer 140 formed on the substrate. The buffer layer 120, channel layer 130 and barrier layer 140 comprise semiconductor material. In one example, the buffer layer 120, channel layer 130 and barrier layer 140 comprise lll-N semiconductor material. However, in other examples, the buffer layer 120, channel layer 130 and barrier layer 140 comprise other lll-V materials such as GaAs-based materials. The buffer layer 120, channel layer 130 and barrier layer 140 may thus be epitaxially grown on the substrate 110. The buffer layer 120, is configured to eliminate defects and provide isolation between the substrate 110 and the channel layer 130 above the buffer layer 120. In some examples, the buffer layer 120 comprises GaN. Channel layer 130 provides the channel in the HEMT for charge carriers to flow. A 2-dimensional electron gas (2DEG) 132 is formed in the channel, which confines the electrons and results in the HEMT exhibiting high electron mobility properties. The 2DEG 132 is formed in the channel layer 130 due to a polarization discontinuity between the barrier layer 140 and the channel layer 130. In some examples, the channel layer 130 comprises GaN and the barrier layer 140 comprises AIGaN. HEMT 100 further comprises a source electrode 150, a drain electrode 160 and a gate electrode 170. As illustrated in Figure 1, the 2DEG 132 is continuous between the source electrode 150 and the drain electrode 160. As such, with no bias voltage applied to the gate electrode 170, the formation of the 2DEG 132 results in current flow between the source electrode 150 and drain electrode 160. The HEMT 100 thus exhibit D-mode behaviour. A negative bias voltage is applied to the gate electrode 170 to turn the HEMT 100 to the ‘off’ state where the formation of the 2DEG is interrupted. Gate electrode 170 is thus positioned over a planar surface of the barrier layer 140. In such examples, gate electrode 170 may thus not comprise a recessed gate, which sits within a recess formed within the barrier layer 140. Figures 2a and 2b are energy band diagrams 200a, 200b illustrating operation of the HEMT 100. Energy band diagrams 200a, 200b illustrate the position of a conduction band 210 relative to a fermi level 220 across the gate 170, barrier layer 140, channel layer 130 and buffer layer 120 of the HEMT 100. Energy band diagram 200a illustrates the position of the conduction band 210 across the HEMT 100 when no bias voltage is applied to the gate 170. In this state, a 2DEG 230 is formed in the channel layer 130 near the interface with the barrier layer 140. In this state, a current thus flows between the source electrode 150 and drain electrode 160 and the HEMT 100 is considered to be in the ‘on’ state. Figure 2b illustrates an energy band diagram 200b showing the position of the conduction band 210 across the HEMT 100 when a negative bias voltage is applied to the gate 170. In this state, the applied voltage pulls the conduction band 210 above the fermi level 220, such that the 2DEG is no longer formed in the channel layer 130 in the region beneath the gate electrode 170. A negative bias voltage can thus be applied to the gate 170 to turn the HEMT 100 into the ‘off’ state. The HEMT 100 thus typically exhibits D-mode operation. As described above, this is not always desirable as additional circuitry is then used in applications where E-mode behaviour is preferable. It is possible to form a HEMT which exhibits E-mode behaviour by forming p-type material between the gate electrode 170 and the barrier layer 140 to form a HEMT 100’. Figure 3a and 3b are energy diagrams 300a, 300b illustrating operation of a HEMT exhibiting E-mode behaviour. Energy band diagrams 300a, 300b illustrate the position of a conduction band 310 relative to the fermi level 320 across a p-type material 380, barrier layer 140’, channel layer 130’ and buffer layer 120’ of a HEMT 100’. The p-type material 380 is positioned between the barrier layer 140’ and the gate electrode (not illustrated). Energy band diagram 300a illustrates the position of the conduction band 310 across the HEMT 100’ when no bias voltage is applied to the gate. In this state, the conduction band 310 is above the fermi level 320 and prevents the formation of a 2DEG in a region beneath the gate electrode. As such, in this state, a current does not flow between a source electrode 150’ and a drain electrode 160’ of the HEMT 100’, to operate the HEMT 100’ in an ’off’ state. Energy band diagram 300b illustrates the position of the conduction band 310 across the HEMT 100’ when a positive bias voltage is applied to the gate. In this state, the conduction band 310 is pulled below fermi level 320 in the channel layer 130’, such that a 2DEG 230 is formed in the channel layer 130’ in the region beneath the gate 170. A continuous 2DEG is thus formed in the channel layer 130’ between the source electrode 150 and drain electrode 160, and a current thus flows between the source electrode 150’ and a drain electrode 160’, to operate the HEMT 100’ in the ‘on’ state. The addition of the p-type material 380’ can thus result in a HEMT exhibiting E-mode behaviour, which can be desirable in some applications. However, working with p-type dopants in some material systems can be challenging. For example, where a HEMT is formed with lll-N semiconductor material, doping the material p-type typically involves the use of Mg. Mg is difficult to introduce into 11 l-N semiconductor material during epitaxial growth. Furthermore, etch processes for p-type lll-N materials can be difficult and risk detrimentally affecting 2DEG properties in the finally fabricated HEMT. Examples according to the present disclosure provide a HEMT that operates with E-mode behaviour without the use of p-type material. Examples according to the present disclosure provide a HEMT including a gate electrode and a gate dielectric over the barrier layer, where the gate electrode comprises a work function configured to interrupt formation of a 2DEG in the channel layer, when a zero bias voltage is applied to the gate electrode. The work function of the gate electrode manipulates the band structure of the conduction band in the channel layer such that the conduction band of the channel layer is pulled above the fermi level when no bias voltage is applied to the gate. The work function of the gate electrode thus prevents the formation of the 2DEG in the channel layer in a region beneath the gate electrode. When a positive bias voltage is applied to the gate, the HEMT is turned to the ‘on’ state where the conduction band in the channel layer is pulled below the fermi level to form a continuous 2DEG, allowing a current to flow between the source and drain terminals of the HEMT. Figure 4 illustrates a HEMT 400 according to examples of the present disclosure. HEMT 400 comprises corresponding elements to HEMT 100 described above. Said common elements are labelled with corresponding reference numerals and may operate with substantially the same functionality to that described above. HEMT 400 further comprises a gate electrode 470 comprising a material with a high work function. As described above, the work function of the gate electrode 480 is configured to interrupt formation of a 2DEG 132 in the channel layer 130 when a zero bias voltage is applied to the gate electrode 470. This state is illustrated in Figure 4, where the 2DEG 132 is interrupted in the region of the channel layer 130 beneath the gate electrode 470. The 2DEG 132 is thus interrupted and non-continuous between the source electrode 150 and the drain electrode 160. Current flow thus does not occur between the source electrode 150 and the drain electrode 160, such that the HEMT 400 is in the ‘off’ state and exhibits E-mode behaviour. The gate electrode 470 thus comprises a material with a high work function configured to cause the E-mode behaviour of the HEMT. In some examples, the gate electrode comprises a work function of about 4 eV or more. In some examples, the gate electrode comprises a work function of about 5 eV or more. In some examples, the gate electrode may comprise a work function between 4-6 eV. In some examples, the gate electrode 470 may comprise a metal. Some metals possess a high work function, which can be configured to prevent the formation of the 2DEG in the channel layer 130 beneath the gate electrode 470. For example, the gate electrode may comprise Pt, Al or W. However, in other examples, the gate electrode 470 may comprise a metal nitride, such as TiN. In some examples, the gate electrode 470 may comprise an alloy. For example, forming the gate electrode may comprise depositing a metal and doping the metal to form an alloy. The gate electrode 470 may thus comprise many materials comprising a work function configured to cause band bending in the channel layer 130 and interrupt formation of the 2DEG in the channel layer 130. HEMT 400 further comprises a gate dielectric 480 between the gate electrode 470 and the barrier layer 140. The gate dielectric 480 may comprise any suitable dielectric material, such as, SiaN4, SiO2, SiON, AI2O3 or HfO2. In some examples, the gate dielectric 480 comprises a thin material. In some examples, the gate dielectric may be thin enough to allow the work function of the gate electrode 470 to cause band bending in the channel layer 130, butthick enough to prevent gate leakage from forming a continuous 2DEG in the channel layer 130, when the HEMT 400 is in the ‘off’ state and no bias voltage is applied to the gate electrode 470. In some example, the gate dielectric 480 may comprise a thickness of 10 nm or less. In some examples, the gate dielectric 480 may comprise a thickness of 5 nm or less. In some examples, the gate dielectric 480 may comprise a thickness of 3 nm or less. In some examples, the gate dielectric 480 may comprise a thickness of between 3-2 nm. HEMT 400 further comprises barrier layer 140, which may comprise a material configured to induce a 2DEG in the channel layer 130. In some examples, the barrier layer 140 may comprise AIN, AIGaN, AllnGaN or AlInN. However, as described above, gate electrode 470 is configured to interrupt formation of the 2DEG in the channel layer 130 when a zero bias voltage is applied to the gate electrode 470. In a similar manner to the gate dielectric 480, the barrier layer 140 may be thin enough to allow the work function of the gate electrode 470 to cause band bending in the channel layer 130, but thick enough to prevent gate leakage from forming a continuous 2DEG in the channel layer, when the HEMT 400 is in the ‘off’ state and no bias voltage is applied to the gate electrode 470. In some examples, the barrier layer 140 may comprise a thickness between 1-30 nm. In some examples, the barrier layer 140 may comprise a thickness between 4-16 nm. In some examples, the barrier layer 140 may comprise a thickness of 4 - 6 nm. The materials and thicknesses of the gate electrode 470, gate dielectric 480 and barrier layer 140 can thus affect how the work function of the gate electrode 470 causes band bending in the channel layer 130 in order to prevent formation of the2DEG in the channel layer 130. Similarly, the materials and thicknesses of the gate electrode 470, gate dielectric 480 and barrier layer 140 can thus be adjusted in order to set an appropriate threshold voltage (Vt) to turn the HEMT 400 from the ‘off’ state to the ‘on’ state to form a continuous 2DEG in the channel layer 130. Combinations of gate electrode 740, gate dielectric 480 and barrier layer 140 may thus result in the HEMT 400 exhibiting E-mode behaviour. In one example, gate electrode 470 may comprise Pt with a work function of 5.65 eV, the gate dielectric 480 may comprise AI2O3 and comprise a thickness of 10 nm, the barrier layer 140 may comprise Alo.25Gao.75N and a thickness of 4-10 nm and the channel layer 130 may comprise GaN with a thickness of about 20 nm. In another example, the gate electrode 470 may comprise a metal with a work function of 5 eV, the gate dielectric 480 may comprise AI2O3 and comprise a thickness of 10 nm, the barrier layer 140 may comprise Alo.25Gao.75N with a thickness of 4-6 nm and the channel layer 130 may comprise GaN with a thickness of about 20 nm. In such examples, HEMT 400 may exhibit E-mode behaviour. In another example, the gate electrode 470 may comprise a metal with a work function of about 5.65 eV, the gate dielectric 480 may comprise AI2O3 and comprise a thickness of 10 nm, the barrier layer 140 may comprise AlxGai-xN, where 0.15 <x <0.25, with a thickness of 4-10 nm and the channel layer 130 may comprise GaN with a thickness of 15-20 nm. In such examples, HEMT 400 may exhibit E-mode behaviour. Figures 5a and 5b are energy diagrams 500a, 500b illustrating operation of the HEMT 400 exhibiting E-mode behaviour. Energy band diagrams 500a, 500b illustrate the position of a conduction band 510 relative to the fermi level 520 across gate electrode 470, gate dielectric 480, barrier layer 140, channel layer 130 and buffer layer 120 of HEMT 400. Energy band diagrams 500a, 500b further illustrate the position of the vacuum energy level 530 relative to the conduction band 510. The position of the vacuum energy level 530 relative to the conduction band 510 illustrates the work function of the gate electrode 470, gate dielectric 480, barrier layer 140, channel layer 130 and buffer layer 120 of HEMT 400. Energy band diagram 500a illustrates operation of the HEMT 400 when no bias voltage is applied to the gate electrode 470. Energy band diagram 500a shows a relatively large difference 0G between the conduction band 510 and the vacuum energy level 530 across the gate electrode 470. This large difference represents the work function ¢0 of the gate electrode 470 and is constant. The work function between the conduction band 510 and the vacuum energy level 530 is also constant for all materials of the HEMT 400. Furthermore, the vacuum energy level 530 is continuous at the interfaces between the layers of the HEMT 400. As such, with no bias voltage applied to the gate electrode 470, the large work function 0g of the gate electrode 470 pulls the conduction band 510 away from the fermi level 520 for the barrier layer 140, channel layer 130 and buffer layer 120 of HEMT 400. This results in the conduction band 510 across the channel layer 130 being pulled above the fermi level 520, such that, a 2DEG is prevented from forming in the channel layer 130 in a region beneath the gate electrode 470. Energy band diagram 500b illustrates operation of the HEMT 400 when a positive bias voltage is applied to the gate electrode 470. As illustrated, the conduction band 510 across the gate electrode 470 is greatly pulled down due to the application of the positive voltage. This movement of the conduction band 510 thus, in turn, pulls down the conduction band 510 across the gate dielectric 480, barrier layer 140, channel layer 130 and buffer layer 120. The movement of the conduction band 510 thus allows the conduction band 510 in the channel layer 130 to be pulled below the fermi level 520 to result in formation of the 2DEG 230 in a region beneath the gate electrode 470. A continuous 2DEG can thus be formed in the channel layer 130 between the source electrode 150 and the drain electrode 160 to result in current flow. Thus, the HEMT 400 is in the ‘off’ state when no bias voltage is applied to the gate electrode 470 and in the ‘on’ state when a positive bias voltage is applied to the gate electrode 470. The HEMT 400 thus exhibits E-mode behaviour. Figures 6a-c illustrate process steps in a method for forming a HEMT according to examples of the present disclosure. Figure 6a illustrates a first step 600a in which buffer layer 120, channel layer 130 and barrier layer 140 are formed on the substrate 110. In some examples, forming the buffer layer 120, channel layer 130 and barrier layer 140 on the substrate 110 may comprise epitaxially growing the buffer layer 120, channel layer 130 and barrier layer 140 on the substrate 110. Buffer layer 120, channel layer 130 and barrier layer 140 may thus comprise semiconductor material. In one example, the buffer layer 120, channel layer 130 and barrier layer 140 comprise 11 l-N semiconductor material. For example, the buffer layer 120 may comprise GaN, the channel layer 130 may comprise GaN and the barrier layer 140 may comprise AIGaN. Substrate 110 may thus comprise a material configured to permit the formation of 11 l-N semiconductor materials thereon. For example, substrate 110 may comprise Si, SiC, GaN or AIN. In other examples, buffer layer 120, channel layer 130 and barrier layer 140 may comprise alternative lll-N semiconductor materials, as described above. In other examples, the buffer layer 120, channel layer 130 and barrier layer 140 may comprise alternative lll-V semiconductor materials, such as, 11 l-As based materials. Figure 6b illustrates a second process step 600b in which dielectric material 480’ is formed on the barrier layer 140 and gate material 470’ is formed on the dielectric material 480’. In some examples, the dielectric material 480’ and the gate material 470’ may be epitaxially grown on the barrier layer 140. In one example, the gate dielectric material 480’ may comprise SiaN4 or AI2O3, which may be epitaxially grown on the barrier layer 140. In some examples, the gate material 470’ may comprise any suitable material, which may be epitaxially grown on the dielectric material 480’. In examples where the dielectric material 480’ and the gate material 470’ are epitaxially grown on the barrier layer 140, the dielectric material 480’ and the gate material 470’ may be epitaxially grown in the same reactor as the reactor used to grow the buffer layer 120, channel layer 130 and barrier layer 140. Epitaxially growing the dielectric material 480’ and the gate material 470’ in the same reactor as the buffer layer 120, channel layer 130 and barrier layer 140 may improve the surface quality between the layers and reduce the chance of defects forming at the interfaces between the layers. In particular, it is common in HEMT fabrication to form the buffer layer 120, channel layer 130 and barrier layer 140 in an epitaxial growth reactor and transfer the grown semiconductor layers to an alternative deposition machine to form the dielectric material 480’ and the gate material 470’. However, in such examples, surface defects may form on the barrier layer 140, which can detrimentally impact the affect of the high work function gate material 470’ resulting in inconsistent E-mode HEMT behaviour. In other examples, however, the dielectric material 480’ and the gate material 470’ may be deposited on to the barrier layer 140 using an alternative deposition machine to an epitaxial reactor used for forming the buffer layer 120, channel layer 130 and barrier layer 140. In such examples, process step 600b may thus be conveniently implemented into HEMT fabrication supply chains. In such examples, a protective film may thus be epitaxially grown over the barrier layer 140 and be subsequently removed prior to formation of the dielectric material 480’ and the gate material 470’. For example, the protective film may be deposited on to the barrier layer 140 in the epitaxial growth reactor for forming the buffer layer 120, channel layer 130 and barrier layer 140 to appropriately protect the surface of the barrier layer 140 from defects. In some example, the protective film may comprise SiN. The grown layers may be transferred to an alternative deposition machine where the protective film can be removed and the dielectric material 480’ and gate material 470’ may be deposited on to the barrier layer 140. In other examples, the dielectric material 480’ and gate material 470’ may be deposited on to the barrier layer 140 using a combination of epitaxial growth and alternative deposition techniques. For example, the gate dielectric material 480’ may be epitaxially grown on the barrier layer 140 and the gate material 470’ may be deposited on to the barrier layer 140 using an alternative deposition technique such as those described above. In such examples, the gate dielectric material 480’ may be epitaxially grown on the barrier layer 140 using the same reactor used to epitaxially grow the buffer layer 120, channel layer 130 and barrier layer 140. Figure 6c illustrates a third process step 600c for forming a HEMT according to examples of the present disclosure. In process step 600c, source electrode 150 and drain electrode 160 are formed on channel layer 130. For example, source electrode 150 and drain electrode 160 may be formed using etching and deposition techniques where portions of the gate material 470’, gate dielectric material 480’ and barrier layer 140 may be etched to provision areas form the deposition of source electrode 150 and drain electrode 160. Process step 600c further illustrates that gate dielectric 480 and gate electrode 470 are formed on barrier layer 140. For example, portions of the gate dielectric material 480’ and gate electrode material 470’ may be appropriately masked and etched to form the gate dielectric 480 and gate electrode 470. Process step 600c thus illustrates a step where a HEMT is formed with a high work function gate electrode 470 to exhibit E-mode behaviour. Figure 7 illustrates an example of a semiconductor wafer 790. Semiconductor wafer 790 comprises elements in common to the elements described above. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. Semiconductor wafer 790 comprises an E-mode HEMT 400 formed on substrate 110. E-mode HEMT 400 again comprise a high work function gate electrode 470, which results in the HEMT 400 exhibiting E-mode behaviour. Semiconductor wafer 790 further comprises a D-mode HEMT 700 also formed on the substrate 110. D-mode HEMT 700 comprises a buffer layer 720, channel layer 730, barrier layer 740, source electrode 750, drain electrode 760 and gate dielectric 780, which may substantially correspond in features and functionality to buffer layer 120, channel layer 130, barrier layer 140, source electrode 150, drain electrode 160 and gate dielectric 480 of E-mode HEMT 400. D-mode HEMT 700 further comprises a gate electrode 770. Gate electrode 770 may not comprise a high work function material and may thus permit the formation of a 2DEG 732 in a region in the channel layer beneath the gate electrode 770, when a zero bias voltage is applied to the gate electrode 770. A continuous 2DEG 732 is thus formed between the source electrode 750 and the drain electrode 760 resulting in current flow between the source electrode 750 and drain electrode 760 when a zero bias voltage is applied to the gate electrode 770. As such, HEMT 700 exhibits D-mode behaviour. In some examples, the first gate electrode 470 may comprise a material with a work function greater than or equal to 5 eV and the second gate electrode 770 may comprise a material with a work function less than 5 eV. Semiconductor wafer 790 further comprises dividing region 702. Dividing region 702 is a schematic illustration of a region for dividing E-Mode HEMT 400 and D-mode HEMT 700. For example, dividing region may comprise a doped semiconductor region. Semiconductor wafer 790 thus presents a semiconductor wafer where an E-mode HEMT 400 and D-mode HEMT 700 can be fabricated on a common substrate 110. For example, buffer layers 120, 720, channel layers 130, 730 and barrier layers 140, 740 can be formed from common semiconductor layers grown on the substrate 110. For example, a buffer layer, channel layer and barrier layer can be epitaxially grown on substrate 110, in a similar to that described above. Said buffer layer, channel layer and barrier layer can subsequently be fabricated into buffer layers 120, 720, channel layers 130, 730 and barrier layers 140, 740. Additionally, source electrodes 150, 750 and drain electrodes 160, 760 can be fabricated on the semiconductor wafer 790 using common fabrication techniques. In a similar manner to that described above, gate dielectric material and gate electrode material can be deposited on the semiconductor wafer 790. Gate dielectric 480 and the gate electrode 470 can be fabricated on semiconductor wafer 790. For example, portions of the semiconductor wafer 790 can be masked and etched to form the gate dielectric 480 and the gate electrode 470 in a similar manner to that described above. Additionally, portions of the semiconductor wafer 790 can be masked and etched to remove the gate dielectric material and gate electrode material from the semiconductor layers to provision an area for the formation of gate electrode 770 of D-mode HEMT 700. For example, gate electrode material may be deposited to form the gate electrode 770, for example, using atomic layer deposition (ALD) techniques. As such, the gate material of the HEMT 400 and the HEMT 700 can thus be fabricated appropriately to form a E-mode HEMT 400 and a D-mode HEMT 700 on a common semiconductor wafer 790. Such a semiconductor wafer 790 can enable the formation of advanced circuitry such as logic circuitry on the same semiconductor wafer. Figure 8 illustrates an example of a semiconductor wafer 890. Semiconductor wafer 890 comprises elements in common to the elements described above. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. Semiconductor wafer 890 comprises an E-mode HEMT 400 and a D-mode HEMT 800. D-mode HEMT 800 comprises a buffer layer 720, channel layer 730, source electrode 750, drain electrode 760, gate electrode 870 and gate dielectric 780 which may substantially correspond in features and functionality to buffer layer 120, channel layer 130, barrier layer 140, source electrode 150, drain electrode 160 and gate dielectric 480 of E-mode HEMT 400. The common elements of E-mode HEMT 400 and D-mode HEMT 800 may thus be fabricated in a corresponding manner such as using any of the techniques described above. D-mode HEMT 800 further comprises a barrier layer 840. As illustrated in Figure 8, barrier layer 840 comprises a larger thickness than the barrier layer 140 of E-mode HEMT 400. The thickness of the barrier layer 840 may thus mean that for a given gate dielectric 780 and given gate electrode 870, the HEMT 800 exhibits D-mode behaviour. For example, gate dielectric 480 and gate electrode 470 of E-mode HEMT 400 may comprise substantially corresponding materials and thicknesses to gate dielectric 780 and gate electrode 870. Furthermore, the barrier layer 140 of E-mode HEMT 400 and barrier layer 840 of D-mode HEMT 800 may comprise a corresponding material. The thinner thickness of the barrier layer 140 may be such that the work function of the gate electrode 470 can interrupt formation of the 2DEG 132 in the channel layer 130 such that HEMT 400 exhibits E-mode behaviour. However, the thicker thickness of barrier layer 840 may mean the work function of the gate electrode 870 does not interrupt formation of the 2DEG in the channel layer 730, such that the HEMT 800 exhibits D-mode behaviour. In some examples, E-mode HEMT 400 and D-mode HEMT 800 may be fabricated on substrate 110. For example, as described above, a buffer layer, channel layer and barrier layer can be epitaxially grown on substrate 110. Said buffer layer, channel layer and barrier layer can subsequently be fabricated into buffer layers 120, 720, channel layers 130, 730 and barrier layers 140, 840. In such examples, a thick barrier layer may be grown on substrate 110 corresponding to the thickness of barrier layer 840. The barrier layer material can subsequently be masked and a portion of the barrier layer material can be etched to form the barrier layer 140 with a reduced thickness. Gate dielectrics 480, 780, source electrodes 150, 750, drain electrodes 160, 760 and gate electrodes 470, 870 can subsequently be fabricated on the barrier layers 140, 840. In such examples, gate dielectrics 480, 780 and gate electrodes 470, 480 may comprise corresponding materials, which may improve wafer 890 fabrication speed and throughput, compared to using different materials for the gate dielectrics 480, 780 and gate electrodes 470, 480. Similarly, source electrodes 150, 750 and drain electrodes 160, 760 may comprise corresponding materials. Figure 9 illustrates an example of a semiconductor wafer 900. Semiconductor wafer 900 comprises elements in common to the elements described above. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. Semiconductor wafer 900 comprises a first E-mode HEMT 400, second E-mode HEMT 901 and a D-mode HEMT 902. E-mode HEMT 901 comprises corresponding features to HEMTs 700, 800 described above. E-mode HEMT 901 thus comprise an interrupted 2DEG 932. Second E-mode HEMT 901 further comprises an etch stop layer 910 between the barrier layer 740 and the gate dielectric 780. As will be described in more detail below, etch stop layer 910 may be utilized in the fabrication of the semiconductor wafer 900. In some examples, the etch stop layer 910 may be configured to result in HEMT 901 exhibiting E-mode behaviour. In some examples, however, E-mode HEMT 901 may comprise a different threshold voltage to E-mode HEMT 400. For example, gate electrode 470 and gate electrode 970 may comprise a corresponding material. The increased distance between the channel layer 730 and gate electrode 970 in HEMT 901 due to the etch stop layer 910, compared to the channel layer 130 and gate electrode 470 of E-mode HEMT 400, may therefore result in a band bending effect where the threshold voltage of E-mode HEMT 400 and E-mode HEMT 901 is different. In some examples, the etch stop layer 910 may comprise AIN, AIScN or a metal rich layer. In some examples, the etch stop layer may comprise a plurality of sub-layers comprising any combination of AIN, AIScN or a metal rich layer. D-mode HEMT 902 comprises buffer layer 920, channel layer 930, barrier layer 940, etch stop layer 911, source electrode 950, drain electrode 960 and gate dielectric 980 and gate electrode 971, which may comprise corresponding features and functionality to buffer layer 720, channel layer 730, barrier layer 740 etch stop layer 910, source electrode 750, drain electrode 760, gate electrode 970 and gate dielectric 780, respectively, of second E-mode HEMT 901. D-mode HEMT 902 further comprises a second barrier layer 990 between the etch stop layer 911 and the gate dielectric 980. Second barrier layer 990 may thus increase the distance between the gate electrode 971 and the channel layer 930 such that the HEMT 902 exhibits D-mode behaviour. For example, the gate electrode 971 may comprise a corresponding high work function metal to gate electrode 470 and gate electrode 970. The second barrier layer 990 thus increases the distance between the channel layer 930 and gate electrode 971, compared to E-mode HEMTs 400, 901, which comprise a shorter distance between their respective gate electrodes 470, 970 and channel layers 130, 730. As such, with no bias voltage applied to the gate electrode 971, a continuous 2DEG 933 forms in the channel layer 930 between source electrode 950 and drain electrode 960. In a similar manner to that described above, layers may be grown on substrate 110, which can subsequently be fabricated into the individual layers of E-mode HEMT 400, E-mode HEMT 901 and D-mode HEMT 902. For example, buffer layer material, channel layer material and first barrier layer material may be grown on substrate 110, which can be fabricated into buffer layers 120, 720, 920, channel layers 130, 730, 930 and barrier layers 140, 740, 940. Furthermore, etch stop layer material and second barrier layer material may be formed on the first barrier layer material to form etch stop layers 910, 911 and second barrier layer 990. For example, once the etch stop material layer and the second barrier material layer have been formed, portions of the second barrier layer can be etched to form the second barrier layer 990. In a similar manner, portions of the etch stop material layer can be etched to form the etch stop layers 910, 911. In this way, D-mode and E-mode HEMTs can be integrally formed on a common substrate 110. E-mode HEMT 901 thus comprises an etch stop layer 910. However, in other examples, an etch stop layer may be configured between a gate dielectric and barrier layer in a similar manner to HEMT 901 to result in the HEMT exhibiting D-mode behaviour. For example, the thickness and / or composition of etch stop layer 910 may be configured to result in a HEMT exhibiting D-mode behaviour. Semiconductor wafer 900 thus presents a semiconductor wafer comprising E-mode HEMTs 400, 901 and D-mode HEMT 902, which can be conveniently fabricated on a common wafer. Figure 10 illustrates a HEMT 1000. HEMT 1000 comprises elements in common to the elements described above. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. HEMT 1000 comprises a back barrier 125. In some examples, HEMTs can suffer from drain lag where electrons from the channel layer 130 can become trapped in defects in the buffer 120. In some examples, back barrier 125 may thus be configured to confine electrons to the channel layer 130 and prevent electrons from the channel layer 130 migrating to defects in the buffer layer 120 to reduce drain lag effects. In some examples, the back barrier 125 may comprise AIGaN. In some examples, the back barrier may comprise a thickness of about 1 nm to about 2000 nm. In some examples, the back barrier may comprise a thickness of about 50 nm to about 500 nm. Figure 11 illustrates a HEMT 1100. HEMT 1100 comprises elements in common to the elements described above. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. HEMT 1100 comprises a barrier layer 1140 and a channel layer 1130 over the barrier layer 1140. HEMT 1100 further comprises gate dielectric 480 over the channel layer 1130 and gate electrode 470 over the gate dielectric. Barrier layer 1140 is configured to induce a 2DEG 132 in the channel layer 1130, in a similar manner to that described. Thus, in some examples, the barrier layer 1140 may comprise AIGaN and the channel layer 1130 may comprise GaN, as similarly described above. Similarly, as described above, the high work function of the gate electrode 470 interrupts formation of the 2DEG 132 to result in the HEMT 1100 exhibiting E-mode behaviour. The barrier layer 1140 is below the channel layer 1130. In such examples, forming the barrier layer 1140 below the channel layer 1130 may result in the barrier 1140 acting as a back barrier confining electrons to the 2DEG and preventing the electrons from drifting into the buffer layer 120. Furthermore, forming the barrier layer 1140 below the channel layer 1130 may result in the threshold voltage Vth of the HEMT 1100 being decoupled from the carrier density of the 2DEG 132 leading to improved gate control. In some examples, the channel layer 1130 further comprises N-polar GaN material. GaN typically epitaxially forms with a Ga-polar upper surface. However, in some examples, GaN can be formed with a N-polar orientation at its upper surface. In some examples, the epitaxial growth substrate and the epitaxial growth conditions can be controlled to achieve N-polar GaN. However, in other examples, the GaN material can be epitaxially formed with a Ga-polar surface and layered transferred to result in GaN material with a N-polar surface. The GaN channel layer 1130 may thus comprise a Ga-polar surface 1132 and a N-polar surface 1134, wherein the N-polar surface 1134 is proximate to the gate dielectric 480 and the Ga-polar surface 1132 is distal from the gate dielectric 480. In such examples, the HEMT 1100 with a channel layer 1130 comprising a N-polar surface 1134 may exhibit E-mode behaviour. In one example, the gate electrode may comprise Pt with a work function of 5.65 eV, the gate dielectric 480 may comprise AI2O3 comprising a thickness of 10 nm, the channel layer 1130 may comprise GaN with a thickness of 5-15 nm and the barrier layer 1140 may comprise AI0.15-0.25Ga0.75-0.85N with a thickness of 20 nm. As illustrated in Figure 11, HEMT 1100 may not comprise a substrate or a buffer layer. In some examples, the barrier layer 1140 and the channel layer 1130 may be formed by epitaxially growing the barrier layer 1140 and the channel layer 1130 on a substrate, as similarly described above. Furthermore, a buffer layer may be epitaxially grown between the barrier layer 1140 and the substrate. In some examples, the substrate and buffer layer may be removed from the barrier layer 1140 during fabrication of the HEMT 1100. Thus, a HEMT according to examples of the present disclosure may comprise a substrate and buffer layer as described above, or alternatively, a HEMT according to examples of the present disclosure may not comprise a substrate and buffer layer Figure 12 is a band diagram simulation 1200 showing the conduction band 1210, fermi level 1220 and valence band 1230 for a HEMT. Band diagram 1200 illustrates the conduction band 1210, fermi level 1220 and valence band 1230 for a HEMT 400 according to the example of Figure 4. The HEMT comprises a gate electrode 170 comprising Pt with a work function of 5.65 eV, a gate dielectric 480 comprising AI2O3 comprising a thickness of 10 nm, a barrier layer 140 comprising Alo.25Gao.75N comprising a thickness of 4 nm, a channel layer 130 comprising GaN comprising a thickness of about 20 nm and a buffer layer 120 comprising C-doped GaN comprising a thickness of about 50 nm. Band diagram 1200 illustrates the conduction band 1210, fermi level 1220 and valence band 1230 for the above-described HEMT where a 0 V bias voltage is applied to the gate electrode 170. As illustrated, the conduction band 1210 is above the fermi level 1220. When a positive bias voltage is applied to the gate electrode 170, the conduction band 1210 is pulled below the fermi level 1220 to form a 2DEG in the channel layer 130. The HEMT thus exhibits E-mode behaviour. Figure 13 is a band diagram simulation 1300 showing the conduction band 1210, fermi level 1220 and valence band 1230 for a HEMT. Band diagram 1300 illustrates the conduction band 1210, fermi level 1220 and valence band 1230 for a HEMT 1100 according to the example of Figure 11. The HEMT comprises a gate electrode 170 comprising Pt with a work function of 5.65 eV, a gate dielectric 480 comprising AI2O3 comprising a thickness of 10 nm, a channel layer 1130 comprising GaN comprising a thickness of about 15 nm and a barrier layer 1140 comprising Alo.25Gao.75N comprising a thickness of 20 nm. Band diagram 1300 illustrates the conduction band 1210, fermi level 1220 and valence band 1230 for the above-described HEMT where a 0 V bias voltage is applied to the gate electrode 170. As illustrated, the conduction band 1210 is above the fermi level 1220. When a positive bias voltage is applied to the gate electrode 170, the conduction band 1210 is pulled below the fermi level 1220 to form a 2DEG in the channel layer 130. The HEMT thus exhibits E-mode behaviour. Figure 14 illustrates process steps in a method 1400 for forming a HEMT for E-mode operation. The method 1400 comprises, in a first step 1410, forming a channel layer and a barrier layer. The method 1400 further comprises, in a second step 1420, forming a gate dielectric. The method 1400 further comprises, in a third step, forming a gate electrode, wherein the gate electrode comprises a work function configured to interrupt formation of the 2DEG in the channel layer when a zero bias voltage is applied to the gate electrode. The present disclosure further provides an RF module comprising a HEMT according to examples of the present disclosure. In some examples the RF module may comprise one of: a switch module, a power amplifier module, a transmitter module, a receiver module and a transceiver module. The present disclosure further provides an electronic device comprising an RF module according to examples of the present disclosure. In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise a handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console or similar. In some examples the electronic device may comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, or similar. In some examples the electronic device may comprise an audio accessory device, such as headphones, earphones, wireless headphones, true wireless headphones, earbuds, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing 5 machine, or similar. It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does 10 not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope. 15

Claims

1. A high electron mobility transistor, HEMT, for enhancement mode operation; the HEMT comprising:a channel layer;a barrier layer configured to induce a two-dimensional electron gas, 2DEG, in the channel layer;a gate dielectric; anda gate electrode;wherein the gate electrode comprises a work function configured to interrupt formation of the 2DEG in the channel layer, when a zero bias voltage is applied to the gate electrode.

2. The HEMT according to claim 1 wherein the gate electrode comprises a metal.

3. The HEMT according to claim 1 or 2 wherein the gate electrode comprises an alloy.

4. The HEMT according to any preceding claim wherein the gate electrode comprises a metal nitride.

5. The HEMT according to any preceding claim wherein the gate electrode comprises a work function greater than 5 eV.

6. The HEMT according to any preceding claim wherein the barrier layer comprises a thickness between 1-30 nm.

7. The HEMT according to any preceding claim wherein:the channel layer is over the barrier layer;the gate dielectric is over the channel layer; andthe gate electrode is over the gate dielectric.

8. The HEMT according to any preceding claim wherein the gate dielectric comprises a thickness of 10 nm or less.

9. The HEMT according to any preceding claim further comprising an etch stop layer between the gate electrode and the gate dielectric.

10. The HEMT according to any preceding claim wherein the channel layer and the barrier layer comprise 11 l-N semiconductor material.

11. A semiconductor wafer comprising the HEMT according to any preceding claim.

12. The semiconductor wafer according to claim 11 further comprising a HEMT for depletion mode operation.

13. A radio frequency, RF, module comprising the HEMT according to any of claims 1-10.

14. An electronic device comprising the RF module according to claim 13.

15. A method for forming a HEMT, the method comprising:forming a channel layer and a barrier layer, wherein the barrier layer is configured to induce a two-dimensional electron gas, 2DEG, in the channel layer;forming a gate dielectric; andforming a gate electrode, wherein the gate electrode comprises a work function configured to interrupt formation of the 2DEG in the channel layer when a zero bias voltage is applied to the gate electrode.

16. The method according to claim 15 wherein forming the channel layer; forming the barrier layer; forming the gate dielectric; and forming the gate electrode comprises:epitaxially growing the channel layer;epitaxially growing the barrier layer;epitaxially growing gate dielectric material; andepitaxially growing gate electrode material.

17. The method according to claim 16 wherein the channel layer, the barrier layer, the gate dielectric material and the gate electrode material are grown in the same reactor.

18. The method according to claim 15 further comprising forming a protective film over the channel layer and the barrier layer; and removing the protective film prior to forming the gate dielectric.

19. The method according to claim 18 wherein forming the protective film comprises epitaxially growing the protective film over the channel layer and the barrier layer.

20. The method according to claim 19 wherein forming the channel layer; forming the barrier layer; and epitaxially growing the protective film comprises epitaxially growing the channel layer, barrier layer and protective film in the same reactor.

21. The method according to any of claims 15-20 wherein forming the gate electrode comprises depositing a metal and doping the metal to form an alloy.

22. The method according to any of claims 15-21 further comprising forming an etch stop layer between the barrier layer and the gate dielectric material; and forming a second barrier layer over the etch stop layer.

23. The method according to claim 22 further comprising:etching the second barrier layer;etching the etch stop layer; andforming the gate dielectric over the barrier layer.

24. A method of forming a plurality of HEMTs comprising forming the HEMT according to any of claims 15-23.

25. The method according to claim 24, when dependent on claim 23, wherein forming a second HEMT for depletion mode operation comprises:etching the second barrier layer; andforming the gate dielectric over the etch stop layer.27

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