Electronic apparatus and random number generator

Abstract

An analogue-to-digital converter (ADC) comprises one or more voltage comparators 4a-g that receive an input signal voltage 12 comprising a randomised distribution of voltage values. The comparators a

Description

Field The present invention is in the field of electronic apparatus using one or more voltage comparators, in particular, but not exclusively, relating to quantum random number generators using an analogue-to-digital converter. Background A Random Number Generator (RNG) is a type of hardware random number generator that outputs random numbers. A Quantum RNG (QRNG) outputs random numbers utilising quantum phenomena. Several previous examples of QRNG's exist including those using vacuum fluctuations and Amplified Spontaneous Emission noise (ASE). An example of random numbers generated using phase fluctuations is provided in 'Generation of random numbers by measuring phase fluctuations from a laser diode with a silicon-on-insulator chip', by Francesco Raffaelli et al., Optics Express Vol. 26, Issue 16, pp. 19730-19741 (2018). One example of an existing prior art QRNG is shown in the system P2 of figure la. In this figure, the thicker black arrow-headed lines show optical signals whilst the thinner arrow-headed lines show electronic signals. A laser P4 outputs continuous wave light P6 towards a 50 / 50 beam splitter P8. The beam splitter P8 routes 50% of the intensity of the light P6 towards a first photodetector PlOa and 50% of the light towards a second photodetector PlOb. Each photodetector PlOa / b converts the optical radiation P6 to a continuous analogue electrical current P12 wherein photodiode PlOa outputs current CA and photodiode PlOb outputs current CB. A difference of the currents (CA-CB) is made at P14. The difference signal between CA and CB is then input into a transimpedance amplifier P16 that converts the difference-current signal to a voltage signal that is, in turn, input into an Analogue-to-Digital Converter (ADC) P18 that samples the analogue signal at a clocked rate and allocates each sampled voltage to an output voltage with a particular voltage range. The system P2 uses a balanced detector system. The output of the balanced detector is essentially quantum vacuum fluctuations given that you are taking the electrical signal arising from 50% of the total optical signal detector signal away from the other electrical signal associated with the remaining 50% of the total optical signal. Thus, the result is random about an average voltage of 0V. The output of P16 is a distribution of the sampled analogue voltage signals vs voltage as shown in figure lb wherein the 'counts' represent each sample of the analogue voltage signal. A similar existing RNG is described in: 'A homodyne detector integrated onto a photonic chip for measuring quantum states and generating random numbers' by Francesco Raffaelli et al 2018 Quantum Sci. Technol. 3 025003 DOI 10.1088 / 2058-9565 / aaa38f. The output P20 of amplifier P16 is a Gaussian distribution P22 centred about an average voltage of zero volts. The ADC P18 in this example is a 2-bit system. The ADC creates a number of voltage 'bins' equal to 2N , where N is the number of bits for the system. Thus, in this prior art example, the ADC splits the distribution into four equal-width voltage bins labelled 00, 01,10 and 11 respectively. The bins are defined by voltage thresholds P24a-d and the zero-voltage line. Each bin represents a different number or bit. Hence if a set of balanced detector counts yielded a negative voltage in the bin

[00] then this output be output as a different number, hence bit, than a further set of balanced detector counts yielded a negative voltage in the bin

[01] . The randomness of the vacuum fluctuations thus produces a string of random bits taken from 00, 01,10,11. The width dV of each bin in figure lb is the same. As shown in figure lb, the number of counts in the bins

[01] and

[10] far exceed that of the outermost bins [00, 11], A random voltage signal generated just using the ADC P18 would not be optimally random because of the bias of counts to the voltage bins 01,10 provided by the Gaussian distribution P22. The output of the ADC P18 therefore has an unsuitable level of randomness for many applications. Previous attempts to solve this problem include that of figure lc. For figure lc, a computer (not shown) receives the output of the ADC P18 of figure la. The computer post-processes the output of the ADC P18 and re-balances the counts such that instead of each voltage bin being equal in voltage width (dV), the area under the curve for each bin dA is the same. Doing this means that the total number of counts per bin is equalised between the four output bits 00, 01,10,11, hence providing a greater degree of randomness of the four output bits. The computer may achieve this by effectively moving the middle two voltage bin defining thresholds P24b and P24c towards the zero-volt line. Issues arise in implementing the prior art system of figure lc that uses a computer to post-process the ADC signal. One issue is the extra computer or computer module required to do this. Another is the susceptibility of the prior art system of an attack directed between the ADC P18 and the computer. For systems, such as cryptographic communication systems, that use random numbers, this presents a security issue. An ADC used in the above prior art uses voltage comparators. Voltage comparators are devices used in a range of different applications. Previous voltage comparators compare two voltages and output a digital signal indicating which is larger. Standard voltage comparators use two analogue input terminals V{+} and V{-} and one binary digital output. A window comparator typically has a pair of voltage comparators. The output of a window comparator indicates whether the measured signal is within the voltage range bounded by two different thresholds (an "upper" threshold and a "lower" threshold). Previous window comparators have three voltage windows defined by voltage boundaries wherein two of the windows have at least one voltage boundary defined by the inherent operating range of the device. This presents issues for flexibility of defining window width. Another example of an ADC is a logarithmic ADC wherein the voltage boundaries of each voltage 'bin', hence the voltage range, are defined on a predefined logarithmic relationship. Again, this presents issues for flexibility of defining window width. One example of an ADC using voltage comparators is shown in figure 2. The ADC P30 of figure 2 uses a plurality of voltage comparators P32 and a priority encoder P34. The priority encoder in this example is an 8-line to 3-line priority encoder. An analogue input signal Vin is input into each of the comparators P32 as the '+' (non-inverting) voltage input. A reference voltage VREF is input into the (inverting) voltage input of the top comparator P32. The voltage VREF is then sequentially divided down by a plurality of serially connected resistors of equal resistance 'R' before the VREF voltage line connects to ground. At each voltage reduction (after each resistor) the reduced voltage is input into the next comparator P32. The ADC shown in figure 2 therefore has voltage bin widths of the same magnitude. Again, this presents issues for flexibility of defining window width. Summary In a first aspect there is presented a random number generator, RNG, comprising an Analogue to Digital Converter, ADC, the ADC comprising one or more voltage comparators and configured to: i) receive a plurality of input signal voltages; the plurality of input signal voltages comprising a randomised distribution of voltage values; ii) determine a voltage grouping for each input signal voltage using the one or more voltage comparators; the determined voltage grouping comprises a voltage range comprising the voltage of input signal voltage; the magnitude of the voltage range of at least one voltage grouping is different to the magnitude of the voltage range of at least another of the voltage groupings; iii) generate an output voltage for each of the plurality of input signal voltages based on the respectively determined voltage grouping, the output voltage for generating random numbers. The RNG of the first aspect may be adapted according to any teaching herein, including but not limited to any one or more of the following options. Optionally, the voltage groupings are predefined. Optionally the voltage groupings are predefined by the RNG. Optionally the voltage groupings are predefined by the ADC. Optionally, at least one of the voltage groupings is determined for a subset of the plurality of input signal voltages. Optionally, each voltage range is different to the voltage range of the other voltage groupings. Optionally, each voltage range covers a different set of voltages than the other voltage ranges of the other voltage groupings. Optionally, the voltage ranges are non-overlapping. Optionally, each voltage grouping comprises a voltage range that borders at least one other voltage range of a different voltage grouping. Optionally, the at least one voltage grouping comprises a first voltage grouping determined for a first subset of the plurality of input signal voltages; a second voltage grouping is determined for a further subset of the plurality of input signal voltages; the first voltage grouping comprises a different voltage range than the second voltage grouping. Optionally, the ADC comprises a Flash ADC. Optionally, the RNG comprises a plurality of voltage comparators. Optionally, each of the plurality of voltage comparators comprises a first and a second voltage signal input. Optionally, the plurality of input signal voltages are input into the first or second voltage signal inputs of the plurality of voltage comparators. Optionally, the first voltage signal input comprises a non-inverting input; and, the second voltage signal input comprises an inverting input. Optionally, the plurality of voltage comparators are electrically connected in series with respect to an electrical input carrying the plurality of input signal voltages. Optionally, the plurality of input signal voltages are input into a common one of: a) an non-inverting input; b) an inverting input, of each of the voltage comparators electrically connected in series. Optionally, the plurality of input signal voltages are input into the ADC via a first ADC electrical input (Vin, 12). Optionally, the plurality of voltage comparators are electrically connected in series between a second ADC electrical input (VREF, 7) and an end electrical terminal (10), the second ADC electrical input being different to the first ADC electrical input. Optionally, the second ADC electrical input (VREF, 7) is for inputting a direct current, DC, voltage. Optionally, one of the first or second voltage comparator inputs, for each voltage comparator, is electrically connected to the second ADC electrical input. Optionally, the ADC comprises a plurality of electrically resistive elements electrically connected in series between the second ADC electrical input and the end electrical terminal (10). Optionally the electrically resistive elements comprise any of variable potentiometers; resistors. Optionally, the ADC comprises: a) a first electrical connection, between the second ADC electrical input (VREF, 7) and a first of the electrically resistive elements; b) a second electrical connection, between the first electrical connection and a second of the electrically resistive elements; c) a third electrical connection, between the second electrical connection and the end electrical terminal (10); each of the first, second and third electrical connections electrically connecting to a respective different voltage comparator. Optionally, the potential difference between the first and second electrical connections is different to the potential difference between the second and third electrical connections. Optionally a resistance value of the first electrically resistive element is different to a resistance value of the second resistive element. Optionally, second resistive element is smaller than the first resistive element. Optionally, a third of the resistive elements is electrically connected between the second resistive element and the end electrical terminal (10), the third resistive element comprising a resistance greater than the second resistive element. Optionally, the plurality of input signal voltages are input into the first or second voltage signal inputs of the plurality of voltage comparators. Optionally, each of the voltage comparators are electrically connected to an electrical power supply comprising a first terminal voltage and a second terminal voltage; each of the voltage comparators being supplied with a common first terminal voltage and a common second terminal voltage. Optionally, the RNG comprises an encoder comprising a plurality of inputs; each of the voltage comparators comprises an output for outputting an output signal voltage; each encoder input for receiving at least one voltage signal associated with an output signal voltage from at least one voltage comparator. Optionally, the RNG comprises a priority encoder comprising a plurality of inputs, each of the voltage comparators comprises an output for outputting a first output signal voltage; each voltage comparator output is electrically connected to a respective different priority encoder input. Optionally, at least one, or one, of the plurality encoder inputs is connected to an electrical end terminal. Optionally the said electrical end terminal is an electrical ground. Optionally, the priority encoder comprises a plurality of second outputs, each for outputting a voltage signal; the voltage signals output from the plurality of second outputs being for defining a random number. Optionally, the ADC comprises: a Successive Approximation Register, SAR; and, a Digital to Analogue Converter, DAC, wherein: an electrical output from one of the voltage comparators electrically connects to an input of the SAR; a plurality of electrical outputs from the SAR are electrical connected to an input of the DAC, an electrical output of the DAC is electrically connected to an input of the said voltage comparator. OptionaIly, the SAR is configured to output from each of its electrical outputs: a first voltage associated with a logical high; a second voltage for a logical low. Optionally, the DAC is configured to: generate: a first non-zero voltage upon the output of a first of the SAR electrical outputs comprising a logical high; added to at least, a second non-zero voltage upon the output of a second of the SAR electrical outputs comprising a logical high. Optionally, the DAC is configured to output a summed voltage from its electrical output, wherein the summed voltage comprises the first nonzero voltage and second non-zero voltage. Optionally, the first non-zero voltage is larger than, and a non-integer multiple of, the second nonzero voltage. Optionally, the DAC is configured to change at least one of the first or second non-zero voltages to a different non-zero voltage that is associated with a respective logical high output from the SAR. Optionally, the ADC comprises a processor for: determining a new voltage value for use by the DAC; outputting a control signal to the DAC to change at least one of the first or second non-zero voltage values. Optionally, the random number generator may further comprise an electromagnetic, EM, system; the EM system comprising one or more photodetectors for receiving EM radiation and outputting electrical signals; the input voltage signals received by the ADC based on the output electrical signals. Optionally, the random number generator may be configured such that the EM system further comprises an EM source. Associated with the second aspect is a method. The method is for generating an output voltage using a random number generator, RNG. The RNG comprises an Analogue to Digital Converter, ADC, the ADC comprises one or more voltage comparators. The method comprising: i) receiving, with the ADC a plurality of input signal voltages; the plurality of input signal voltages comprising a randomised distribution of voltage values; ii) determining, using the ADC, a voltage grouping for each input signal voltage using the one or more voltage comparators; the determined voltage grouping comprises a voltage range comprising the voltage of input signal voltage; the magnitude of the voltage range of at least one voltage grouping is different to the magnitude of the voltage range of at least another of the voltage groupings; iii) generating, using the ADC, an output voltage for each of the plurality of input signal voltages based on the respectively determined voltage grouping, the output voltage for generating random numbers. The method of the first aspect may be adapted according to any teaching herein, including but not limited to any one or more of the options presented above for the RNG of the first aspect. In a second aspect there is presented an electronic apparatus comprising one or more voltage comparators; the electronic apparatus configured to: i) receive a plurality of input signal voltages; and, ii) determine a voltage grouping, from a plurality of voltage groupings, for each input signal voltage using the one or more voltage comparators; the determined voltage grouping comprises a voltage range comprising the voltage of the input signal voltage; the voltage range of at least a first of the plurality of voltage groupings: a) comprises a different voltage magnitude to the voltage magnitude of at least another of the voltage groupings; b) is determined by an input voltage to at least one of the comparators; the said input voltage determined based on target proportion of the input signal voltages for the respective voltage grouping; iii) output a voltage signal based on the determined voltage groupings. The electronic apparatus of the second aspect may be adapted according to any teaching herein, including but not limited to any one or more of the following options. Optionally, the electronic apparatus may be an Analogue to Digital Converter (ADC). The electronic apparatus may be integrated into a single device or may be multiple separate devices electrically linked with one or more electrical wires or other electrical connection. Generally, unless otherwise stated, operational connections between different components of the electrical apparatus are provided by physical connections of an electrical current carrying material, for example a conductor or semiconductor. Non-limiting examples may be electrical wires or electrical tracks. Optionally, any of the voltage comparators may compare one analogue voltage level with another analogue voltage level, or some preset reference voltage, and produce an output signal based on this voltage comparison. Optionally, any of the voltage comparators may comprise two voltage signal input ports; an output port; a positive electrical supply rail +Vcc; a negative electrical supply rail -Vcc. Optionally the input signal voltages are input into the one or more comparators. In some examples the input signal voltage may be modified before being input into a comparator. Optionally, the electronic apparatus may be configured such that at least one of the one or more voltage inputs into the voltage comparator is a feedback voltage; the feedback voltage associated with a previous output voltage of the one or more comparators. Optionally, the voltage range for at least two voltage grouping is defined by a first voltage threshold and a second voltage threshold; each of the first and second voltage thresholds being determined by one or more voltage inputs into at least one of the voltage comparators; each voltage range being different to the voltage range of the other voltage groupings; Optionally, the system may output a voltage signal associated with at least one of the input signal voltages wherein the output voltage signal is based on the determined voltage groupings. Optionally, at least one voltage grouping is associated with a different output voltage signal than an output voltage signal associated with another voltage grouping. Optionally, the output voltage signal comprises a plurality of output voltage signals wherein each output voltage signal is associated with a different input signal voltage. Optionally, each voltage grouping is associated with a different output voltage signal to at least one of the other output voltage signals associated voltage group. Associated with the second aspect, there is presented a method. The method is for outputting a voltage signal from an electronic apparatus comprising one or more voltage comparators; the method comprising: i) receiving, by the electronic apparatus, a plurality of input signal voltages; and, ii) determining, using the electronic apparatus, a voltage grouping, from a plurality of voltage groupings, for each input signal voltage using the one or more voltage comparators; the determined voltage grouping comprises a voltage range comprising the voltage of the input signal voltage; the voltage range of at least a first of the plurality of voltage groupings: a) comprises a different voltage magnitude to the voltage magnitude of at least another of the voltage groupings; b) is determined by an input voltage to at least one of the comparators; the said input voltage determined based on target proportion of the input signal voltages for the respective voltage grouping; iii) outputting, using the electronic apparatus, the voltage signal based on the determined voltage groupings. The method of the second aspect may be adapted according to any teaching herein, including but not limited to any one or more of the options presented above relating to the electronic apparatus. In a third aspect there is presented an electronic apparatus comprising one or more voltage comparators; the electronic apparatus configured to: i) receive a plurality of input signal voltages; and, ii) determine a voltage grouping for each input signal voltage using the one or more voltage comparators; the determined voltage grouping comprises a voltage range comprising the voltage of the input signal voltage; the magnitude of the voltage range of at least one voltage grouping is different to the magnitude of the voltage range of at least another of the voltage groupings; at least one voltage input into the voltage comparator is a feedback voltage; the feedback voltage associated with a previous output voltage of the one or more comparators; iii) output a voltage signal based on the determined voltage groupings. The electronic apparatus of the third aspect may be adapted according to any teaching herein, including but not limited to any one or more of the following options. The options listed for the second aspect may also be used for the third aspect. Optionally, the electronic apparatus may be configured such that each voltage range being different to the voltage range of the other voltage groupings. Associated with the third aspect is a method. The method is for outputting a voltage signal using an electronic apparatus comprising one or more voltage comparators. The method comprising: i) receiving, using the electronic apparatus, a plurality of input signal voltages; and, ii) determining, using the electronic apparatus, a voltage grouping for each input signal voltage using the one or more voltage comparators; the determined voltage grouping comprises a voltage range comprising the voltage of the input signal voltage; the magnitude of the voltage range of at least one voltage grouping is different to the magnitude of the voltage range of at least another of the voltage groupings; at least one voltage input into the voltage comparator is a feedback voltage; the feedback voltage associated with a previous output voltage of the one or more comparators; iii) outputting, using the electronic apparatus, a voltage signal based on the determined voltage groupings. The method of the third aspect may be adapted according to any teaching herein, including but not limited to any one or more of the options for the electronic apparatus of the third aspect. Brief description of the drawings Embodiments of the present invention will now be described in detail with reference to the accompanying drawings, in which: Figure la shows an example of a prior art system for use in generating random numbers; Figure lb shows an example of an output of figure lb; Figure lc shows an example of an output of a prior art system that uses a computer to rebalance the output of figure la; Figure 2 shows a prior art example of an ADC; Figure 3a shows an example of an electronic apparatus; Figure 3b shows an example of an electronic apparatus similar to figure 3a but with another resistor; Figure 4a shows another example of an electronic apparatus; Figure 4b shows an example of an alternative set of components for inputting voltage signals into an encoder; Figure 4c shows an example of comparator output voltages compared to Vin; Figure 5 shows an example of a QRNG; Figure 6 shows an example of a subsystem for producing a Vin signal; Figure 7 shows an example of another ADC; Figure 8 shows an example of DAC apparatus for use with the ADC in figure 7. Figure 9 shows an examples of equi-spaced voltage bins against a normal distribution; Figures lOa-lOc show a CDF calculated from figure 9 that gives rise to unequal probability distribution bins; Figures lla-llc show the CDF of figure 10b used to generate unequal voltage bin widths; Figures 12 shows another example of DAC apparatus for use with the ADC in figure 7. Detailed description There is presented electronic apparatus, RNGs and associated methods. In addition, as used herein, the wording "and / or" is intended to represent an inclusive-or. That is, "X and / or Y" is intended to mean X or Y or both, for example. As a further example, "X, Y, and / or Z" is intended to mean X or Y or Z or any combination thereof. The terms "including," "comprising" and variations thereof mean "including but not limited to," unless expressly specified otherwise. A listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. The terms "a," "an" and "the" mean "one or more," unless expressly specified otherwise. It should be noted that terms of degree such as "substantially", "about" and "approximately" as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. These terms of degree may also be construed as including a deviation of the modified term if this deviation would not negate the meaning of the term it modifies. It should also be noted that the terms "coupled" or "coupling" as used herein can have several different meanings depending in the context in which these terms are used. For example, the terms coupled or coupling may be used to indicate that an element or device can electrically, optically, or wirelessly send data to another element or device as well as receive data from another element or device. Furthermore, any recitation of numerical ranges by endpoints herein includes all numbers and fractions subsumed within that range (e.g. 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.90, 4, and 5). It is also to be understood that all numbers and fractions thereof are presumed to be modified by the term "about" which means a variation of up to a certain amount of the number to which reference is being made if the end result is not significantly changed. Further, although method steps may be described (in the disclosure and / or in the claims) in a sequential order, such methods may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of methods described herein may be performed in any order that is practical. Further, some steps may be performed simultaneously. Examples of electronic apparatus and RNGs are presented underneath wherein it is to be understood that each example may be adapted according to other teachings herein that are not necessarily specified for the respective example. In particular, items, configurations or steps may be added, replaced or removed. Furthermore, examples may be adapted to include general optional features described herein including, but not limited to, those listed in the summary. Furthermore, any general examples, herein, of the electronic apparatus, RNGs and associated methods may be adapted to utilise items, configurations or steps from any of the examples. In particular, any example described herein may be adapted to use any of or more of, but not limited to, the following from any of the other examples herein: types and numbers of electronic component; operating ranges and / or values of components; values of properties of components such as resistance; operating principles of components; component connection configurations and connection types; uses of apparatus or devices; further connectable components such as optical or opto-electronic components or other electronic components. For all examples described herein, it is to be assumed that where components are electrically connected to another, and / or output / input electronic signals, they do so via an electrical current carrying medium such as a wire or electrical track that physically connects the said component(s). The current carrying medium may comprise a conductor such as a metal. Figure 3a shows an example of an electronic apparatus 2. The apparatus 2 may form at least part of an ADC and optionally a random number generator such as but not limited to a QRNG. The ADC may comprise a flash-ADC configuration. The electronic apparatus 2, in this and other examples, may be used for purposes other than generation of random numbers from an analogue input signal. For example, the electronic apparatus may be used for an input signal with a pre-defined, non-random, set of voltage values. The electronic apparatus 2 in this example comprises seven voltage comparators 4a-g and a priority encoder 6. Any number of comparators may be used, preferably 2N-1 comparators wherein N is the number of digital bits required to be output be the electronic apparatus 2. Each voltage comparator 4a-g comprises two input ports for receiving voltage signals. One is the non-inverting input'+', the other is the inverting inputEach voltage comparator 4a-4g comprises an output port for outputting a digital voltage that is, in turn input into a different input port of the priority encoder 6. Each voltage comparator 4a-g comprises a positive electrical supply rail +Vcc; a negative electrical supply rail -Vcc, although these are not shown in the figure. The apparatus further comprises seven serially connected resistors 8a-8g wherein the series of resistors 8a-8g are connected between a reference input voltage signal VREF (input to the apparatus 2 at input port 7), and an electrical ground 10. The electrical connection between the VREF input port 7, through resistors 8a-8g, to ground 10 is referred to as the VREF-line. The values of the resistors are as follows with respect to a nominal resistance 'R': 8a=0.48R; 8b=0.36R; 8c=0.32R; 8d=0.32R; 8e=0.36R; 8f=0.48R; 8g=R. The numbers of resistors and their values are for example purposes only and may be varied, in particular a plurality of resistors may be used, for example three or more, between three and (any one of) 4, 5, 6, 7, 8, 9,10, 11,12,13,14,15,16,17,18,19, 20 resistors. At least two of the resistors have a different resistance. Optionally, the value of resistance of different resistors along the VREF line from input port 7 to ground 10, may vary. Any one or more of the resistors may be: a potentiometer, such as a digital potentiometer; or any other electronic device or system that can vary the voltage reference input into a comparator. This variation of resistance may optionally include any one or more of the following optional configurations described underneath. At least a first resistor may have first resistance value. At least a second resistor may have a second resistance value lower than the first resistance value. At least a third resistor may have a third resistance value higher than the second resistance value. The first, second and third resistors are different resistors. The first and third resistors may comprise the same resistance value or a different resistance value. One or more further resistors may be used along the VREF line that may comprise the same resistance or a different resistance to any of the first, second or third resistance values. The resistance value of resistors, sequentially from input port 7 to ground 10, may: either reduce or remain constant from the first resistor to the second resistor; either increase or remain constant from the second resistor to the third resistor. The second resistor may comprise the lowest resistance of the resistors. One or more further resistors may comprise the second resistance and be adjacently connected to the second resistor. The resistance values of the resistors may sequentially decrease in a step-wise fashion from the first resistor to the second resistor. The resistance values of the resistors may sequentially increase in a step-wise fashion from the second resistor (or a further resistor comprising the second resistance) to the third resistor. The resistors comprising the second resistance may be bunched into an adjacently connected chain along the VREF line. Resistors comprising the second resistance may have the lowest resistance of all the resistors along the VREF line. The chain of resistors having the second resistance may be adjacently connected, at each end of the chain, to other resistors having a higher resistance. The resistance values of the resistors at least including the first, second and third resistors may form a symmetrical distribution about: a) the second resistor; or b) about a connection along the VREF line between two resistors having the second resistance. The distribution of resistor values along the VREF line may be associated with, and / or derived from, an input voltage distribution 'Vin', as described below and elsewhere herein. The above optional resistor configurations may be used with other examples herein. Optionally, the components that define the reference voltages for each comparator 4a-4g in figure 3a may be different to resistors. For example, another example of the electronic apparatus 20 is shown in figure 4. Figure 4 is similar to figure 3a with like references showing like components. In this example the apparatus 20 comprises an Digital to Analogue Converter (DAC), for example a high resolution, low speed DAC. The DAC outputs voltages V0-V6 along respective electrical lines 22a-22g, into the '-' input terminal of the respective comparators 4a-4g. Similar to figure 3a, each comparator 4a / g has an electrical energy supply rail VDD / VSS and has the same voltage signal VIN input to the '+' input port of the respective comparator. Each comparator 4a-g outputs a voltage signal that is input into a digital encoder 24 that in turn outputs a binary signal upon electrical outputs 16a-c. The example of figure 4 may be adapted and may be used to adapt other examples, as prescribed elsewhere herein. Turning back to the example in figure 3a. An electrical connection is made between the VREF line to the '-' input port of the first comparator 4a. This connection is made at a position along the VREF line between the input port 7 and the resistor 8a. The voltage input into the comparator 4a from the VREF line is therefore the input voltage input into input port 7. The voltage input into the comparator 4a is the same as the voltage input to resistor 8a. An electrical connection is made between the VREF line to the input port of the second comparator 4b. This connection is made at a position along the VREF line between the resistor 8a and resistor 8b. The voltage input into the comparator 4b is the same as the voltage input to resistor 8b. An electrical connection is made between the VREF line to the input port of the third comparator 4c. This connection is made at a position along the VREF line between the resistor 8b and resistor 8c. The voltage input into the comparator 4c is the same as the voltage input to resistor 8c. An electrical connection is made between the VREF line to the input port of the fourth comparator 4d. This connection is made at a position along the VREF line between the resistor 8c and resistor 8d. The voltage input into the comparator 4d is the same as the voltage input to resistor 8d. An electrical connection is made between the VREF line to the input port of the fifth comparator 4e. This connection is made at a position along the VREF line between the resistor 8d and resistor 8e. The voltage input into the comparator 4e is the same as the voltage input to resistor 8e. An electrical connection is made between the VREF line to the input port of the sixth comparator 4f. This connection is made at a position along the VREF line between the resistor 8e and resistor 8f. The voltage input into the comparator 4f is the same as the voltage input to resistor 8f. An electrical connection is made between the VREF line to the input port of the seventh comparator 4g. This connection is made at a position along the VREF line between the resistor 8f and resistor 8g. The voltage input into the comparator 4g is the same as the voltage input to resistor 8g. The VREF line between the input port 7 and ground 10 may be equivalent to a plurality of voltage dividers in series wherein the voltage-divided output is used as an input into one of the comparators 4a-g. The voltage output by the VREF line that is input into each comparator 4a-g may be defined by the following voltage divider equation: ^REFout = V REFin ^remainder *Ri+R remainder' [Equ. 1] wherein VREFin is the input voltage into the divider; VREFout is the output voltage of the divider that is used as an input to a comparator; Ri is the input resistance that VREFm is applied to prior to VREFout; Rremainder is the combined resistance of the rest of the VREF line after VREFout. For the example in figure 3a, assuming the input VREF at port 7 is 1 volt, the voltage input values to the inverting inputare presented in table 1. Table 1. Comparator Inverting input voltage values. Comparator Voltage at inverting input 4a 1 4b 0.855421687 4c 0.746987952 4d 0.65060241 4e 0.554216867 4f 0.445783133 4g 0.301204819 A further voltage signal input port 12 is used to receive a set of one or more input voltages signals 'Vin'. The voltage signal may be a continuous analogue signal or a set of time digitised voltage signals. For purposes of this discussion, it is assumed that the Vin port 12 receive an analogue voltage signal. The voltage signal, over time, may comprise a distribution of voltages. The distribution may be unknown or known (predetermined). The distribution may centre about a central voltage value such as, but not limited to, zero volts or another DC offset voltage. The distribution may be a normal (Gaussian) distribution along x (wherein x is voltage in this implementation) as depicted in equation 2 wherein ji is the mean or expectation of the distribution (and also its median and mode), while the parameter o (termed 'sigma') is its standard deviation, however other distributions are possible. f(x) = —=e 2l a ) aV2n [Equ. 2] The distribution may be substantially symmetric about the central voltage distribution line. In other words, over a particular time period the majority (or all) of the voltages of the analogue voltage signal may take a value between the lowest and highest voltages of the distribution wherein the amount of time the analogue voltage signal comprises particular voltages is determined by the distribution. The voltage range of Vin is preferably at least partially overlapping with the voltage range of VREF. The voltage range of VREF being the voltages between and including: a) the voltage at the input port 7; and, b) the voltage at opposing terminal port 10 at the end of the VREF line. The voltage range of Vin may be the same as, larger than, or smaller in magnitude than the voltage range of VREF. The voltage range of Vin may include one or more voltage values that are greater than the volage value of VREF at the input port 7. The term 'greater than' here meaning having a more positive voltage value. The voltage range of Vin may include one or more voltage values that are less than the volage value of VREF at the opposing electrical terminal port 10 (which in figure 3a is zero volts, but may be another positive or negative voltage). The term 'less than' here meaning having a more negative voltage value. The voltage range of Vin may include one or more voltage values that are greater than the input voltage into any of the comparators 4a-g from the VREF line. The voltage range of Vin may include one or more voltage values that are less than the input voltage into any of the comparators 4a-g from the VREF line. Preferably, the voltage range of Vin may include one or more voltage values that are greater than the highest input voltage, from the VREF line, that is input into the comparators 4a-g, which for figure 3a would be the voltage input into the inverting input of comparator 4a. Preferably, the voltage range of Vin may include one or more voltage values that are lower than the lowest input voltage, from the VREF line, that is input into the comparators 4a-g, which for figure 3a would be the voltage input into the inverting input of comparator 4g. In the alternative, the voltage range of Vin may be within most of the voltage range of the VREF line, for example: over 80%, over 90%, over 95%, over 99% of the Vin voltage distribution is within the VREF voltage range. In figure 3a the opposing terminal voltage port of the VREF line is 0 volts as it is electrically coupled to ground, however other end terminal voltages may be used such as but not limited to, a +ve voltage or a -ve voltage of any magnitude, such as but not limited to + / -IV, + / -2V, + / -3V, + / -4V, + / -5V, + / -6V, + / -7V, + / -8V, + / -9V, + / -10V. The analogue signal voltage Vin may be derived from another apparatus, device or set of one or more components. Examples of such further apparatus are described and shown elsewhere herein, for example with figure 5a. The analogue voltage output by such further apparatus may be used as the input into port 12 of this example (or any other example). Alternatively, one or more devices may be used to convert the voltage output into a signal suitable for input into port 12. Examples may include a bias-tee or clamping circuit, or other electronic circuitry to adjust the voltage range of the analogue signal prior to input into port 12, for example increasing or decreasing the voltage or the upper and / or lower limits of the range. The adjustment of the voltage range may be so that the voltage range of Vin fully overlaps or at least partially overlaps the voltage range of VREF. In addition, or in the alternative. Additionally, or alternatively, the voltage ranges of VREF and Vin may be made to overlap by changing the terminal voltage of the VREF line. In figure 3a the voltages provided to the comparators 4a-g, by taking electrical taps of the VREF line, extend from a) +VREF, wherein +VREF is the input voltage into port 7; to b) a further positive voltage at ((0.301) x (+VREF)), wherein the value 0.301 is taken from the inverting input of comparator 4g, in Table 1. The analogue voltage signal received at port 12 is provided as an input into the '+' input ports of each of the comparators 4a-4g. The comparators are thus connected to the Vin signal via a parallel arrangement and receive the same input voltage at a time't'. As a variation, one or more resistors may be connected in between the parallel connections to the '+' input ports of the comparators and / or between the Vin port 12 and the first 4a of the comparators. The output of each comparator 4a-g is input into a separate and different input port, D0-D7, of the priority encoder 6. The output voltage signal of comparator 4a is input into priority encoder at input port DO. The output voltage signal of comparator 4b is input into priority encoder at input port DI. The output voltage signal of comparator 4c is input into priority encoder at input port D2. The output voltage signal of comparator 4d is input into priority encoder at input port D3. The output voltage signal of comparator 4e is input into priority encoder at input port D4. The output voltage signal of comparator 4f is input into priority encoder at input port D5. The output voltage signal of comparator 4g is input into priority encoder at input port D6. The priority encoder 6 comprises supply rail connections Vdd and ground 14 wherein a further input port of the priority encoder (that is not electronically coupled to a comparator) is coupled to the same ground 14. The priority encoder 6 includes three output ports, 16a, b, c. The output voltages of at least two of the output ports 16a-c output binary voltage levels that, together, define a digital value associated with the input voltage signal Vin. In general, the priority encoder 6, in this example, receives N inputs (where N is typically 4, 8 or 16), and asserts an output binary code of M=log2N bits (so the M-bit binary code is typically 2, 3, or 4 bits). The apparatus 2 typically comprises an input clock system, driven by one or more electronic signals (for example output from a further electrical apparatus). The clock system drives each comparator, in synchronisation, to sample the input signal Vin. It should be understood that the number and values of components and associated connections in the example above may be varied. As an example, the resistors 8a-8g may take the respective values 4.76kQ, 3.56kQ, 3.19kQ, 3.19kQ, 3.56kQ, 4.76kQ, 38.5kQ, where VREF is 0.615V and the Vin value input into port 12 is a normal distribution with peak centre at 0.5V, and sigma of 0.1V, such that the 5-sigma tails are beyond 0 and IV. An alternative to this example with the resistors 8a-8g taking the respective values 4.76kQ, 3.56kQ, 3.19kQ, 3.19kQ, 3.56kQ, 4.76kQ, 38.5kQ, is shown in figure 3b wherein like numbers represent like components. Here, a further resistor 8h is placed in series with resistors 8a-g and electrically connected along the VREF line between the port 7 (not shown in figure 3b) and the electrical connection from the VREF line to the inverting input of comparator 4a. resistor 8h takes the resistive value 38.5kQ. The resistors 8a, 8a-8g therefore take respective resistance values mirrored about the electrical connection to the inverting input to comparator 4d. The example in figure 3b works by setting Vin as a normal distribution with centre at 0.5V, and sigma of 0.1V, such that the 5 sigma tails are beyond 0 and IV. VREF at port 7 for figure 3b is IV. Operation Turning back to figure 3a, in operation, an analogue voltage signal is input as Vin to input port 12. At the same time a constant direct current (DC) voltage signal VREF is input into input port 7. The series of resistors 8a-8g sequentially drop the voltage between port 7 and ground 10 such that each input port of each comparator 4a-4g receives a different voltage by electrically connecting to the VREF electrical line wherein at least one of the resistors 8a-f is electrically connected along the VREF electrical line between the connection between any two different electrical connections between the VREF line and respective different comparators 4a-4g. The input voltage Vin is input simultaneously, as a common voltage value, to the non-inverting '+' port for each of the comparators 4a-4g. A clock source is input into each comparator 4a-g so that each comparator samples both the VREF (or voltage divided VREF) and the Vin at the same time point as the other comparators 4a-4g. The clock signal sends in clocking voltage pulses in a periodic manner at a constant clocking frequency, although in principle the clocking frequency may change overtime. As an alternative, each comparator 4a-g may have its own internal clock that is presynchronised with the other comparator internal clocks. The voltage comparators 4a-g are preferably op-amp voltage comparators, operating in open-loop configuration, that compare the magnitudes of the two voltage inputs at the '+' and input voltage terminals (or 'ports') and determines which is the largest of the two. The output of the comparator 4a-g is dependent on the value of the input voltage, Vin with respect to the input DC voltage level tapped from the VREF line, wherein the output is HIGH when the voltage on the non-inverting input is greater than the voltage on the inverting input, and LOW when the non-inverting input is less than the inverting input voltage. The HIGH, LOW conditions remain true regardless of whether the Vin is connected to the inverting or the non-inverting input of the comparator 4a-g. The output from the comparator 4a-g swings either fully to its positive supply rail, +Vcc or fully to its negative supply rail, -Vcc. In other words, changes in the two analogue inputs voltages at the '+' and inputs causes the comparator 4a-g to behave like a digital bistable device as triggering causes it to have two possible output states, +Vcc or -Vcc. The values of any of the supply rails may be a +ve voltage value, 0-volts or a negative voltage value as long as +Vcc has a higher voltage than -Vcc. The value of the output voltage from a comparator 4a-g is dependent on the power supply voltage. For purposes of this discussion, we denote the HIGH output level as '1' and the LOW output level as 0, however in practice these will be different voltage signals. Figure 4c shows a graph of the comparator output voltages for a given Vin where the inverting inputs are those of table 1. The different output voltage response of different comparators 4a-g are shown with different lines wherein each comparator outputs a zero-voltage at respectively lower Vin values until a threshold is reached whereby the comparator 4a-g output a HIGH (IV) value for voltages higher than its threshold. As is shown in the figure, there is a non-periodic nature to the Vin values at which different comparators output a HIGH voltage. In other words, the voltage difference between: a) the threshold (LOW-HIGH transition) Vin voltage for comparator 4g; and b) the threshold (LOW-HIGH transition) Vin voltage for comparator 4f; is greater than the voltage difference between: c) the threshold (LOW-HIGH transition) Vin voltage for comparator 4f; and d) the threshold (LOW-HIGH transition) Vin voltage for comparator 4e. At the priority encoder 6, the output voltage signal from each comparator 4a-g is input into a separate and different input electrical port D0-D7 wherein one of the priority encoder input ports, (in this example, D7), is connected to ground 14 for a 0V signal. This ground-connected input adds an additional bit of information to the seven output comparators because there needs to be 8-lines input into the priority encoder to provide 8 bits for the example in figure 3a. The priority encoder inputs comprise a set of inputs, each having a different priority. The inputs may be spatially arranged in the priority order. The voltage comparators may be assigned output their respective voltage signals to a different priority encoder input such that comparator 4a receiving the highest voltage at its inverting input outputs a signal to the priority encoder input DO with the lowest priority. The rest of the voltage comparators 4b-g are sequentially assigned to the next most-lowest priority input of the priority encoder 6. The Boolean truth table for the priority encoder of figure 3a is shown in Table 2. The 'X' in table 1 denotes that the value can be 0 or 1, in other words, if two or more inputs to the priority encoder are active at the same time, the input having the highest priority will take precedence. The number of inputs and outputs of the priority encoder 6 may vary for other implementations. Additionally, or alternatively, none, or one or more of the inputs may be connected to ground or a +ve or -ve voltage supply rail. Table 2: Priority comparator 6 inputs and outputs Inputs Outputs D7 D6 D5 D4 D3 D2 DI DO 16c 16b 16a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 X 0 1 0 0 0 0 0 0 1 X X 0 1 1 0 0 0 0 1 X X X 1 0 0 0 0 0 1 X X X X 1 0 1 0 0 1 X X X X X 1 1 0 0 1 X X X X X X 1 1 1 In an alternative to using the priority encoder, a standard encoder may be used together with a set of Exclusive-OR (XOR) gates XOR1-7 as shown in figure 4b. Figure 4b shows a portion of the circuit of figure 3a wherein like references represent like features. Instead of a priority encoder 6, a standard encoder 26 is used wherein a set of XOR gates XOR1-7 are used to receive the inputs from comparators 4a-4g and output electrical signal voltages to the standard encoder 26. Turning back to figure 3a, for a particular clocking time, hence sample time, each of the comparators 4a-g uses the current voltage values of the input VREF and Vin to output a voltage value that is, in turn, input into the priority encoder 6. This process of sampling generation of an output from the priority encoder is preferably repeated for each clock signal. The sampling and generation of the ADC signal may be performed for only one clock signal or multiple clock signals. Preferably the said process is repeated over a time't'. The priority encoder outputs different sets of output voltages on outputs 16a-c. Each output voltage set is dependent upon the all the voltage signals at the inputs D0-D7 at a particular time, as evident from Table 2. The set of voltage comparators 4a-g are electrically connected to the VREF line such that for each Vin input voltage at port 12 a set of output voltages are output from the comparators wherein each output voltage set is associated with a continuous group of input voltages Vin. Each Vin voltage value group comprises a continuous voltage range that borders but does not overlap with the voltage range from another voltage group. For example, for voltages upto a first voltage threshold of Vin, none of the comparators 4a-g output a high voltage; for voltages between the first voltage threshold and a second voltage threshold only comparator 4a outputs a high voltage and the remaining comparators 4b-g output a low voltage;; for voltages between the second voltage threshold and a third voltage threshold only comparators 4a and 4b output a high voltage and the remaining comparators 4c-g output a low voltage; etc. This is depicted in figure 4c. Because of the non-regular distribution of comparator output voltages for a given Vin input voltage as shown in figure 4c, the priority encoder 6 outputs a different output voltage set (see Table 2), for a different range of input voltage values Vin at port 12. Example of a QRNG Figure 5 shows an example of a quantum random number generator, QRNG, 28. The QRNG comprises a first subsystem 30 for generating the analogue voltage signal Vin for inputting into the electronic apparatus 2 that comprises the ADC as shown in figure 3a. In the first subsystem 30, the thicker black arrow-headed lines show optical signals whilst the thinner arrow-headed lines show electronic signals. An EM source such as a laser 32 outputs continuous wave light 34 towards a 50 / 50 optical intensity beam splitter 36. the EM radiation may have any wavelength but is preferably optical. The splitter 36 directs a first portion of the EM radiation along a first spatial path and a second portion along a second spatial path. The first and second spatial paths are spatially separate from each other. The splitter 36 may take any form include any of a bulk optic beam splitter, a fibre-optic splitter or an integrated optic splitter. The beam splitter 36 routes 50% (or substantially 50%, for example 50% within 0.5%, or 0.4%, or 0.3%, or, 0.2%, or 0.1%) of the intensity of the light 34 towards a first photodetector 40a via a mirror 38. The beam splitter 36 also outputs 50% (or substantially 50%) of the light towards a second photodetector 40b. Each photodetector 40a / b converts the optical radiation 34 to a continuous analogue electrical current 42, 44 wherein photodiode P40a outputs current 42 and photodiode 40b outputs current 44. Photodetectors 40a and 40b are electrically connected to device 46. Device 46 receives currents 42 and 44 and outputs the difference between them. Preferably the optical path length between the laser 32 and the photodetector 40a is substantially the same, or identical to the optical path length between the laser 32 and the photodetector 40b. Preferably the electrical path length between photodetector 40a and device 46 is substantially the same or identical to the electrical path length between photodetector 40b and device 46. The photodetectors may be any suitable photodetector including any of: PN photodiodes; PIN photodiodes; avalanche photodiodes; Metal-semiconductor-metal photodetectors. The output of the photodetectors is typically a photocurrent carried by one or more wires or electronic tracks. The subsystem 30 may comprise further optical or opto-electronic components between the EM source 32 and the photodetectors 40a / b such as, but not limited to: one or more EM attenuators along the EM paths the first and second portions take before getting to the photodetectors 40a / b (for example to ensure the amount of EM radiation entering the photodetectors is equal or substantially the same). The paths the EM radiation takes from the EM source 32 to the photodetectors may be any of: free space paths; fiber-optic paths; integrated optic paths. Accordingly, an of the optical or opto-electronic components used in the subsystem may be any of: bulk-optic, integrated optic or fiber-optic. The difference signal between 44 and 42 is then input into a transimpedance amplifier 48 that converts the difference-current signal to a voltage signal that is, in turn, input into a bias tee that changes the DC values of the voltage signal via +ve or -ve voltage addition. The output of the bias tee 50 is input into the electrical input port 12. The subsystem 30 uses a balanced detector system. In a similar manner to figure la, the electrical output of subsystem 30 is essentially electrical voltages corresponding to quantum vacuum fluctuations. Thus, the result is random about an average voltage of 0V that is increased or decreased in average (DC) voltage by the bias tee 50. DC voltage values that may be added by the bias tee may include between 0.12-10V, more preferably 0.1-1V. The bias tee 50 preferably introduces a DC voltage to the analogue voltage signal that centres the analogue voltage signal at a voltage value corresponding to a particular voltage value defined by the voltage comparators and / or encoder 6. Such a defined voltage value may be any of, but not limited to: a voltage value defining a boundary between different voltage ranges that define the output signals of the encoder, a voltage value within a voltage range of a voltage grouping. For example, the ADC may comprise a plurality of voltage groupings defined by comparators 4a-g and the encoder 6. Two of voltage-adjacent voltage groupings are referred to as a first and second voltage grouping wherein each of the first and second voltage grouping are also respectively adjacent to another different voltage grouping. The first voltage grouping has a narrower voltage range than its other adjacent voltage grouping. The second voltage grouping has a narrower voltage range than its other adjacent voltage grouping. A voltage shared at the border between, or a voltage otherwise between, the voltage ranges of the first and second voltage is the target voltage value that the bias-tee aligns the analogue voltage signal to. The analogue voltage signal may comprise a time varying voltage value distribution, for example Gaussian or another distribution like a Lorentzian, that may comprise a peak centred upon a central voltage value wherein the peak refers to the most common voltage of the analogue voltage. The bias tee or other DC voltage adapting device may move the peak of the distribution to the target voltage. The subsystem 30 may be adapted in configuration and components. Furthermore, one or more further electronic components may be used to create the VIN reference signal generally including any of: one or more electronic controllers for driving and controlling any of the components such as the laser; one or more capacitors or resistors for affecting any of the electronic signals. The laser 32 (or other EM source used in its place) may be any laser that is detectable by the photodetectors 40a / b. The mirror 38 may not be required if the subsystem 30 is re arranged and / or includes other beam steering components. Figure 6 shows an alternate way of generating the analogue voltage signal Vin, for inputting into an electronic apparatus such as the electronic apparatus 2, and is described underneath. Further examples of generating an analogue voltage signal Figure 6 shows a further example of a subsystem 100 (also referred to as a 'VIN-apparatus') 100 for generating an analogue voltage signal VIN. The combination of the VIN-apparatus in figure 6 and an electronic apparatus described in other examples herein may form at least part of a QRNG. In this figure, the thicker black arrow-headed lines show EM signals (for example optical signals) whilst the thinner arrow-headed lines show electronic signals. An EM source 102, for example a laser, outputs continuous wave EM radiation. The EM radiation has a coherence length L. The output EM radiation is input into an EM splitter 104 that outputs a first portion of the input EM radiation along a first spatial path 106a and a second portion along a second spatial path 106b. The first and second spatial paths 106a / b are spatially separate from each other. Both the first and second EM paths 106a / b electromagnetically link the EM splitter 104 to an EM combiner 108 such that the first and second portions of EM radiation propagate along each separate path and are input into the combiner 108. The EM splitter and / or combiner may take any form include any of a bulk optic beam splitter, a fibreoptic splitter or an integrated optic splitter. The EM path length of path 106b, between the EM splitter 104 and EM combiner 108, is longer than the equivalent EM path length of path 106b, by a difference AL. Preferably, AL is the same as or longer (for example any of 1% longer, 2% longer, 5% longer, 10% longer) than the coherence length of the EM source 102. The EM path length in this and other examples herein is intended to mean the effective path length taken by the EM radiation that factors in both the physical length and the refractive index of the medium(s) the EM ration takes along the length of the respective paths. The EM combiner is preferably a 2x1 port combiner or a 2x2 port combiner wherein at least one of the output EM ports of the combiner 108 carries EM radiation from the first and second portions of EM radiation. This combined output is input into a photodetector 110. The photodetector 110 may be a photodetector as described in other examples of the VIN apparatus described herein. Preferably the intensity of EM radiation in the first portion and second portion is substantially the same, for example the EM splitter may be a 50 / 50 splitter. The splitter may have other splitting ratios. The VIN-apparatus may comprise further optical or opto-electronic components between the EM source and the photodetector such as, but not limited to: one or more EM attenuators along the EM paths the first and second portions take before getting to the photodetectors (for example to ensure the amount of EM radiation entering the combiner 108 is equal or substantially the same). The paths the EM radiation takes from the EM source to the photodetectors may be any of: free space paths; fiber-optic paths; integrated optic paths. Accordingly, an of the optical or opto-electronic components used in the VIN-apparatus may be any of: bulk-optic, integrated optic or fiber-optic. The VIN-apparatus may comprise a device that hybridly or monolithically integrates the components onto a common platform. The output of the photodetector 110 is a photocurrent that is input into one or more further electronic components 112 such as: a capacitor to filter out the DC component of the electronic signal. The current output from the capacitor or the photodetector 110 may be input into transimpedance amplifier similarly to other examples of the subsystem 30 described herein. In operation, the VIN apparatus 100, of figure 6, detects combined EM radiation wherein the EM radiation along the first and second paths add up in a non-coherent manner. The combined signal includes phase noise. If the resulting electronic signal output from the photodetector 110 has the average current removed (for example by a DC filter or capacitor), then the remaining current is the phase noise. This phase noise, when converted to a voltage signal, typically has a Gaussian noise distribution centred at 0 volts. As with other examples of a subsystem 30 for generating a Vin signal an electronic component such as a bias-tee may be used to change the central voltage of the Vin voltage distribution. Preferably the EM source 102 outputs EM radiation, for example light, through the process of stimulated emission. Preferably the EM source 102 is operated to have an EM output power intensity that is close to the stimulated emission threshold. By doing this the amount of phase noise output for the output average intensity is high. The above examples are examples of producing a RNG signal from an EM radiation source and thus are QRNG's. Other apparatus may be used to generate an analogue signal with an at least partially randomised time dependent current distribution, including but not limited to any of: a linear feedback shift register, or any other device for outputting electronic noise. Alternative example of an electronic apparatus Figure 7 shows another example of an ADC 200 using a Successive Approximation Register (SAR), hereinafter SAR-ADC. General adaptions and considerations to other ADC examples herein may apply to the is example including but not limited to types of electrical connection, operation of a comparator and use of other electronic equipment to control the operation of the ADC. Furthermore, the SAR-ADC may receive VREF and Vin electrical signals from electrical signal sources used in other examples herein, for instance using Vin for the subsystem 30 of figure 5 or subsystem 100 of figure 6. The analogue Vin signal is input via an electrical connection 202 into a voltage comparator 204. The electrical connection is input into the non-inverting input'+', however the inputs to the inverting and non-inverting inputs of comparator 204 may be swapped around. The SAR-ADC 200 may have an electrical input port 212 for receiving the Vin. The other comparator input, which in figure 7 is the inverting input, is electrically connected to another part of the electronic circuit shown in the figure and described underneath. The comparator has electrical connections to an electrical supply (not shown). The electrical output of the comparator 204 is electrically linked via an electrical connection 206 to an electrical input of an SAR 208. The SAR in this example comprises three electrical outputs for outputting voltage signals along three corresponding electrical connections 210a-c. An electrical tap 212a-c is taken from each connection 210a-c, wherein each electrical tap is an electrical connection carrying current at the output voltage of its respective electrical output of the SAR 208. The group of electrical taps 212a-c are used to generate a multi-bit value for allocating to a range of Vin values similar to the 'output' columns of table 2 in a previous example. Although the SAR 208 in this example shows three output 210a-c, any number of two or more, or three or more outputs electrical connections may be used. The SAR may operate by maintaining a register of output voltage values to be output from output connections 210a-c until either the SAR is reset with a reset signal (for example after a set of cycles is completed (see below) or after a new voltage signal is received along input connection 206. The SAR may be clocked with an internal or shared clock as described for other examples herein, where each time the clock triggers within a set of cycles, the SAR 208 takes the present voltage value along 206 as the new input voltage signal. The SAR 208 sets-up a new register for each set of cycles (see below) wherein the default starting values of the most to least significant bits are 'high' for the most significant bit and low elsewhere. When the SAR receives the first new signal along 206 it decides to either: a) if the input signal along 206 is high, maintains the most significant bit as high (along 210a) and changes the next most significant bit from low to high (along 210b), b) if the input signal along 206 is low, changes the most significant bit to low and changes the next most significant bit to high (along 210b). For each further cycle, in the same cycle set after the first cycle, the SAR performs similar operations but shifts the most significant bit of interest to the next most significant bit, in other words, for the second cycle the SAR 208 changes or maintains the second most significant bit (along 210b) from its previous value and changes the next most significant bit from low to high (if there is a next most significant bit). Each output electrical connection 210a-c is associated with a different bit in a set of bits output from the SAR 208. The bits may have a 'HIGH' or '1' output logic represented by a first voltage value or one or more voltage values above a threshold voltage. The bits may have a 'LOW' or '0' output logic represented by a second voltage value different to the first voltage value, or one or more voltage values below a threshold voltage. Each bit signal is assigned a priority related to the bit significance. For example: output 210a may carry the electrical signal for the most significant bit; output 210b may carry the electrical signal for the next most significant bit after 210a; output 210c may carry the electrical signal for the next most significant bit after 210b. For purposes of further discussion, an example of a 'high' voltage indicating that a bit is active, and intended to be output from SAR 208, may be IV and a low voltage indicating that a bit is not active, and intended not to be output from SAR 208, may be 0V. The electrical outputs 210a-c of the SAR are electrically connected to corresponding electrical inputs of a digital to analogue converter apparatus 214 comprising one or more Digital to Analogue Converters (DAC), wherein each electrical output 210a-c is electrically connected to a different, separate electrical input of the DAC apparatus 214. The DAC apparatus 214 comprises an electrical input that receives electrical signals, in particular voltage signals at VREF along an electrical connection 217 that connects to an input port 207. The DAC apparatus 214 comprises an electrical output for outputting one or more voltage signals along an electrical connection that inputs the said DAC apparatus output electrical signals to the inverting input of the comparator 204. An example of a DAC apparatus 214 for use with the apparatus of figure 7 is shown in figure 8. In operation, the output of the DAC apparatus 214 outputs a non-standard output distribution of voltages, thus producing non-equal voltage ranges for the different voltage groupings. In general, the DAC apparatus 214 outputs a voltage value along output 216, wherein the voltage value comprises a summation of one or more voltage values corresponding to whether the input signals along 210a-c are high or low. In other words, for each 'high' signal along the outputs 210a-c, a voltage value is added to the total voltage value output along connection 216. When the voltage input along 210a is high, the DAC apparatus 214 adds a first voltage (for example 0.5V) to the total output voltage along output 216. When the voltage input along 210a is low, the DAC apparatus 214 adds 0 voltage to the total output voltage along output 216. When the voltage input along 210b is high, the DAC apparatus 214 adds a second different voltage (for example 0.25V) to the total output voltage along output 216. When the voltage input along 210b is low, the DAC apparatus 214 adds 0 voltage to the total output voltage along output 216. When the voltage input along 210c is high, the DAC apparatus 214 adds a second different voltage (for example 0.125V) to the total output voltage along output 216. When the voltage input along 210c is low, the DAC apparatus 214 adds 0 voltage to the total output voltage along output 216. Thus, if the input along 210a and 210c were high but 210b was low then the DAC apparatus 214 would output 0.5V + 0V + 0.125V = 0.625V. A standard SAR-ADC may use a DAC having voltages for each significant bit being half of the voltage of the adjacent more significant bit with the most significant bit associated with voltage at half the total voltage range required by the DAC. A standard DAC may therefore output a total voltage according to a power series. In the present DAC apparatus 214, the voltage values associated with the incoming bits along 210a-c take a different distribution to the standard DAC. The DAC voltages per bit may be initially set or may be changed from an initial voltage value / bit distribution, for example changed from the standard divide by two, to another distribution rule or set of voltage values. The DAC apparatus 214 may therefore optionally be tuneable insofar that the output analogue voltage along electrical connection 216 may change for a given same set of inputs from connections 210a-c, upon a respective tuning of the DAC apparatus 214. In other words, the DAC apparatus 214 may be initially configured to output a particular voltage value along output connection 216 for a given set of inputs and then subsequently tuned to give a different output voltage along output connection 216 for the same given set of inputs. This may be achieved by assigning a different output voltage for one or more of the different input signals along connection 210a-c. The ADC 200 may optionally comprise a feedback system wherein the DAC apparatus 214 receives a further electrical input via an electrical connection 219. The connection 219 is output from a computation system that analysis the Vin voltage distributions over time and determines whether to output signals to change the setting of the DAC apparatus 214, as described in more detail elsewhere underneath. This connection 219 is shown to originate from the SAR 208 wherein the SAR 208 is assumed to contain the computation system, but may be from a separate device (not shown) such as a computer or electrical controller. In general, the processes for operating the ADCs herein and determining the internal voltages used to set the voltage bin widths may be performed by computing modules on hardware or software. Examples of hardware are presented elsewhere herein but may include electronic computer memory, processors and controllers and other computer components. The memory may store executable code to perform methods for implementing processes discussed herein. Such coded methods may comprise one or more algorithms. In operation, the SAR ADC 200 inputs the same Vin voltage signal into the comparator 204 a plurality of times, sequentially in time. Each input of the Vin value to the comparator 204 corresponds to a particular operation cycle of the SAR-ADC wherein subsequent inputs of the same Vin voltage, either immediately before or immediately after, correspond to a further cycle of the same set of cycles. Each cycle comprises the following steps: 1) the Vin voltage value is input to the comparator 204 wherein at the same time a voltage signal along 216 is also input into the comparator 204; 2) the resulting output of the comparator 206 is input into the SAR 208; 3) the resulting outputs 210a-c of the SAR are input into the DAC apparatus 214; 4) the resulting voltage signal is output along 216 for inputting into the comparator 204 at the same time as the next Vin is input for the next cycle. As an example, assume Vin is 0.6V for a set of 3 cycles and that: the voltage associated at the DAC apparatus 214 with 210a being high is 0.5V; the voltage associated at the DAC apparatus 214 with 210b being high is 0.25V; the voltage associated at the DAC apparatus 214 with 210c being high is 0.125V; the voltage being output along connection 216 starts with 0.5V and corresponds to the SAR having its register set to 210a being high and 210b and 210c being low. For the first cycle the comparator compares Vin = 0.6V to the inverting input of 0.5V and outputs a high output signal along connection 206. Upon receiving the high input along connection 206, the SAR 208: a) locks the most significant bit to continually be high (thus 210a stays as 'high'); and b) changes the second most significant bit from low to high so that the output along 210b is high. The least significant bit represented by the output 210c remains low. The DAC apparatus 214 receives the bit sequence 110 along 210a-c respectively and outputs a voltage value of 0.5V + 0.25V + 0V = 0.75V. The first cycle is completed. For the second cycle the comparator compares Vin = 0.6V to the inverting input of 0.75V and outputs a low output signal along connection 206. Upon receiving the low input along connection 206, the SAR 208: a) changes the 2nd most significant bit to continually be low (thus 210a stays as 'high' but 210b changes to low); and b) changes the least most significant bit from low to high so that the output along 210c is high. The DAC apparatus 214 receives the bit sequence 101 along 210a-c respectively and outputs a voltage value of 0.5V + 0V + 0.125V = 0.625V. The second cycle is completed. For the third cycle the comparator compares Vin = 0.6V to the inverting input of 0.625V and outputs a low output signal along connection 206. Upon receiving the low input along connection 206, the SAR 208: a) changes the least most significant bit to continually be low (thus 210a stays as 'high', 210b stays as low but 210c changes back to low). The DAC apparatus 214 receives the bit sequence 100 along 210a-c respectively and outputs a voltage value of 0.5V + OV + OV = 0.5V. The third and last cycle in this set is completed and the values of 210a-c, that are also output as 212a-c respectively, are used as the digital output of the SAR-ADC for this particular value of Vin = 0.6. This above example is using standard SAR-ADC voltage values of 0.5, 0.25, 0.125V, however the present application may either start with such a standard voltage set and then change values or otherwise use values that are not the standard 'divide by two'. Each Vin voltage values for each cycle for the same cycle set may be generated in different ways. One way is ensuring that the Vin voltage value that is common for the same set is constantly input in time over the time period required for the SAR-ADC 200 to complete all its cycles for the same set. Another way is to copy the Vin voltage value and input it to the comparator 204 as time separated voltage input pulses into the comparator wherein the time separation is at least as long as the time is takes the updated voltage value (from the last voltage pulse) along 216 to reach the comparator 204. The number of cycles may be related to the number of bits output by the register, hence the number 'n' of outputs 210a-c. For example, the number of cycles in a set may be 'n' or 'n'+l. For a given cycle set, each time a cycle completes the SAR-ADC operates to try to direct the values of 210a-c to give rise to a voltage value along 216 that is closer to the Vin value. A completed set of cycles may be used to determine a first set of output values for the ADC 200 along electrical output lines 212a-c, wherein the set corresponds to the same Vin value. As stated above, the SAR ADC 200 may include a tuneable DAC apparatus 214 that allows the SAR ADC to be adapted to output a set of digital bits along 212a-c. Each set of different digital bits output along 212a-c correspond to a range of Vin voltages for a voltage grouping that is different to the voltage range of a different voltage grouping represented by a different set of bits along 210a-c. For example, output bits 111 along 212a-c represent a voltage grouping at the end of a voltage distribution of Vin whereas output bits 110 along 212a-c represent a further voltage grouping adjacent (in voltage range) to the voltage grouping for bits 111. The SAR ADC 200 may be used in a set of calibration measurements to determine what the voltage distribution is for Vin, for example whether it is gaussian as discussed for figure lb, and then adapting the SAR-ADC to generate voltage groupings that have equal, or substantially equal counts per voltage grouping, for the same incoming Vin voltage distribution on further Vin input signals. This calibration process may involve running the SAR-ADC for a plurality of sets of cycles, for example any of but not limited to: 10,100,1000 cycle sets. Ideally the calibration procedure runs a plurality of cycle sets such that multiple final outputs along 212a-c are found for the same output bits; in other words, the calibration procedure continues until at least one of the output bit strings (e.g. 101) has been determined for at least two separate cycle sets. Once the distribution is known, the SAR ADC may adapt the DAC apparatus 214 to output voltage values that allow for the SAR-ADC to output bits along 212a-c that correspond to voltage groupings having particular voltage widths. These widths are preferably set so that equal, or almost equal numbers of counts are allocated to each voltage grouping. This adaptation preferably occurs by changing the voltage value, in the DAC apparatus 214, assigned to one or more particular HIGH inputs of 210a-c. For example, the calibration procedure may start with an initial set of voltages for the inputs 210a-c, which may be the standard 'divide by two' voltage set. After testing the Vin distribution for, say, 1000 cycle sets, a computer system in the SAR 208 outputs an electrical control signal to change the voltage output by the DAC apparatus for the second most significant bit (which corresponds to 210b). Thus, originally the standard 'divide-by-two' configuration of voltages in the DAC apparatus 214 may have this bit output 0.25V to the total output voltage, however upon executing the calibration measurements the computer system determines that this bit is required to be 0.3V. The computer system thus sends a signal along connection 219 to make this change in the DAC apparatus 214. Figure 8 shows an example of a DAC apparatus 214. The VREF signal is input into a plurality of potentiometers R1-R7 that are electrically connected in series to ground 250. Before the first potentiometer RI, and thereafter after each potentiometer R1-R7, a separate electrical connection is made to a switch, Sl-8 such that the switches Sl-8 are connected in parallel. The voltage input to each switch, V0-V7 therefore takes a different voltage to the other voltage inputs. The output of each switch Sl-8 is connected to a common electrical point 250 in the circuit from which the output electrical signal of the DAC is output from. The output voltage is the sum of the voltages V0-V7, which depends on which switches (switch 1-8) are open and closed and the resistance values of the potentiometers R1-R7. In this example only one switch S1-S8 is closed for any one output. The DAC apparatus 214c in figure 8 is an example of a ladder DAC where the voltage groupings are set by the potentiometers R1-R7. The DAC apparatus 214 comprises a controller (not shown) that receives three digital bits in input and converts those inputs into, through a look-up table, to eight control signal channels and these control whether the corresponding switch is open or closed. A resistor (not shown) is also included along each electrical connection from each respective switch Sl- S8 to the common electrical point 250. The potentiometer R7 is connected to ground 260, hence V7 is 0V, however a further resistor may be inserted between R7 and ground 260 to give V7 a non-zero voltage value. Figure 12 shows a further example of a DAC apparatus 214 wherein like references between figure 12 and figure 8 represent like features. A 3-to-8 decoder 230 receives inputs bO, bl, b2 from the SAR 208 wherein b2 is the Most Significant Bit (MSB) connect to output 210c; bl is connected to output 210b; bO is the Least Significant Bit (LSB) and is connect to output 210a. The 3-to-8 decoder 230 controls the switches Sl-8 to be closed once at the time. In this configuration the DAC apparatus 214 never has 2 switches closed at the same time. The switch function Sl-8 can be replaced with Mosfet or other similar technologies (logic 0 = open , logic 1 = closed). Table 3 shows the switches that are closed for a given set of digital inputs along b2, bl, bO. Table 3. b2,bl,bO Switch 8 Switch 7 Switch 6 Switch 5 Switch 4 Switch 3 Switch 2 Switch 1 0,0,0 1 0 0 0 0 0 0 0 0,0,1 0 1 0 0 0 0 0 0 0,1,0 0 0 1 0 0 0 0 0 0,1,1 0 0 0 1 0 0 0 0 1,0,0 0 0 0 0 1 0 0 0 1,0,1 0 0 0 0 0 1 0 0 1,1,0 0 0 0 0 0 0 1 0 1,1,1 0 0 0 0 0 0 0 1 VRef is connected to 207. Vout is connected to 216. The DAC apparatus 214 comprises a set of output voltage channels ChO-6. The voltages from the channels are between VREF and ground (or another reference voltage different to VREF). Seven channels are shown but the apparatus 214 can have any plurality of channels. Each voltage channel outputs a different voltage V0-V6 to a terminal of a respective different switch S1-S7 such that when the respective switch is closed, the output voltage from that channel becomes the output voltage along 216 of the DAC apparatus. The input voltage to switch S8 is connected to ground. In this example device 232 may be a multi-output potentiometer that can controllably output a plurality of voltages wherein at least one, potentially plurality, more preferably all voltage outputs may be adjusted upon receipt of a control signal. A further example is presented below of how the SAR-ADC 200 generates voltage groupings that provide a uniform distribution of average counts / group to a Gaussian distribution of Vin input voltage signals. At first the SAR-ADC 200 collects a number of samples (for example 100 for good statistics). These samples constitute a distribution, which can be a normal distribution. This information is collected and held in a computer memory in the SAR 208. Initially the ADC voltage grouping (or 'bins') will be equally spaced such that a distribution will be faithfully represented by the ADC itself. In the SAR-ADC 200 this corresponds to a set of voltage values that may be output from the DAC apparatus 214 along output connection 216 of 0V, 0.125V, 0.25V, 0.375, 0.5V, 0.625, 0.75V or 0.875V for a Vref =1V. Figure 9 shows eight voltage bins for such a standard DAC setting, with each bin corresponding to a voltage output 216 by the DAC apparatus 216 and a bit value output along 212a-c. Figure 9 shows the voltages at the ends of the bins wherein: bin with bits 000 extends between 0V-0.125V; bin with bits 100 extends between 0.125V-0.25V; bin with bits 010 extends between 0.25V-0.375V; bin with bits 110 extends between 0.375V - 0.5V; bin with bits 001 extends between 0.5V - 0.625V; bin with bits 101 extends between 0.625V - 0.75V; bin with bits Oil extends between 0.75V - 0.875V; bin with bits 111 extends between 0.875V- IV. The computing unit in the SAR 208 also comprises a processor that calculates the voltage settings for the ADC bins that would map a gaussian distribution into a uniform distribution. In this example, this is done by: calculating the Vin signal's cumulative distribution function of the measured original distribution, then, the inverse of this is taken, for equally probable distribution intervals. Other ways of achieving the same result may be possible. This yields a new set of intervals to which the voltage values of the SAR-ADC can be set to produce any kind of distribution (in this case a uniform one) for any given distribution in input (in this case Gaussian). For example, a new sets of voltage values 0V, 0.385V, 0.432V, 0.468V, 0.5V, 0.532V, 0.568V, 0.615V, IV as shown in figure 11c. Figures lOa-c, together with figures lla-c, show an example of the process of determining new voltage bin widths in more detail. For this example, the DAC apparatus 214 of figure 12 is used. In this example Vref = IV, whilst Vin (212, 202) = 0.4V. At the start up, block 214 acts as a standard DAC wherein: V0=0.875V; Vl=0.75V; V2=0.625V; V3=0. 5V; V4=0.375V; V5=0.25V; V6=0.125V; V7=0.0V. We initially discuss, generally how the SAR-ADC works with its standard values V0-V7 as stated above before moving into figures lOa-lOc, lla-llc. Output 210c (MSB) is set to High (logic 1) (b2 = 1, bl = 0, bO = 0), the encoder closes switch 4, Vout (216) = 0.5V. Comparator 204 compares Vin (202) with output 21. Because 0.4V <0.5V, 210c becomes Low (logic 0) and shifts the high bit to 210b (thus bl=l, but b2-0 whilst b0=0). Encoder 230 closes only switch S6. This makes Vout 216 = 0.25V for this input [b2 = 0, bl = 1, bO = 0], At the comparator 204 again, 0.4V >0.25V therefore bl is set always at logic 1. However, bO is then set to 1 (LSB), thus the inputs to the DAC apparatus 214 are b2 = 0, bl = 1, bO = 1. The encoder 230 closes switch 5 such that Vout 216 = 0.375V. Back at the comparator 208 again 0.4V >0.375V therefore bO is set always at logic 1. The process thus provides an analog to digital conversion of 0.4V, in this case, to a digital word Oil along output voltage channels 212a,b,c. This process will convert from analogue to digital, a gaussian distribution. We now turn to figures lOa-llc to discuss how the use of the feedback control can act directly on the digital interface of an internal DAC to accommodate any change required to voltage bin voltage width to turn the voltage bins into a uniform distribution. This specific example of the feedback turns a Gaussian distribution into a uniform distribution. The ADC 200 collects a number of samples of Vin. Any number of samples may be used, for example 100. Increasing the number of samples improves the statistics. These samples constitute a distribution, which can be a normal distribution. This sampling information is collected and stored in a memory in the register apparatus 208. Before the feedback is implemented to adjust some or all of the V0-V7 voltages of the DAC apparatus 214, the ADC bins are set so that they are equally spaced (hence have the same or similar voltage widths) such that a distribution will be faithfully represented by the ADC itself. In the SAR-ADC this corresponds to voltage values for the bins at 216 of 0, 0.125V, 0.25V, 0.375, 0.5V, 0.625, 0.75V or 0.875V, with Vref =1V. The computer processing unit inside the SAR 208 calculates the voltage settings for the ADC bins that would map a gaussian distribution into a uniform distribution. In the alternative, a different computer processing unit outside of the SAR 208 may perform this task. There now follows an example of how this could be done, although there may be other ways of achieving the same result. First the processor calculates the signal's cumulative distribution function (CDF) of the measured original distribution stored in the memory of the SAR unit 208. The CDF is shown in figure 10b. Figure 10c shows these intervals in relation to a probability distribution wherein the vertical axes in figures 10b and 10c are Voltage running from 0V to VREF. As can be seen in figure 10c given the CDF curve of figure 10b the common fixed width starting voltage bins of figure 10a yield non-uniform count probabilities per bin, with the middle two bins (0.375V-0.5V and 0.5V-0.625V) giving the greatest probability of there being a count. The CDF maps the voltage bin widths to the probability of a input voltage being in that bin. Secondly, as shown in figures lla-llc, the processor calculates its inverse, for equally probable distribution intervals. Thus, an inverse CDF calculation is made. In other words, the processor starts with uniform probability bins in figure 11a and used the CDF to calculate new voltage bin widths from the CDF mapping. This yields a new set of intervals as shown in figure 11c to which the voltage values V0-V7 of the DAC apparatus 214, of the ADC 200, can be set to produce any kind of distribution (in this case uniform) for any given distribution in input (in this case Gaussian). For example, the new sets of voltage values 0V, 0.385V, 0.432V, 0.468V, 0.5V, 0.532V, 0.568V, 0.615V, IV define the voltage bin widths. Once the new voltage bin widths (referred to as 'modified binning') have been determined and the DAC apparatus changed to represent such voltages, the apparatus 200 may be used for new incoming voltage signals. The following is an example of the previous Vin of 0.4V and Vref of IV being input into the SAR-ADC 200 with the DAC apparatus 214 channels set so the modified voltages as follows: V7=0V; V6=0.385V; V5=0.432V; V4=0.468V; V3=0.5V; V2=0.532V; Vl=0.568V; V0=0.615V. At the start, output 210c (MSB) is set to High (logic 1) such that b2 = 1, bl = 0, bO = 0. The encoder 230 closes switch S4, so Vout 216 = 0.5V. Comparator 204 compares Vin 202 with the Vout 216. Because 0.4V <0.5V, 210c becomes Low (logic 0) and shift the high bit to 210b and changes the MSB to 0. Thus, b2=0, bl = 1, bO = 0. The encoder 230 then closes only switch S6. Vout 216 is therefore = 0.432V with b2 = 0, bl = 1, bO = 0. Because 0.4V <0.432V, bl is then set to logic value 0 and bO is set to 1. Thus b2 = 0, bl = 0, bO = 1. The encoder 230 then closes switch S7 such that Vout 216 is then 0.385V. Because 0.4V >0.385V, bO is set always at logic 1. The analog to digital conversion of 0.4V in this case is therefore a digital word 001 along outputs 212a,b,c. Thus, in existing DACs where the values of the resistive elements R are all the same, the DAC would produce signals that are equi-spaced. Unlike existing DACs, the DAC apparatus 214 presented herein produces a different, non-equi-spaced voltage distribution. Some portions of the above description present the features of the invention in terms of algorithms and symbolic representations of operations on information. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. These operations, while described functionally or logically, are understood to be implemented by computer programs. Furthermore, the reference to these arrangements of operations in terms of modules should not be considered to imply a structural limitation and references to functional names is by way of illustration and does not infer a loss of generality. Unless specifically stated otherwise as apparent from the description above, it is appreciated that throughout the description, discussions utilising terms such as "processing" or "identifying" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system memories or registers or other such information storage, transmission or display devices. Certain aspects of the method or system include process steps and instructions described herein in the form of an algorithm. It should be understood that the process steps, instructions, of the said method / system as described and claimed, may be executed by computer hardware operating under program control, and not mental steps performed by a human. Similarly, all of the types of data described and claimed may be stored in a computer readable storage medium operated by a computer system, and are not simply disembodied abstract ideas. The method / system also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored on a computer readable medium that can be executed by the computer. Such a computer program is stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, application specific integrated circuits (ASICs), or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus. Furthermore, the computers referred to in the specification may include a single processor or may be architectures employing multiple processor designs for increased computing capability. Any controller(s) referred to above may take any suitable form. For instance, the controller(s) may comprise processing circuitry, including the one or more processors, and the memory devices comprising a single memory unit or a plurality of memory units. The memory devices may store computer program instructions that, when loaded into processing circuitry, control the operation of the route provider and / or route requester. The computer program instructions may provide the logic and routines that enable the apparatus to perform the functionality described above. The computer program instructions may arrive at the apparatus via an electromagnetic carrier signal or be copied from a physical entity such as a computer program product, a non-volatile electronic memory device (e.g. flash memory) or a record medium such as a CD-ROM or DVD. Typically, the processor(s) of the controller(s) may be coupled to both volatile memory and non-volatile memory. The computer program is stored in the non-volatile memory and may be executed by the processor(s) using the volatile memory for temporary storage of data or data and instructions. Examples of volatile memory include RAM, DRAM, SDRAM etc. Examples of non-volatile memory include ROM, PROM, EEPROM, flash memory, optical storage, magnetic storage, etc. The terms 'memory', 'memory medium' and 5 'storage medium' when used in this specification are intended to relate primarily to memory comprising both non-volatile memory and volatile memory unless the context implies otherwise, although the terms may also cover one or more volatile memories only, one or more non-volatile memories only, or one or more volatile memories and one or more non-volatile memories. The algorithms and operations presented herein can be executed by any type or brand of computer 10 or other apparatus. Various general-purpose systems may also be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent to those of skill in the art, along with equivalent variations. In addition, the method / system is not described with reference to any particular programming language. It is appreciated that a 15 variety of programming languages may be used to implement the teachings of the invention as described herein.

Claims

1. A random number generator, RNG, comprising an Analogue to Digital Converter, ADC, the ADC comprising one or more voltage comparators and configured to:i) receive a plurality of input signal voltages; the plurality of input signal voltages comprising a randomised distribution of voltage values;ii) determine a voltage grouping for each input signal voltage using the one or more voltage comparators; the determined voltage grouping comprises a voltage range comprising the voltage of input signal voltage;the magnitude of the voltage range of at least one voltage grouping is different to the magnitude of the voltage range of at least another of the voltage groupings;iii) generate an output voltage for each of the plurality of input signal voltages based on the respectively determined voltage grouping, the output voltage for generating random numbers.

2. The RNG as claimed in claim 1 wherein the voltage groupings are predefined.

3. The RNG as claimed in claims 1 or 2 wherein the voltage groupings are predefined by theADC.

4. The RNG as claimed in any preceding claim wherein at least one of the voltage groupings is determined for a subset of the plurality of input signal voltages.

5. The RNG as claimed in any preceding claim wherein each voltage range is different to the voltage range of the other voltage groupings.

6. The RNG as claimed in any preceding claim wherein each voltage range covers a different set of voltages than the other voltage ranges of the other voltage groupings.

7. The RNG as claimed in any preceding claim wherein the voltage ranges are non-overlapping.

8. The RNG as claimed in any preceding claim wherein each voltage grouping comprises avoltage range that borders at least one other voltage range of a different voltage grouping.

9. The RNG as claimed in any preceding claim wherein the at least one voltage grouping comprises a first voltage grouping determined for a first subset of the plurality of input signal voltages; a second voltage grouping is determined for a further subset of the plurality of input signalvoltages; the first voltage grouping comprises a different voltage range than the second voltage grouping.

10. The RNG as claimed in any preceding claim wherein the ADC comprises a Flash ADC.

11. The RNG as claimed in any preceding claim wherein the RNG comprises a plurality of voltagecomparators; each of the plurality of voltage comparators comprises a first and a second voltage signal input.

12. The RNG as claimed in any preceding claim wherein the plurality of input signal voltages are input into the first or second voltage signal inputs of the plurality of voltage comparators.

13. The RNG as claimed in any preceding claim wherein the first voltage signal input comprises a non-inverting input; and, the second voltage signal input comprises an inverting input.

14. The RNG as claimed in any preceding claim wherein the plurality of voltage comparators are electrically connected in series with respect to an electrical input carrying the plurality of input signal voltages.

15. The RNG as claimed in any preceding claim wherein the plurality of input signal voltages are input into the ADC via a first ADC electrical input (Vin, 12); the plurality of voltage comparators are electrically connected in series between a second ADC electrical input (VREF, 7) and an end electrical terminal (10), the second ADC electrical input being different to the first ADC electrical input; the ADC comprises a plurality of electrically resistive elements electrically connected in series between the second ADC electrical input and the end electrical terminal (10); the ADC comprises:a) a first electrical connection, between the second ADC electrical input (VREF, 7) and a first of the electrically resistive elements;b) a second electrical connection, between the first electrical connection and a second of the electrically resistive elements;c) a third electrical connection, between the second electrical connection and the end electrical terminal (10);each of the first, second and third electrical connections electrically connecting to a respective different voltage comparator.

16. The RNG as claimed in claim 16 wherein the potential difference between the first and second electrical connections is different to the potential difference between the second and third electrical connections.

17. The RNG as claimed in any preceding claim wherein the ADC comprises:a Successive Approximation Register, SAR; and,a Digital to Analogue Converter, DAC,wherein:an electrical output from one of the voltage comparators electrically connects to an input of the SAR;a plurality of electrical outputs from the SAR are electrical connected to an input of the DAC, an electrical output of the DAC is electrically connected to an input of the said voltage comparator.

18. The RNG as claimed in claim 17 wherein the SAR is configured to output from each of its electrical outputs:a first voltage associated with a logical high;a second voltage for a logical low.

19. The RNG as claimed in any of claims 17 or 18 wherein the DAC is configured to:generate:a first non-zero voltage upon the output of a first of the SAR electrical outputs comprising a logical high; added to at least,a second non-zero voltage upon the output of a second of the SAR electrical outputs comprising a logical high.

20. The RNG as claimed in any preceding claim further comprising an electromagnetic, EM, system; the EM system comprising one or more photodetectors for receiving EM radiation and outputting electrical signals; the input voltage signals received by the ADC based on the output electrical signals.

21. An electronic apparatus comprising one or more voltage comparators; the electronic apparatus configured to:i) receive a plurality of input signal voltages; andii) determine a voltage grouping, from a plurality of voltage groupings, for each input signal voltage using the one or more voltage comparators; the determined voltage grouping comprises a voltage range comprising the voltage of the input signal voltage;the voltage range of at least a first of the plurality of voltage groupings:a) comprises a different voltage magnitude to the voltage magnitude of at least another of the voltage groupings;b) is determined by an input voltage to at least one of the comparators; the said input voltage determined based on target proportion of the input signal voltages for the respective voltage grouping;iii) output a voltage signal based on the determined voltage groupings.

22. The electronic apparatus of claim 21 wherein the at least one of the one or more voltageinputs into the voltage comparator is a feedback voltage; the feedback voltage associated with a previous output voltage of the one or more comparators.

23. The electronic apparatus of claims 21 or 22 wherein the voltage range for at least two voltage grouping is defined by a first voltage threshold and a second voltage threshold; each of the first and second voltage thresholds being determined by one or more voltage inputs into at least one of the voltage comparators; each voltage range being different to the voltage range of the other voltage groupings.

24. The electronic apparatus of any of claims 21-23 wherein the output voltage signal comprises a plurality of output voltage signals wherein each output voltage signal is associated with a different input signal voltage.

25. The electronic apparatus of any of claims 21-24 wherein each voltage grouping is associated with a different output voltage signal to at least one of the other output voltage signals associated voltage group.41

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