Quantum decoder

Abstract

A computer-implemented method for decoding errors in a quantum computer system is disclosed. The quantum computer system comprises a register of quantum devices and a decoder apparatus receiving syndr

Description

This disclosure relates to methods, systems, and apparatuses for use in decoding errors in a quantum computer system. Background Quantum computers hold the potential to revolutionize various fields of science and technology. However, today's quantum computers cannot realise these transformational possibilities because their fundamental components, qubits, are highly error-prone. To unlock the transformative possibilities of quantum computing, the error rates for operating on quantum data must be dramatically reduced. This issue may be addressed in part by hardware improvements as physicists and engineers get better at building more stable qubits, but these advancements alone won't be enough to enable algorithms to run with millions or billions of operations reliably. There is a need for quantum error correction methods, however these methods present significant challenges. Fault-tolerant quantum computation will likely involve millions of physical data qubits, generating a huge amount of data which must be processed extremely quickly and in real-time. Both classical and quantum error correction methods seek to identify and address errors in information storage and processing. However, these general approaches operate in fundamentally different ways due to the unique principles of quantum mechanics. For example, while classical information is encoded using classical bits which exist in a well-defined state (either 0 or 1) at any given time, quantum information is encoded using a register of quantum devices such as a register of qubits, which can exist in superpositions of states (both 0 and 1 simultaneously) and exhibit entanglement. In addition, since directly measuring the state of a qubit causes the state to collapse, quantum error correction techniques must measure certain properties of the quantum system to infer the existence of errors, while mitigating the effects of measurements on the quantum state. Some quantum error correction codes involve decoding a "syndrome", which can be considered to be a signature associated with an error state of the physical qubits. A decoder is used to identify an error (or errors) which could have caused the syndrome. A "decoding graph" can be used to facilitate decoding of the syndrome, for example by grouping "defects" in the syndrome. These defects generally provide an indication of end points of chains of errors on physical data qubits in the error correction code. Errors generally create a pair of defects, and an objective of quantum error correction techniques is to identify and match up these defects. After the defects in the syndrome have been grouped, a next step can be determined. For example, a correction for the error state can be determined and applied. Decoding algorithms designed to operate on this type of data can be run by decoding hardware comprising a plurality of processing elements (PEs). It is beneficial to parallelise the execution of multiple PEs at some or all steps of the decoding algorithm, for example using a distributed decoding algorithm. Distributed decoding algorithms comprise at least some parallelisation in the execution of PEs. Often these PEs are connected using data links in hardware. Each node in the decoding graph may be associated with a different PE according to a 1:1 mapping, in order to enable parallelisation. This plurality of PEs may be formed in a regular structure such as a grid, and a grid of PEs can be referred to as a processing grid. Connections are created between neighbouring PEs, i.e. PEs associated with nodes which neighbour each other in the decoding graph, via data links in the processing grid. These data links enable a PE to communicate, e.g. query and share data, with other PEs in the processing grid. In this way, data can be propagated through the network of PEs in the processing grid. However, these data links contribute to the complex nature of realising quantum decoders in hardware. For a successful distributed quantum decoder, the data links should be highly optimised and efficient, and should not impact the execution of the quantum decoding algorithm. In current implementations, many links are needed between PEs in order to realise distributed quantum decoders. A drawback with current implementations of distributed quantum decoders is that the processing grid is rigid and cannot be generalised to different decoding graphs. Each interpretation of the decoding problem represents a link between PEs in the distributed grid. If a different decoding graph is needed, the implementation of the physical processing grid needs to be changed in hardware. If a different processing grid configuration is needed, it is difficult and time consuming to physically re route the data links. Current known implementations of data links between hardware modules use known interface protocols, such as SPI, I2C, AXI, AXI4, AXI4-Lite etc. These protocols use significant resources during physical implementation. This affects the overall utilization of an FPGA and directly impacts the cost of an ASIC. Also, scaling becomes an issue for distributed quantum decoders as the number of processing elements scale with increasing code distance. In other words, the minimum weight of an undetectable error increases with the number of processing elements. As the number of PEs increase, the number of data links in the hardware increase. Increasing the number of links in hardware leads to complications in hardware design and implementation, including high spatial overhead, complicated designs and spatial inefficiencies. These all further feed into the difficulty of having to physically reroute the links each time a new decoding problem is to be solved using hardware. Furthermore, the number of data links in the hardware impacts the power budget of the implemented hardware. Therefore, a large number of data links in the hardware undesirably leads to a larger power budget. The present application seeks to address these and other disadvantages encountered in the prior art by providing an improved quantum error correction method for decoding a quantum error correction code from a quantum computer, and an improved apparatus and system suitable for implementing such a method. Summary According to an aspect, a computer-implemented method is provided, for decoding errors in a quantum computer system. The quantum computer system comprises a decoder apparatus and a register of quantum devices. The decoder apparatus comprising a plurality of distributed processing elements, PEs. The method comprises: performing, by the plurality of PEs, a distributed decoding algorithm. The distributed decoding algorithm requires communication between linked PEs of the plurality of distributed PEs. The communication between linked PEs comprises: sending, from a first PE to an intermediate PE, a data bundle. The data bundle comprises an indicating portion which indicates a destination PE, and an information portion comprising information intended for the destination PE. The communication between linked PEs further comprises directing, by the intermediate PE, the data bundle to the destination PE based on the indicating portion. Communication from a first PE to a destination PE via an intermediate PE allows for data to be routed through data links that exist in hardware when there is no single data link existing between the first PE and destination PE. This routing allows for a reduced number of data links between PEs. Reducing the number of data links between PEs allows for simpler hardware and an improved spatial overhead. The ability to route data bundles through a fewer number of data links allows for improved adaptability of hardware. A reduced number of data links is also associated with a reduced cost and a reduced power budget. The reduction of data links further makes the hardware realisation of distributed decoding algorithms more scalable. As there is a reduction in the number of physical resources and therefore a reduction in complexity, larger scale decoding problems can be realised more easily. Optionally, the intermediate PE is a first intermediate PE, and the directing comprises: sending, by the first intermediate PE, the data bundle to a second intermediate PE based on the indicating portion. The directing may further comprise directing, by the second intermediate PE, the data bundle to the destination PE based on the indicating portion. Furthermore, there may be a third intermediate PE, and so on. Optionally, the information portion comprises a query for the destination PE, and the communication between linked PEs further comprises: receiving, by the destination PE, the data bundle. The communication may further comprise determining, by the destination PE, that the indicating portion indicates the destination PE. The communication may further comprise forming a second data bundle. The second data bundle may comprise a second indicating portion which indicates the first PE and a second information portion which comprises second information intended for the first PE, wherein the second information comprises a response to the query. Optionally, the first PE is directly coupled to the intermediate PE via a data link, but is not directly coupled to the destination PE via a data link. Optionally, each PE is connected to multiple other PEs of the plurality of PEs via respective ports. Each PE may comprise its own dedicated memory storing a routing table. For a particular PE, the routing table may map possible destination PEs to ports of the particular PE which should be used when directing data bundles to the possible destination PEs. A port connects a data link to a particular PE. Each PE is connected to multiple other PEs of the plurality of PEs via respective ports. Therefore, a port is used for the communication between two PEs. A port has an associated identifier assigned to uniquely identify a connection endpoint of a data link to a particular PE. Optionally, the communication between PEs further comprises receiving, by the intermediate PE, the data bundle. The communication may further comprise identifying, by the intermediate PE, the destination PE based on the indicating portion. The communication may further comprise determining, by the intermediate PE and based on the routing table stored in the dedicated memory of the intermediate PE, a port associated with sending the data bundle to the destination PE. The communication may further comprise directing, by the intermediate PE, the data bundle to the destination PE via the determined port. Optionally, the data bundle further comprises a source portion which indicates the first PE, wherein the first PE created the data bundle. Optionally, the method further comprises receiving, at the decoder apparatus, syndrome data representative of an error state of the quantum devices in the register of quantum devices. The syndrome data may comprise a plurality of defects, wherein the syndrome data is representable as a decoding hypergraph comprising a plurality of nodes connected by hyperedges representing error mechanisms associated with the plurality of quantum devices. Each PE of the plurality of distributed PEs may be associated with one or more nodes of the decoding hypergraph. Performing the distributed decoding algorithm may comprise determining, by the decoder apparatus, a correction for the error state. As each of the distributed PEs may be associated with one or more nodes of a decoding hypergraph, the data links connecting PEs may be associated with the edges between nodes in a decoding hypergraph. A specific configuration of data links between PEs can therefore be associated with a single decoding hypergraph. In the absence of routing data through an intermediate PE, the data links between PEs would need to physically be reconfigured each time a new decoding hypergraph is to be realised in hardware decoders. The ability to route through an intermediate PE allows for different decoding hypergraphs to be configured in a single decoding apparatus, without needing to physically take apart and reconfigure the data links. This leads to simpler and more versatile decoding apparatus that can decode more than a single type of hypergraph. Furthermore, time does not need to be spent physically reconfiguring the data links every time a different decoding hypergraph needs to be realised. Optionally, each PE of the plurality of PEs comprises its own dedicated memory. Neighbouring PEs may be PEs associated with two nodes which neighbour each other in the hypergraph. The communication between linked PEs may comprise each PE reading data from and / or writing data to the dedicated memory of at least one of its neighbouring PEs. The use of "neighbouring" in "neighbouring PEs" refers to the nodes associated with the PEs being neighbours in the decoding hypergraph. "Neighbouring PEs" does not refer to PEs that are next to each other in the processing grid. However, PEs that are next to each other in the processing grid may be associated with neighbouring nodes in the decoding hypergraph. Therefore, neighbouring PEs can be PEs that are next to each other in the processing grid. Optionally, the dedicated memory of each PE stores attributes relating to the one or more nodes associated with the PE. Optionally, the first PE and the destination PE are neighbouring PEs. Optionally, the distributed decoding algorithm is a clustering algorithm, and the clustering algorithm grows and merges clusters of nodes based on the number of defects in each cluster until a final cluster state is reached, The correction for the error state may be based on the final cluster state. Optionally, the clustering algorithm comprises a growth stage. The growth stage may comprise one or more PEs updating a growth parameter associated with at least one of its associated nodes by one unit up to a maximum growth parameter value, and storing the updated growth parameter in its dedicated memory. Optionally, the clustering algorithm further comprises a merge stage, wherein the information portion comprises a query seeking to determine a growth factor of a node associated with the destination PE. Optionally, the clustering algorithm further comprises a sync stage. The information portion may comprise a query seeking to determine an activity status and / or a busyness status of a node associated with the destination PE. Optionally, performing the distributed decoding algorithm further comprises measuring a logical state encoded in the quantum devices of the quantum computer to obtain a logical state measurement. Performing the distributed decoding algorithm may further comprise applying the correction for the error state to the logical state measurement. According to another aspect of the present invention, a decoder apparatus is provided, comprising a controller, a plurality of distributed processing elements, PEs, and computer memory. The decoder apparatus is configured to perform any of the methods set out above or disclosed herein. According to another aspect of the present invention, a quantum computer system is provided, comprising a register of quantum devices and the decoder apparatus according to any of the methods set out above or disclosed herein. Figures Specific embodiments are now described, by way of example only, with reference to the drawings, in which: Figures la-e show an example of a process for decoding a patch of surface code using a clustering decoder; Figure 2 is a flowchart depicting a local clustering decoder algorithm according to the present disclosure; Figure 3a h show an example of a process for decoding a patch of surface code using a local clustering decoder algorithm; Figures 4a-d each show a graph depicting a processing grid of processing elements; Figure 5 is a graph depicting ports between processing elements; Figure 6 depicts example routing tables for part of the processing grid of Figure 4b; Figure 7 depicts example routing tables for part of the processing grid of Figure 4c; Figure 8 depicts example routing tables for part of the processing grid of Figure 4d; Figure 9 is a graph depicting a method according to the present disclosure; Figure 10 is a graph depicting a method according to the present disclosure; Figure 11 is an example embodiment of a quantum computer system; Figure 12 is an example embodiment of a computer program product. Detailed Description In overview, and without limitation, the application discloses a method for decoding errors in a quantum computer system. Quantum devices, for example qubits, associated with quantum computer systems are inherently noisy and prone to error. Syndrome measurements do not disturb quantum information encoded on the quantum devices, but the resulting data can be used to identify and diagnose errors. Syndrome data can be represented on a decoding hypergraph with nodes and hyperedges. It is known to use decoding algorithms on the syndrome data, for example using clustering algorithms to grow and merge clusters of nodes based on the number of defects in each cluster until a final cluster state is reached. As described above, it is beneficial to use distributed decoding algorithms in order to improve the speed and efficiency in which errors can be decoded. Distributed decoding algorithms may be implemented by a plurality of processing elements (PEs) in an ordered arrangement of PEs, e.g. in the form of a processing grid, and a controller can execute a plurality of PEs in parallel at one or more steps of the distributed decoding algorithm. PEs may be linked to one or more other PEs via data links in order to facilitate the communication between PEs. In approaches of the present disclosure, while a distributed decoding algorithm is performed, communication between PEs which are not directly linked to one another may be achieved by sending information via at least one intermediate PE. When sending information from a first PE to another PE that is not directly connected to the first PE by a data link, the information is routed through the physical data links that exist in the hardware. This is achieved by the information being sent via a data bundle, which includes not only the information itself, e.g. a query or an answer to a query from another PE, but also an indicating portion which indicates a destination PE where the information should be routed to. In this way, the data bundle can be routed through the plurality of PEs to the destination PE, and there is no need for the 'source' PE and the 'destination' PE to be physically connected via a direct data link. Methods of the present disclosure improve the spatial overhead and reduce the complexity of design of the hardware. Fewer data links need to be present in the hardware compared to prior methods. This leads to simpler hardware which, depending on the implementation, may have a smaller footprint. The reduction in the number of data links is also associated with a reduced cost and a reduced power budget. In implementations of distributed decoding algorithms that require a large number of PEs, this improvement over prior art methods becomes more significant. As the number of PEs needed to implement a distributed decoding algorithm increases, for example for implementing a large decoding graph, this improvement over prior methods becomes even more significant. In addition, the methods of the present disclosure allow an improved flexibility and adaptability in design of the hardware. Physical data links do not need to be rerouted whenever different decoding graphs need to be implemented, and therefore many different decoding graphs can be realised in just one design of the hardware. This is opposed to prior methods, in which hardware would need to be redesigned and data links would need to be physically rerouted each time a different decoding graph were to be implemented. Several terms and concepts will be discussed in the present application, and though the skilled person will be familiar with this terminology and these concepts, the following section serves to provide additional context to the reader. A quantum computing system (also referred to herein as a quantum computer or quantum computer system) is a computing system that exploits quantum mechanical phenomena (i.e. using quantum devices). The quantum devices may be any quantum devices capable of storing quantum information (i.e. any devices suitable for encoding information using quantum computational states). The quantum devices may be qubits. Alternatively, the quantum devices may be other devices capable of storing quantum information, such as qudits or qutrits. While the description herein will primarily refer to qubits, any reference herein to qubits should be understood to also encompass other types of quantum devices unless explicitly stated otherwise. Building a useful fault-tolerant quantum computer will require quantum error correction hardware that can receive and process enormous amounts of error information (i.e. syndrome data) in real-time almost instantaneously. A delay in decoding can lead to the creation of a backlog that grows exponentially with the size of the computation, which will ultimately lead to failure of the quantum computation. The speed of the decoder acts as a bottleneck to the number of qubits in a quantum error correction code (and therefore also as a bottleneck to reducing logical error rates). Improvements to decoding hardware and algorithms help to prevent this backlog, thereby enabling quantum computers with higher numbers of qubits and lower error rates because faster decoders can handle quantum error correction codes involving more data qubits, and using more data qubits leads to a reduction in logical error rates when performing fault-tolerant quantum computation. Herein, the term "hardware" may be used interchangeably with terms such as "hardware decoder" and "quantum error correction hardware". Quantum error correction codes generally involve decoding a "syndrome", which can be considered to be a signature associated with an error state of the physical qubits in the code (two different errors can potentially have the same syndrome). A "decoder" is then used to identify an error which could have caused the syndrome (or possibly just a correct operation that can be used to correct the logical qubit states encoded in the code e.g. a single bit representing whether the eventual logical measurement outcomes need to be flipped). Decoding hypergraphs (especially decoding graphs) are used in many error correction codes (such as topological error correction codes including the surface code) to facilitate decoding of the syndrome by grouping "defects" in the syndrome (these defects generally provide an indication of end points of chains of errors on physical data qubits in the error correction code). A decoding hypergraph is a hypergraph (in the mathematical sense) comprising hyperedges representing error mechanisms, and nodes (or vertices) representing differences in successive syndrome measurements (or more generally, a decoding hypergraph comprises nodes representing detectors, which are measurement results that sum to zero (e.g. modulo 2 sum) during perfect (i.e. error-free) operation of the quantum computing system). The decoding hypergraph may have one or more boundaries, which involve hyperedges extending beyond the hypergraph (e.g. to one or more virtual boundary nodes), i.e. the decoding hypergraph may be a sub-hypergraph of a larger hypergraph including the virtual boundary node(s)). Conventionally, some error correction literature has referred to "rough" boundaries and "smooth boundaries". However, the "smooth" boundaries in such literature are not actually boundaries in the above sense, and they will not be referred to as boundaries in the present disclosure. Accordingly, the boundaries referred to herein are synonymous with the "rough" boundaries in such literature. Clustering algorithms decode syndromes by clustering defects into groups. A cluster of decoding graph edges is formed around each defect (defects are located at a subset of nodes of the decoding graph), and these clusters are grown by including additional edges until all defects are included in a cluster containing an even number of defects (or the cluster touches a boundary of the decoding graph), with overlapping clusters being merged after each growth stage. Correction(s) to the encoded logical state can then be determined based on the clustering of defects. Since an objective of this category of quantum error correction approaches is to correct errors by grouping defects, some algorithms seek to decode syndromes by clustering defects. An example of this approach is described in (Delfosse, N. and Nickerson, N.H. (2021) 'Almost-linear time decoding algorithm for topological codes', Quantum, 5, p. 595. doi:10.22331 / q-2021-12-02-595). Every 'odd' cluster, i.e. every grouping of nodes (or 'vertices') that is associated with an odd number of defects, grows until it becomes an "even" cluster, for example a cluster associated with an even number of defects. The number of defects in the cluster is a primary factor which affects the "parity" of a cluster. Each node which is part of an odd cluster grows outward until it encounters another cluster, at which point the clusters merge. If the parity of the new, merged cluster is even, then it stops growing. Otherwise, it continues to grow. This continues until all clusters have an even parity. There may be other criteria which cause a cluster to stop growing, such as if a cluster touches a boundary of the decoding graph. Next steps can then be determined based on the decoded syndrome. For example, correction(s) to the encoded logical state can be determined based on the clustering of defects. This overview has been simplified for brevity and to aid quick understanding, and the limitations of this simplified overview will be understood by the skilled person. A syndrome (also referred to as syndrome data) is a collection of values (e.g. measurement values, generally based on qubit measurements, in particular syndrome qubit measurement) representative of an error state of physical data qubits in the quantum computer. The syndrome may also include decoding hypergraph location information for each syndrome value - e.g. a coordinate or index value. Syndrome data may be obtained by measuring a plurality of syndrome qubits (e.g. surface code stabiliser measurements). The decoder may receive the syndrome data as raw (e.g. analogue) measurement data, or the syndrome data may be pre processed (e.g. processed into digital form by a control system). A defect (also referred to as an excitation or measurement event) generally represents the end of a chain (or hyperchain) of errors in the decoding hypergraph (the chain of errors may span both space-like and temporal dimensions of the decoding hypergraph). Defects are non-trivial syndrome values, and they may correspond to a change in value of a syndrome qubit measurement outcome between successive rounds of syndrome measurement. A decoding system (also referred to herein as a decoder or quantum error decoding system) is a classical computing system that decodes syndromes and provides one or both of (i) possible error locations (i.e. which data qubits may have experienced an error), and (ii) a correction for the qubit error state. It is possible to determine a correction during decoding without determining error locations, and the correction may be a single bit representing whether a logical error has occurred. The correction can generally be tracked by a classical computer (e.g. by the decoder or a control system) and does not generally need to be applied to the quantum devices. The decoder may be a dedicated hardware device (e.g. implemented using an FPGA or ASIC or similar) or it may be a software component implemented using a CPU. The quantum error correction code may be a surface code (e.g. planar code) error correction procedure. Alternatively, the quantum error correction code may be any other error correction code that utilises a decoding hypergraph (e.g, a decoding graph), such as other topological quantum error correction codes. The decoding hypergraph may be a decoding graph, and the hyperedges may be edges. A hypergraph is a generalisation of a graph in which edges ("hyperedges") can be connected to more than two nodes (graphs are a specific type of hypergraph in which each edge connects to two nodes). The methods of the present invention apply equally to decoding hypergraphs. Accordingly, any reference herein to decoding graphs and edges should be understood to also encompass decoding hypergraphs and hyperedges respectively. The quantum computing system (e.g. a control system of the quantum computing system) may be further configured to measure a logical state encoded in the quantum devices and apply the correction to the measured logical state (the correction may be applied at the control system, at the decoding system or at some other subsystem of the quantum computing device, such as a device operating at the algorithmic / application layer of the quantum stack). The clusters may also be referred to as sets / groups / collections, or any similar term that refers to a grouping of defects. The quantum error correction method may be a surface code (e.g. planar code) error correction procedure. Alternatively, the quantum error correction method may be any other error correction procedure that can be decoded by grouping defects on a decoding graph, such as other topological quantum error correction codes. One skilled in the art will appreciate that the details of how the correction is identified, and how it is based on the clusters of defects, will depend upon the configuration of the error correction method in question. For example, identifying the correction for the error state may comprise: identifying a logical operator for the quantum error correction method involving physical qubits of the quantum computer system that are associated with the boundary of the decoding graph; determining a parity of a total number of clusters that the logical operator intersects that contain an odd total number of defects, wherein an even parity indicates that the logical operator is in a correct logical state and an odd parity indicates that the logical operator is in an incorrect logical state. The parity of a cluster can be described in terms of different bases, for example a parity can be discussed as being even / odd, or 0 / 1. These definitions may be used interchangeably herein. Parity can be discussed in terms of nodes and clusters, and may be used somewhat interchangeably. Initially, the parity of a node, and therefore the parity of its cluster, is dependent on whether the node is a defect or not. For example, a node that is a defect will have an odd parity and a node that is not a defect will have an even parity. As discussed above, the distributed decoding algorithm of the present disclosure may be a clustering algorithm. A clustering algorithm grows and merges clusters of nodes based on the number of defects in each cluster until a final cluster state is reached. The correction for the error state can therefore be determined based on the final cluster state. Figures la-e depict an example of a process for decoding a patch of surface code using a clustering decoder. The aim of clustering decoders is to cluster defects together into a set of decodable clusters. Several different variants of clustering algorithms exist, and one skilled in the art will appreciate that other clustering decoding algorithms may be used instead of or as well as that shown in Figures la-e. Figures la-e depict decoding graphs 110, 120,130, 140 and 150. Figures la-e depict stages of the clustering process, where Figure la is the first stage and Figure le is the last stage of this example clustering process. Conventional decoding algorithms primarily focus on error mechanisms that leave qubits in a computational basis state (e.g. some superposition of the |0) and |1) states), such as bit-flip and phase-flip errors. The circles on the decoding graphs 110,120,130, 140,150 depict nodes of the decoding graph. The nodes of the decoding graphs 110,120, 130, 140, 150 correspond to syndrome qubits. With no errors, syndrome qubits are in the |0) state, as illustrated by the empty circles in Figures la-e. The hashed circles in Figures la-e correspond to defects, i.e. syndrome qubits in the |1) state. In Figures la-e, the defects are labelled as 112a-f in the decoding graphs. The numbering of the rows (from 0-6) and columns (from 0-7) of the nodes on the decoding graph is included for ease of reference. The edges of the decoding graphs 110, 120, 130, 140, 150 correspond to data qubits, with weights determined by the error probability. The decoding graphs have some edges that only connect to a single node; these edges represent boundaries of the decoding graph. The boundaries can conceptually be considered to all connect to one or more virtual nodes / boundary nodes. One skilled in the art will appreciate that the nuances of the decoding graph will depend upon the error correction code being implemented, and that some decoding graphs (e.g. those for toric codes) do not have boundaries. The concept of boundaries can be extended to hyperedges, in which hyperedges at a boundary may connect to a virtual node in addition to one or more nodes of the decoding hypergraph. While the graphs in Figure la-e can be used as basic decoding graphs, it is also possible to use more complex decoding graphs, for example with an extra dimension representing time, in which there is not necessarily a one-to-one correspondence between data qubits and decoding graph edges. One skilled in the art will appreciate that the physical qubits do not necessarily need to be physically arranged as shown in Figures la-e. Figure la shows a first graph 110, depicting an example decoding graph. In this example, there are 6 defects 112a-f in the decoding graph. Decoding algorithms such as clustering algorithms may be used to decode the defects 112a-f. The illustrated clustering algorithm begins by placing each defect 112a-f in its own cluster. The defects 112a-f may be referred to as the first defect 112a, second defect 112b, third defect 112c, fourth defect 112d, fifth defect 112e and sixth defect 112f. This naming convention is used for ease of reference, and not indicative of any order associated with the defects. Figure lb shows a second graph 120, depicting the result of a first stage of growth using the clustering algorithm. In graph 120, each cluster has grown out by a half edge in each of the four directions of the decoding graph. The growth of each cluster is depicted by bold black lines along the edges of the graph. Each of these clusters has grown due to the presence of an odd number of defects in each cluster, specifically one in each cluster, in this case. In Figure lb, by growing each cluster out by half-edges of the graph, two pairs of clusters have connected; the cluster containing the first defect 112a is in contact with the cluster containing the second defect 112b, and the cluster containing the third defect 112c is in contact with the cluster containing the fourth defect 112d. Any clusters that are touching will merge into a larger cluster, such that there is a cluster containing the first defect 112a and second defect 112b, and another cluster containing the third defect 112c and fourth defect 112d, in this example. In each iterative round of the clustering algorithm, each cluster containing an odd number of defects may extend outwards by a half-edge of the graph, dependent on whether or not the cluster is connected to a boundary. Each cluster containing an even number of defects stops growing. As both of these clusters now contain an even number of defects, they will stop growing. As the clusters containing the fifth defect 112e and sixth defect 112f remain isolated (containing an odd number of defects), they will keep growing. Clusters with an even number of defects can be said to have an even parity, and clusters with an odd number of defects can be said to have an odd parity. Figure lc shows a third graph 130, depicting the result of a second stage of growth using the clustering algorithm. As the clusters containing the fifth defect 112e and sixth defect 112f contained an odd number of defects in graph 120, in the second growth stage both of these clusters grew by half an edge in each of the four connected edges of the decoding graph. After the second stage of growth, the cluster containing the fifth defect 112e still only contains one defect. However, the cluster containing the sixth defect 112f has reached the boundary at point (0, 2) on the decoding graph. A cluster that has reached a boundary will not grow further, and therefore the cluster containing the sixth defect 112f will stop growing. Figure Id shows a fourth graph 140, depicting the result of a third stage of growth using the clustering algorithm. After the third stage of growth, the cluster containing the fifth defect 112e touches the cluster containing the third defect 142c and fourth defect 142d. Therefore a larger cluster is formed containing the third defect 112c, fourth defect 112d and fifth defect 112e. As this cluster has an odd number of defects and is not touching the boundary, this cluster will keep growing. Figure le shows a fifth graph 150, depicting the result of a fourth stage of growth using the clustering algorithm. After the fourth stage of growth, there are two clusters in the decoding graph 150. Both of the clusters in the decoding graph 150 are "neutral" clusters (which may also be referred to as stable clusters): a first neutral cluster 152 and a second neutral cluster 154. Each of the two remaining clusters is "neutral" due to having an even number of defects and / or having met the boundary. The first neutral cluster 152 contains the third defect 112c, fourth defect 112d, fifth defect 112e and sixth defect 112f. This first cluster 152 is formed due to the cluster containing the third defect 112c, fourth defect 112d and fifth defect 112e meeting the cluster containing the sixth defect 112f. The second neutral cluster 154 contains the first defects 112a and the second defect 112b. The second neutral cluster 154 has not grown since the first stage of growth, depicted in Figure lb. The first neutral cluster 152 contains 4 defects and the second neutral cluster 154 contains 2 defects. As the first neutral cluster 152 and the second neutral cluster 154 both contain an even number of defects, both the first neutral cluster 152 and the second neutral cluster 154 stop growing. It can also be noted that the first neutral cluster 152 is also connected to the boundary and this alone could be enough to make the cluster "neutral", regardless of whether the cluster contains an odd or even number of defects. As all the defects are in "neutral" clusters, the clusters can now be decoded by any conventional means. For example, the error can be decoded by defining a logical operator involving edges at a boundary of the decoding graph (e.g. the boundary edges on either the left or the right side of the decoding graph in Figure 4a-e) and counting how many clusters this logical operator intersects that contain an odd total number of defects. If the parity of this count is even, then the defined logical operator is considered to be free from error. However, if the parity is odd then the defined logical operator is considered to be in an error state, and its logical value should be flipped when it is measured. In this way, a single bit can be used to track the error state of the defined logical operator (i.e. it is not necessary to determine physical qubit error locations and physical qubit corrections). Upon using prior art approaches to cluster decoding, data conflicts can occur when processing elements associated with nearby or neighbouring nodes attempt to access the same information. For example, with reference to the example described above, when the cluster containing the first defect 112a met the cluster containing the second defect 112b, the edges of the two clusters may be growing out at the same rate, and therefore each cluster may require to 'know' about the other cluster's presence at the same time. With reference to figures 1-e, and assuming a 1:1 mapping between processing elements (on the decoding apparatus) and nodes (on the hypergraph), it is possible that, as the clusters grow using the prior algorithm, a first processing element associated with a first node may have requested information from a second, neighbouring processing element associated with a second node, at the same time the second processing element made the same or a similar request for information to the first processing element. Because the hardware implementing the prior art method must account for this possibility, separate input and output connections between each neighbouring processing element are required so that a node can both make queries and receive them at the same time. In addition, while the first processing element requests information from the second processing node, it is also possible that a third processing element associated with a third node requested information from the second processing node at the same time. Because the hardware implementing the prior art method must account for this possibility too, each processing element must have sufficient memory requirements to enable a request from a node to be stalled. For example, in this scenario, the second processing element must have sufficient memory to stall the request from the third processing element while the request from the first processing element is dealt with. While reference has been made primarily to requests for information, processing elements associated with neighbouring nodes may also write (not just read) information in each other's memories while performing the decoding algorithm. Therefore, the possibility arises that a first processing element may be stalled in its attempt to update information in a neighbouring second processing element's memory, while a request from a third processing element reads that same information. This scenario stalls the ability of nodes to update their neighbouring nodes with correct information, which in turn enables incorrect information to be passed through the network of nodes, further slowing down the decoding process. Therefore distributed decoding algorithms which make use of parallelisation of PEs can be used to implement conflict-free scheduling. An example of a parallelised algorithm that can be used in this conflict-free scheduling method is a local clustering decoder (LCD) algorithm. LCD is a distributed parallelised clustering decoder. Figure 2 depicts, at a high-level, the stages of the LCD algorithm 200. The flowchart of figure 2 could also be described as a state transition diagram. The new algorithm may be described as a parallelised LCD algorithm. The algorithm 200 comprises several stages, including an initialisation or initialising stage 205, a growing or growth stage 210, a merging stage 215, a picking stage 220, a syncing stage 225 and a stopping or exiting stage 230. The algorithm 200 comprises several steps, where each step is associated with one of the stages depicted in Figure 2. Each processing element is configured to perform the steps of algorithm 200 in respect of its associated node or nodes, such that all of the processing elements perform the LCD algorithm collectively, and together. Examples of code which could be used to implement each stage of the algorithm 200 are provided below, on the final pages of the description. The algorithm comprises several conceptual similarities with the algorithm described above with respect to figures la-e, and reference to the accompanying description of figures la-e may aid understanding of the algorithm 200. Each step of the algorithm 200 may be performed by one or more nodes at any given time. The description of the algorithm 200 may refer to a node in question, or a 'particular' node, where the node in question may be any single node in the decoding graph at a point in time. Also, the description of the algorithm 200 may sometimes refer to a node taking action, such as a node checking information with a neighbouring node. The skilled person will understand that this is shorthand for the processing element(s) associated with the node(s) taking the action. In addition, the present disclosure may refer to a node "growing", or "merging with its neighbour", and the like. Again, the skilled person will understand that this is shorthand for the associated processing elements performing actions such as updating a growth parameter associated with a particular node, or updating a cluster index associated with a particular node, and the like. In order to obtain parallelisation of a distributed decoder, PEs can be grouped. In particular, the PEs are grouped into a plurality of groups of PEs. These groups of PEs perform the steps of each stage of the clustering algorithm sequentially and successively, such that each group moves through the stages of the clustering algorithm. Groups of PEs may perform the steps of each stage of the clustering algorithm sequentially; for example, in a first stage of the clustering algorithm, the PEs in a first group of PEs may perform one or more steps associated with the first stage, then PEs in the second group perform the one or more steps associated with the first stage, then PEs in the third group perform the one or more steps associated with the first stage, and so on until each group of PEs has performed the one or more steps. In a subsequent second stage, the PEs in the first group may perform one of more steps associated with the second stage, then PEs in the second group may perform the one or more steps associated with the second stage, and so on. In this way, conflicts between neighbouring nodes can be avoided. The PEs are grouped such that conflict is avoided between neighbouring nodes (i.e. nodes connected to each other by one hyperedge on the hypergraph). For the effects of the grouping to be maximised, the groups should be formed such that no node has a neighbouring node which is associated with a different PE, where those PEs are in the same group. In other words, for any particular node on the hypergraph, the neighbouring nodes of the particular node must be either: i) associated with the same PE as that associated with the particular node (in which case the PE can schedule tasks for the neighbouring nodes to avoid conflict, for example by assigning each node in its 'batch' of nodes the steps of the algorithm successively as will be explained); or ii) associated with a different PE to the PE associated with the particular node, where these PEs are in different groups (in which case, since the groups of PEs perform tasks successively rather than at the same time, the neighbouring nodes will never send conflicting requests to one another). Further to point i), these neighbouring nodes form part (or all) of the "batch" of nodes associated with that PE, as will be explained. In some implementations of the present disclosure, each of the plurality of PEs is associated with a respective batch of nodes of the decoding hypergraph, where each batch contains multiple nodes. In this implementation, each PE performs one or more first steps of the clustering algorithm by performing them in respect of each of the nodes in its batch of nodes successively. In other words, each PE with a batch of nodes performs tasks in respect of each of its associated nodes in sequence. In this way, conflict between nodes in the same batch is avoided. Further to point ii), according to the present disclosure, neighbouring PEs (i.e. PEs associated with nodes which neighbour one another on the hypergraph) can be coupled via a bidirectional link. Figure 2 depicts an algorithm 200 for clustering nodes in a decoding hypergraph or graph. The growth of clusters on a decoding graph is often described in terms of tree growth, where a cluster may be referred to as a "tree". Continuing this analogy, each cluster has a "root" node, whereby all nodes in a cluster are descended from the root node. As a cluster grows, the root node may become the "parent" to other nodes in the cluster, as more nodes are added to the edge of the cluster. The edge of the cluster may also be known to the skilled person as the "boundary" of the cluster. Similarly, a new node added to a cluster may be described as a "child" node to a parent node. Therefore a large cluster will exhibit a series of child-parent relationships along the branches of the cluster tree, all the way back to the root node. If a child node has an odd parity, it may be described herein as an odd child. At the beginning of the algorithm 200, each node is the root of its own cluster tree, as there is one node per cluster. As a cluster grows, the root of the cluster may change, for example upon merging with one or more other clusters. Clusters may be associated with an activity status. The activity status of a cluster is either active or inactive. An active cluster is a cluster that comprises an odd number of defects and is not touching a boundary of the decoding graph. A node is active if its cluster is active. Therefore, an active cluster and an active node may be used somewhat interchangeably. A cluster is inactive if there are an odd number of defect nodes in the cluster or the cluster meets the boundary of the decoding graph. When a cluster is inactive, all the nodes within that cluster will be inactive, such that all the nodes in the cluster will stop growing. Therefore an inactive cluster and an inactive node may also be used somewhat interchangeably. A node that is a defect will initially be active and a node that is not a defect will initially be inactive. Therefore, the activity of a node, and hence a cluster, may be related to the node's parity. Processing elements and / or nodes may be deemed busy or not busy. Multiple processing elements may be connected to a controller, in which the controller controls the processing of each processing element it is connected to. For example, the controller instructs processing elements to be in certain stages of the method 200. A processing element becoming busy is used to flag to the controller that something has changed. In the situation where each processing element is associated with a plurality of nodes, a processing element is busy when at least one of its nodes is busy. For example, a node is busy if its data changes during the merging or syncing stages, as described below. If a node is busy, the controller must re-run the current stage to allow the other processing elements to process the change that has occurred to the node. In implementations of the present disclosure, one node may be assigned to each processing element, e.g. in a 1:1 mapping. Alternatively, multiple nodes may be assigned to each processing element. As set out above, the multiple nodes assigned to a processing element may be referred to as a "batch" of nodes. Equivalently, similar words such as "group" may be used to refer to the multiple nodes assigned to a processing element. When multiple nodes are associated with each processing element, the stages of the method 200 may be performed with an extra outer loop, such that each stage of the method 200 is performed for each node in the batch. This is best appreciated by inspection of the code listings provided toward the end of this description. At step 205, the LCD algorithm is in the "initialising" stage. The initialising stage may include setting up initial parameters associated with the decoding hypergraph used in the algorithm 200. Each PE comprises its own dedicated memory, and this memory is used to store attributes relating to the one or more nodes associated with the PE. For PEs which have a batch of nodes, the dedicated memory is used to store information associated with each node in the batch. The attributes associated with each node may comprise one or more of an index of the node, a cluster index, a growth parameter, a defect flag indicating whether the node is associated with a defect; an activity flag indicating whether the node and / or a cluster to which the node belongs is active; a parity flag indicating a parity of the node, and a busyness flag indicating whether the node is busy, and the like. Stage 205 comprises initialising these attributes to starting values. For example, step 205 may comprise assigning each node a node index. At step 205, each node in the decoding graph is assigned to its own cluster, so that each node is initialised with its own cluster index. Therefore at step 205, the node index and cluster index may be the same. The parent of each node may be initialised to be the node itself. In other words, each node is initialised to be the root of its own singleton cluster. In an example, non-limiting implementation, attributes for each node, and their initialised values, may be as follows: nindex The index of the node. Must be in [2, N), where N is the number of nodes in the decoding graph. The indices 0 and 1 are reserved for the boundary nodes on the left and right-hand side of the patch cindex The index of the node's cluster. Must be in [0, N), where N is the number of nodes in the decoding graph. Initially, node.cindex = node.nindex parent The parent of the node in the tree of its cluster. Must be in [0, N), where N is the number of nodes in the decoding graph. Initially, node.parent = node Growth parameter The degree to which the node has grown. Must be in [0, 2], where 0 represents un-grown, 1 half-grown and 2 fully-grown. Initially, node.growth = 0 defect True if the node is defective. Must be in [0, 1], since this is a Boolean flag. Initially, node.defect = syndrome[node.nindex] active True if the node is active. Must be in [0, 1], since this is a Boolean flag. Initially, node.active = node.defect parity True if the node is odd. Must be in [0,1], since this is a Boolean flag. Initially, node.parity = node.defect busy True if the node is busy. Must be in [0,1], since this is a Boolean flag. Initially, node.busy = 0 As will be appreciated from the following description, algorithm 200 involves neighbouring PEs reading data from and / or writing data to the dedicated memory of their neighbouring PEs, and this comprises reading an attribute and / or updating an attribute in the dedicated memory of the neighbouring PE. The dedicated memory of each PE stores attributes relating to the one or more nodes associated with the PE. At stage 210, the algorithm 200 is in the "growing" stage. In the growing stage, active nodes (i.e. those nodes in an active cluster) which haven't already reached a maximum growth parameter value have their growth parameter increased. Therefore, at stage 210, the size of one or more clusters in the decoding graph grows. In the growth stage, a PE may update a growth parameter associated with at least one of its associated nodes by one unit, and store the updated growth parameter in its dedicated memory. This may only happen if the node is active. Active nodes form part of an active cluster, i.e. a cluster with an odd number of defects and which has not merged with one or more boundary nodes of the hypergraph. A "growth parameter" is used to define the degree of growth of each node in a cluster. In practice, the growth parameter may be considered to be quantity such as a radius around a node. The growth parameter value may take values which correspond to "ungrown", "half-grown", and "fully-grown", at any point in the growth cycle of a cluster. In this example, "ungrown" is a minimum value and "fully-grown" is a maximum value of the growth parameter value. The increase of the growth parameter value from ungrown to half-grown may be referred to as one unit, and similarly the increase from half-grown to fully-grown. In an example, the growth parameter can be increased from 0 (minimum value), to 1 (half-grown), to 2 (a maximum value). Once at the maximum value, the nodes cannot be "grown" any further. A half-grown growth parameter of a node may span half an edge along each of its incident edges of the decoding graph. A fully-grown growth parameter of a node may span a full edge along each of its incident edges of a hypergraph. Therefore if two neighbouring nodes are half-grown, they are connected by one fully grown edge on the decoding graph. If instead two nodes are separated by a distance of two edges on the decoding graph, they may be connected at the stage of both of those nodes having fully-grown edges. At stage 210, any active nodes that have an ungrown or half-grown growth parameters associated with them in the decoding graph will increase their growth parameter by a unit. Any active nodes with a fully-grown growth parameter will remain with a fully-grown growth parameter, and the edge will not continue to grow. At stage 215, the algorithm 200 is in the "merging" stage. In the merge stage, one or more PEs query the dedicated memory of a neighbouring PE to determine whether a sum of the growth parameters of neighbouring nodes meets a growth parameter threshold. Two inactive clusters, and therefore two inactive nodes, cannot be merged in the merge stage. However, the merge stage may be performed on inactive nodes in order to accurately propagate information. Only one cluster needs to be active for a merge to occur. In other words, an active cluster can merge with another active cluster, or with an inactive cluster. A growth parameter threshold is met when a fully-grown edge is formed between two neighbouring nodes. The growth parameter threshold may be met when the sum of the growth parameter values of two neighbouring nodes is equal to or greater than 2 units. For example, two neighbouring nodes would meet this criteria if they both had a half-grown edge, and were therefore connected. In the merge stage, different clusters are merged when the growth parameter threshold is met between neighbouring nodes in different clusters. When it has been determined, that two clusters should be merged, it then needs to be determined which cluster index to assign to the new cluster. Therefore, if the growth parameter threshold is met, the one or more PEs additionally determine whether one or more merging criteria are met. A purpose of the merging criteria is to determine which cluster index value to use for the new cluster. The one or more merging criteria are based on a cluster index value stored in the dedicated memory of the neighbouring PE. One or more of the 19 merging criteria may be based on the cluster index of the neighbouring node being less than the cluster index of the node in question. If the one or more merging criteria are met for a particular cluster, the one or more PEs merge the clusters by updating a cluster index in their dedicated memories for those nodes associated with the particular cluster. If the one or more merging criteria are not met, the cluster indices are not updated for those nodes. The cluster index of multiple nodes may be updated within the dedicated memory of the same PE within the merging stage. In summary, a node will (typically) adopt the cluster index of a neighbour connected to it by a fully-grown edge if the neighbour has a cluster index less than the cluster index of the node. At the beginning of stage 215, the status of the node in question may be set to not busy. At stage 215, clusters that met during stage 210 may merge into a single, larger cluster. Typically, two clusters will meet by one fully-grown edge and they will become one single, resultant cluster during the merge. Alternatively, three or more clusters may meet at the same time by a fully-grown edge between each cluster. Alternatively, two clusters could meet by two or more fully-grown edges at one time, and so on. As the clusters merge, the status of the node is set to busy. During the merging stage 215, the cluster index, parent or parity of a node can change. When two or more clusters merge, the cluster index of one or more of the clusters may change, such that the resultant cluster has one cluster index. In this example of the algorithm 200, the cluster index of the resultant cluster is taken to be the cluster index of the merging cluster that has the lowest cluster index. However, in alternative implementations, the resultant cluster may take on another cluster index, such as the largest cluster index of the merging clusters, for example. When the node in question is connected to a neighbour by a fully-grown edge, the cluster index of the node in question is updated to be the cluster index of the neighbour if the cluster index of the neighbour is lower than that of the node in question. The parent node of the node in question may then change as the clusters merge. The node in question may become a child node to the neighbouring node. In other words, the neighbouring node may become the parent node to the node in question as the clusters merge. Once the resultant cluster is formed, a root of the resultant cluster may be allocated. The root of the resultant cluster will be decided based on the parenthood relationships in the merging clusters. For example, the root node of the resultant cluster may be the root of the merging cluster with the lowest cluster index. The root of the new larger cluster may be another node, such as the root node of the merging cluster with the largest cluster index. The parity of the resultant cluster may be decided after the merge. Each child node in the cluster relays its parity onto its parent, if the child node in question is odd. This relaying of the parity may in practice be an addition modulo two. For example, for a child node with an odd parity (i.e. a parity of 1) and its parent node with an even parity (i.e. parity of 0), the child node may relay its odd parity such that the child node has a parity of 0 and the parent node has a parity of 1. This operation will not be performed for the node which is the root of the cluster, as the root node may be defined as its own parent node. As data is being changed in this process, the node in question is set to busy when relaying the parity information to its parent. This relaying of parity information is repeated for each node within the cluster until the parity of each child node in the cluster is even. This process may be repeated multiple times for each node. For example, if at least one child node in the resultant cluster starts with an odd parity and therefore relays this parity information, this process will need to happen at least twice for each node. This is because the odd parity child node will be in the busy state. Each node in the cluster will then need to be checked again until all of the child nodes are not busy, in order to continue to the next stage. The parity of the root node will therefore represent the parity of the cluster. At the end of the merging state, the parity of each cluster will be equal to the parity of the root node, i.e. the node with the lowest index in the cluster. The merging stage 215 may involve communication between PEs in order for PEs to query and send information to each other. For example, during the merging stage 215, one PE may communicate the parity of a child node associated with that PE to PE associated with its parent node. At stage 220, the algorithm 200 is in the "picking" stage. In the picking stage, one or more PEs update the activity of the root node associated with one or more clusters formed by one or more of their associated nodes in their dedicated memories. The parity of the root node of a cluster determines the activity of the cluster. If the root of the resultant cluster has an odd parity, the one or more PEs put the root node associated with this resultant cluster into an active state. Therefore this resultant cluster is said to be active. If the root of the resultant cluster has an even parity, the one or more PEs put the root node associated with this resultant cluster into an inactive state. Therefore this resultant cluster is said to be inactive. At the end of the picking stage, the nodes in a cluster that are not the root node are set to be inactive. Therefore, at the end of the picking stage, only the root node of a cluster will be active. At step 225, the algorithm 200 is in the "syncing" stage. In stage 225, one or more PEs update the activity flag and / or busyness flag associated with one or more nodes in their dedicated memory. The one or more PEs propagate the activity status of the root node of one or more clusters to other nodes of the one or more clusters. If the node in question is connected by a fullygrown edge to a neighbour that is active, the node in question becomes busy. By determining that these nodes are connected by a fully grown edge, we are considering nodes that are in the same cluster. The node in question will then become active if it is busy or if it was already active before this step. The picking stage ensures that all nodes in an odd parity cluster must be active. As represented by the arrow looping from the end of the syncing stage back to the start, the syncing stage is repeated until none of the nodes are busy. The syncing stage 225 may involve communication between PEs in order for PEs to query and send information to each other. For example, during the syncing stage 225, a PE associated with a root node may communicate the activity status of the root node to another PE that is associated with a node in the same cluster as the root node. The explanations of stages 205 225 have generally been given in terms of one resultant cluster. However, the algorithm 200 is scalable to multiple clusters on the decoding graph. For example, there may be multiple clusters growing simultaneously or at different times during the stages of the algorithm 200. If one or more clusters in the decoding graph are still active at the end of stage 225, the algorithm 200 goes back to the growing stage at step 210. At stage 230, the algorithm 200 is in the "exiting" stage. The exiting stage will begin once a stopping criterion is reached. The groups of PEs perform the steps of each stage of the clustering algorithm until the stopping criterion is reached. This stopping criterion defines the final cluster state. The stopping criterion is reached when each cluster of the decoding hypergraph has even parity, i.e. either comprises an even number of defects, or has reached the boundary of the decoding hypergraph. In other words, if there are no active clusters remaining in the decoding graph in the syncing stage, the algorithm 200 will continue to the exiting stage 230, in which the algorithm stops. This could include clusters that have an odd parity but have met the boundary, and therefore will not continue growing. At step 230, the decoding graph will contain one or more neutral clusters in which the errors can be decoded. Correction(s) to the encoded logical state can then be determined based on the final cluster state, i.e. based on the clustering of defects. Figures 3a h show decoding graphs 310, 320, 330, 340, 350, 360, 370 and 380. Figures 3a h depict a simplified example of a process for decoding a patch of surface code using the algorithm 200 depicted in figure 2. Figure 3a depicts a first stage, and Figure 3h depicts a last stage of decoding a patch of surface code. Each stage of the decoding process shown in Figures 3a-h may show the result of a stage of the algorithm 200, shown in Figure 2, as detailed below. However, stages of the decoding process may also not correspond to a stage of the algorithm 200 or may show the result of multiple stages of the algorithm 200. The circles and squares on the decoding graphs both represent nodes. The circles represent inactive nodes and the squares represent active nodes. Empty nodes represent nodes with an even parity and filled-in nodes represent nodes with an odd parity. The nodes of the decoding graphs depicted in Figures 3a-h may correspond to syndrome qubits in a quantum computing system. Each node is labelled with its cluster index above it and its node index below it. The cluster index of a node depicts the number of the cluster that the node belongs to. In Figure 3a the nodes are labelled with cluster indices 0 to 12, meaning each node belongs to a cluster numbered 0 to 12. The cluster index of a node may change through the clustering algorithm, as will be seen by inspection of Figures 3a-h. The node index of a node depicts a number associated with the node, in order to easily refer to different nodes in a decoding graph. Each node in the decoding graphs of Figures 3a-g will have a different node index to every other node in the decoding graph. The exception to this is the boundary nodes which may have the same node index as at least one other node in the decoding graph. The node index of a node stays constant through the clustering algorithm, and therefore through Figures 3a-h. In Figures 3a-h, possible connections between nodes are represented using dotted lines. While the graphs in Figure 3a-h can be used as basic decoding graphs, it is also possible to use more complex decoding graphs, for example with an extra dimension representing time, in which there is not necessarily a one-to-one correspondence between qubits and decoding graph edges. One skilled in the art will appreciate that the physical qubits do not necessarily need to be physically arranged as shown in Figures 3a-h. In Figures 3a-h, the block lines between nodes show the extent of the growth parameter of a node on the decoding graph at a particular time, i.e. ungrown, half-grown or fully-grown. The arrows on fully-grown edges display parenthood relationships between nodes, i.e. an arrow pointing from node 1 to node 2 signifies that node 2 is a parent of node 1 and similarly that node 1 is the child of node 2. Figures 3a-h contain boundary nodes 312a-c, 314a-c. The boundary nodes 312a-c, 314a-c show the nodes on the boundary of the decoding graph. The boundary nodes 312a-c are the boundary nodes on the left boundary of the decoding graph and the boundary nodes 314a-c are the boundary nodes on the right boundary of the decoding graph. The boundary nodes 312a-c each have a node index of 0 and the boundary bodes 314a-c each have a node index of 1. One skilled in the art will appreciate that the nuances of the decoding graph will depend upon the error correction code being implemented, and that some decoding graphs (e.g. those for toric codes) do not have boundaries. The graphs 310, 320, 330, 340, 350, 360, 370 and 380 may each represent information derived from the hypergraph at one of the stages of the algorithm 200 described above in relation to Figure 2. Figures 3a-h schematically depict the general process of the method 200 for this example decoding graph, however not every step of the process is shown in Figures 3a-h for simplicity and brevity. In the example decoding graph given in Figures 3a-h, all of the 12 nodes are assigned to one single processing element for simplicity. In other words, the 12 nodes are part of one PE's batch of nodes. Figure 3a shows a first graph 310. The graph 310 depicts an example decoding graph. In this example decoding graph, there are 3 defects present. The defects are at node / cluster indices 6, 10 and 11. The defects are demonstrated by filled-in square nodes. The square shape of the node means that the node is active and the fact that the node is filled-in means that the node has an odd parity. All of the nodes in the graph 310 have ungrown edges. The graph 310 is included here to demonstrate the decoding problem, and therefore does not correspond directly to the result of a stage of the algorithm 200. Figure 3b shows a second graph 320. The graph 320 depicts the result of a first growing stage, correlating with stage 210 of method 200. In this first growing stage, the PE updates the growth parameter associated with the nodes at node indices 6,10 and 11, i.e. the defects. The PE updates the growth parameter of these nodes by one unit and stores the updated value of the growth parameter in its dedicated memory. In the graph 320, this updated growth parameter for defects at node indices 6, 10 and 11 is shown by each of these nodes growing out by half an edge. This half-edge growth is along each of the four edges incident to each of these nodes on the decoding graph. Therefore the extent of clusters 6, 10 and 11 have grown in this step. As the current stage is not syncing, the controller puts the PE into the next stage, i.e. the merging stage at stage 215 in method 200. Due to the lack of fully-grown edges, no cluster indices change. Also since there are no nodes with odd children, no parities change. Similarly, the PE moves through the subsequent picking and syncing stages (stage 220 and 225, respectively) without changing the activity of the nodes. After the syncing stage, the PE has not reached the stopping criterion as multiple clusters have an odd parity. The PE remains active and so the controller puts the PE back into the growing stage (stage 210). Figure 3c shows a third graph 330. The graph 330 depicts the result of a second growing stage, once again correlating with stage 210 of method 200. In this second growing stage, each defect / cluster (at node indices 6, 10 and 11) has grown out its growth parameter by a half-edge along all possible edges surrounding it on the decoding graph. In other words, the PE associated with each of the nodes at node indices 6,10 and 11 increases a growth parameter associated with these nodes by one unit in its memory. Therefore the extent of clusters 6,10 and 11 have grown in this step. The three clusters in the graph containing defects are now connected to each other by at least one fully-grown edge. At the same time, the cluster with cluster index 11 has met the boundary at node 0. The PE associated with the nodes of the decoding graph will then update the cluster index of the nodes associated with the clusters 6, 10 and 11. Figure 3d shows a fourth graph 340. The graph 340 depicts the result of a merging stage, correlating with step 215 of method 200. In this merging stage attributes for multiple nodes are updated in the memory of the PE. This merging stage starts a flood, where many cluster indices and parent nodes change as the union often clusters take shape. As explained in step 215, the parent-child relationship between nodes will change based on the cluster index of neighbouring nodes. For example, the defect node at node index 10 is now connected by a fully-grown edge to the neighbours with node indices 8, 9, 12 and 13. As neighbouring node 8 has the lowest cluster index, defect node 10 will have an updated cluster index in the memory of the PE to that of cluster 8, and node 8 will become its parent. During this change, the node will be put into the busy state. As explained with regards to stage 215, the defects at node indices 6,10 and 11 relay their odd parity to their parents. During this change, the node will also be put into a busy state, if it was not already in a busy state. At the end of this merge, by cycling through all the nodes in the cluster, the nodes with node index 4 and 8 have an odd parity. Some of the edges between nodes in Figure 3d do not show parent-child relations due to the order in which the nodes have been processed in this example. As multiple changes of parent and parity have occurred during this merge, at least one node is still in the busy state, and therefore the merge will continue further. Figure 3e,f and g show graphs 350, 360, and 370, respectively. These graphs depict further merge steps, once again correlating with stage 215 of method 200. The merge continues due to at least one node still being in the busy state, as child-parent relationships and node parities continue to be updated in the memory of the PE whilst cycling through the nodes in the resultant cluster. Equivalently, the merging stage re-runs until all children in the resultant cluster have an even parity. Graph 370 depicts the final merge step, in which the child-parent relationships and node parities of the cluster reach their final merged state. In the final merged state, each node in the resultant cluster has the cluster index 0 stored in the memory of the PE. The root of the cluster tree is the node with node index 0, which has an odd parity. This can be seen by all the child-parent relationships in the cluster pointing back to cluster 0. In this example, the resultant cluster has an overall odd parity, however it ceases to continue growing as the resultant cluster has met the boundary. Figure 3h shows an eighth graph 380. The graph 380 depicts picking and syncing stages after the final merge stage, correlating to step 220 and step 225 of method 200 respectively. In the picking stage, the PE updates the activity of the root node associated with the resultant cluster. In the syncing stage, the PE updates the activity status of the child nodes based on the activity of the root node of the resultant cluster. The PE updates the busyness flag of multiple nodes associated with the resultant cluster in its dedicated memory . If one or more nodes are still busy at the end of the syncing stage, this stage may be repeated one or more times, as described above. These final picking and syncing stages deactivate the defect nodes 6,10 and 11. The LCD algorithm proceeds into the exiting stage, corresponding with step 230 of method 200. The logical correction equals the parity of the topmost boundary node on the left i.e. a parity of 1. This is equivalent to the sum modulo 2 of the number of defects in cluster 0. Distributed decoding algorithms of the type described above can be performed using a plurality of distributed PEs, for example implemented using FPGAs and ASICs. The resulting decoder can be configured to perform, for example, a clustering algorithm such as the LCD algorithm. The PEs may be arranged in an ordered arrangement. The ordered arrangement may take the form of an array or grid, for example. A grid of PEs is often depicted laid out in a square grid manner, and in some implementations this may reflect the actual hardware implementation. However, it should be understood that many different arrangements are possible and while reference is frequently made herein to a "grid" it should be understood that this is not an essential feature. Even when a "grid" is used, implementations other than square or rectangle are also possible, such as in other shapes of two dimensional arrangements and three dimensional structures. Decoding graphs may be made up of one or more layers, wherein each layer is associated with a decoding round. Therefore, each layer in the decoding graph may be associated with different moments in time and may be referred to as a "time slice". A decoding algorithm may be performed on each layer of the decoding graph, and then repeated again in each decoding round. As would be understood by the skilled person, the purpose of having multiple decoding rounds is to allow the decoder to understand and / or correct measurement errors that may have occurred between decoding rounds, and hence between time slices. Furthermore, multiple decoding rounds allow syndrome measurement errors to be accounted for. Each PE of the plurality of distributed PEs is associated with one or more nodes of the decoding hypergraph. Each PE in the processing grid may be associated with a different node in the decoding graph according to a 1:1 mapping or each PE in the processing grid may be associated with more than one node in the decoding graph. Herein, a grid of processing elements may also be referred to as an array of elements. Figures 4a-d each show a graph depicting different example processing grids 400, 410, 420, 430 of PEs 402. In Figures 4a-d, each of the processing grids 400, 410, 420, 430 comprises a 6 by 6 grid of PEs 402, such that there are 36 PEs 402. Each of the PEs 402 in Figures 4a-d are represented by a square with an index inside. Each index is in the form 'PEX' where 'PE' denotes the phrase processing element and X denotes the index of the processing element in the processing grid. The index of each processing element is in the range 0 to 35 in this example. Figures 4a-d show examples where the bottom-right PE is termed PEO. The index increments by 1 in the right-to-left direction until hitting the boundary. The indexing then continues from the right-most element in the next line in similar manner. This process is repeated until all elements of the grid are exhausted and have appropriate index. Figure 4a depicts a processing grid 400 without any data links between PEs. Figures 4b-d depict processing grids 410, 420, 430 with data links between PEs, as will be described below. Figures 4a-d show examples of processing grids 400, 410, 420, 430 applicable to decoding a planar surface code patch of size 5x5x6 (a surface code patch of distance 5 with 6 rounds of syndrome extraction). Each processing element 402 in the processing grids 400, 410, 420, 430 are essentially small decoding engines that can process several nodes in a serial manner and / or in a parallel manner at different stages of the decoding algorithm. The depicted processing grids 400, 410, 420, 430 are two dimensional grids of processing elements. Two dimensional processing grids are significantly easier to implement in hardware than corresponding three dimensional processing grids in the prior art. By implementing a method in which a PE is associated with more than one node, the processing grid requires fewer components than the corresponding three dimensional processing grids. Figures 4a and 4b depict example processing grids 400, 410 of processing elements 402 according to prior disclosures. Figure 4a is used as an illustration of an example layout of processing elements 402 in a two 26 dimensional processing grid 400. Figure 4b shows the processing grid of Figure 4a, but with data links 412, 414, 416, 418 coupling multiple PEs 402 in the processing grid 410. Data links are depicted as bidirectional arrows. The data links 412, 414, 416, 418 are physical links in hardware which allow the communication between PEs. For example, a data link connecting a first PE to a second PE will allow the first and second PEs to communicate with each other, for example send or query data. The data links 412, 414, 416, 418 are bidirectional links, meaning that the information can be sent in either direction along the data link. For example, when a first PE can send information to a second PE and the second PE can send information to the first PE using the same data link. Data links 412, 414, 416, 418 are used to directly couple PEs in a processing grid. The phrase "directly coupled" refers to the presence of a physical data link in the hardware between PEs. The data links 412, 414, 416, 418 in Figure 4b can be classified into four different types of data link: spatial links 412, temporal links 414, short hook links 416 and long hook links 418. Spatial links 412 are associated with spatial errors in a decoding graph. Spatial links 412 are data links that connect two PEs in the processing grid wherein both of the PEs are associated with nodes that are in the same time slice of the decoding graph. For example, in Figure 4b, PE34 and PE35 are directly coupled via a data link that is a spatial link 412. The spatial links 412 are depicted as horizontal links between two PEs in the processing grid that are directly next to each other, for example PE34 and PE35 in Figure 4b. A spatial error could exist between any two neighbouring nodes in the decoding graph 110 of Figure la, for example, as these nodes would be in the same time-slice. Temporal links 414 are associated with temporal errors in a decoding graph. Temporal links 414 are data links that connect two PEs in the processing grid wherein both of the PEs are associated with nodes that are in different time slices of the decoding graph. For example, in Figure 4b, PE12 and PE18 are directly coupled via a data link that is a temporal link 414. The temporal links 414 are depicted as vertical links between two PEs in the processing grid that are directly next to each other, for example PE12 and PE18 in Figure 4b. A temporal error could exist between two nodes in different time slices, wherein time-slices depict repeat measurements. Short hook links 416 and long hook links 418 are two different types of hook link that can be used in a processing grid. In general, hook links are data links that connect two PEs in the processing grid wherein both of the PEs are associated with mid-circuit errors, as the skilled person will be familiar with. Short hook links 416 and long hook links 418 are both depicted as diagonal links between two PEs in the processing grid that are not directly next to each other. For example, in Figure 4b, PE17 and PE22 are directly coupled via a data link that is a short hook link 416 and PE5 and PE9 are directly coupled via a data link that is a long hook link 418. The data links 412, 414, 416, 418 are depicted in particular orientations herein. For example, spatial links are depicted as horizontal links and temporal links are depicted as vertical links. However, in hardware, these links could be any orientation and these particular orientations are only consistent throughout the application for simplicity. Figure 4c depicts an example processing grid 420 of processing elements 402 which, by virtue of the method(s) of the present disclosure, can be used to perform a distributed decoding algorithm. The processing grid 420 of Figure 4c is the processing grid 410 of Figure 4b, but with the long hook links 418 removed from the processing grid. The processing grid 420 of Figure 4c therefore comprises the following data links: spatial links 412, temporal links 414 and short hook links 416. According to the present disclosure, the long hook links 418 in the processing grid 410 of Figure 4b can be "approximated" in the processing grid 420 of Figure 4c. In other words, there are no physical data links in hardware for the long hook links, and instead the communication via long hook links is performed via "routing" communication through multiple physical data links. The communication via the "approximated" link is herein referred to as a "route". There may be more than one intermediate PE in the route. The "intermediate PE" may be a first intermediate PE. For example, the communication between linked PEs may comprise sending a data bundle from a first PE to a first intermediate PE, sending the data bundle from the first intermediate PE to a second intermediate PE, and directing the data bundle to the destination PE by the second intermediate PE. The use of more than one intermediate PE may be necessary when the first PE and destination PE have a shortest route which comprises the use of three or more data links. For example, if the first PE was PE5 and the destination PE was PE14 in the processing grid 420 of Figure 4c, more than one intermediate PE would be used in the communication from PE5 to PE14. Similarly, this can be extended to a third intermediate PE, a fourth intermediate PE, and so on. A data bundle comprises an indicating portion which indicates a destination PE, and an information portion comprising information intended for the destination PE. The data bundle is therefore directed by the intermediate PE to the destination PE based on the indicating portion of the data bundle. When sending a data bundle from a first PE to a destination PE, there may instead be two intermediate PEs. In such a case, the communication between linked PEs comprises sending a data bundle from a first PE to an intermediate PE, sending the data bundle from the intermediate PE to a second intermediate PE, and directing the data bundle to the destination PE by the second intermediate PE. In most cases, when approximating a long hook link, a short hook link will be in the route if a short hook link is present. Therefore, information can be sent from a first PE to a destination PE via an "indirect coupling". The first PE and destination PE are said to be "linked", but not "directly coupled". When choosing the route to be taken when approximating a data link, it is desirable to take the route with the fewest physical data links. There may also be multiple different routes to choose from which comprise the same number of fewest physical data links. In this case, an arbitrary optimal route may be chosen. For example, the linking / communication between PE10 and PE14 in Figure 4c (and therefore the approximated long hook link between PE10 and PE14) can be described as follows in the absence of a long hook link: 1) The spatial link between PE10 and PE9. 2) The short hook link between PE9 and PE14. Therefore, the communication between PE10 and PE14 may be performed via the spatial link between PE10 and PE9, and the short hook link between PE9 and PE14. In this example, PE10 is the first PE, PE9 is the intermediate PE and PE14 is the destination PE. This example shows only one possible route for the communication between PE10 and PE14. For example, another route could include the short hook link between PE10 and PE15 and then the spatial link between PE15 and PE14. This allows the physical data link between PE10 and PE14 to be absent from the processing grid. This approach can be extended for all the long hook links in the processing grid 430. The absence of the long hook links in Figure 4c highlights the improvement in the physical hardware compared to the implementation of Figure 4b, due to simplified routing complexity resulting in a simplified design. Figure 4d depicts an example processing grid 430 of processing elements 402 which, by virtue of the method(s) of the present disclosure, can be used to perform a distributed decoding algorithm even with fewer data links than shown in Figure 4a. The processing grid 430 of Figure 4d is the processing grid 420 of Figure 4c, but with the short hook links 416 removed. The processing grid 420 of Figure 4c therefore comprises the following data links: spatial links 412 and temporal links 414. The processing grid 420 of Figure 4c does not comprise any hook links. According to the present disclosure, the long hook links 410 and short hook links 416 in the processing grid 410 of Figure 4b can be "approximated" in the processing grid 430 of Figure 4d. In other words, there are no physical data links in hardware for the long hook links or the short hook links, and instead the communication via long hook links and short hook links is performed via "routing" communication through multiple physical data links. The approximation of a short hook link is performed in a similar way to the approximation of a long hook link described with respect to Figure 4c. For example, the linking / communication between PE10 and PE15 in Figure 4d (and therefore the approximated short hook link between PE10 and PE15) can be described as follows in the absence of a short hook link: The spatial link between PE10 and PE9. The temporal link between PE9 and PE15. Therefore, the communication between PE10 and PE15 may be performed via the spatial link between PE10 and PE9, and the temporal link between PE9 and PE15. In this example, PE10 is the first PE, PE9 is the intermediate PE and PE15 is the destination PE. In addition, the linking / communication between PE10 and PE14 in Figure 4d (and therefore the approximated long hook link between PE10 and PE14) can be described as follows in the absence of a long hook link: The spatial link between PE10 and PE9. The temporal link between PE9 and PE15 The spatial link between PE15 and PE14. Therefore, the communication between PE10 and PE14 may be performed via the spatial link between PE10 and PE9, the temporal link between PE9 and PE15, and the spatial link between PE15 and PE14. In this example, PE10 is the first PE, PE9 is the intermediate PE, PE15 is the second intermediate PE and PE14 is the destination PE. In another example, the temporal link between PE9 and PE15 could be a spatial link between PE9 and PE8. Also, the spatial link between PE15 and PE14 could be a temporal link between PE8 and PE14. When the route differs in this way, the first PE and destination PE will be the same, however one or more of the intermediate PEs may be different in the route. The proposed route between PE10 and PE14 with respect to Figure 4d is different to the proposed route with respect to Figure 4c. This is because the route proposed with respect to Figure 4c comprises a short hook link, whereas the route with respect to Figure 4d does not comprise a short hook link, as there are no short hook links present in Figure 4d. Therefore a different route will need to be taken in the absence of short hook links. This allows the physical data link between PE10 and PE14, and PE10 and PE15, to be absent from the processing grid. This approach can be extended for all the hook links in the processing grid 440 and therefore the hardware to implement the processing grid 430 of Figure 4d is simplified compared to the hardware required to implement Figure 4b, and even Figure 4c. Other implementations are also possible in order to simplify the hardware over prior approaches. For example other implementations may comprise only one or some short hook links and / or one or some long hook links in the hardware, which will still simplify the hardware in comparison to the processing grid of Figure 4b. In this case, the short hook links and / or long hook links that are present may be used instead of the need for routing through one or more intermediate PEs. Each PE in the processing grid could be a first PE, an intermediate PE or a destination PE based on the communication that is happening at any one time. The role of the PE can therefore change based on the communication. For example, when sending a data bundle from PEO to PE7, PEO is the first PE, PE1 / PE6 may be an intermediate PE and PE7 is the destination PE. At another moment in time, when sending a data bundle from PE7 to PEO, PE7 is the first PE, PE1 / PE6 may be the intermediate PE and PEO is the destination PE. Therefore, PEO and PE7 had different roles based on the different communications. This applies to all of the PEs in a processing grid. A port can be used to send information from the particular PE and / or to receive information to the particular PE. The proposed route from a first PE to a destination PE is determined by a "routing table". Each PE comprises its own dedicated memory storing a routing table. A routing table may comprise a mapping of destination PEs to respective ports. For a particular PE, the routing table maps possible destination PEs to ports of the particular PE which should be used when directing data bundles to the possible destination PEs, In other words, when a data bundle is directed to a particular PE, the routing table in the dedicated memory of the particular PE will be used to guide the data bundle to the destination PE. Therefore, a data bundle arriving at a particular PE will be guided to a destination PE via the determined port. Figure 5 is a graph 500 depicting ports 504 associated with a first PE 502. There are 8 ports associated with the first PE 502 in this example, wherein the ports are labelled with a number 0 7. These numbers can be used as an associated identifier for the ports. The bidirectional arrows in Figure 5 depict the data links 412, 414, 416, 418 as shown in Figures 4b-d. The ports link one PE to another, such that information can be transferred between the PEs via a data link. The graph 500 shows the 8 different ports associated with the first PE 502. In the graph 500 of Figure 5, there are four different types of data link that associate with a port: spatial links 412, temporal links 414, short hook links 416 and long hook links 418, as described previously. For example, when sending a data bundle from a first PE to a destination PE via the determined port 3, a spatial link 412 will be used. A port associated with a first PE is used to send a data bundle, and a port associated with a destination PE is used to receive the data bundle. When sending a data bundle from a first PE 502 to a destination PE via the determined port 5, a long hook link 418 will be used. Port 5 is the port associated with the first PE 502 for sending the data bundle. The destination PE may use a different port number to receive the data bundle. For example, the destination PE may use port 2 to receive the data bundle. Therefore, two ports may be needed to communicate from a first PE to destination PE, with one port being associated with a first PE and another port being associated with the destination PE. Each port 0 7 will be connected to a different PE in a processing grid, such that each port is associated with the communication of information for the first PE 502 to 8 different PEs, in the example of Figure 5. There may be 31 a different number of ports associated with each PE, This may be due to whether the PE is close to a boundary of a processing grid, or due to the types of data link used in the hardware for that particular processing grid. Essentially the number of ports associated with a particular PE will be based on the number of PEs next to that PE on the processing grid and the number of data links connected to that particular PE. Figure 5 shows the four different types of data link between PEs as in Figure 4b. For example, PEs 7 10 in the processing grid 410 of Figure 4b will each have 8 respective ports associated with them, whereas PEO only has two respective ports associated with it. Furthermore, each of the PEs in the processing grid 430 of Figure 4d will be associated with either two, three or four ports. For example, PEO is associated with two ports, PE6 is associated with three ports and PE7 is associated with four ports. This discussion of ports has been given with reference to a first PE and a destination PE. A first PE and destination PE were used for simplicity of the description of communication from one PE to another. Alternatively, for example, the destination PE could instead be an intermediate PE. In this case, there is a port associated with the first PE and a port associated with the intermediate PE, and the description above still applies. Figures 6-8 depict example routing tables. Each PE comprises its own dedicated memory storing a routing table. For a particular PE, the routing table maps possible destination PEs to ports of the particular PE which should be used when directing data bundles to the possible destination PEs. Figure 6 depicts example routing tables for part of the processing grid 410 of Figure 4b. At the top of Figure 6 is a processing grid 610 which is part of the processing grid 410 of Figure 4b. Each PE will be associated with ports 0-7 as in Figure 5. Figure 6 comprises 6 different routing tables 620, 630, 640, 650, 660, 670 that are associated with the above processing grid 610 in Figure 6. Each routing table 620, 630, 640, 650, 660, 670 is associated with a different particular PE. Specifically, each routing table 620, 630, 640, 650, 660, 670 maps the possible destination PEs to ports of a different particular PE. The first routing table 620 maps possible destination PEs to ports of PE11. The second routing table 630 maps possible destination PEs to ports of PE10. The third routing table 630 maps possible destination PEs to ports of PE9. The fourth routing table 640 maps possible destination PEs to ports of PE5. The fifth routing table 660 maps possible destination PEs to ports of PE4. The sixth routing table 670 maps possible destination PEs to ports of PE3. Each routing table 620, 630, 640, 650, 660, 670 may comprise a title detailing its particular PE, in other words its associated first PE for a communication of a data bundle from the particular PE. Each routing table 620, 630, 640, 650, 660, 670 may comprise a column titled 'Destination PE' with a list of possible destination PEs of the particular PE. The destination PEs as in the 'Destination PE' column of a routing table show the possible PEs that a data bundle can be sent to using a single data link from the particular PE that stores the routing table. Although a routing table may be used to send a data bundle from a first PE to a destination PE, it may instead be used to send a data bundle from a first PE to a destination PE, from an intermediate PE to another intermediate PE or from an intermediate PE to a destination PE. Therefore, the routing table of a particular PE may detail the port used for only part of the journey to a destination PE in the 'Destination PE' column. Each routing table 620, 630, 640, 650, 660, 670 further comprises a column titled 'Port' with a list of possible ports of the particular PE, mapped to the list of possible destination PEs. Specifically, the routing table comprises the ports that are used to send data from the particular PE to a destination PE. In Figure 6, the routing tables 620, 630, 640, 650, 660, 670 only show the possible route from first PE to destination PE via one single port on a particular PE. The port associated with the destination PE used to receive the data bundle is not in the routing table of the first PE. In the routing tables 620, 630, 640, 650, 660, 670 of Figure 6, all destination PEs can be communicated with from the particular PE using one single data link. The routing tables 620, 630, 640, 650, 660, 670 of Figure 6 do not comprise sending a data bundle using routing and therefore the routing tables 620, 630, 640, 650, 660, 670 are associated with prior approaches. The routing tables described herein are lookup tables and may not be in the table layout as shown in Figures 6-8. A routing table may be in any suitable data structure for mapping ports to destination PEs. In practice the routing table may be a lookup table in the form of an array or a hash map, for example. In other words, the routing tables may not have columns or headings as described in the example above, but may be stored as another suitable data structure to store the same mapping information. In the first routing table 620, there are only two possible destination PEs. In other words, PE11 only has two possible destination PEs (PE5 and PE10) that can each be communicated with using only one data link from PE11. Therefore, there are only two associated ports (ports 0 and 3, respectively) that PE11 can use in order to send communication to other PEs in this processing grid 610. In the second routing table 630, there are four possible destination PEs. In other words, PE10 has four possible destination PEs (PE4, PE5, PE9, PE11) that can each be communicated with using only one data link from PE10. Therefore, there are four associated ports (ports 0,1, 3 and 4, respectively) that PE10 can use in order to send communication to other PEs in this processing grid 610. The size of each routing table will depend upon how "far" packets need to be communicated (which will in turn depend upon the decoding graph connectivity). It should be noted that if the whole processing grid 410 of Figure 4b were to be used as the processing grid 610 of Figure 6, more possible destination PEs would be possible for some of the PEs. For example, the first routing table 620 and the sixth routing table 670 would instead have 6 possible destination PEs when considering the first PEs PE11 and PE3, respectively, in the processing grid 410 of Figure 4b. There are many possible alternatives of routing tables to the routing tables described herein. The routing tables described herein comprise two columns. A routing table may comprise any number of rows and / or columns. Each column in the routing table may store different information to the 'Destination PE' and 'Port' as described herein. The information of the routing table could also be stored in a different data format, for example in a list form. The indicating portion of the data bundle may comprise one of the destination PEs as detailed in the 'Destination PE' column of the routing table of the particular PE. The information in the information portion of the data bundle will depend upon the type of distributed decoding algorithm. The distributed decoding algorithm may be a clustering algorithm, as described previously with respect to Figures 1-3. The clustering algorithm may comprise one or more stages in which one or more parameter values are updated in the dedicated memory of one or more PEs. For example, the clustering algorithm may comprise a growth stage, wherein the growth stage comprises one or more PEs updating a growth parameter associated with at least one of its associated nodes by one unit up to a maximum growth parameter value, and storing the updated growth parameter in its dedicated memory. This clustering algorithm may comprise one or more stages in which PEs communicate with one another, as described above with respect to Figure 3. In the merge stage of the decoding algorithm 300 as shown in Figure 3, the information portion comprises a query seeking to determine a growth factor of a node associated with the destination PE. In the sync stage of the decoding algorithm 300 as shown in Figure 3, the information portion comprises a query seeking to determine an activity status and / or a busyness status of a node associated with the destination PE. Therefore, the information portion and therefore the communication between PEs may vary based on the stage of the clustering algorithm. The information portion may further vary depending on the type of distributed decoding algorithm being used. For example, the information portion may comprise one or more of an index of the node, a cluster index, a growth parameter, a defect flag indicating whether the node is associated with a defect, an activity flag indicating whether the node and / or a cluster to which the node belongs is active, a parity flag indicating a parity of the node, and a busyness flag indicating whether the node is busy; or a request for any one of these items from a dedicated memory of the destination PE. The data bundle may further comprise a source portion which indicates the first PE, wherein the first PE created the data bundle. Therefore the source portion may comprise the title of the routing table. For example the first routing table 620 has the title 'Routing Table PE11'. Figures 7 and 8 depict example routing tables that incorporate routing, as per the method of the present disclosure. Figure 7 depicts example routing tables for part of the processing grid 420 of Figure 4c. At the top of Figure 7 is a processing grid 710 which is part of the processing grid 420 of Figure 4c. The processing grid 710 comprises 6 PEs, which are numbered PE3-PE5 on the bottom row and PE9-11 on a second row of the processing grid 710. Figure 7 comprises the same routing tables as in Figure 6, however the routing tables 620, 630, 640, 650, 660, 34 670 are associated with the above processing grid 710 in Figure 7. As described above, the processing grid 420 of Figure 4c does not comprise long hook links between PEs, therefore the processing grid 710 of Figure 7 also does not comprise long hook links. Therefore, the routing tables 620, 630, 640, 650, 660, 670 of Figure 7 comprise routing in order to "approximate" long hook links, as described previously. The following routing tables of Figure 7 are identical to those in Figure 6: the first routing table 620, the second routing table 630, the fifth routing table 660, and the sixth routing table 670. In other words, these routing tables of Figure 7 show the same particular PE, possible destination PEs and ports as those in Figure 6. The third routing table 640 and the fourth routing table 650 are different between Figure 6 and Figure 7, due to the removal of long hook links in Figure 7 compared to Figure 6. This is because there are no available ports of PE9 or PE5 that connect to long hook links. For example, the third routing table 640 of Figure 7 shows the same four possible destination PEs of the third routing table of Figure 6, however the ports used are different. The four possible destination PEs are PE3, PE4, PE5 and PE10. In the third routing table 640 of Figure 6, the corresponding ports to these destination PEs are 0, 1, 2 and 4, respectively. In the third routing table 640 of Figure 7, the corresponding ports to these destination PEs are 0,1,1 and 4, respectively. Therefore the port used in the third routing table from first PE9 to destination PE5 is different between Figure 6 and Figure 7. In the processing grid 610 of Figure 6, there exists a long hook link between PE5 and PE9, which corresponds to port number 2 when transmitting a data bundle from PE9 to PE5. In the processing grid 610 of Figure 7, no such long hook link exists and therefore routing is required to the destination PE. The following details an example of routing a data bundle from a first PE to a destination PE using the routing tables as in Figure 7. For example, PE5 of the processing grid 710 may be a first PE and PE9 of the processing grid 710 may be a destination PE of a data bundle. In other words, PE5 may want to query the information stored in the dedicated memory of PE9. The fourth routing table 650 is associated with the particular PE, PE5, and is stored in the dedicated memory of PE5. The fourth routing table 650 details that a destination PE of PE9 is mapped to port 3 of the particular PE, PE5. The data bundle is sent via port 3 of PE5. When sending the data bundle from port 3 of PE5, a short hook link is used. The data bundle is then received at PE10. PE10 is not the destination PE; PE9 is instead the destination PE. Therefore, PE10 is an intermediate PE in the route from first PE to destination PE in this example. The third routing table 640 details that a destination PE of PE9 is mapped to port 4 of the intermediate PE, PE10. The data bundle is sent via port 4 of the intermediate PE, PE10. When sending the data bundle from port 4 of PE10, a spatial link is used. The data bundle is then received at PE9, the destination PE. Therefore, the routing table of each particular PE in the route is used to send a data bundle from a first PE to a destination PE. In this example, there was only one intermediate PE, PE10, necessary from the route from first PE, PR5, to destination PE, PE9. Further details of this process will be described later with respect to Figure 10. Figure 8 depicts an example routing table for part of the processing grid 430 of Figure 4d. At the top of Figure 8 is a processing grid 810 which is part of the processing grid 430 of Figure 4d. Similarly to Figure 7, the processing grid 810 of Figure 8 comprises 6 PEs, which are numbered PE3-5 on the bottom row and PE9-11 on a second row of the processing grid 810 in Figure 8. Figure 8 comprises the same routing tables as in Figure 7, however the routing tables 620, 630, 640, 650, 660, 670 are associated with the processing grid 810 in Figure 8. As described above, the processing grid 430 of Figure 4d does not comprise short hook links or long hook links between PEs, therefore the processing grid 810 of Figure 8 also does not comprise short hook links or long hook links. Therefore, the routing tables 620, 630, 640, 650, 660, 670 of Figure 8 comprise routing in order to "approximate" short hook links and / or long hook links, as described previously. The following routing tables of Figure 8 are identical to those in Figure 7: the first routing table 620 and the sixth routing table 670. In other words, these routing tables of Figure 8 show the same particular PE, possible destination PEs and ports as those in Figure 7. The second routing table 630, third routing table 640, fourth routing table 650 and the fifth routing table 660 are different between Figure 7 and Figure 8, due to the removal of short hook links in Figure 8 compared to Figure 7. This is because there are no available ports of PE10, PE9, PE5 or PE4 that connect to short hook links. For example, the third routing table 640 of Figure 8 shows the same four possible destination PEs of the third routing table of Figure 7, however the ports used are different. The four possible destination PEs are PE3, PE4, PE5 and PE10. In the third routing table 640 of Figure 7, the corresponding ports to these destination PEs are 0, 1,1 and 4, respectively. In the third routing table 640 of Figure 7, the corresponding ports to these destination PEs are 0, 0, 0 and 4, respectively. Therefore the port used in the third routing table 640 from first PE9 to destination PE4 and destination PE5 is different between Figure 7 and Figure 8. In the processing grid 610 of Figure 7, there exists a short hook link between PE9 and PE4, which corresponds to port number 1 when transmitting a data bundle from PE9 to PE4. In Figure 8, no such short hook link exists and therefore routing is required to the destination PE. In addition, the route from PE9 to PE5 in Figure 7 makes use of a short hook link, whereas the route from PE9 to PE5 in Figure 8 does not. Similarly to an above example with respect to Figure 7, the following details an example of routing a data bundle from a first PE to a destination PE using the routing tables as in Figure 8. For example, PE5 of the processing grid 810 may be a first PE and PE9 of the processing grid 810 may be a destination PE of a data bundle. In other words, PE5 may 'want' to query the information stored in the dedicated memory of PE9. The fourth routing table 650 is associated with the particular PE, PE5, and is stored in the dedicated memory of PE5. The fourth routing table 650 details that a destination PE of PE9 is mapped to port 3 of the particular PE, PE5. The data bundle is sent via port 6 of PE5. When sending the data bundle from port 3 of PE5, a spatial link is used. The data bundle is then received at PE4. PE4 is not the destination PE in this case; PE9 is instead the destination PE. Therefore, PE4 is an intermediate PE in the route from first PE to intermediate PE in this example. The fifth routing table 660 details that a destination PE of PE9 is mapped to port 3 of the intermediate PE, PE4. The data bundle is sent via port 3 of the intermediate PE, PE4. When sending the data bundle from port 3 of PE4, a spatial link is used again. The data bundle is then received at PE3. PE3 is also not the destination PE. Therefore, PE3 is a second intermediate PE. The intermediate PE4 may instead be referred to as a first intermediate PE. The sixth routing table 670 details that a destination PE of PE9 is mapped to port 7 of the second intermediate PE, PE3. The data bundle is sent via port 7 of the second intermediate PE, PE3. When sending the data bundle from port 7 of PE3, a temporal link is used. The data bundle is then received at PE9, the destination PE. In this example, a first intermediate PE and a second intermediate PE were used for the route from first PE, PE5, to destination PE, PE9. This is in contrast to the example of the route given with respect to Figure 6, which only required one intermediate PE due to the use of a short hook link. Further details of this process will be described later with respect to Figure 10. Figure 9 depicts a method 900 according to the present disclosure. Optional steps of the method 900 are shown with a dashed outline in Figure 9. The method 900 is a computer-implemented method for decoding errors in a quantum computer system, for example a quantum computer system 1100 as depicted in Figure 11, which comprises a decoder apparatus and a register of quantum devices such as qubits. The decoder apparatus comprises a plurality of distributed processing elements, PEs. The distributed decoding algorithm is performed by the plurality of PEs. The distributed decoding algorithm requires communication between linked PEs of the plurality of distributed PEs. The method 900 of Figure 9 depicts the communication between linked PEs. Each PE of the plurality of PEs is associated with one or more nodes of a decoding hypergraph, e.g. either in a 1:1 assignment or an assignment in which each PE is associated with multiple nodes in a 'batch' of nodes. The decoder apparatus may comprise a controller and computer memory, where the controller acts to move each processing element through the various stages of the clustering algorithm. The decoder apparatus is configured to perform the method 900. The method 900 will be described alongside an example of communication between the linked PEs PE5 and PE9 in the processing grid 810 of Figure 8. In particular, an example will be detailed of PE5 being a first PE and PE9 being a destination PE, as used previously with respect to Figures 7 and 8. This example will be given with reference to the PEs in the processing grid 810 of Figure 8. At step 902, a data bundle is sent from a first PE to an intermediate PE. The data bundle may be sent via a data link from the first PE to the intermediate PE. The data bundle comprises an indicating portion which indicates a destination PE, and an information portion comprising information intended for the destination PE. The information may be a query for the destination PE, where a reply to the query is needed as part of the distributed decoding algorithm, for example. At step 904, the data bundle is directed to the destination PE. If there is only one intermediate PE, the data bundle is directly sent, by the intermediate PE, to the destination PE based on the indicating portion. However, 37 the directing may comprise directing the data bundle toward the destination PE via one or more additional intermediate PEs. Therefore if the route between the first PE and the destination PE comprises more than one intermediate PE, the data bundle is directed, by the first intermediate PE, to the destination PE via a second intermediate PE based on the indicating portion. The first PE is directly coupled to the intermediate PE via a data link, but is not directly coupled to the destination PE via a data link. In the case of more than one intermediate PE, the first intermediate PE is also coupled to the second intermediate PE via a data link, but the first intermediate PE is not directly coupled to the destination PE via a data link. This same pattern carries on for multiple intermediate PEs, such that the first PE is not directly coupled to the destination PE, but the first and destination PE may be indirectly coupled, for example via one or more intermediate PEs. The data bundle is sent via a particular port of the first PE. For example, and with reference to Figure 8, the first PE may be PE5 and the destination PE may be PE9. In this example, after consultation of PE5's routing table, the data bundle is sent from PE5 via port 3 to an intermediate PE PE4. When sending the data bundle from port 3 of PE5, a spatial link is used. The data bundle is received at port 4 of PE4. PE4 determines, based on the indicating portion in the data bundle, that the information is not intended for PE4 and needs to be rerouted. PE4 consults its own routing table, and sends the data bundle via its port 3 to a second intermediate PE, PE3. PE3 may send the data bundle via port 7 of PE3. PE3 directs the data bundle from port 3 of PE3 via a temporal link. At step 906, the data bundle is received by the destination PE. In this example, the data bundle is received by the destination PE PE9. The data bundle is received via a respective port associated with the PE in the hardware. Continuing the above example, the data bundle is received at the destination PE PE9 via port 0 of PE9. At step 908, the destination PE determines that the indicating portion indicates the destination PE. The destination PE may determine that it is the intended destination PE for the received data bundle by comparing the indicating portion of the data bundle to the identification of the PE in its own dedicated memory (e.g. by comparison with its own index number). The destination PE recognises that the received data bundle has reached its intended destination PE. Therefore, the destination PE does not need to further route the data bundle. At step 910, a second data bundle is formed. The second data bundle may be formed in response to the first data bundle received by the destination PE at step 906. If the destination PE is replying to a query from the first PE, then the second data bundle comprises a second indicating portion which indicates the first PE. The second data bundle may further comprise a second information portion which comprises second information intended for the first PE. The second data bundle may comprise a response to the query. In addition to an indicating and an information portion, the first data bundle sent at step 902 and received at step 906 may further comprise a 'source' portion which indicates the PE which generated the data bundle. In this example, the source portion indicates the first PE, as the first PE created the data bundle. This enables a response to be sent back to the first PE in response to its query. The destination PE can therefore direct and send a second data bundle back to the first PE, which created the first data bundle. For example, the destination PE9 may send a second data bundle back to the first PE, PE5. This second data bundle may comprise a parameter of the decoding algorithm associated with the destination PE, for example the busyness status of PE9. In the following discussion of a second data bundle, the naming convention will be kept the same as the discussion of the first data bundle. For example, the destination PE will remain PE9 and the first PE will remain PE5. However, PE5 could instead be referred to as the destination PE of the second data bundle and PE9 may instead be referred to as the first PE of the second data bundle. The route of the second data bundle may be the reverse route of the first data bundle. For example, the route of the first data bundle may be from PE5 to PE3 to PE4 to PE9, and the route of the second data bundle may be from PE9 to PE4 to PE3 to PE5. However, the route of the second data bundle may be different to the first data bundle. For example, the second data bundle may take a route from PE9 to PE10 to PE11 to PE5. The route taken of the first data bundle and of the second data bundle is dependent on the routing tables of the PEs in the process grid. At step 912, the second data bundle is sent from the destination PE to an intermediate PE. In this example, the second data bundle is sent from port 0 of PE9 to PE3. The second data bundle is received at port 7 of PE3. As in step 904, the step 912 may further comprise sending the second data bundle from one intermediate PE to another intermediate PE. In this example of sending a second data bundle from PE9 to P5, there are two intermediate PEs, PE3 and PE4. Therefore, in this example, the second data bundle is further sent from PE3 to PE4. The second data bundle is sent from port 4 of PE3. The second data bundle is received at port 3 of PE3. At step 914, the second data bundle is directed to the first PE. The intermediate PE may direct the second data bundle to the first PE. There may be one or more intermediate PEs, in which case, the second data bundle is directed to the first PE via one or more intermediate PEs. In other words, the directing of the second data bundle may comprise sending the second data bundle to the first PE or sending the second data bundle via additional intermediate PEs to the first PE. In this example, the second data bundle is directed to the first PE, PE5 via two intermediate PEs. At step 916, the second data bundle is received by the first PE (i.e. the original source PE). In this example, the second data bundle is received at port 3 of the first PE, PE5. The first PE will then determine that the first PE of the second data bundle has been reached. The first PE will determine that the second indicating portion indicates the first PE, and is therefore intended for the first PE, by comparing its index number to the second indicated portion of the second data bundle. The first data bundle can be referred to as a "request" and the second data bundle can be referred to as a "response" to the request. The request and / or response may contain a 'handshake' to enable continued communication between the first and destination PE, and therefore method 900 may take place multiple times, with different information included in the data bundles, as part of a 'handshake' and subsequent information exchange process. An example protocol for the handshakes performed in the request and / or response is a ready / valid handshake, which the skilled person will be familiar with. The ready / valid handshake can be used in the request and / or response, and more specifically, for the communication between PEs in the request and / or response. For example, successfully sending a data bundle from a first PE to an intermediate PE and receiving the data bundle at the intermediate PE may rely on both "ready" and "valid" flags to complete the handshake. The intermediate PE may accept the data in the same cycle, and the "ready" and "valid" flag outputs may change state. Other similar handshake protocols may be used. Common handshake protocols that could be used have 2, 3 or 4 phases, for example. The "request" of the first data bundle may comprise a "request payload" and the "response" of the second data bundle may comprise a "response payload". The request payload and the response payload may comprise multiple parameters to be communicated between PEs. The request payload may comprise an "offset" parameter and may further comprise an "offset valid" parameter. The offset parameter is associated with a node offset within a PE and the offset valid parameter indicates if the request frame is valid. The offset parameter is associated with the way that an PE would request one or more parameters from a neighbouring PE's own dedicated memory. For example, during the merging and / or syncing stages, the one or more PEs activated during the stage require data from a neighbouring PE. The required data my be a cluster index parameter, a growth parameter and / or activity status parameter, for example, as previously described with respect to Figure 3. Therefore, an active PE at any stage may create a "request frame". The response payload may comprise a cluster index parameter, a growth parameter and / or an activity status parameter, as previously described with respect to Figure 3. The response payload may further comprise a "neighbour valid" parameter which indicates if a response frame is valid. A "response frame" may be prepared by the destination PE. In the response frame, queried parameters are added to the response payload. The "neighbour valid" parameter is updated to indicate that this is a valid response. The routing PEs then would route this response frame to the first PE. While not shown, the method 900 may further comprise receiving, at the decoder apparatus, syndrome data representative of an error state of the quantum devices in the register of quantum devices. The syndrome data comprises a plurality of defects, wherein the syndrome data is representable as a decoding hypergraph comprising a plurality of nodes connected by hyperedges representing error mechanisms associated with the plurality of quantum devices. Each PE of the plurality of distributed PEs is associated with one or more nodes of the decoding hypergraph. Furthermore, performing the distributed decoding algorithm may comprise determining, by the decoder apparatus, a correction for the error state. While not shown, the method 900 may further comprise the decoder apparatus determining a correction. The correction corrects for the error state of the quantum devices, and may be based on a final cluster state. The final cluster state is reached when the clustering algorithm stops or exists. Once the final clustering state has been reached, a correction can be determined in a known way. For example, the method may comprise measuring a logical state encoded in the quantum devices of the quantum computer to obtain a logical state measurement, and applying the correction for the error state to the logical state measurement. While not shown in the flowchart, it should be understood that method 900 may comprise generating, by the first PE, the data bundle, for example as part of the distributed decoding algorithm. The method 900 advantageously utilises communication via one or more intermediate PEs to perform a distributed decoding algorithm, for example the clustering algorithm described above with respect to Figure 2. A first PE is directly coupled to an intermediate PE via a data link, but is not directly coupled to the destination PE via a data link. Therefore, fewer data links are necessary in hardware compared to prior approaches. Figure 10 depicts a method 1000 according to the present disclosure. The optional steps of the method 1000 are shown with a dashed outline in Figure 10. The method 1000 comprises steps 1002,1004,1006, 1008 and 1010. Step 1002 of method 1000 of Figure 10 relates to step 902 of method 900 of Figure 9. Step 1010 of method 1000 of Figure 10 relates to step 904 of method 900 of Figure 9. The method 1000 of Figure 10 comprises steps 1004, 1006 and 1008 that are not steps of the method 900 of Figure 9. The steps 1004,1006 and 1008 further describe the communication between a first PE and a destination PE via an intermediate PE. The steps 1004, 1006 and 1008 may be repeated in the case of there being more than one intermediate PE in the route from first PE to destination PE. The method 1000 of Figure 10 will be given with an example of a first PE PE5 and a destination PE PE1O in the processing grid 810 of Figure 8. At step 1002, a data bundle is sent from a first PE to an intermediate PE. This step is the same as step 902 of the method 900. In this example, a data bundle is sent from PE5 to PE4. At step 1004, the data bundle is received by the intermediate PE. In this example, a data bundle is received by PE4. At step 1006, the intermediate PE identifies the destination PE based on the indicating portion of the data bundle. The indicating portion of the data bundle indicates a destination PE. At step 1008, the intermediate PE determined a port associated with sending the data bundle to the destination PE. The port associated with the destination PE is determined by the intermediate PE and is based on the routing table stored in the dedicated memory of the intermediate PE. In this example, the destination PE is PE10 and the relevant routing table is the routing table 660 for PE4 in Figure 8. This routing table is stored in the dedicated memory of PE4. The routing table 660 for PE4 in Figure 8 details that a data bundle for destination PE10 should be sent via port 7 of PE4. At step 1010, the data bundle is directed to the destination PE by the intermediate PE via the determined port. In this example, PE4 sends the data bundle to PE10 via port 7 of PE4. A schematic of an exemplary quantum computing system 1100 suitable for performing the method of the present disclosure is shown in Figure 11. The quantum computing system 1100 comprises a plurality of physical qubits 1106 (unless specified otherwise, reference herein to qubits should be understood to refer to physical qubits rather than logical qubits). The qubits 1106 include data qubits used to encode logical qubit states, and syndrome qubits (or auxiliary qubits) used to perform syndrome measurements for quantum error correction. While the exemplary quantum computing system 1100 uses qubits 1106, one skilled in the art will 41 appreciate that the invention described herein is also applicable to quantum computing systems that use other quantum devices, such as qutrits and qudits. Accordingly, it should be understood that any reference herein to qubits is applicable to any type of quantum devices that can be used to encode quantum information. The qubits 1106 are controlled by a control system 1104 having one or more classical processors. The control system 1104 transmits control signals (e.g. RF pulses) to the qubits 1106 for performing operations on the qubits 1106 (including measurement operations) and receives measurement information from the qubits 1106. The measurement information will generally be analogue data signals, although the analogue signals may alternatively be converted to digital signals before being transmitted to the control system 1104 in some implementations (e.g. the qubits 1106 may be provided with one or more analogue to digital converters). The control system 1104 may receive high-level instructions from an algorithmic system or similar (not shown) and convert these high-level instructions (such as logic gates) into low-level qubit instructions (e.g. microwave pulses etc.), which may be in analogue format. The quantum computing system 1100 also comprises a decoding system 1102 (also referred to herein as a decoder). The decoding system 1102, which is generally a classical computing system, receives an error syndrome (also referred to as syndrome data) obtained from measurements of syndrome qubits. The error syndrome may comprise raw analogue measurement data, or it may alternatively be pre-processed (e.g. into digital format) by the control system 1104. The decoding system 1102 may be connected to the control system 1104 and receive the error syndrome via the control system 1104 as illustrated in Figure 11 (potentially via one or more additional intermediary systems), or in alternative examples the decoding system 1102 may be connected directly to the qubits 1106 and receive the error syndrome from the qubits 1106 (e.g. as raw analogue signals or digital measurement values). The decoding system 1102 uses a decoding process / algorithm to decode the error syndrome to determine a correction for an error state of the qubits 1006 associated with the error syndrome (i.e. an error state that causes the measured error syndrome). The decoding system 1102 comprises a plurality of PEs in the manner described extensively above. At compiletime, nodes may be assigned to processing elements of the hardware; for example so that each PE has a batch of nodes and / or such that each PE is grouped according to the grouping rules described herein. One skilled in the art will appreciate that the quantum computing system 1100 may also comprise additional intermediary components positioned between the illustrated components, and that the illustrated components may be connected in a different configuration (e.g. the decoding system 1102 may be connected directly to the qubits 1106 as previously described). Figure 12 depicts a computer-readable medium 1200 according to the present disclosure. The various methods described above may be implemented by a computer program. The computer program may include computer code (e.g. instructions) 1210 arranged to instruct a computer to perform the functions of one or more of the 42 various methods described above. The steps of the distributed decoding algorithm described herein may be performed in any suitable order. For example, the steps of the clustering algorithm 200 may be performed in any suitable order. The computer program and / or the code 1210 for performing such methods may be provided to an apparatus, such as a computer, on one or more computer readable media or, more generally, a computer program product 1200)), depicted in Figure 11. The computer readable media may be transitory or non transitory. The one or more computer readable media 1200 could be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, ora propagation medium for data transmission, for example for downloading the code over the Internet. Alternatively, the one or more computer readable media could take the form of one or more physical computer readable media such as semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read only memory (ROM), a rigid magnetic disc, and an optical disk, such as a CD ROM, CD R / W or DVD. The instructions 1210 may also reside, completely or at least partially, within the memory and / or within the controller circuitry 1104 during execution thereof by the computing system 1100, the memory and the controller circuitry 1104 also constituting computer-readable storage media. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other implementations will be apparent to those of skill in the art upon reading and understanding the above description. Although the present disclosure has been described with reference to specific example implementations, it will be recognized that the disclosure is not limited to the implementations described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A computer-implemented method for decoding errors in a quantum computer system, the quantum computer system comprising a decoder apparatus and a register of quantum devices, the decoder apparatus comprising a plurality of distributed processing elements, PEs; the method comprising:performing, by the plurality of PEs, a distributed decoding algorithm, wherein the distributed decoding algorithm requires communication between linked PEs of the plurality of distributed PEs;wherein the communication between linked PEs comprises:sending, from a first PE to an intermediate PE, a data bundle comprising an indicating portion which indicates a destination PE, and an information portion comprising information intended for the destination PE; anddirecting, by the intermediate PE, the data bundle to the destination PE based on the indicating portion.

2. The method of claim 1, wherein the intermediate PE is a first intermediate PE, and the directing comprises:sending, by the first intermediate PE, the data bundle to a second intermediate PE based on the indicating portion; andsending, by the second intermediate PE, the data bundle to the destination PE based on the indicating portion.

3. The method of any preceding claim, wherein the information portion comprises a query for the destination PE, and the communication between linked PEs further comprises:receiving, by the destination PE, the data bundle;determining, by the destination PE, that the indicating portion indicates the destination PE; andforming a second data bundle comprising a second indicating portion which indicates the first PE and a second information portion which comprises second information intended for the first PE, wherein the second information comprises a response to the query.

4. The method of any preceding claim, wherein the first PE is directly coupled to the intermediate PE via a data link, but is not directly coupled to the destination PE via a data link.

5. The method of any preceding claim, wherein each PE is connected to multiple other PEs of the plurality of PEs via respective ports; wherein each PE comprises its own dedicated memory storing a routing table; and wherein, for a particular PE, the routing table maps possible destination PEs to ports of the particular PE which should be used when directing data bundles to the possible destination PEs.

6. The method of claim 5, wherein the communication between PEs further comprises:receiving, by the intermediate PE, the data bundle;identifying, by the intermediate PE, the destination PE based on the indicating portion;determining, by the intermediate PE and based on the routing table stored in the dedicated memory of the intermediate PE, a port associated with sending the data bundle to the destination PE; anddirecting, by the intermediate PE, the data bundle to the destination PE via the determined port.

7. The method of any preceding claim, wherein the data bundle further comprises a source portion which indicates the first PE, wherein the first PE created the data bundle.

8. The method of any preceding claim, further comprising:receiving, at the decoder apparatus, syndrome data representative of an error state of the quantum devices in the register of quantum devices, the syndrome data comprising a plurality of defects, wherein the syndrome data is representable as a decoding hypergraph comprising a plurality of nodes connected by hyperedges representing error mechanisms associated with the plurality of quantum devices, and wherein each PE of the plurality of distributed PEs is associated with one or more nodes of the decoding hypergraph; andwherein performing the distributed decoding algorithm comprises determining, by the decoder apparatus, a correction for the error state.

9. The method of claim 8, wherein each PE of the plurality of PEs comprises its own dedicated memory, wherein neighbouring PEs are PEs associated with two nodes which neighbour each other in the hypergraph, and wherein the communication between linked PEs comprises each PE reading data from and / or writing data to the dedicated memory of at least one of its neighbouring PEs.

10. The method of claim 9, wherein the dedicated memory of each PE stores attributes relating to the one or more nodes associated with the PE.

11. The method of claim 9 or claim 10, wherein the first PE and the destination PE are neighbouring PEs.

12. The method of any of claims 8 to 11, wherein the distributed decoding algorithm is a clustering algorithm, and the clustering algorithm grows and merges clusters of nodes based on the number of defects in each cluster until a final cluster state is reached; wherein the correction for the error state is based on the final cluster state.

13. The method of claim 12, wherein the clustering algorithm comprises a growth stage; wherein the growth stage comprises one or more PEs updating a growth parameter associated with at least one of its associated nodes by one unit up to a maximum growth parameter value, and storing the updated growth parameter in its dedicated memory.

14. The method of claim 13, wherein the clustering algorithm further comprises a merge stage; wherein the information portion comprises a query seeking to determine a growth factor of a node associated with the destination PE.

15. The method of claim 12 to 14, wherein the clustering algorithm further comprises a sync stage;wherein the information portion comprises a query seeking to determine an activity status and / or a busyness status of a node associated with the destination PE.

16. The method of any of claims 8 to 15, wherein performing the distributed decoding algorithm further5 comprises:measuring a logical state encoded in the quantum devices of the quantum computer to obtain a logical state measurement; andapplying the correction for the error state to the logical state measurement.

17. A decoder apparatus comprising a controller, a plurality of distributed processing elements, PEs, and10 computer memory; the decoder apparatus being configured to perform the method of any preceding claim.

18. A quantum computer system comprising a register of quantum devices and the decoder apparatus according to claim 17.Application No: GB2412882.9 Examiner: Alessandro PotenzaClaims searched: 1-18Date of search: 30 January 2025Patents Act 1977: Search Report under Section 17Documents considered to be relevant:Category Relevant to claims Identity of document and passage or figure of particular relevance X 1-18 US 5181017 A (IBM) see figures 1, 5 and column 1, lines 20-22 and 29-33; column 3, lines 38-44; column 8, lines 5-14 X 1-18 US 2011 / 066825 Al (XMOS) see figures 3, 9 and paragraph 2 X 1-18 US 2012 / 0120959 Al (HEWLETT PACKARD) see figure 9 and paragraph 65 X 1-18 JP HO 1251266 A (TOSHIBA) see figures 2, 4-5; page 394, first column, lines 2-20; page 394, bottom paragraphs of first and second columns; page 395, first column, lines 1-4 A - Arxiv.org, Barber B et al, "A real-time, scalable, fast and highly resource efficient decoder for a quantum computer", 2023, available from https: / / arxiv.org / pdt72309.05558vl (BARBER) A - Arxiv.org, LIYANAGE N et al, "FPGA-based Distributed Union-Find Decoder for Surface Codes", 20 March 2024, available from https: / / arxiv.org / pdf72406.08491vl (LIYANAGE) A IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Heer MJ et al, "Novel Union-Find-based Decoders for Scalable Quantum Error Correction on Systolic Arrays", 2023, DOI 10.1109 / IPDPSW593 00.2023.00092 (HEER)Categories:X Document indicating lack of novelty or inventive step A Document indicating technological background and / or state of the art. Y Document indicating lack of inventive step if combined with one or more other documents of same category. P Document published on or after the declared priority date but before the filing date of this invention. & Member of the same patent family E Patent document published on or after, but with priority date earlier than, the filing date of this application.Field of Search:International Classification:Subclass Subgroup Valid From G06N 0010 / 70 01 / 01 / 2022 G06F 0015 / 17 01 / 01 / 2006 G06F 0015 / 173 01 / 01 / 2006

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