Semiconductor structures

Abstract

The present disclosure relates to a semiconductor structure 300. The semiconductor structure 300 comprises: a channel layer 130; a barrier layer 140, that is configured to induce a two-dimensional ele

Description

Technical field The present application relates to a semiconductor structure. The present application further relates to a semiconductor device, power management device a vehicle and a method of manufacturing a semiconductor structure. Background Forming semiconductor devices from lll-N semiconductor materials is becoming increasingly desirable. Si has dominated the semiconductor industry for many decades. However, lll-N semiconductor materials, such as GaN, possess desirable electronic and photonic properties, outperforming Si in many aspects. The high electron mobility transistor (HEMT) is a semiconductor device commonly formed from lll-N materials. lll-N HEMTs typically exhibit a higher breakdown voltage and greater electron mobility than Si MOSFETs. The use of lll-N HEMTs has therefore found use in power and radio frequency (RF) communications applications. HEMTs exhibit high electron mobility due to the formation of a two-dimensional electron gas (2DEG) in the channel layer of the HEMT. Typically, an AIGaN barrier layer is formed over a GaN channel layer. The AIGaN barrier layer induces the formation of a 2DEG in the GaN channel layer. Whilst the formation of the 2DEG is a desirable property it commonly results in HEMTs exhibiting depletion mode (D-mode) behaviour where a negative bias voltage is applied to the HEMT in order to turn the HEMT to the ‘off’ state. The D-mode behaviour of a HEMT is typically not as desirable as an enhancement mode (E-mode) operation, where a transistor is normally in the ‘off state and a positive bias voltage is applied to turn the transistor to the ‘on’ state. For D-mode operation, a driver circuit or negative bias generator is typically added to a circuit to appropriately control the HEMT. Such circuitry is not commonly used for E-mode operation. Summary It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques. According to a first aspect there is provided a semiconductor structure that comprises a channel layer and a barrier layer. The barrier layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The semiconductor structure further comprises a semiconductor layer comprising a first porous portion and a non-porous portion. The non-porous portion is configured to prevent formation of the 2DEG in a portion of the channel layer. The semiconductor structure further comprises a first electrical contact over the non-porous portion. According to a second aspect there is provided a semiconductor device comprising the semiconductor structure according to the first aspect. According to a third aspect there is provided a power management device comprising the semiconductor device according to the second aspect. According to a fourth aspect there is provided a method of forming a semiconductor structure that comprises: forming a channel layer; forming a barrier layer configured to induce a two-dimensional electron gas (2DEG) in the channel layer; forming a semiconductor layer comprising a first porous portion and a non-porous portion, wherein the non-porous portion is configured to prevent formation of the 2DEG in a portion of the channel layer; and forming a first electrical contact over the non-porous portion. Brief description of the drawings For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is an example of a semiconductor structure; Figure 2 is another example of a semiconductor structure; Figure 3 is another example of a semiconductor structure; Figures 4a-d are examples of process steps in a method of forming a semiconductor structure. Detailed Description Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metalorganic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition. Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer. A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Alo.25Gao.75As means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As. Crystalline means a material or layer with a single crystal orientation. In epitaxial growth or deposition subsequent layers with the same or similar lattice constant follow the registry of the previous crystalline layer and therefore grow with the same crystal orientation. In-plane is used herein to mean parallel to the surface of the substrate; out-of-plane is used to mean perpendicular to the surface of the substrate. Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb). A substrate may be on-axis, that is where the growth surface aligns with a crystal plane. For example it has <100> crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane. Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction. Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type. A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and / or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function. A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided. A fully depleted porous layer means a layer in which there are no charge carriers. Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer. Throughout the present disclosure corresponding elements in the Figures are labelled with corresponding reference numerals. To provide additional context to the description of the examples according to the present disclosure, there now follows a further discussion of the drawbacks, which conventional techniques suffer from. Figure 1 is an example of a conventional HEMT 100. HEMT 100 comprises a substrate 110 and a buffer layer 120, a channel layer 130 and a barrier layer 140 formed on the substrate. The buffer layer 120, channel layer 130 and barrier layer 140 comprise semiconductor material. In one example, the buffer layer 120, channel layer 130 and barrier layer 140 comprise lll-N semiconductor material. However, in other examples, the buffer layer 120, channel layer 130 and barrier layer 140 comprise other lll-V materials such as GaAs-based materials. The buffer layer 120, channel layer 130 and barrier layer 140 may thus be epitaxially grown on the substrate 110. The buffer layer 120, is configured to eliminate defects and provide isolation between the substrate 110 and the channel layer 130 above the buffer layer 120. In some examples, the buffer layer 120 comprises GaN. Channel layer 130 provides the channel in the HEMT for charge carriers to flow. A 2-dimensional electron gas (2DEG) 132 is formed in the channel, which confines the electrons and results in the HEMT exhibiting high electron mobility properties. The 2DEG 132 is formed in the channel layer 130 due to a polarization discontinuity between the barrier layer 140 and the channel layer 130. In some examples, the channel layer 130 comprises GaN and the barrier layer 140 comprises AIGaN. HEMT 100 further comprises a source contact 150, a drain contact 160 and a gate contact 170. As illustrated in Figure 1, the 2DEG 132 is continuous between the source contact 150 and the drain contact 160. As such, with no bias voltage applied to the gate contact 170, the formation of the 2DEG 132 results in current flow between the source contact 150 and drain contact 160. The HEMT 100 thus exhibit D-mode behaviour. A negative bias voltage is applied to the gate contact 170 to turn the HEMT 100 to the ‘off’ state where the formation of the 2DEG is interrupted. As described above, in some applications, the D-mode behaviour of a HEMT is less desirable than E-mode behaviour. In E-mode operation, the HEMT is normally in an ‘off’ state and a positive bias voltage is applied to the gate contact 170 to turn the HEMT to the conducting ‘on’ state. Although many conventional HEMTs typically exhibit D-mode behaviour, some HEMT designs have been developed that can exhibit E-mode behaviour. Figure 2 illustrates a HEMT 200 configured for E-mode behaviour. HEMT 200 comprises a heavily doped n-type (N+) semiconductor portion 281 between the gate contact 170 and the barrier layer 140. In some examples, the N+ semiconductor portion comprises GaN. The N+ semiconductor portion 281 pushes electrons away from the interface between the channel layer 130 and barrier layer 140 to result in an interruption of the 2DEG 132 in the portion of the channel layer 130 beneath the N+ semiconductor portion 281. As such, the 2DEG 132 is not continuous between the source electrode 150 and the drain electrode 160 and the HEMT 200 is in the off state. Therefore, with a zero bias voltage applied to the gate contact 170, the HEMT 200 is in the off state and the HEMT 200 thus exhibits E-mode behaviour. In order to turn the HEMT 200 to the conducting ‘on’ state, a positive bias voltage is applied to the gate contact 170. The positive bias voltage counteracts the effect of the N+ semiconductor portion 281 to result in the formation of a continuous 2DEG 132 between the source electrode 150 and drain electrode 160. HEMT 200 further comprises a first dielectric portion 282 between the source contact 150 and gate contact 170. The HEMT 200 further comprises a second dielectric portion 284 between the drain contact 160 and the gate contact 170. The first dielectric portion 282 is configured to provide isolation between the source contact 150 and the gate contact 170. The second dielectric portion 284 is configured to provide isolation between the drain contact 160 and the gate contact 170. The first and second dielectric portions 282, 284 further do not perturb the formation of the 2DEG 132 in the channel layer 130. As such, the 2DEG is present in regions of the channel layer 130 beneath the first and second dielectric portions 282, 284. Thus, when a positive bias voltage is applied to the gate contact 170, a continuous 2DEG can be formed between the source contact 150 and drain contact 160 to turn the HEMT 200 into the conducting ‘on’ state. HEMT 200 can thus exhibit E-mode behaviour. However, fabrication of the HEMT 200 suffers from a number of drawbacks. Formation of the HEMT 200 involves the epitaxial deposition of a N+ semiconductor layer over the barrier layer 140. The N+ semiconductor layer is etched and the first and second dielectric portions 282, 284 are deposited into the etched areas of the N+ semiconductor layer. Etching the N+ semiconductor layer in a manner that does not detrimentally impact the barrier layer 140 is challenging. In particular, the etching process can cause defects at the upper surface of the barrier layer 140. The defects create surface states, which results in the HEMT 200 exhibiting nonlinear behaviour. Examples according to the present disclosure provide a semiconductor structure, which can form a HEMT exhibiting E-mode behaviour and removes the etching processes that can result in defects at the upper surface of the barrier layer. Examples according to the present disclosure provide a semiconductor structure comprising a semiconductor layer comprising a porous portion and a non-porous portion. The non-porous portion is configured to prevent formation of a 2DEG in at least a portion of the channel layer. For example, in the portion of the channel layer under the non- porous portion. The porous portion is configured to act as a dielectric and provide isolation effects between electrical contacts formed on the semiconductor structure. In some examples, the porous portion and the non-porous portion may comprise GaN. As described above, N+ GaN can be utilised to interrupt formation of a 2DEG in a channel layer to result in a HEMT exhibiting E-mode behaviour. The non-porous portion of the semiconductor structure may thus comprise N+ GaN. It has also been observed that electrochemically etching N+ GaN can result in the porosification of the semiconductor material to form porous GaN. Porous GaN is resistive and results in a material exhibiting dielectric properties. The porous portion of the semiconductor layer can thus provide isolation properties between electrical contacts formed on the semiconductor structure. In particular, the formation of the porous portion of the semiconductor layer can provide a step to form isolating material between electrical contacts that removes the etching step used to form dielectric portions 282, 284 of HEMT 200, which can detrimentally impact the barrier layer 140. The formation of the non-porous portion and porous portion of the semiconductor structure according to the present disclosure can be formed in a self-aligned manner. For example, an electrical contact, such as a gate contact can be formed over a N+ GaN layer. The semiconductor structure can be subjected to an electrochemical etching process where the semiconductor structure is typically submerged in a bath comprising an electrolyte. An electrode is applied to a backside of the semiconductor structure and an additional electrode is placed in the bath with the semiconductor structure. A current is applied to the electrodes, which results in the electrolyte penetrating the N+ GaN material to porosify the N+ GaN material. The porosification process is selective to the N+ GaN material and thus the remaining layers of the semiconductor structure are substantially unaffected by the electrochemical etch process. In examples according to the present disclosure, the gate contact formed over the semiconductor structure shields the N+ GaN material to provision portions of the N+ GaN material that are porosified and not porosified. The portion of the N+ GaN layer beneath the gate contact is shielded, which provisions the formation of the non-porous portion. Areas of the N+ GaN layer that are not shielded are porosified to form the porous portion. The electrochemical etch process according to examples of the present disclosure is thus self-aligned. Furthermore, examples according to the present disclosure can thus provide a technique for forming dielectric material, which avoids the use of an etching process, which can result in the formation of defects at the upper surface of the barrier layer 140. Figure 3 is an example of a semiconductor structure 300. Semiconductor structure 300 comprises a N+ portion 281 situated beneath the gate contact 170. N+ portion 281 comprises a non-porous portion configured to prevent formation of the 2DEG 132 in a portion of the channel layer 132, in a similar manner to that described above. For example, the N+ portion 281 may comprise N+ GaN Semiconductor structure 300 further comprises a first porous portion 382 between the source contact 150 and the gate contact 170. The first porous portion 382 may comprise dielectric properties to provide isolation between the source contact 150 and the gate contact 170. For example, the first porous portion 382 may comprise porous GaN. Semiconductor structure 300 further comprises a second porous portion 384 between the drain contact 160 and the gate contact 170. The second porous portion 384 may comprise dielectric properties to provide isolation between the drain contact 160 and the gate contact 170. For example, the second porous portion 384 may comprise porous GaN. As will be described in more detail below, the N+ portion 281, first porous portion 382 and second porous portion 382 may be fabricated from a common semiconductor layer comprising N+ semiconductor material, such as, N+ GaN. As illustrated in Figure 3, edges of the gate contact 170 align with edges of the N+ portion 281. As will further be described below, the N+ portion 281 may be formed as part of a self-aligned electrochemical etch process, where the gate contact 170 shields the N+ portion 281 from porosification. As further illustrated in Figure 3, the 2DEG 132 is formed in the channel layer 130 in regions beneath the first porous portion 382 and second porous portion 384. The dielectric properties of the first porous portion 382 and second porous portion 384 may not perturb the formation of the 2DEG 132 in the channel layer 130, which results from a polarization discontinuity between the barrier layer 140 and channel layer 130. Thus, when a zero bias voltage is applied to the gate contact 170, edges of the 2DEG 132 may align with edges of the first porous portion 382 and second porous portion 384. Figures 4a-d illustrate process steps in a method of forming the semiconductor structure 300. Figure 4a illustrates a first step 400a in which nucleation layer 115, buffer layer 120, channel layer 130, barrier layer 140 and N+ semiconductor layer 280 are formed on the substrate 110. The nucleation layer 115, buffer layer 120, channel layer 130, barrier layer 140 and N+ semiconductor layer 280 may thus form a layer stack 410 formed on substrate 110. As will be described in more detail below, the N+ semiconductor layer 280 is fabricated into the N+ portion 281, the first porous portion 382 and the second porous portion 384. The layer stack 410 may comprise lll-V semiconductor material, such as lll-N semiconductor material. Thus, in some examples, nucleation layer 115, buffer layer 120, channel layer 130, barrier layer 140 and N+ semiconductor layer 280 may be epitaxially formed on the substrate 110, for example, using MBE or MOCVD techniques. In one example, the nucleation layer 115 may comprise AIN, buffer layer 120 may comprise (AI)GaN, channel layer 130 may comprise GaN, barrier layer 140 may comprise AIGaN and N+ semiconductor layer 280 may comprise GaN. Substrate 110 may thus comprise a material for the epitaxial formation of the layer stack 410 thereon. For example, the substrate 110 may comprise Si, SiC, sapphire or GaN. N+ semiconductor layer 280 may be doped using any suitable n-type dopant. For example, where the N+ semiconductor layer 280 comprises GaN, the n-type dopant may comprise Si or Ge. In some examples, the N+ semiconductor layer 280 may comprise a doping concentration of 1 x 1018 cm-3 to 1 x 1021 cm-3. Figure 4a further illustrates the absence of a 2DEG in the channel layer 130. The presence of the N+ semiconductor layer 280 results in electrons being pushed away from the interface with the channel layer 130 and barrier layer 140 to prevent formation of the 2DEG. As will be described in more detail below, portions of the N+ semiconductor layer 280 are porosified to result in the formation of the 2DEG in regions of the channel layer 130. Figure 4a illustrates that the layers of the layer stack 410 are formed directly on one another in a sequential stack. However, one skilled in the art will understand that one or more layers may be inserted between layers of the layer stack 410, such as a spacer layer between the channel layer 130 and barrier layer 140, or a backbarrier layer between the channel layer 130 and buffer layer 120. Furthermore, one or more of the layers of the layer stack 410 may comprise a plurality of sub-layers. Figure 4b illustrates a second step 400b in which a gate contact 170 is formed over the N+ semiconductor layer 280. The gate contact 170 may be formed using any suitable fabrication technique. In one example, gate contact material may be deposited over the N+ semiconductor layer 280. The gate contact material may be subsequently patterned and etched to form the gate contact 170. In some examples, the gate contact 170 may comprise W, Ti, TiN, Ta or TaN. Figure 4c illustrates a third step 400c in which N+ portion 281, first porous portion 382 and second porous portion 384 have been formed in N+ semiconductor layer 280. As described above, some semiconductor material, such as lll-N semiconductor materials can be porosified using an electrochemical etch process. The porosification process is selective to N+ lll-N semiconductor material. As such the semiconductor structure illustrated in Figure 4c can be subjected to an electrochemical etch process where portions of the N+ semiconductor layer 280 are porosified, but the other layers of the semiconductor structure, which are not N+, are substantially unaffected by the electrochemical etch process. As such, nucleation layer 115, buffer layer 120, channel layer 130 and barrier layer 140 are substantially unaffected by the electrochemical etch process. The electrochemical etch process thus results in the formation of the first porous portion 382 and the second porous portion 384. However, non-porous N+ portion 281 is additionally formed beneath the gate contact 170. The gate contact 170 shields the non-porous N+ portion 281 during the porosification process, such that it is not porosified. As described above, during the electrochemical etch process, the semiconductor structure is submerged in a bath of electrolyte material. An electrode is applied to the semiconductor structure, for example, on the backside of the substrate 110 and an additional electrode is placed in the electrolyte bath. The electrodes are configured such that the N+ semiconductor layer is between the two electrodes. A current is applied to the two electrodes and the electrolyte reacts with the N+ semiconductor layer 280 to porosify the material and form the first porous portion 382 and second porous portion 384. However, the gate contact 170 shields a portion of the N+ semiconductor material from the electrolyte such that the material beneath the gate contact is not porosified. As such, the configuration of the gate contact 170 results in the formation of the non-porous N+ portion 281. The selective nature of the electrochemical etch process and the configuration of the gate contact 170 thus results in edges of the gate contact 170 substantially aligning with edges of the non-porous N+ portion 281. The formation of the non-porous N+ portion 281 is thus self-aligning. The gate contact 170 may thus comprise a material configured to appropriately shield the non-porous N+ portion 281 during the electrochemical etch process. In one example, the gate contact 170 may comprise W, Ti, TiN, Ta or TaN. As further illustrated in Figure 4c, 2DEG 132 is formed in regions of the channel layer 130 beneath the first porous portion 382 and the second porous portion 384. The first porous portion 382 and second porous portion 382 are resistive and possess dielectric properties. As such, the first porous portion 382 and second porous portion 382 do not modify the behaviour of carriers in the channel layer 130, and the polarization discontinuity between the barrier layer 140 and channel layer 130 results in the formation of the 2DEG 132 in portions of the channel layer 130. The non-porous N+ portion 281 continues to comprise electrical properties that prevent formation of the 2DEG in the channel layer 130, in a region of the channel layer 130 beneath the non-porous N+ portion 281. Figure 4d illustrates a fourth process step 400d in which source contact 150 and drain contact 160 are formed. Source contact 150 contacts channel layer 130. In one example, a through-via may thus be formed through the first porous portion 382 and the barrier layer 140, and the source contact 150 may be deposited into the via. In a similar manner, the drain contact 160 contacts the channel layer 130. In one example, a through-via may thus be formed through the second porous portion 384 and the barrier layer 140, and the drain contact 160 may be deposited into the via. Due to the dielectric properties of the first porous portion 382, the first porous portion 382 can provide isolation between the source contact 150 and the gate contact 170. Similarly, due to the dielectric properties of the second porous portion 384, the second porous portion 384 can provide isolation between the drain contact 160 and the gate contact 170. Figure 400d thus illustrates the formation of an E-mode HEMT. In some examples, the source contact 150 and the drain contact 160 may be formed prior to the formation of the first porous portion 382 and second porous portion 384. For example, referring again to Figure 4b, a through-via may be formed through the N+ semiconductor layer 280 and the barrier layer 140, and the source contact 150 may be deposited into the via. In a similar manner, in one example, a through-via may be formed through the N+ semiconductor layer 280 and the barrier layer 140, and the drain contact 160 may be deposited into the via. The semiconductor structure may subsequently be subjected to an electrochemical etch process, as similarly described above with respect to Figure 4c. Portions of the N+ semiconductor layer 280 between the source contact 150, drain contact 160 and gate contact 170 may thus be exposed in the porosifictaion process. Said portions of the + semiconductor layer 280 may thus be porosified to form the first porous portion 382 and the second porous portion 384. Figures 4a-d thus illustrate a method for forming a semiconductor structure according to examples of the present disclosure. The electrochemical etch step described with respect to Figure 4c enables the formation of dielectric material for isolating the gate contact 170 from the source contact 150 and the drain contact 160. Furthermore, the self-aligned nature of the electrochemical etch step removes masking and etch steps involved in the formation of dielectric material for conventional HEMTs. Furthermore, the removal of the mask and etch steps can maintain the high-quality upper surface of the barrier layer 140 and prevent the formation of surface traps, which often occur as a result of the etch step. The present disclosure further provides a semiconductor device comprising a semiconductor structure according to examples of the present disclosure. In some examples the semiconductor device may comprise a semiconductor device for managing or transferring power. In some examples the semiconductor device may comprise a high electron mobility transistor (HEMT). The present disclosure further provides a power management device comprising a semiconductor device according to examples of the present disclosure. In some examples the power management device may manage or transfer power within an automotive vehicle, industrial machine or power infrastructure equipment. In some examples the power management device may comprise a power supply or power converter, such as a DC-DC converter, an AC-DC converter, a DC-AC converter or similar. In some examples the power management device may comprise a device for converting electrical energy to kinetic energy, such as a traction inverter or similar. In some examples the power management device may comprise a device for charging a battery, such as an onboard charger (OBC), a wireless charging device, or similar. In some examples the power management device may comprise a motor or a motor drive. In some examples the power management device may comprise a device for use in an energy storage system (ESS), such as a fuel cell inverter, ESS DC-DC converter or similar. In some examples the power management device may comprise a device for inputting power to, or outputting power from the grid, such as a three-phase inverter, three-phase rectifier, or similar. The present disclosure further provides a vehicle comprising a power management device according to examples of the present disclosure. In some examples the vehicle may comprise an automotive vehicle such as a car, a van, a heavy goods vehicle (HGV), a bus, a motorbike, or similar. In some examples the vehicle may comprise an aviation vehicle, such as an aeroplane, helicopter, or similar. In some examples the vehicle may comprise an aeronautical vehicle, such as a boat, ship or similar. It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

1. A semiconductor structure comprising:a channel layer;a barrier layer configured to induce a two-dimensional electron gas, 2DEG, in the channel layer;a semiconductor layer comprising a first porous portion and a non-porous portion, wherein the non-porous portion is configured to prevent formation of the 2DEG in a portion of the channel layer; anda first electrical contact over the non-porous portion.

2. The semiconductor structure according to claim 1 wherein edges of the first electrical contact align with edges of the non-porous portion.

3. The semiconductor structure according to claim 1 or 2 wherein the semiconductor layer comprises GaN.

4. The semiconductor structure according to any preceding claim wherein the semiconductor layer is doped N+.

5. The semiconductor structure according to any preceding claim wherein the first electrical contact comprises a gate contact.

6. The semiconductor structure according to any preceding claim further comprising a second electrical contact; and wherein the first porous portion is between the first electrical contact and the second electrical contact.

7. The semiconductor structure according to claim 6, when dependent on claim 5, wherein the second electrical contact comprises one of a source contact and a drain contact.

8. The semiconductor structure according to any preceding claim wherein the semiconductor layer further comprises a second porous portion; wherein the non-porous portion is between the first porous portion and the second porous portion.

9. The semiconductor structure according to claim 8 further comprising a third electrical contact; wherein the second porous portion is between the first electrical contact and the third electrical contact.

10. The semiconductor structure according to claim 9, when dependent on claim 7, wherein the third electrical contact comprises the other of the source contact and the drain contact.

11. The semiconductor structure according to any preceding claim wherein the first electrical contact comprises W, Ti, TiN, Ta and TaN.

12. A semiconductor device comprising the semiconductor structure according to any preceding claim.

13. A power management device comprising the semiconductor device according to claim 12.

14. A vehicle comprising the power management device according to claim 13.

15. A method of forming a semiconductor structure comprising:forming a channel layer;forming a barrier layer configured to induce a two-dimensional electron gas, 2DEG, in the channel layer;forming a semiconductor layer comprising a first porous portion and a non-porous portion, wherein the non-porous portion is configured to prevent formation of the 2DEG in a portion of the channel layer; andforming a first electrical contact over the non-porous portion.

16. The method according to claim 15 further comprising:forming the semiconductor layer;responsive to forming the semiconductor layer, forming the first electrical contact over the semiconductor layer;responsive to forming the first electrical contact, forming the first porous portion and the non-porous portion.

17. The method according to claim 16 wherein forming the first porous portion and the non-porous portion comprises electrochemically etching the semiconductor layer.

18. The method according to any of claims 15-17 wherein the edges of the first electrical contact align with edges of the non-porous portion.

19. The semiconductor structure according to any of claims 15-18 wherein the semiconductor layer comprises GaN.

20. The semiconductor structure according to any of claims 15-19 wherein the semiconductor layer is doped N+.

21. The semiconductor structure according to any of claims 15-20 wherein the first electrical contact comprises a gate contact.

22. The semiconductor structure according to any of claims 15-21 further comprising a second electrical contact; and wherein the first porous portion is between the first electrical contact and the second electrical contact.

23. The semiconductor structure according to claim 22, when dependent on claim 21, wherein the second electrical contact comprises one of a source contact and a drain contact.

24. The semiconductor structure according to any of claims 15-23 wherein the semiconductor layer further comprises a second porous portion; wherein the non-porous portion is between the first porous portion and the second porous portion.

25. The semiconductor structure according to claim 24 further comprising a third electrical contact; wherein the second porous portion is between the first electrical contact and the third electrical contact.19

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