Address translation for accelerator-triggered memory access requests

Abstract

An apparatus comprises processing circuitry 6 to execute instructions; memory management circuitry 16 associated with the processing circuitry, to perform address translation in response to memory access instructions executed by the processing circuitry; and accelerator control interface circuitry 14 to exchange control signals with at least one hardware accelerator 22 configurable, based on instructions executed by the processing circuitry, to perform a delegated task. The memory management circuitry is configured to support a plurality of active translation contexts, each active translation context being defined by context information stored in a corresponding set of context control registers. The plurality of active translation contexts include at least one accelerator translation context in which address translation is performed for accelerator-triggered memory access requests issued by the at least one hardware accelerator. The hardware accelerator accesses the memory system using virtual addresses, and reuses the memory management circuitry of the processing circuitry for address translation