Processor system

Abstract

A processor system with processor cores and an interface unit that receives first instructions, generates second instructions from the first instructions with an order that depends on a configuration of the processor cores and performs an operation based on the second instructions. The second instructions may be generated by determining a flow of processing sub-operations for the operation in question and allocating resources to each. This may be done by a pre-trained model. A performance characteristic may be provided for each sub-operation for optimisation. In an embodiment the instructions correspond to different instruction set architectures. In an embodiment the first instructions may comprise prefixes that determine an algorithm for generating the second instructions and a body for generating the second instructions. The algorithm may depend on a state of the interface unit. The algorithm may be a vector processing algorithm. The interface unit may comprise a non-integrated element seperate from the processor cores that may be arranged in a chip or chiplet separate to the chip or chiplet of the processor cores. The interface unit may comprise an element integrated within an integrated processor core, which may be arranged in a chip or chiplet with the integrated processor core. Figure 2