Semiconductor device having single-member conductive leads coupled to both sides of a die, and method for forming, and system incorporating, the semiconductor device

Abstract

A semiconductor device includes: a housing; a die disposed in the housing and having a first surface and a second surface; a first single component conductive lead electrically coupled to the first surface and extending through the housing; and a second single member conductive lead electrically coupled to the second surface and extending through the housing. Such semiconductor devices may be manufactured more easily, cheaply, and / or faster than existing semiconductor devices, and / or may accommodate larger semiconductor dies for a given device footprint.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202380099116.2 (22) Application Date 2023.06.06 (85) PCT International Application Entering National Phase Date 2025.12.05 (86) PCT International Application Application Data PCT / US2023 / 024511 2023.06.06 (87) PCT International Application Publication Data WO2024 / 253639 EN 2024.12.12 (71) Applicant Siliconix Company Address California, USA (72) Inventor Lin Changzhi T. Qiu (74) Patent Agency Yongxin Patent & Trademark Agency Co., Ltd. 72002 Patent Attorney Wang Yongjian (51) Int.Cl. H10W 70 / 40 (2026.01) H10W 72 / 50(2026.01) H10W 76 / 12(2026.01) H10D 80 / 20(2026.01) H10W 95 / 00(2026.01) (54) Title of Invention Semiconductor Device Having Single-Component Conductive Leads Coupled to Both Sides of a Die, Method for Forming a Semiconductor Device, and System Containing a Semiconductor Device (57) Abstract A semiconductor device includes: a housing; a die disposed in the housing and having a first surface and a second surface; a first single-component conductive lead electrically coupled to the first surface and extending through the housing; and a second single-component conductive lead electrically coupled to the second surface and extending through the housing. Compared with existing semiconductor devices, this semiconductor device can be manufactured more easily, cheaper, and / or faster, and / or can accommodate a larger semiconductor die for a given device coverage area. Claims (3 pages), Description (9 pages), Drawings (13 pages), CN 121866898 A, 2026.04.14, CN 1 21 86 68 98 A. 1. A semiconductor device comprising: a housing; a die disposed within the housing and having a first surface and a second surface; a first single-component conductive lead electrically coupled to the first surface and extending through the housing; and a second single-component conductive lead electrically coupled to the second surface and extending through the housing.2. The semiconductor device of claim 1, further comprising: a plurality of single-component conductive leads including the first single-component conductive lead, the plurality of single-component conductive leads being electrically coupled to the first surface and extending through the housing; and a plurality of other single-component conductive leads including the second single-component conductive lead, the plurality of other single-component conductive leads being electrically coupled to the second surface and extending through the housing. 3. The semiconductor device of claim 1, further comprising: a plurality of single-component conductive leads including the first single-component conductive lead, the plurality of single-component conductive leads being electrically coupled to the first surface and electrically coupled to each other and extending through the housing; and a plurality of other single-component conductive leads including the second single-component conductive lead, the plurality of other single-component conductive leads being electrically coupled to the second surface and electrically coupled to each other and extending through the housing. 4. The semiconductor device of claim 1, further comprising one or more transistors disposed on the die. 5. The semiconductor device of claim 1, further comprising: a transistor disposed on the die and having a drain and a source; a plurality of single-component conductive leads including the first single-component conductive lead, the plurality of single-component conductive leads being electrically coupled to one of the drain and the source; and a plurality of other single-component conductive leads including the second single-component conductive lead, the plurality of other single-component conductive leads being electrically coupled to the other of the drain and the source. 6. The semiconductor device of claim 1, further comprising: a conductive plate disposed on the exterior of the housing; a plurality of single-component conductive leads including the first single-component conductive lead, the plurality of single-component conductive leads being electrically coupled to the first surface and electrically coupled to the conductive plate; and a plurality of other single-component conductive leads including the second single-component conductive lead, the plurality of other single-component conductive leads being electrically coupled to the second surface. 7. The semiconductor device of claim 1, further comprising: a conductive plate disposed on the exterior of the housing; a transistor disposed on the die and having a drain and a source; a plurality of single-component conductive leads including the first single-component conductive lead, the plurality of single-component conductive leads being electrically coupled to the conductive plate and to one of the drain and the source; and a plurality of other single-component conductive leads including the second single-component conductive lead, the plurality of other single-component conductive leads being electrically coupled to another of the drain and the source.8. A method comprising: attaching a first side of each of at least one die to a corresponding stage of a leadframe strip; and attaching a second side of each of the at least one die to a corresponding stage of a jig frame strip. 9. The method of claim 8, wherein: attaching the first side comprises soldering the first side of each of the at least one die to a corresponding stage of the leadframe strip; and attaching the second side comprises soldering the second side of each of the at least one die to a corresponding stage of the jig frame strip. 10. The method of claim 8, further comprising: forming solder on each stage of the leadframe strip before attaching the first side of each of the at least one die to a corresponding stage of the leadframe strip; and forming solder on each stage of the jig frame strip before attaching the second side of each of the at least one die to a corresponding stage of the jig frame strip. 11. The method of claim 8, further comprising: aligning the jig frame strip with the lead frame strip before attaching a respective stage of the jig frame strip to a second side of each of the at least one die. 12. The method of claim 8, further comprising: aligning an alignment mark of the jig frame strip with a corresponding alignment mark of the lead frame strip before attaching a respective stage of the jig frame strip to a second side of each of the at least one die. 13. The method of claim 8, further comprising: encapsulating each die in the die to form a chip. 14. The method of claim 13, further comprising: testing the chip before separating the chip from the lead frame strip and the jig frame strip. 15. The method of claim 13, further comprising: removing impurities from the chip, the lead frame strip, and the jig frame strip before separating the chip from the lead frame strip and the jig frame strip. 16. The method of claim 13, further comprising: plating the exposed leads of the chip before separating the chip from the lead frame strip and the clamp frame strip. 17. The method of claim 13, further comprising: marking the housing formed by encapsulating the chip before separating the chip from the lead frame strip and the clamp frame strip. 18. The method of claim 13, further comprising: separating the chip from the lead frame strip and the clamp frame strip. 19. The method of claim 18, further comprising: shaping the exposed leads of the chip after separating the chip from the lead frame strip and the clamp frame strip.20. A system comprising: a controller; a filter network; and a switching circuit configured to drive the filter network in response to the controller to generate a regulated output signal, the switching circuit having one or more semiconductor devices, each semiconductor device comprising: a housing; a die disposed in the housing and having a first surface and a second surface; a first single-component conductive lead electrically coupled to the first surface and extending through the housing; and a second single-component conductive lead electrically coupled to the second surface and extending through the housing. 21. The system of claim 20, wherein at least one of the one or more semiconductor devices comprises a MOS transistor. Claims 3 / 3 Page 4 CN 121866898 A Semiconductor device having single-component conductive leads coupled to both sides of a die, a method for forming a semiconductor device, and a system comprising a semiconductor device Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to an improved arrangement of a chip having a die, wherein leads are attached to both surfaces of the die and extend from a housing encapsulating the die. Background Art

[0002] In the manufacture of known transistor chips, leads are attached to both surfaces of a die. Attachment of leads to conductive pads on the bottom surface of the die can be achieved by placing a first lead on the conductive pads of the die and forming a conductive connection, for example, by soldering. This can be done simultaneously with multiple leads and each die or multiple dies before the leads / die are separated from the lead frame. Then, the connection of one or more leads to conductive pads on the second (top) surface of the die is performed separately (i.e., typically not simultaneously with the placement and attachment of other second leads) and in a more complex manner than the placement and attachment of the first leads. The second leads can also be multi-part.

[0003] There is a need to improve this type of assembly to enhance manufacturability and reduce the chance of defects. Summary of the Invention

[0004] In one embodiment, a semiconductor device is provided, comprising: a housing; a die (bare die) disposed within the housing and having a first surface and a second surface; a first single-component conductive lead electrically coupled to the first surface and extending through the housing; and a second single-component conductive lead electrically coupled to the second surface and extending through the housing. Compared to existing semiconductor devices, this semiconductor device is, for example, cheaper to manufacture and / or can accommodate a larger die for a given device footprint.

[0005] In another embodiment, a system is provided that includes (in combination with) a controller and one or more such semiconductor devices.

[0006] In yet another embodiment, a method for manufacturing one or more semiconductor devices is provided, comprising: attaching a first side of each of at least one die to a corresponding stage (pad) of a lead frame strip; and attaching a second side of each of the at least one die to a corresponding stage of a jig frame strip. Compared to existing methods for manufacturing a given number of semiconductor devices, this method can be cheaper, less complex, and / or faster, and / or can produce a higher percentage of usable semiconductor devices.

[0007] A more detailed understanding can be obtained from the following description, given by way of example in conjunction with the accompanying drawings, wherein like reference numerals indicate like elements, and wherein: FIG1A is a view of an NMOS power transistor according to an embodiment; FIG1B is a schematic symbol of the NMOS power transistor of FIG1A; FIG2 is a cross-sectional perspective side view of a conventional NMOS power transistor; FIG3 is a cross-sectional perspective side view of an NMOS power transistor according to an embodiment; FIG4A to FIG4C are respective plan views of a lead frame (LF) strip, a clamp frame (CF) strip, and a CF strip disposed on and aligned with the LF strip according to an embodiment; FIG5 is a plan view of an LF strip according to an embodiment; FIG6 is a plan view of the LF strip of FIG5 according to an embodiment, wherein solder is formed on the surface of a die stage (base, pad); Figure 7 is a plan view of the LF strip of Figure 6 according to an embodiment, wherein the die is disposed on a die stage with solder; Figure 8 is a plan view of the LF strip of Figure 7 according to an embodiment, wherein solder is formed on the exposed surface of the die; Figure 9 is a plan view of a CF strip aligned with and disposed on the LF strip of Figure 8 and a stage for the CF strips disposed on the exposed surface of the respective dies according to an embodiment; Figure 10 is a CF strip and LF strip of Figure 9 according to an embodiment, wherein the die and a portion of the leads are encapsulated (forming a housing); Figure 11 is a flowchart of a method for forming a semiconductor device such as the transistors of Figures 1A, 3 and 12 according to an embodiment; Figure 12 is a cross-sectional perspective side view of a conventional NMOS power transistor having a given occupied area, with an indication of the maximum permissible die size. Figure 13 is a cross-sectional perspective side view of a packaged NMOS power transistor having the same given footprint as the transistor of Figure 12 and having an indication of the maximum permissible die size according to an embodiment; and Figure 14 is a schematic diagram of a system including one or more of the semiconductor devices of Figures 1A, 3 and 12 according to an embodiment.Detailed Description

[0008] Certain terms are used in the following description for convenience only and not for limitation. The terms “inward” and “outward” refer to directions toward and away from the portions marked in the figures. The terms “top” and “bottom” refer to directions on the objects shown in the figures. References to a list of items cited as, for example, “at least one of a or b” (where a and b represent the listed items) mean any single item of item a or b, or a combination of a and b. This will also be applied in a similar manner to a list of three or more items, such that individual items or combinations thereof are included. Unless otherwise stated, the terms “about” and “approximately” cover + or -10% of indicated values. Terms include the words specifically pointed out above, their derivatives, and words with similar meanings.

[0009] FIG1A is an isometric view of a packaged semiconductor device (here, an NMOS power transistor 100 having package 102) according to one embodiment. The power transistor 100 is suitable for many applications, such as as one of the output transistors of a switching power supply (not shown in FIG1A). Package 102 includes an optional drain pad 104 (which may also be configured as a heat sink), drain leads 106 coupled to the drain pad 104, source leads 108, gate leads 110, and a housing 112. At the ends opposite to the optional drain pad 104, the drain leads 106 may be electrically connected together. Alternatively, in embodiments omitting the drain pad 104, each drain lead 106 may extend into the housing and be electrically coupled (connected) to a pad on the surface of a die (bare die) (not shown in FIG. 1A) within the housing 112. As described below in conjunction with FIG. 1B, transistor 100 may be configured to have an inherent body diode (not shown in FIG. 1A) coupled within the housing 112 to the body region of the transistor (not shown in FIG. 1A) via the source of the transistor (not shown in FIG. 1A). In one embodiment, transistor 100 is a vertical enhancement-mode NMOS power transistor. Specification 2 / 9 pages 6 CN 121866898 A

[0010] FIG1B shows a schematic symbol 120 of the NMOS power transistor 100 of FIG1A in an embodiment where the transistor is an enhancement-type transistor. According to the schematic symbol 120, the transistor 100 includes a gate (G) 122, an N-type drain (D) 124, an N-type source (S) 126, a P-type body 128, and an inherent PN junction diode (generally referred to as an "inherent body diode" or "body diode") 130.

[0011] When the gate-to-source voltage is less than the threshold voltage, the NMOS transistor 100 operates in its cutoff region, during which the drain-to-source current is relatively small (e.g., a few to tens of microamps (μA), and generally approximately 0 amps (A)).

[0012] When the drain-to-source voltage is greater than and less than, the NMOS transistor 100 operates in its linear region, or "transistor" region, during which time, for a given value, the value of is proportional to.

[0013] And when both are greater than and greater than, the NMOS transistor 100 operates in its saturation region, during which time the value of is proportional to (many applications of NMOS transistors require that circuits including NMOS transistors be configured such that the NMOS transistors operate in their saturation region).

[0014] If the drain voltage is lower than the source voltage when the NMOS transistor 100 operates in or near its off mode, then the inherent body diode 130 can conduct source-to-drain current if the source-to-drain voltage is greater than the threshold or "on" voltage of the body diode. For example, the body diode 130 can conduct source-to-drain current for a relatively short period of time during the discharge of the phase inductor of a switching power supply such as a buck converter.

[0015] FIG2 is a cross-sectional perspective side view of a conventional NMOS power transistor 200, which includes a die (bare die) 202, a lead frame stage (base, pad) 204, a first lead 206, a second lead 208 having an inner portion 210 and an outer portion 212, and a housing 214.

[0016] During the manufacture of the transistor 200, the first lead 206 is attached to a lead frame (e.g., integral with the lead frame), which includes the stage 204 and facilitates placing the first lead onto conductive pads (not shown in FIG2) on a first side (here, the bottom) of the die 202 and attaching (typically by soldering) the first lead to the conductive pads. The first lead is only separated from the lead frame after the first lead 206 has been attached to the conductive pads of the die. Furthermore, because other first leads are also attached to the lead frame, multiple first leads can be simultaneously placed on and attached to the corresponding conductive pads on the first side of the die.

[0017] In contrast, compared to the placement and attachment of the first leads 206, the second leads 208 are placed separately (i.e., not typically simultaneously with the placement and attachment of other second leads) and in a more complex manner on the conductive pads (not shown in FIG. 2) on the second side (here, the top) of the die 202 and attached to those conductive pads.

[0018] First, the inner portion 210 of the second lead 208 is attached (typically soldered) to the conductive pads on the upper side of the die 202. However, if the die 202 and the inner portion 210 are rotated relative to each other in a plane parallel to the die 202 during the placement and attachment process, or are otherwise misaligned (even by a relatively small amount), the resulting transistor 200 may become unusable and may therefore be discarded or "wasted".After attaching the inner portion 210 to the conductive pads on the upper surface of the die 202, the outer portion 212 of the second lead 208 is placed onto the inner portion and attached by soldering or fusion, thereby forming an attachment joint 216. However, if the inner portion 210 and the outer portion 212 are rotated relative to each other in a plane parallel to the die 202 or otherwise misaligned (even by a relatively small amount) during the placement and attachment process, the resulting transistor 200 may become unusable and may therefore be discarded or "wasted". Furthermore, the attachment joint 216 is an additional potential point of failure. Additionally, placing and attaching the second lead 208 separately is time-consuming and therefore reduces the throughput of the transistor 200 manufacturing process (i.e., the number of semiconductor devices per unit time). Furthermore, the volume occupied by the attachment connector 216 reduces the area available for the die 202 within the housing 214, and thus limits the maximum die size that the housing can accommodate for a given footprint of the transistor 200.

[0019] Therefore, there is a need for a semiconductor device with leads that can be placed more reliably and can accommodate larger dies for a given device footprint, and / or a semiconductor manufacturing process that is more reliable, cheaper, and / or has higher throughput than existing processes.

[0020] FIG3 is a cross-sectional perspective side view of an NMOS power transistor 300 according to an embodiment, which includes a die 302, a lead frame stage 304, a first lead 306, a second lead 308, and a housing 314.

[0021] During the manufacture of transistor 300, a first lead 306 is attached to a lead frame (not shown in FIG. 3) (e.g., integral with the lead frame). This facilitates placing the first lead onto a conductive pad (not shown in FIG. 3) on a first side (here, the bottom) of die 302 and attaching (typically by soldering) the first lead to that conductive pad. The first lead is only separated from the lead frame after the first lead 306 has been placed and attached to the conductive pad on the first side of the die. Furthermore, because other first leads are also attached to the lead frame, multiple first leads can be simultaneously attached to corresponding conductive pads on the first side of the die.

[0022] Similarly, during the manufacture of transistor 300, unlike the second lead 208 of FIG. 2, the second lead 308 is a single piece (a single component) attached to the jig frame (not shown in FIG. 3). This facilitates placing the second lead onto the conductive pads (not shown in FIG. 3) on the second side (here, the top) of the die 302 and attaching (typically by soldering) the second lead to the conductive pads (not shown in FIG. 3) on the second side of the die. The second lead is only separated from the jig frame after the second lead 308 has been placed and attached to the conductive pads on the second side of the die.Furthermore, because other second leads are also attached to the fixture frame, multiple second leads can be simultaneously attached to corresponding conductive pads on the second side of the die.

[0023] As described below, because the second lead 308 is a single component, it is less prone to errors compared to the multi-component lead 208 of FIG. 2. Furthermore, because the second lead 308 is attached to the fixture frame during placement and attachment to the top side of the die, rotational and other misalignment errors can be reduced, minimizing at least one potential point of failure (e.g., because there is no attachment connector such as connector 216 of FIG. 2), housing 314 can accommodate a die 302 larger than housing 214 (FIG. 2), and the process for manufacturing transistor 300 can be more reliable than the process for manufacturing transistor 200 of FIG. 2. Moreover, because multiple second leads 308 can be simultaneously attached to die 302, the process for manufacturing transistor 300 can be faster (i.e., higher throughput), cheaper, and / or less complex than the process for manufacturing transistor 200 of FIG. 2.

[0024] In FIG3, the first lead 306 extends (protrudes) from the top (non-mounting) side 307 of the housing 314, bends at the first bend 306a (bends upward in FIG3), has an oriented (oriented upward in FIG3) extension 306b, and then bends outward to form a contact area 306c, which is generally aligned with the bottom (mounting) side 309 of the housing 314. The second lead 308a, extending from the side of housing 314 opposite to the first lead 306, also includes a first bend 308a (an upward bend in FIG. 3) extending from the surface of die 302 opposite to the lead frame platform 304 (an upward bend in FIG. 3), the first bend transitioning to an outwardly oriented extension 308b extending through the side of housing before reaching a second bend 308c (an upward bend in FIG. 3), the second bend 308c transitioning to an extension 308d (an upward bend in FIG. 3), the extension 308d transitioning via a third bend 308e to a contact area 308f, the contact area 308f being substantially aligned with the bottom (mounting) side 309 of housing.

[0025] FIG. 4A is a plan view of a lead frame strip 400 according to an embodiment.

[0026] FIG. 4B is a plan view of a clamp frame strip 402 according to an embodiment.

[0027] FIG4C is a plan view of the fixture frame strip 402 disposed on and aligned with the lead frame strip 400 according to an embodiment, as per page 4 / 9 of the specification 8 CN 121866898 A.

[0028] Referring to Figures 4A-4C, a die (not shown in Figures 4A-4C) is placed on a stage 406 of a leadframe 400, and conductive pads on the bottom of the die are electrically coupled (e.g., by soldering) to leads 408 of the leadframe strip. A coupling agent (e.g., adhesive solder) can hold each die to the corresponding pad, or a separate adhesive or other bonding agent can be used instead of or as a supplement to the coupling agent.

[0029] A clamping frame strip 402 is then placed on the die-filled leadframe strip 400, and the clamping frame strip 402 is aligned with the leadframe strip using alignment holes or other alignment marks 410. The leadframe strip 400 and the clamping frame strip 402 move toward each other such that the leadframe strip and the clamping frame strip "clamp" the die.

[0030] Next, the stage 412 of the fixture frame strip 402 is brought into contact with the top of the die (not shown in Figures 4A-4C) so that the conductive pads on the top of the die are electrically coupled (e.g., by soldering) to the leads 414 of the fixture frame strip.

[0031] The die and portions of the leads 408 and 414 are then encapsulated in a housing made of a suitable material (such as epoxy or ceramic) (not shown in Figures 4A-4C, but similar to the housing 1000 of Figure 10) to form a semiconductor chip.

[0032] Next, the semiconductor chip is separated from the lead frame strip 400 and the fixture frame strip 402.

[0033] Still referring to Figures 4A-4C, because the lead frame strip and the fixture frame strip allow multiple semiconductor chips to be formed simultaneously, the cost, complexity, and / or manufacturing time per chip can be reduced compared to a process in which the leads 208 (Figure 2) are placed individually and coupled to the pads on the semiconductor die. For example, although the lead frame strip 400 and the clamp frame strip 402 are shown to accommodate twenty-four dies, the lead frame strip and the clamp frame strip can be configured to accommodate any suitable number of dies, such as thirty-two, sixty-four, two hundred and fifty-six, or five hundred and twelve dies. Furthermore, relative to a process in which leads 414 are individually placed and coupled to pads on the dies (leads 208 in FIG. 2), alignment holes and alignment marks 410 can reduce the severity and occurrence of alignment errors, thereby improving process yield.

[0034] FIG. 5 is a plan view of a lead frame strip 500 having a stage 502, leads 504, and alignment holes and marks 506 according to an embodiment.Although the leadframe strip 500 is shown as comprising twenty-four platforms 502 configured to accommodate twenty-four dies (not shown in FIG. 5), the leadframe strip may comprise any suitable number of platforms (e.g., twelve, sixteen, thirty-two, forty-eight, sixty-four, seventy-two, ninety-six, one hundred and twenty, one hundred and twenty-eight, one hundred and forty-four, one hundred and sixty-eight, one hundred and ninety-two, two hundred and sixteen, two hundred and forty, and two hundred and fifty-six) of dies configured to accommodate any suitable number (e.g., twelve, sixteen, thirty-two, forty-eight, sixty-four, seventy-two, ninety-six, one hundred and twenty, one hundred and twenty-eight, one hundred and forty-four, one hundred and sixty-eight, one hundred and ninety-two, two hundred and sixteen, two hundred and forty, and two hundred and fifty-six).

[0035] FIG. 6 is a plan view of the leadframe strip 500 of FIG. 5 according to an embodiment, wherein solder 600 is formed on the surface of the die platform 502.

[0036] FIG7 is a plan view of the lead frame strip 500 of FIG6 according to an embodiment, wherein a die 700 is disposed on a die carrier 502 with solder.

[0037] FIG8 is a plan view of the lead frame strip 500 of FIG7 according to an embodiment, wherein solder 800 is formed on the exposed surface of the die 700.

[0038] FIG9 is a plan view of a clamp frame strip 900 having a die carrier 902, a lead 904, and alignment holes and markings 906 disposed on the lead frame strip 500 of FIG8 according to an embodiment, wherein the alignment holes and markings are aligned with corresponding alignment holes and markings 506 of the lead frame strip 500 (see FIG5), and the clamp frame strip carriers 902 are respectively disposed on the exposed surfaces of the respective dies 700 and respectively include conductive pads (not shown in FIG9) electrically coupled (e.g., by solder) to the corresponding conductive pads on the die surfaces. And the conductive pads of the fixture frame strip stage 902 are conductively coupled (e.g., through solder) to the leads 904. Specification 5 / 9 pages 9 CN 121866898 A

[0039] FIG10 is a plan view of a structure 1002 obtained from the fixture frame strip 900 and lead frame strip 500 of FIG9 (not visible in FIG10) according to an embodiment, wherein portions of the die 700 of FIG9 (not visible in FIG10) and the leads 504 and 904 are enclosed in corresponding housings 1000.

[0040] FIG11 is a flowchart 1100 of a method (sometimes referred to as a “semiconductor process” or “semiconductor manufacturing process”) for forming a semiconductor device such as the transistor 100 of FIG1A, the transistor 300 of FIG3, or the transistor 1300 of FIG13 according to an embodiment.

[0041] Referring to Figures 5-11, a semiconductor process for manufacturing semiconductor devices or chips (such as transistor 100 of Figure 1A, transistor 300 of Figure 3, or transistor 1300 of Figure 13) is described according to one embodiment.

[0042] Referring to Figures 5 and 11, an unfilled leadframe strip 500 is introduced into the processing line.

[0043] Referring to Figures 6 and 11, at 1102, solder 600 is formed on the die stage 502 of the leadframe strip 500. For example, the solder can be printed onto conductive pads (not shown in Figure 6) disposed on the stage 502 and coupled to the leads 504 respectively. The solder 600 can also act as an adhesive to secure the die (see Figure 7) to the stage 502; alternatively, an adhesive separate from the solder (independent of the solder) can be formed, for example, by printing onto portions of the stage other than the conductive pads. In one embodiment, solder printing is a suitable solder formation technique because it provides precise control over the volume of solder deposited on the stage 502.

[0044] Referring to Figures 7 and 11, at 1104, a die 700 is attached to a die carrier 502 of a lead frame strip 500. The die 700 is attached to the carrier 502 such that solder 600 (Figure 6) electrically couples conductive pads (not shown in Figure 7) on the bottom surface of the die to corresponding conductive pads (not shown in Figure 7) on the die-facing surface of the carrier 502, wherein these carrier conductive pads are electrically coupled to corresponding groups of leads 504. For example, item 1104 may include solder reflow (reflow soldering). Thus, after item 1104 is completed, the circuitry on each die 700 is coupled to the corresponding group of leads 504 via the conductive pads of the carrier 502, the solder, and the conductive pads of the die 700. Furthermore, as described above in conjunction with Figures 6 and 11, the die 700 can be secured to the stage 502 by solder 600 (e.g., adhesive solder) or by a separate adhesive.

[0045] Referring to Figures 8 and 11, at 1106, solder 800 is formed on the exposed surface of the die 700 (the upper surface in Figure 8). For example, solder 800 can be printed on conductive pads (not shown in Figure 8) disposed on the exposed surface of the die 700 and coupled to corresponding circuits on the die, respectively. Solder 800 can also act as an adhesive to secure the die 700 to the stage 902 of the jig frame strip 900, as described below in conjunction with Figure 9; alternatively, adhesive separate from the solder can be formed, for example, by printing on portions of the upper surface of the die other than the conductive pads. In one embodiment, solder printing is a suitable solder formation technique because it can provide precise control over the volume of solder deposited on the die 700.

[0046] Referring to Figures 9 and 11, at 1108, the clamp frame strip 900 is aligned with the lead frame strip 500. For example, strips 500 and 900 are aligned by using one or more alignment tools (not shown in Figure 9) to align the alignment hole or mark 506 with the corresponding alignment hole or mark 906.Due to this alignment of the clamp frame strip 900 with the lead frame strip 500, each platform 902 of the clamp frame strip is aligned with the corresponding platform 502 of the lead frame strip 500 (see FIG. 5), and thus with the corresponding die 700. In other words, due to the alignment of the lead frame strip 500 with the clamp frame strip 900, each die 700 is effectively “clamped” between the corresponding pair of platforms 502 and 902.

[0047] Still referring to FIG. 9 and FIG. 11, at 1110, the clamp frame strip 900 is moved toward the lead frame strip 500, while achieving alignment to attach the platform 902 of the clamp frame strip to the die 700. A stage 902 is attached to a die 700 such that solder 800 (FIG. 8) electrically couples conductive pads (not shown in FIG. 9) on the exposed surface of the die (the top surface in FIG. 9) to corresponding conductive pads (not shown in FIG. 9) on the die-facing surface of the stage 902, wherein these stage conductive pads are electrically coupled to corresponding grouped leads 904. For example, item 1110 may include solder reflow. Thus, after completing item specification 6 / 9 pages 10 CN 121866898 A 1110, the circuitry on each die 700 is coupled to the corresponding grouped leads 904 via the conductive pads of the stage 902, the solder, and the conductive pads on the top surface of the die 700 (the surface facing the stage 902). Furthermore, as described above in conjunction with FIG. 8 and FIG. 11, the stage 902 can be attached to the die 700 by solder 800 (e.g., adhesive solder) or by a separate adhesive.

[0048] Referring to Figures 10 and 11, at 1112, the die 700 of Figure 9 (the die not visible in Figure 10) and portions of the leads 504 and 904 extending from the die (see, for example, Figures 7 and 9) are encapsulated with a suitable material to form a housing 1000. For example, epoxy resin or other plastics may be molded (e.g., injection or another type of molding) around the die 700 to form the housing 1000. Alternatively, the housing may be formed of ceramic or may be hermetically sealed. And, in another example, the encapsulated die 700 may each be formed to include a corresponding conductive plate, such as the ground plane or drain plate 104 of Figure 1A.

[0049] Referring to Figure 11, at 1114, the resulting structure 1002 of Figure 10 is post-encapsulated. For example, cleaning structure 1002 (removing residues) or otherwise cleaning it, plating the exposed portions of leads 504 and 904 (e.g., with tin (Sn)), and laser marking the housing 1000 (e.g., with part number and supplier).

[0050] Next, at 1116, the contained semiconductor component, device, or chip is separated from the lead frame strip 500 and the fixture frame strip 900, and referring to FIG. 3, the exposed portions of leads 504 and 904 remaining after component separation are shaped to form external leads, such as leads 306 and 308. Alternatively, each set of leads 504 or 904 may be coupled together or may be a solid piece, and may be shaped in the same manner as the leads are separated from each other.

[0051] Then, at 1118, the separated semiconductor component, device, or chip is tested. For example, the component may be subjected to electrical signal testing, such as JTAG boundary scan or electrical and thermal stress testing.

[0052] Next, at 1120, the semiconductor component, device, or chip is classified based on the test results at item 1118.

[0053] Referring again to Figures 5-11, the semiconductor process described in conjunction with flowchart 1100 can produce semiconductor components, devices, or chips (sometimes referred to as “ICs” or “integrated circuits”), which, on a chip-by-chip basis, are up to about 40% cheaper to manufacture than equivalent chips manufactured by other processes, and can increase the yield of acceptable ICs by up to about 1.5%.

[0054] Figure 12 is a cross-sectional perspective side view of a conventional NMOS power transistor 1200 having a die 1202 and manufactured according to a separate lead placement process similar to the process described above in conjunction with Figure 2 and utilizing a dual-component lead 1204 (indicated together with the total length) similar to the dual-component lead 208 of Figure 2.

[0055] FIG13 is a cross-sectional perspective side view of an NMOS power transistor 1300 having a die 1302 and manufactured according to the process described above in conjunction with FIG5-11, and utilizing a single-component lead 1304 (one such lead is shown in FIG13 and indicated along with the total length), which is similar to the single-component leads 306 and 308 of FIG3. In FIG13, the single-component lead 1304 rises upward from the top surface of the die 1302 at a first bend 1304a, then transitions to an extension 1304b that extends outward beyond (through) the housing 1305, then bends downward at a second bend 1304c, and then further extends outward to a connection region 1304d that is generally at approximately the same level as the lead 1306, which is connected to the bottom surface of the die 1302. Therefore, leads 1304 and 1306 provide the same functionality as leads 1204 and 1206 of the conventional transistor 1200 of FIG12.

[0056] Referring to Figures 12 and 13, the power transistor 1300 may have a maximum die size that is up to about 30% larger than the maximum die size that the power transistor 1200 may have. That is, the maximum die size allowed by the semiconductor chip package produced by the manufacturing process described above in conjunction with Figures 5-11 is up to about 30% larger than the maximum die size allowed by the package manufactured by the process of using a single lead placement process with dual-component leads 1204 as described above in conjunction with Figures 2 and 12. For example, = is 3.7 mm (mm) compared to = 4.41 mm. Specification 7 / 9 pages 11 CN 121866898 A

[0057] Figure 14 is a schematic diagram of a system 1400 according to an embodiment, the system 1400 including one or more of the NMOS transistors 100, 300 or 1300 of Figures 1, 3 and 13. For illustrative purposes, system 1400 is described as including two NMOS transistors 1300; however, it should be understood that if one or both transistors are replaced with NMOS transistors 100 or 300, system 1400 will be similarly configured and will function similarly.

[0058] In one embodiment, system 1400 is a single-phase buck converter power supply that includes a power controller 1402, a switching circuit 1404, and a filter circuit 1406, and is configured to provide a regulated output voltage to a load 1408.

[0059] Controller 1402 may be a conventional power controller and is configured to receive (or its derivative) as a feedback signal, and may also be configured to receive (or its reciprocal) as another feedback signal, depending on in which control mode power system 1400 is configured to operate. For example, if controller 1402 employs current-mode control, the controller may form a current control loop that receives the voltage as input. Controller 1402 is also coupled between the controller power supply and circuit ground.

[0060] The switching circuit 1404 includes a high-side NMOS transistor 1410 and a low-side NMOS transistor 1412, both of which are the same as or similar to the NMOS transistor 1300 in FIG. 13. The drain of the high-side transistor 1410 is coupled to the input voltage, its gate is coupled to receive the control signal Control_Highside from the controller 1402, and its source is coupled to the input node 1414 of the filter circuit 1406. The drain of the low-side transistor 1412 is coupled to the input node 1414 of the filter circuit 1406, its gate is coupled to receive the control signal Control_Lowside from the controller 1402, and its source is coupled to circuit ground.

[0061] The filter circuit 1406 includes an inductor 1416 coupled between the input node 1414 and the output node 1418 of the filter circuit 1406, and includes a capacitor 1420 coupled between the output node 1418 of the filter circuit and circuit ground.

[0062] The load 1408 can be any suitable load, such as a microprocessor, microcontroller, or other integrated circuit.

[0063] In operation, the power controller 1402 generates a Control_Highside with a level that “turns on” transistor 1410 and a Control_Lowside with a level that “turns off” transistor 1412. A linearly increasing current flows from the drain-source junction of the “turning on” transistor 1410, through the inductor 1416, to the capacitor 1420 and the load 1408. The corresponding component of this linearly increasing current powers the load 1408 and charges the capacitor 1420.

[0064] After a period of time, the power controller 1402 generates a Control_Highside with a level that “turns off” transistor 1410 and a Control_Lowside with a level that “turns on” transistor 1412. After this switching transition, a linearly decreasing current flows from circuit ground through the source-drain junction of the “on” transistor 1412 and through inductor 1416 to capacitor 1420 and load 1408. The corresponding component of this linearly decreasing current powers load 1408 and charges capacitor 1420. Depending on the timing of the “turn-off” of transistor 1410 relative to the “on” of transistor 1412, the intrinsic diode of transistor 1412 (see FIG. 1B) can be forward biased and conduct for a period of time before transistor 1412 is fully “on”.

[0065] Subsequently, the power controller 1402 repeats this switching cycle, thereby adjusting the duty cycle of the transistor 1410 in such a way as to adjust to a value such as 1.1 volts (V). The controller 1402 and the power system 1400 are configured to adjust to a value such as 1.1 volts (V).

[0066] Further details regarding the structure and operation of the power system 1400 and similar power supplies are known.

[0067] Referring to Figures 1A-1B, Figures 3-11 and 13-14, alternative embodiments are envisioned. For example, although a process for packaging the NMOS transistor described on pages 8 / 9 of the specification 12 CN 121866898 A is described, other semiconductor components, devices, chips and / or ICs (such as PMOS transistors, bipolar transistors, BiCMOS transistors, microcontrollers and / or microprocessors) can be packaged according to the above semiconductor packaging process.Furthermore, system 1400 may be a power supply other than a single-phase buck converter, such as a multiphase buck converter, boost converter, buck-boost converter, and / or flyback converter with or without a coupling inductor, may be a current regulator as an alternative and / or supplement to a voltage regulator, and / or may be a system other than a power supply.

[0068] Although features and elements of the disclosed subject matter have been described in specific combinations in the embodiments, each feature or element may be used alone without other features and elements of the embodiments, or in various combinations with or without other features and elements of the disclosed subject matter.

[0069] Although features and elements have been described above in specific combinations, those skilled in the art will understand that each feature or element may be used alone or in any combination with other features and elements. Instruction manual page 9 / 9, page 13, CN 121866898 A, Figure 1A; Instruction manual figure 1 / 13, page 14, CN 121866898 A, Figure 1B; Instruction manual figure 2 / 13, page 15, CN 121866898 A, Figure 2, Figure 3; Instruction manual figure 3 / 13, page 16, CN 121866898 A, Figure 4A, Figure 4B, Figure 4C; Instruction manual figure 4 / 13, page 17, CN 121866898 A, Figure 5; Instruction manual figure 5 / 13, page 18, CN 121866898 A, Figure 6; Instruction manual figure 6 / 13, page 19, CN 121866898 A, Figure 7; Instruction manual figure 7 / 13, page 20, CN 121866898 A, Figure 8; Instruction manual figure 8 / 13, page 21, CN 121866898 A, Figure 9; Instruction manual figure 9 / 13, page 22, CN 121866898 Figure 10, Appendix to the Instruction Manual, Page 10 / 13, 23 CN 121866898 Figure 11, Appendix to the Instruction Manual, Page 11 / 13, 24 CN 121866898 Figure 12, Figure 13, Appendix to the Instruction Manual, Page 12 / 13, 25 CN 121866898 Figure 14, Appendix to the Instruction Manual, Page 13 / 13, 26 CN 121866898 A.

Claims

1. A semiconductor device comprising: case; A die, the die being disposed within the housing and having a first surface and a second surface; A first single-component conductive lead is electrically coupled to the first surface and extends through the housing; as well as A second single-component conductive lead is electrically coupled to the second surface and extends through the housing.

2. The semiconductor device according to claim 1, further comprising: The plurality of single-component conductive leads, including the first single-component conductive lead, are electrically coupled to the first surface and extend through the housing; as well as The second single-component conductive lead includes a plurality of other single-component conductive leads, which are electrically coupled to the second surface and extend through the housing.

3. The semiconductor device according to claim 1, further comprising: The plurality of single-component conductive leads, including the first single-component conductive lead, are electrically coupled to the first surface and to each other and extend through the housing; as well as The second single-component conductive lead includes a plurality of other single-component conductive leads, which are electrically coupled to the second surface and to each other and extend through the housing.

4. The semiconductor device of claim 1, further comprising one or more transistors disposed on the die.

5. The semiconductor device according to claim 1, further comprising: A transistor, the transistor being disposed on the die and having a drain and a source; Including a plurality of single-component conductive leads, the plurality of single-component conductive leads being electrically coupled to one of the drain and the source; and The plurality of other single-component conductive leads, including the second single-component conductive lead, are electrically coupled to another of the drain and the source.

6. The semiconductor device according to claim 1, further comprising: A conductive plate, which is disposed on the outside of the housing; Including a plurality of single-component conductive leads, the plurality of single-component conductive leads being electrically coupled to the first surface and to the conductive plate; and The second single-component conductive lead includes a plurality of other single-component conductive leads, which are electrically coupled to the second surface.

7. The semiconductor device according to claim 1, further comprising: A conductive plate, which is disposed on the outside of the housing; A transistor, the transistor being disposed on the die and having a drain and a source; Including a plurality of single-component conductive leads, the plurality of single-component conductive leads being electrically coupled to the conductive plate and electrically coupled to one of the drain and the source; and The plurality of other single-component conductive leads, including the second single-component conductive lead, are electrically coupled to another of the drain and the source.

8. A method comprising: Attach the first side of each die in at least one die to the corresponding stage of the lead frame strip; as well as The second side of each of the at least one die is attached to the corresponding stage of the clamp frame strip.

9. The method according to claim 8, wherein: The attachment of the first side includes welding the first side of each of the at least one die to a corresponding platform of the lead frame strip; and The attachment of the second side includes welding the second side of each of the at least one die to the corresponding platform of the jig frame strip.

10. The method of claim 8, further comprising: Solder is formed on each platform of the lead frame strip before attaching the first side of each of the at least one die to the corresponding platform of the lead frame strip. as well as Solder is formed on each platform of the clamp frame strip before the second side of each of the at least one die is attached to the corresponding platform of the clamp frame strip.

11. The method of claim 8, further comprising: Before attaching the respective platform of the clamp frame strip to the second side of each of the at least one die, align the clamp frame strip with the lead frame strip.

12. The method of claim 8, further comprising: Before attaching the respective platform of the clamp frame strip to the second side of each of the at least one die, align the alignment marks of the clamp frame strip with the corresponding alignment marks of the lead frame strip.

13. The method of claim 8, further comprising: Each die in the die is encapsulated to form a chip.

14. The method of claim 13, further comprising: The chip is tested before it is separated from the lead frame strip and the clamp frame strip.

15. The method of claim 13, further comprising: Before separating the chip from the lead frame strip and the clamp frame strip, the chip, the lead frame strip and the clamp frame strip are cleaned of impurities.

16. The method of claim 13, further comprising: Before separating the chip from the lead frame strip and the clamp frame strip, the exposed leads of the chip are plated.

17. The method of claim 13, further comprising: Before separating the chip from the lead frame strip and the clamp frame strip, the housing formed by encapsulating the chip is marked.

18. The method of claim 13, further comprising: Separate the chip from the lead frame strip and the clamp frame strip.

19. The method of claim 18, further comprising: After separating the chip from the lead frame strip and the clamp frame strip, the exposed leads of the chip are formed.

20. A system comprising: Controller; Filter networks; as well as A switching circuit, configured to drive the filter network in response to the controller to generate a regulated output signal, the switching circuit having one or more semiconductor devices, each semiconductor device comprising: case; A die, the die being disposed within the housing and having a first surface and a second surface; A first single-component conductive lead, the first single-component conductive lead being electrically coupled to the first surface and extending through the housing; and A second single-component conductive lead is electrically coupled to the second surface and extends through the housing.

21. The system according to claim 20, wherein, At least one of the one or more semiconductor devices includes a MOS transistor.

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