Receive module and method for receiving differential signal in serial bus system

Abstract

To provide a receive module and a reception method, for receiving differential signals in a serial bus system.SOLUTION: In a sending / receiving device, a receive circuit 15 included in a receive module includes: a first voltage divider 1531 for setting a first receive threshold; a first comparator 151 for evaluating differential signals CAN_H, CAN_L received from a bus using the first receive threshold; a second voltage divider 1532 for setting a second receive threshold or a third receive threshold; a second comparator 152 for evaluating the differential signals received from the bus using the second receive threshold or the third receive threshold set by the second voltage divider; and a switching unit 1533 for the switchover between the second receive threshold and the third receive threshold depending on an operating mode of the receive module, the switching unit being capable of switching the receive module for a first communications phase or a second communications phase of a communication on the bus. Each of the first and second voltage dividers is connected to the bus.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a receiving module and method for receiving differential signals in a serial bus system that can be used in a transmitting / receiving device (transceiver).

Background Art

[0002] Serial bus systems are used for the transmission of messages or data in technical facilities. For example, a serial bus system can enable communication between sensors and control devices in a vehicle or a technical manufacturing facility. There are various standards or data transmission protocols for data transmission. In particular, the CAN bus system, the LVDS bus system (LVDS = Low Voltage Differential Signaling), the MSC bus system (MSC = Microsecond Channel), and 10BASE-T1S Ethernet are known.

[0003] In the CAN bus system, messages are transmitted using the CAN and / or CAN FD protocol as described in the standard ISO-11898-1:2015 as the CAN protocol specification for CAN FD. In CAN FD, during transmission on the bus, switching is performed between a low-speed operation mode in the first communication phase (arbitration phase) and a high-speed operation mode in the second communication phase (data phase). In the CAN FD bus system, a data transmission rate exceeding 1 Mbit / s (1 Mbps) is possible in the second communication phase. CAN FD is used by many manufacturers in vehicles at an initial stage with an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s.

[0004] To enable even higher data rates in the second communication phase, there are successor bus systems to CAN FD, such as CAN-SIC and CAN XL. CAN-SIC, according to the CiA601-4 standard, can achieve data rates of approximately 5-8 Mbit / s in the second communication phase. CAN XL requires data rates exceeding 10 Mbit / s in the second communication phase, and the standard for this (CiA610-3) is currently defined by the CAN in Automation (CiA) organization. In addition to pure data transfer over the CAN bus, CAN XL should also support other functions such as functional safety, data security, and quality of service (QoS). These are fundamental characteristics required for autonomous vehicles.

[0005] In all of the above CAN-based bus systems, with respect to the transmit signal TxD, bus signal CAN_H and ideally bus signal CAN_L are driven separately on the bus. Here, in at least the first communication phase, one bus state is actively driven by bus signals CAN_H and CAN_L. The other bus state is not driven and is set by the termination resistors of the bus lines or bus wires.

[0006] In a CAN bus system, a transmit / receive device is typically used for each communication participant to send and receive bus signals, and this is also called a CAN transceiver or CAN FD transceiver. In CAN XL, the transmit / receive device must be able to transmit the bus signals CAN_H and CAN_L to the bus in the second communication phase at a different physical layer than in the first communication phase, and to receive them at a different reception threshold than in the first communication phase. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model).

[0007] This allows data to be transmitted to the bus at a significantly higher data rate in the second communication phase than in the first. Furthermore, this means that the bus levels of the bus signals CAN_H and CAN_L for the first communication phase may differ from the bus levels for the second communication phase. Here, due to the low error rate, it is important that a subscriber station newly connected to the bus communication can recognize which communication phase is currently taking place on the bus.

[0008] Therefore, for all operational phases of bus communication, it should be ensured that the receiving subscriber station of the bus system can correctly recognize and evaluate the levels of the bus signals CAN_H and CAN_L. [Overview of the project] [Problems that the invention aims to solve]

[0009] Therefore, the object of the present invention is to provide a receiving module and method for receiving differential signals in a serial bus system that solves the aforementioned problems. In particular, the receiving module and method for receiving differential signals in a serial bus system should enable reliable and uncomplicated recognition of bus signals even when the physical layer is switched between two communication phases during bus communication. [Means for solving the problem]

[0010] This problem is solved by a receiving module for receiving differential signals in a serial bus system having the features of claim 1. The receiving module comprises a first voltage divider for setting a first reception threshold, a first comparator connected to the first voltage divider for evaluating a differential signal received from the bus of the bus system at the first reception threshold, a second voltage divider for setting a second or third reception threshold, a second comparator connected to the second voltage divider for evaluating a differential signal received from the bus at a second or third reception threshold set by the second voltage divider, and a switching unit for switching between the second and third reception thresholds according to the operating mode of the receiving module, wherein the receiving module can be switched for a first or second communication phase of communication on the bus. The first and second voltage dividers are connected to the bus, respectively.

[0011] The receiving module described above is configured to ensure that bus signals are reliably and easily recognized when the bus system is operating. This is particularly effective for communications where the physical layer switches between two communication phases for communication on the bus. The receiving module can reliably distinguish between the respective bus states of each communication phase, and therefore between individual communication phases, when communicating on the bus.

[0012] Here, the receiving module described above can meet the specifications for communication in accordance with the CAN XL standard as defined in the CiA610-3 standard. Furthermore, the receiving module described above is configured to convert the signal level of the bus signal into a digital received signal by simultaneous evaluation using two receiving thresholds. Here, the two receiving thresholds used in each communication phase may differ for each communication phase.

[0013] This ensures that the receiving module does not interfere with bus communications when additional subscriber stations attempt to connect and integrate into bus communications. Therefore, subscriber stations can use the receiving module to reliably know whether there is data traffic on the bus. The receiving module reliably assigns the current bus state so that newly added subscriber stations only transmit data to the bus when the bus is free. Therefore, additional connections from subscriber stations that are, for example, being started for the first time or attempting to reintegrate into bus communications after an error in bus communications do not result in an interruption of bus communications.

[0014] As a result, the receiving module implements the ability to use different receive thresholds for arbitration and data phases. This not only enables communication on the bus system at higher bit rates, but also prevents the transmittable bit rate from being reduced by communication errors.

[0015] Further advantageous configurations of the receiving module are described in the dependent claims. The first and second voltage dividers may have circuits including resistors to which the first and second comparators are connected, and the first and second comparators simultaneously evaluate differential signals.

[0016] In one configuration, the first and second voltage dividers have the same number of resistors. In one configuration, the number of resistors in the first resistance path of the first voltage divider for the first differential signal is equal to the number of resistors in the second resistance path of the second voltage divider for the second differential signal, and the number of resistors in the second resistance path of the first voltage divider for the second differential signal is equal to the number of resistors in the first resistance path of the second voltage divider for the first differential signal.

[0017] In one configuration, the number of resistors in the first resistance path of the first voltage divider is greater than the number of resistors in the second resistance path. In the second voltage divider, the number of resistors in the first resistance path is greater than the number of resistors in the second resistance path.

[0018] The switching unit may be configured to allow for additional resistor connection or grounding to disconnect it. Optionally, the switching unit is an NMOS transistor.

[0019] The receiving module may further include a driver for driving a digital received signal to a communication control device of a subscriber station of a bus system, and logic circuits for sending the output signals of a first comparator and a second comparator to the driver when the switching unit sets a second reception threshold, and sending only the output signal of the second comparator to the driver when the switching unit sets a third reception threshold.

[0020] The resistance of the second voltage divider (1532) may have a larger semiconductor area than the resistance of the first voltage divider. The receiving module described above can be part of a transmit / receive device for a subscriber station in a serial bus system. The transmit / receive device may further have a transmit module for transmitting signals to the bus of the bus system.

[0021] The transmit / receive devices described above can be part of a subscriber station for a serial bus system. The subscriber station may further include communication control devices for controlling communication on the bus system and generating digital transmit signals for the transmit module.

[0022] Optionally, subscriber stations are configured for communication on the bus system, and exclusive, conflict-free access to the bus of the bus system is guaranteed, at least temporarily, for the subscriber station.

[0023] The above problem is also achieved by a method for receiving differential signals in a serial bus system having the features of claim 13. The method includes: setting a first reception threshold of a reception module using a first voltage divider, where the first voltage divider is connected to the bus of the bus system; setting a second reception threshold or a third reception threshold of the reception module using a second voltage divider, where the second voltage divider is connected to the bus and a switching unit for switching between the second reception threshold and the third reception threshold according to the operation mode of the reception module is used, and the reception module is switchable for a first or a second communication phase of communication on the bus; receiving a differential signal from the bus by the reception module; evaluating the differential signal received from the bus with the first reception threshold using a first comparator connected to the first voltage divider; and evaluating the differential signal received from the bus with the second or third reception threshold set by the second voltage divider by a second comparator connected to the second voltage divider.

[0024] This method provides the same advantages as described above with respect to the reception module. Further possible implementations of the present invention also include combinations of features or embodiments that are not explicitly mentioned, either described above or below, with respect to the exemplary embodiments. Here, those skilled in the art will also add individual aspects as improvements or supplements to the respective basic forms of the present invention.

[0025] Hereinafter, the present invention will be described in more detail based on exemplary embodiments with reference to the accompanying drawings.

Brief Description of the Drawings

[0026] [Figure 1] It is a simplified block diagram of a bus system according to a first exemplary embodiment. [Figure 2] It is a diagram for explaining the structure of a message that can be transmitted by a subscriber station of a bus system according to a first exemplary embodiment. [Figure 3]Figure 1 shows an example of the ideal time profile for the bus signals CAN_H and CAN_L in the bus system shown in Figure 1. [Figure 4] Figure 3 shows the time profile of the differential voltage VDIFF generated on the bus of the bus system by the bus signal. [Figure 5] This is a simplified block diagram of a transmit / receive device with a receive module for a subscriber station of a bus system, according to a first exemplary embodiment. [Figure 6] This is a circuit diagram of a receiving module according to a first exemplary embodiment. [Figure 7] This is a simplified block diagram of a transmit / receive device with a receive module for a subscriber station of a bus system, according to a second exemplary embodiment. [Figure 8] This figure shows an example of the time profile of the digital transmit signals to be converted to the bus signals CAN_H and CAN_L for the bus of the bus system in Figure 1 during the arbitration phase (SIC operating mode), according to a second exemplary embodiment. [Figure 9] This figure shows the time profiles of the bus signals CAN_H and CAN_L transmitted to the bus based on the transmit signal in Figure 8 during the arbitration phase (SIC operating mode) when the bus changes from a recessive bus state to a dominant bus state and then back to a recessive bus state. [Figure 10] This figure shows an example of the time profile of the digital transmission signals to be converted to the bus signals CAN_H and CAN_L for the bus of the bus system in Figure 1 during the data phase, according to a second exemplary embodiment. [Figure 11] This figure shows the time profiles of the bus signals CAN_H and CAN_L that are transmitted to the bus during the data phase, based on the transmission signal in Figure 10. [Modes for carrying out the invention]

[0027] In drawings, unless otherwise specified, identical or functionally identical elements are given the same reference numeral. Figure 1 shows bus system 1, which may be, for example, a CAN bus system or a CAN-FD bus system, at least partially. Bus system 1 can be used in vehicles such as automobiles and aircraft, or in hospitals, etc.

[0028] In Figure 1, the bus system 1 has a number of subscriber stations 10, 20, and 30, each of which is connected to a bus 40 or bus line having a first bus wire 41 and a second bus wire 42. The bus wires 41 and 42 can also be referred to as CAN_H and CAN_L with respect to signals on the bus 40. Messages 45, 46, and 47 in the form of signals can be transmitted between the individual subscriber stations 10, 20, and 30 via the bus 40. The subscriber stations 10, 20, and 30 may be, for example, control equipment or display devices for automobiles.

[0029] As shown in Figure 1, subscriber stations 10 and 30 each have a communication control device 11 and a transmit / receive device 12. The transmit / receive device 12 has a transmit module 121 and a receive module 122.

[0030] The subscriber station 20 has a communication control device 21 and a transmit / receive device 22. The transmit / receive device 22 has a transmit module 221 and a receive module 222. The transmit / receive devices 12 of subscriber stations 10 and 30 and the transmit / receive device 22 of subscriber station 20 are directly connected to bus 40, although they are not shown in Figure 1.

[0031] The communication control devices 11 and 21 each control the communication between their respective subscriber stations 10, 20, and 30 and at least one other subscriber station among those connected to the bus 40, via the bus 40.

[0032] The communication control device 11 creates and reads first messages 45 and 47, which are, for example, modified CAN messages 45 and 47. Here, the modified CAN messages 45 and 47 are constructed, for example, based on the CAN XL format. The transmit / receive device 12 transmits and receives messages 45 and 47 from the bus 40. The transmit module 121 receives a digital transmit signal TxD generated by the communication control device 11 for one of the messages 45 and 47 and converts it into a signal on the bus 40. The receive module 122 receives signals transmitted on the bus 40 corresponding to messages 45-47 and generates a digital receive signal RxD from those signals. The receive module 122 transmits the receive signal RxD to the communication control device 11.

[0033] The communication control device 21 can be implemented like a conventional CAN controller compliant with ISO 11898-1:2015, i.e., like a conventional CAN controller or CAN FD controller that allows CAN FD. The communication control device 21 creates and reads the second message 46, for example, a CAN FD message 46. The transmit / receive device 22 transmits and receives messages 46 from the bus 40. The transmit module 221 receives the digital transmit signal TxD generated by the communication control device 21 and converts it into a signal for message 46 on the bus 40. The receive module 222 receives signals transmitted on the bus 40 corresponding to messages 45-47 and generates a digital receive signal RxD from those signals. Otherwise, the transmit / receive device 22 can be implemented like a conventional CAN transceiver.

[0034] To transmit messages 45 and 47 via CAN SIC or CAN XL, a frame structure is employed that features proven characteristics contributing to the robustness and ease of use of CAN and CAN FD, particularly identifiers and arbitration functions using the known CSMA / CR method. The CSMA / CR method results in a so-called recessive state on bus 40, which can be overridden by other subscriber stations 10, 20, and 30 on bus 40 with a dominant level or dominant state.

[0035] Using two subscriber stations 10 and 30, it is possible to form and transmit messages 45 using different CAN formats, particularly CAN FD format, CAN SIC format, or CAN XL format, as well as to receive such messages 45, as will be described in more detail below.

[0036] Figure 2 shows a frame 450 with respect to message 45, which is a CAN XL frame, as provided by the communication control device 11 for the transmit / receive device 12 for transmission over bus 40. Here, the communication control device 11 creates the frame 450 as compatible with CAN FD in this exemplary embodiment. Alternatively, the frame 450 is compatible with CAN SIC.

[0037] As shown in Figure 2, frame 450 is subdivided into two distinct communication phases 451 and 452 for CAN communication on bus 40: arbitration phase 451 (first communication phase) and data phase 452 (second communication phase). After the start bit SOF, frame 450 has an arbitration field 453, a control field 454, a data field 455, a checksum field 456, and a frame completion field 457.

[0038] In arbitration phase 451, for example, using identifiers (IDs) having bits IDs 28 to ID 18 in arbitration field 453, subscriber stations 10, 20, and 30 negotiate bit by bit which of them wants to transmit messages 45 and 46 with the highest priority, and therefore obtain exclusive access to bus 40 of bus system 1 for transmission in the subsequent data phase 452 for the time being. In arbitration phase 451, the physical layer is used, as in CAN and CAN-FD. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model).

[0039] A key point in Phase 451 is that the known CSMA / CR method is used, which allows subscriber stations 10, 20, and 30 to access bus 40 simultaneously without the higher-priority messages 45 and 46 being destroyed. This makes it relatively easy to add additional bus subscriber stations 10, 20, and 30 to bus system 1, which is very advantageous.

[0040] The CSMA / CR method results in a so-called recessive state on bus 40, which can be overridden by other subscriber stations 10, 20, and 30 on bus 40 with dominant levels or dominant states. In the recessive state, high-resistance behavior occurs in each subscriber station 10, 20, and 30, which, combined with bus circuit parasitic behavior, results in a longer time constant. As a result, the maximum bit rate of the CAN-FD physical layer today is currently limited to about 2 megabits / second in actual vehicle use.

[0041] In the data phase 452, in addition to a portion of the control field 454, usage data for the CAN-XL frame 450 or message 45 from the data field 455, as well as the checksum field 456, are transmitted. The checksum field 456 may contain a checksum of the data from the data phase 452, including stuff bits, and the sender of the message 45 inserts this checksum as an inverse bit after a predetermined number of identical bits, particularly 10 identical bits. At the end of the data phase 452, the system switches back to the arbitration phase 451.

[0042] The end field of the frame completion phase 457 may include at least one acknowledgment bit. Furthermore, there may be a sequence of 11 identical bits indicating the end of the CAN XL frame 450. At least one acknowledgment bit can be used to indicate whether the receiver found an error in the received CAN XL frame 450 or message 45.

[0043] Only when subscriber station 10 wins the arbitration as the source, thereby gaining exclusive access to bus 40 of bus system 1 for transmission as the source, does the source of message 45 begin sending the bits of data phase 452 to bus 40.

[0044] Therefore, subscriber stations 10 and 30 use a format known from CAN / CAN-FD in accordance with ISO 11898-1:2015, in part, particularly up to the FDF bits (including it), in the arbitration phase 451 as the first communication phase. However, compared to CAN or CAN-FD, the data phase 452 as the second communication phase allows for an increase in the net data transmission rate, particularly to more than 10 megabits per second. Furthermore, it is possible to increase the size of data used per frame, particularly to about 2 kilobytes or any other value.

[0045] Figure 3 shows, on the left, that subscriber stations 10, 20, and 30 transmit signals CAN_H and CAN_L to bus 40 during arbitration phase 451, and these signals alternate between at least one dominant state 401 and at least one recessive state 402. After arbitration in arbitration phase 451, one of subscriber stations 10, 20, and 30 is determined as the winner. Assume that subscriber station 10 won the arbitration. In this case, since subscriber station 10 is the source of message 45 in data phase 452, the transmit / receive device 12 of subscriber station 10 switches its physical layer from the first operating mode (SLOW) to the second operating mode (FAST_TX) at the end of arbitration phase 451. Next, in data phase 452 or the second operating mode (FAST_TX), the transmitting module 121 successively and thus serially generates states L0 or L1 for signals CAN_H and CAN_L on bus 40, depending on the transmitted signal TxD. The frequencies of signals CAN_H and CAN_L can be increased in data phase 452, as shown on the right side of Figure 3. Thus, the net data transmission rate in data phase 452 is increased compared to arbitration phase 451. In contrast, subscriber station 30 is only the receiver of frame 450 in data phase 452 and not the source, so the transmitting / receiving devices 12 of subscriber station 30 switch their physical layer from the first operating mode (SLOW) to the third operating mode (FAST_RX) at the end of arbitration phase 451. After the end of arbitration phase 451, all transmitting / receiving devices 12 of subscriber stations 10 and 30 switch their operating mode back to the first operating mode (SLOW). Therefore, all transmitting / receiving devices 12 also switch their physical layers.

[0046] According to Figure 4, in the arbitration phase 451, ideally, a differential signal VDIFF=CAN_H-CAN_L is generated on the bus 40 with values ​​VDIFF=2V for the dominant state 401 and VDIFF=0V for the recessive state 402. This is shown on the left side of Figure 4. In contrast, as shown on the right side of Figure 4, in the data phase 452, a differential signal VDIFF=CAN_H-CAN_L is generated on the bus 40 with states L0 and L1. State L0 has a value VDIFF=1V. State L1 has a value VDIFF=-1V.

[0047] The receiving module 122 can distinguish between states 401 and 402 using two of the receiving thresholds T1, T2, and T3, respectively, which are within the ranges TH_T1, TH_T2, and TH_T3. For this purpose, the receiving module 122 samples the signal shown in Figure 3 or Figure 4 at time t_A. To evaluate the sampling result, in the arbitration phase 451, the receiving module 122 uses, for example, a receiving threshold T1 of 0.7V and a receiving threshold T2 of -0.35V. In contrast, in the data phase 452, the receiving module 122 uses only the signal evaluated using the receiving threshold T3. When switching between the first to third operating modes (SLOW, FAST_TX, FAST_RX) described above with reference to Figure 3, the receiving module 122 switches the receiving thresholds T2 and T3, respectively, as described below.

[0048] The receive threshold T2 is used to determine whether bus 40 is free when a subscriber station 20 is newly connected to communications on bus 40 and attempts to integrate into communications on bus 40. In the CAN standard, the receive threshold T2 is abbreviated as OOB (= Out-of-Boundary). The condition for a CAN-XL bus without traffic is that a dominant state 401 with a differential voltage VDIFF = 2V does not occur. Therefore, it must not exceed the receive threshold T1, for example, 0.7V. Furthermore, a level due to state L1, which typically has a differential voltage VDIFF = -1V, must not occur. Therefore, the receive threshold T2 must not fall below, for example, -0.35V.

[0049] Each subscriber station 10, 30 switches the operating mode of the transmit / receive device 12 to the arbitration phase 451 operating mode when subscriber station 20 is newly added to the communication on bus 40.

[0050] On the one hand, when subscriber station 10 is started for the first time and integrated into communication on bus 40, it may be necessary to connect subscriber station 10. On the other hand, when subscriber station 10 attempts to reintegrate into communication on bus 40 after an error in bus communication, it may be necessary to connect subscriber station 10. Only when it is recognized that the bus is free may subscriber station 10 itself transmit data, in particular messages 45 and 47, to bus 40 in the above cases.

[0051] Table 1 below shows the configurable values ​​for individual receive thresholds on bus 40. Here, VDIFF_min indicates the lower limit for individual ranges TH_T1, TH_T2, and TH_T3, and the lower limit can be set to a minimum in V units for the corresponding receive thresholds T1, T2, and T3. VDIFF_typ indicates the value that is typically or usually set in V units for the corresponding receive thresholds T1, T2, and T3. VDIFF_max indicates the upper limit for individual ranges TH_T1, TH_T2, and TH_T3, and the upper limit can be set to a maximum in V units for the corresponding receive thresholds T1, T2, and T3.

[0052] [Table 1]

[0053] Figure 5 shows the basic structure of the transmit / receive device 12 of the subscriber station 10. The transmit module 121 is shown in a very simplified form. The transmit module 121 is directly connected to the bus 40 so that it can transmit the transmit signal TxD of the communication control device 11 to the bus 40 and generate the signal shown in Figure 3 on the bus 40.

[0054] The receiving module 122 includes a driver 1221 for the digital received signal RxD, a logic circuit 1222, and a receiving circuit 15. The receiving circuit 15 includes a first receiving comparator 151, a second receiving comparator 152, and a receiving stage 153. The receiving comparators 151 and 152 are low-voltage comparators.

[0055] The receiving circuit 15 is connected between the bus 40 and the logic circuit 1222. The driver 1221 is connected to the output of the logic circuit 1222. The driver 1221 drives or transmits the digital received signal RxD to the communication control device 11.

[0056] In the receiving circuit 15, the receiving stage 153 is connected to the bus 40. When the bus system 1 is operating, the receiving stage 153 generates signals S_1 and S_2 from signals CAN_H and CAN_L, and transfers these signals to the first receiving comparator 151. The first receiving comparator 151 generates the comparator output signal CA1 from signals S_1 and S_2.

[0057] Furthermore, the receiving stage 153 generates signals S_3 and S_4 from signals CAN_H and CAN_L when the bus system 1 is operating, and transfers these signals to the second receiving comparator 152. The second receiving comparator 151 generates the comparator output signal CA2 from signals S_3 and S_4.

[0058] The logic circuit 1222 is configured to output signals CA1 and CA2 to the driver 1221, or to output only signal CA2 to the driver 1221, depending on the operating mode of the transmit / receive device 12. For this purpose, the logic circuit 1222 may have at least one AND gate. Alternatively, the logic circuit 1222 may have other logic components to implement the functions of the receive module 122 described below.

[0059] The receiving stage 153 and the interconnection between the receiving stage 153 and the logic circuit 1222 will be described in more detail with reference to Figure 6. As shown in Figure 6, the receiving circuit 15 further includes a bus bias source (bus biasing) 154, which supplies the voltage CAN_SUPPLY / 2 to the receiving stage 153. Typically, CAN_SUPPLY = 5V is applied. In this case, the bus bias source 154 supplies a voltage of 2.5V to the receiving stage 153.

[0060] The receiving stage 153 includes a first voltage divider 1531, a second voltage divider 1532, a switching unit Sw1, and an operating mode setting unit 1534. The first and second voltage dividers 1531 and 1532 are each supplied with the same voltage from the bus bias source 154, specifically 2.5V for the recessive state 402 (Figure 3).

[0061] The first voltage divider 1531 and the second voltage divider 1532 are, respectively, resistive voltage dividers or resistive voltage dividers. The first voltage divider 1531 has first to seventh resistors R_CH1_A to R_CH7_A for the bus signal CAN_H. The first resistor R_CH1_A is connected at one end to the bus line 41 (CANH). At the other end, the first resistor R_CH1_A is connected in series with the second resistor R_CH2_A and a parallel circuit consisting of the third and fourth resistors R_CH3_A and R_CH4_A in series. One end of the fifth resistor R_CH5_A is connected to the connection point of resistors R_CH3_A and R_CH4_A. Furthermore, the other end of the fourth resistor R_CH4_A is connected to one end of the sixth resistor R_CH6_A. The other ends of resistors R_CH5_A and R_CH6_A are connected to the seventh resistor R_CH7_A. The resistor R_CH7_A is grounded at its other end and therefore connected to terminal 44.

[0062] Furthermore, the voltage divider 1531 also has eighth to twelfth resistors R_CL1_A to R_CL5_A for the bus signal CAN_L. The eighth resistor R_CL1_A is connected at one end to the bus line 42 (CANL). The other end of resistor R_CL1_A is connected in series with the ninth resistor R_CL2_A and the series circuit of the tenth and eleventh resistors R_CL3_A and R_CL4_A. One end of the twelfth resistor R_CL5_A is connected to the connection point of resistors R_CL3_A and R_CL4_A. Furthermore, resistors R_CL2_A, R_CL4_A and R_CL5_A are connected at their respective connection points to the connection points of resistors R_CH2_A, R_CH4_A and R_CH6_A, respectively.

[0063] The first input of the first comparator 151 is connected to the connection point between the first and second resistors R_CH1_A and R_CH2_A. The second input of the first comparator 151 is connected to the connection point between the eighth and ninth resistors R_CL1_A and R_CL2_A.

[0064] The resistive path to ground via resistor R_CH7_A sets the reception threshold T1 in Figure 4. The second voltage divider 1532 has first to seventh resistors R_CL1_B to R_CL7_B for the bus signal CAN_H. The first resistor R_CL1_B is connected at one end to the bus line 41 (CANL). The other end of the first resistor R_CL1_B is connected in series with the second resistor R_CL2_B and a parallel circuit consisting of the third and fourth resistors R_CL3_B and R_CL4_B in series. One end of the fifth resistor R_CL5_B is connected to the connection point of resistors R_CL3_B and R_CL4_B. Furthermore, the other end of the fourth resistor R_CL4_B is connected to one end of the sixth resistor R_CL6_B. The other ends of resistors R_CL5_B and R_CL6_B are connected to switching unit Sw1. Switching unit Sw1 is further connected to resistor R_CL7_B. The resistor R_CL7_B is grounded at its other end and therefore connected to terminal 44.

[0065] Furthermore, the second voltage divider 1532 has eighth to twelfth resistors R_CH1_B to R_CH5_B for the bus signal CAN_L. The eighth resistor R_CH1_B is connected at one end to bus line 42 (CANH). The other end of the eighth resistor R_CH1_B is connected in series with a parallel circuit consisting of the ninth resistor R_CH2_B and the tenth and eleventh resistors R_CH3_B and R_CH4_B in series. One end of the twelfth resistor R_CH5_B is connected to the connection point of resistors R_CH3_B and R_CH4_B. Furthermore, resistors R_CH2_B, R_CH4_B and R_CH5_B are connected at their respective connection points to the connection points of resistors R_CL2_B, R_CL4_B and R_CL6_B.

[0066] The first input of the second comparator 152 is connected to the connection point between the eighth and ninth resistors R_CH1_B and R_CH2_B. The second input of the second comparator 152 is connected to the connection point between the first and second resistors R_CL1_B and R_CL2_B.

[0067] If switch Sw1 is switched accordingly, the resistive path to ground or connection terminal 44 via resistor R_CL7_B sets the reception threshold T2 in Figure 4. If switch Sw1 is switched so that the path to resistor R_CL7_B does not conduct, the reception threshold T3 in Figure 4 is set.

[0068] The resistor circuits in the resistor networks of voltage dividers 1531 and 1532 are configured symmetrically. To satisfy the input resistance Rin requirements for CANH and CANL, the resistive voltage divider paths of voltage dividers 1531 and 1532 have a dual structure and therefore have half the value. Here, Rin_CANH and Rin_CANL = 25kOhm · · · 50kOhm hold. Typically, an input resistance Rin of 37.5kOhm is selected for the connection terminals (pins) for the signal CAN_H and the connection terminals (pins) for the signal CAN_L. In this case, the aforementioned resistive paths of voltage dividers 1531 and 1532 have the following special configuration: The path of CANH through the resistor R_CH1_A of the first voltage divider 1531 to the connection terminal 44 for ground or CAN_GND has a resistance value of approximately 2 × 37.5kOhm. The path of CANH through the resistor R_CH1_B of the second voltage divider 1532 to the ground or CAN_GND connection terminal 44 has a resistance of approximately 2 × 37.5 kOhm. The path of CANL through the resistor R_CL1_A of the first voltage divider 1531 to the ground or CAN_GND connection terminal 44 has a resistance of approximately 2 × 37.5 kOhm. The path of CANL through the resistor R_CL1_B of the second voltage divider 1532 to the ground or CAN_GND connection terminal 44 has a resistance of approximately 2 × 37.5 kOhm.

[0069] According to Table 1 above, thresholds T2 and T3 require an tolerance of half the tolerance at threshold T1 (±200mV), which is ±100mV. Therefore, the resistance of the first voltage divider 1531 is configured to be different from the resistance of the second voltage divider 1532. The resistance of the second voltage divider 1532 has a larger semiconductor area, particularly a silicon area (Si area), than the resistance of the first voltage divider 1531. This reduces the variation in the received threshold, as required according to Table 1.

[0070] In the example in Figure 6, the switching unit Sw1 is a transistor, specifically an NMOS transistor. The abbreviation "NMOS" indicates an n-channel MOSFET, where the abbreviation "MOSFET" represents a metal oxide field-effect transistor. When the operating mode setting unit 1533 controls the switching unit Sw1 with a signal having the value "high", the switching unit Sw1 is either conducting or closed. In this case, a resistive path to ground 43 is established via resistor R_CL7_B. The resistive path to ground via resistor R_CL7_B sets the receive threshold T2 in Figure 4, as described above.

[0071] When the operating mode setting unit 1533 controls the switching unit with a "low" signal, the switching unit Sw1 is either not conducting or open. In this case, the resistive path to ground 43 is switched off via resistor R_CH7_A, and the receive threshold T3 in Figure 4 is set.

[0072] With respect to comparators 151 and 152 and the digital output signals CA1 and CA2 generated by them, the following holds true for the NMOS transistor as the switching unit Sw1.

[0073] [Table 2]

[0074] In other words, when the signal sw_thres of the operating mode setting unit 1533 has the value "high", the first comparator 1531 delivers signal CA1, in which signals S_1 and S_2 are evaluated using the received threshold T1, and the second comparator 1532 delivers signal CA2, in which signals S_3 and S_4 are evaluated using the received threshold T2. In other words, the first comparator 1531 delivers recognition of threshold T1, and the second comparator 1532 delivers recognition of threshold T2.

[0075] In contrast, if the signal sw_thres of the operating mode setting unit 1533 has a value of "low", the first comparator 1531 delivers signal CA1, in which signals S_1 and S_2 are evaluated using the received threshold T1, and the second comparator 1532 delivers signal CA2, in which signals S_3 and S_4 are evaluated using the received threshold T3. In other words, the first comparator 1531 delivers recognition of threshold T1, and the second comparator 1532 delivers recognition of threshold T3.

[0076] Therefore, the voltage dividers 1531 and 1532 form a double voltage divider structure. The voltage dividers 1531 and 1532 divide the bus voltage generated by the signals CAN_H and CAN_L into values ​​that can be processed by the comparators 151 and 152.

[0077] The dual voltage divider structure of the receiving stage 15 allows two different receiving thresholds among the receiving thresholds T1, T2, and T3 to be checked independently and therefore simultaneously. Furthermore, two of the receiving thresholds T1, T2, and T3 can be switched using the switching unit Sw1 controlled by the operating mode setting unit 1534. This allows the receiving thresholds T1 and T2 shown in Figure 4 to be checked independently and simultaneously, or the receiving thresholds T1 and T3 shown in Figure 4 to be checked independently and simultaneously. Therefore, two of the three receiving thresholds T1, T2, and T3 can be switched to a third receiving threshold as needed.

[0078] Therefore, the operation mode setting unit 1533 sets the receive thresholds T1, T2, and T3 according to the currently requested operation mode (SLOW, FAST_TX, FAST_RX) of the transmit / receive device 12.

[0079] Figure 7 shows a transmit / receive device 120 according to a second exemplary embodiment. The transmit / receive device 120 can be used instead of the transmit / receive device 12 in the bus system 1 of Figure 1.

[0080] The transmitting / receiving device 120 includes a transmitting module 1210 and a receiving module 122. The transmitting module 1210 is composed of many components, similar to the transmitting module 121 in the first exemplary embodiment. Therefore, only the differences from the first exemplary embodiment are described below.

[0081] Unlike the first exemplary embodiment, the transmitting module 1210 generates signals CAN_H and CAN_L for the two communication phases on the bus 40, as described below with reference to Figures 8 to 11.

[0082] Figure 8 shows an example relating to a portion of the digital transmission signal TxD, which the transmission module 1210 receives from the communication control device 11 in arbitration phase 451 and generates signals CAN_H and CAN_L relating to bus 40 from it. In Figure 8, the transmission signal TxD changes from state LW (low) to state HI (high) and then back to state LW (low).

[0083] In an ideal scenario, the received signal RxD is the same as the transmitted signal TxD. In such an ideal scenario, there is no transmission delay, especially over bus 40, and no reception errors. As shown in detail in Figure 9, the transmitter module 1210 can generate the signals CAN_H and CAN_L for bus wires 41 and 42 in the operating mode CAN SIC or CAN XL with respect to the transmit signal TxD in Figure 8. Unlike in Figure 3, the signals in Figure 9 also have a state 403(sic). State 403(sic) can be of varying lengths, indicated by state 403_0(sic) during the transition from state 402(rec) to state 401(dom), and by state 403_1(sic) during the transition from state 401(dom) to state 402(rec). State 403_0(sic) is shorter in duration than state 403_1(sic). To generate the signals in Figure 9, the transmitter module 1210 is switched to the SIC operating mode (SIC mode).

[0084] According to the CiA610-3 standard for CAN XL, the execution of the short sic state 403_0 is not required, and the state varies depending on the type of implementation. The duration of the "long" state 403_1(sic) is specified as t_sic < 530 ns for both CAN-SIC and the SIC operating mode in CAN-XL, and it begins from the rising edge of the transmit signal TxD in Figure 8.

[0085] In the "long" state 403_1(sic), the transmitter module 1210 should match the impedance between bus wires 41(CANH) and 42(CANL) as closely as possible to the characteristic wave impedance Zw of the bus line being used. Here, Zw = 100 Ohm or 120 Ohm is applied. This match prevents reflections and thus enables operation at higher bit rates. For clarity, this state will always be referred to as state 403(sic) or sic state 403 below.

[0086] Figure 10 shows an example of another part of the digital transmit signal TxD, which the transmit module 1210 receives from the communication control device 11 (Figure 1) in the data phase 452 and generates signals CAN_H and CAN_L for the bus 40 from it. In Figure 10, the transmit signal TxD changes from state HI (high) to state LW (low) and then back to state HI (high) multiple times.

[0087] As shown in detail in Figure 11, the transmitting module 1210 generates signals CAN_H and CAN_L for bus wires 41 and 42 with respect to the transmitting signal TxD in Figure 10, with state L0 occurring for state LW (low). Furthermore, state L1 occurs for state HI (high).

[0088] With respect to two bus states L0 and L1, the dominant and recessive bus states may be used, at least temporarily, and instead the first and second bus states may be used, both of which may be driven. An example of such a bus system is the CAN XL bus system.

[0089] The receiving module 122 can also receive the signals shown in Figures 9 and 11 in two different communication phases, namely the SIC operation mode or the arbitration phase 451 and the data phase 452. In this regard, the receiving module 122 switches the reception thresholds T2 and T3 for each operation mode, as described above in relation to the previous exemplary embodiment.

[0090] Therefore, the operation mode setting unit 1533 sets the receive thresholds T1, T2, and T3 according to the currently requested operation mode (SIC, FAST_TX, FAST_RX) of the transmit / receive device 120.

[0091] According to a third exemplary embodiment, the first voltage divider 1531 sets the second receiving threshold T2 in Figure 4. The second voltage divider 1532 sets either the first or third receiving thresholds T1, T3 in Figure 4. The resistances of the voltage dividers 1531 and 1532 are set such that a tolerance of ±100mV according to Table 1 above is maintained for all thresholds T1, T2, and T3, as described above with respect to thresholds T2, T3 with reference to the first exemplary embodiment.

[0092] In this case, the logic circuit 1222 is configured so that both comparator signals CA1 and CA2 are always sent to the driver 1221. The receiving module 122 always evaluates the signals CAN_H and CAN_L at the same time or simultaneously using two receiving thresholds, namely receiving thresholds T1 and T2 or receiving thresholds T2 and T3. Furthermore, the two receiving thresholds are evaluated independently of each other.

[0093] This circuit may be advantageous when the receive threshold T2 is also used in the data phase 452, as shown in Figure 4. All of the above-described configurations of the transmitting modules 121, 1210, receiving module 122, transmitting / receiving devices 12, 22, 120, subscriber stations 10, 20, 30, bus system 1, and the methods implemented therein, as described in the first and second exemplary embodiments and their modifications, can be used individually or in all possible combinations. Furthermore, the following modifications in particular are possible.

[0094] The bus systems 1 described above in the first and second exemplary embodiments have been described with reference to bus systems based on the CAN protocol. However, the bus systems 1 in the first and / or second exemplary embodiments may, alternatively, be other types of communication networks in which signals are transmitted as differential signals. In bus systems 1, it is advantageous, but not a mandatory, that exclusive and collision-free access of subscriber stations 10, 20, and 30 to the bus 40 is guaranteed for at least a certain period of time.

[0095] The bus system 1 in the first and / or second exemplary embodiments and their modifications is, in particular, a CAN bus system, a CAN-HS bus system, a CAN FD bus system, a CAN SIC bus system, or a CAN XL bus system. However, the bus system 1 may also be another communication network in which signals as differential signals are transmitted serially over the bus 40.

[0096] Therefore, the functions of the exemplary embodiments described above can be used, for example, with transmit / receive devices 12, 22, and 120 that can be driven by a CAN bus system, a CAN-HS bus system, a CAN FD bus system, a CAN SIC bus system, or a CAN XL bus system.

[0097] The number and arrangement of subscriber stations 10, 20, and 30 in the bus system 1 according to the first and second exemplary embodiments, as well as any modifications thereof, are optional. In particular, the bus system 1 in the first or second exemplary embodiment may contain only subscriber station 10 or only subscriber station 30. [Explanation of Symbols]

[0098] 1. Serial bus system 10, 20, 30 subscriber stations 11, 21 Communication control devices 12, 22, 120 transmitting / receiving devices 121, 1210 Transmitter Module 122 Receiver Module 1221 Driver 1222 Logic Circuits 151 First comparator 152 Second comparator 1531 First voltage divider 1532 Second voltage divider 1533 Switching Unit 40 buses 451 First communication phase 452 Second communication phase CA1 output signal CA2 output signal CAN_H differential signal CAN_L differential signal R_CH1_A~R_CH7_A Resistance R_CH1_B~R_CH5_B Resistance R_CL1_A~R_CL5_A Resistance R_CL1_B~R_CL7_B Resistance RxD Digital Received Signal T1 First reception threshold T2 Second reception threshold T3 Third reception threshold TxD Digital Transmitted Signal

Claims

1. A receiving module (122) for receiving differential signals in a serial bus system (1), a first voltage divider (1531) for setting a first reception threshold (T1), a first comparator (151) connected to the first voltage divider (1531) for evaluating the differential signal (CAN_H, CAN_L) received from the bus (40) of the bus system (1) at the first reception threshold (T1), a second voltage divider (1532) for setting a second reception threshold (T2) or a third reception threshold (T3), a second comparator (152) connected to the second voltage divider (1532) for evaluating the differential signal (CAN_H, CAN_L) received from the bus (40) at the second or third reception threshold (T2, T3) set by the second voltage divider (1532), a switching unit (1533) for switching between the second reception threshold (T2) and the third reception threshold (T3) according to the operation mode of the receiving module (122), the switching unit (1533) being capable of switching the receiving module (122) for a first or second communication phase (451, 452) of communication on the bus (40), comprising the first and second voltage dividers (1531, 1532) being respectively connected to the bus (40), receiving module (122).

2. the first and second voltage dividers (1531, 1532) having a circuit including resistors to which the first and second comparators (151, 152) are connected, the first and second comparators (151, 152) simultaneously evaluating the differential signal (CAN_H, CAN_L), the receiving module (122) according to claim 1.

3. the receiving module (122) according to claim 1, wherein the first and second voltage dividers (1531, 1532) have the same number of resistors.

4. The number of resistors (R_CH1_A to R_CH7_A) in the first resistance path of the first voltage divider (1531) with respect to the first signal (CAN_H) of the differential signal (CAN_H, CAN_L) is equal to the number of resistors (R_CL1_B to R_CL7_B) in the second resistance path of the second voltage divider (1532) with respect to the second signal (CAN_L) of the differential signal (CAN_H, CAN_L), The number of resistors (R_CL1_A to R_CL5_A) in the second resistance path of the first voltage divider (1531) with respect to the second signal (CAN_L) of the differential signal (CAN_H, CAN_L) is equal to the number of resistors (R_CH1_B to R_CH5_B) in the first resistance path of the second voltage divider (1532) with respect to the first signal (CAN_H) of the differential signal (CAN_H, CAN_L), The receiving module (122) according to claim 1.

5. In the first voltage divider (1531), the number of the resistors (R_CH1_A to R_CH7_A) in the first resistance path is greater than the number of the resistors (R_CL1_A to R_CL5_A) in the second resistance path, In the second voltage divider (1532), the number of the resistors (R_CH1_B to R_CH5_B) in the first resistance path is greater than the number of the resistors (R_CL1_B to R_CL7_B) in the second resistance path, The receiving module (122) according to claim 4.

6. The receiving module (122) according to claim 1, wherein the switching unit (1533) is arranged to additionally connect or ground and disconnect a resistor (R_CL7_B).

7. The receiving module (122) according to claim 1, wherein the switching unit (1533) is an NMOS transistor.

8. A driver (1221) for driving a digital reception signal (RxD) to a communication control device (11) of a subscriber station (10; 30) of the bus system (1), A logic circuit (1222) for sending, when the switching unit (1533) sets the second reception threshold (T2), an output signal (CA1) of the first comparator (151) and an output signal (CA2) of the second comparator (152) to the driver (1221), and for sending only the output signal (CA2) of the second comparator (152) to the driver (1221) when the switching unit (1533) sets the third reception threshold (T3), The reception module (122) according to claim 1, further comprising:

9. The reception module (122) according to claim 1, wherein the resistors (R_CH1_B to R_CH5_B; R_CL1_B to R_CL7_B) of the second voltage divider (1532) have a larger semiconductor area than the resistors (R_CH1_A to R_CH7_A; R_CL1_A to R_CL5_A) of the first voltage divider (1531).

10. A transmission / reception device (12; 22; 120) for a subscriber station (10, 20, 30) of a serial bus system (1), A transmission module (121; 1210) for transmitting a signal to a bus (40) of the bus system (1), The reception module (122) according to any one of claims 1 to 9, A transmission / reception device (12; 22; 120) comprising:

11. A subscriber station (10; 20; 30) for a serial bus system (1), The transmission / reception device (12; 22) according to claim 10, A communication control device (11; 21) for controlling communication in the bus system (1) and generating a digital transmission signal (TxD) for the transmission module (121; 1210), A subscriber station (10; 20; 30) comprising:

12. A subscriber station (10, 20, 30) according to claim 11, configured for communication in a bus system (1), wherein exclusive and collision-free access of the subscriber stations (10, 20, 30) to the bus (40) of the bus system (1) is guaranteed at least temporarily.

13. A method for receiving differential signals in a serial bus system (1), comprising: setting a first reception threshold (T1) of a reception module (122) using a first voltage divider (1531), the first voltage divider (1531) being connected to a bus (40) of the bus system (1); setting a second reception threshold (T2) or a third reception threshold (T3) of the reception module (122) using a second voltage divider (1532), the second voltage divider (1532) being connected to the bus (40), and a switching unit (1533) for switching between the second reception threshold (T2) and the third reception threshold (T3) according to an operation mode of the reception module (122) is used, and the reception module (122) is switchable for a first or a second communication phase (451, 452) of communication on the bus (40); receiving differential signals (CAN_H, CAN_L) from the bus (40) by the reception module (122); evaluating the differential signals (CAN_H, CAN_L) received from the bus (40) at the first reception threshold (T1) using a first comparator (151) connected to the first voltage divider (1531); evaluating the differential signals (CAN_H, CAN_L) received from the bus (40) at the second or third reception threshold (T2, T3) set by the second voltage divider (1532) by a second comparator (152) connected to the second voltage divider (1532); and having the method.

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