Switching regulator control circuit

Abstract

To provide a switching regulator control circuit capable of obtaining a stable output voltage over a wide range of input-output voltage difference.SOLUTION: A switching regulator control circuit 1 of an embodiment includes: a comparator circuit 4 for outputting a basic pulse Pb, which indicates duration time of predetermined magnitude relation between the voltage of an error signal Ser and the voltage of a periodic signal Sp by comparing the error signal Ser, which indicates difference between a target voltage and an output voltage Vout of a switching regulator 100, and the periodic signal Sp, which includes a gradually changing interval, and consisting a part of a negative feedback circuit 10; and an output circuit 5 for outputting a control signal Sc indicating conduction time between an input end and an output end of the switching regulator 100 based on the basic pulse Pb. The output circuit 5 includes a pulse shortening circuit 6 for generating a control pulse Pc indicating conduction time by shortening a time width of the basic pulse Pb.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a switching regulator control circuit.

Background Art

[0002] Conventionally, when an electric circuit that operates at a voltage lower than the voltage supplied from a voltage source such as a storage battery is included in various electric devices, a step - down switching regulator is widely used. As shown in FIG. 12, a conventional step - down switching regulator includes an oscillation circuit 91, an error amplifier 92, a reference voltage generation circuit 93 related to the setting of an output voltage, a PWM comparator 94, a buffer 95, a power transistor 96, a diode 97, and a smoothing circuit 98 composed of a coil and a capacitor (see, for example, Patent Document 1).

[0003] The error amplifier 92 outputs an error voltage Ver so as to increase or decrease according to the magnitude of the voltage of the inverting input with respect to the voltage of the non - inverting input. The PWM comparator 94 compares the error voltage Ver with the saw - tooth voltage Vp output by the oscillation circuit 91 and outputs a signal S including a pulse having a time width corresponding to the time when the voltage Ver exceeds the voltage Vp. The power transistor 96 switches the input voltage Vin at the duty ratio of the signal S input via the buffer 95 and supplies it to the smoothing circuit 98. The smoothing circuit 98 is charged and discharged at the duty ratio of the signal S via the power transistor 96 and the diode 97, and the smoothed voltage is output as the output voltage Vout, and is divided by the series connection resistor 99 and returned to the error amplifier 92 as the feedback voltage Vfb. Through the negative feedback circuit including the error amplifier 92, a constant output voltage Vout is output.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] Switching regulators are used under a variety of input and output voltage conditions depending on their wide range of applications. They may be used in situations where the difference between the required output voltage and the input voltage is large, or in situations where it is small. That is, with respect to the duty cycle of signal S in the example in Figure 12, they may be used in a region with an extremely low duty cycle, or conversely, in a region with an extremely high duty cycle. For example, in the automotive sector, where electrification and the sophistication of electronic control are progressing, battery voltages tend to increase, while the operating voltages of many semiconductor integrated circuits used in the diverse electronic control systems remain at around a few volts. Therefore, switching regulators used between automotive batteries and electronic control equipment are sometimes required to operate at a low duty cycle.

[0006] However, conventional switching regulators sometimes fail to provide proper operation across a wide range of duty cycles. For example, they may exhibit unstable control at low duty cycles, resulting in excessive ripple in the output voltage. Thus, conventional switching regulators sometimes fail to adequately meet market demands for proper operation under a wide range of input and output voltage conditions depending on the electronic device being used.

[0007] In view of these problems, the present invention aims to provide a switching regulator control circuit that can stably obtain a desired output voltage over a wider range of the difference between the input voltage and the output voltage than conventional methods. [Means for solving the problem]

[0008] One embodiment of the switching regulator control circuit of the present invention is a switching regulator control circuit that controls a switching element that intermittently switches the conduction state between the input terminal and output terminal of a switching regulator configured to output a target voltage less than or equal to an input voltage, using a negative feedback circuit, and includes a comparison circuit that forms part of the negative feedback circuit and outputs a basic pulse that indicates the duration of a predetermined magnitude relationship between the voltage of the error signal and the voltage of the periodic signal by comparing an error signal indicating the difference between the target voltage and the output voltage of the switching regulator with a periodic signal that includes a gradually changing period, and outputs a basic pulse that indicates the duration of a predetermined magnitude relationship between the voltage of the error signal and the voltage of the periodic signal, and an output circuit that outputs a control signal indicating the conduction time of the switching element based on the basic pulse, wherein the output circuit includes a pulse shortening circuit that shortens the time width of the basic pulse to generate a control pulse indicating the conduction time. [Effects of the Invention]

[0009] According to the switching regulator control circuit of the present invention, a desired output voltage can be stably obtained under a wider range of input-output voltage differences than in the conventional method. [Brief explanation of the drawing]

[0010] [Figure 1] This is a circuit diagram showing an example of a switching regulator control circuit of a self-conducted invention. [Figure 2A] This figure shows the waveform and error voltage near the lower limit voltage of a periodic signal, and illustrates the pulse generated by a comparator circuit in a control circuit that does not have a pulse shortening circuit. [Figure 2B] This diagram illustrates the relationship between error voltage and duty cycle in a control circuit without a pulse shortening circuit when distortion occurs near the lower limit voltage of a periodic signal. [Figure 3] This figure shows an example of the relationship between error voltage and duty cycle in a switching regulator control circuit according to an embodiment of the present invention. [Figure 4] This figure illustrates the operation of a switching regulator control circuit according to an embodiment of the present invention. [Figure 5]This is a circuit diagram showing an example of a pulse shortening circuit in one embodiment of the present invention. [Figure 6] This figure shows the voltage waveforms at each part of the pulse shortening circuit in the example shown in Figure 5. [Figure 7] This is a circuit diagram showing a first modified example of AVA. [Figure 8] This is a circuit diagram showing a second modified example of one embodiment of the present invention. [Figure 9] This is a circuit diagram showing a third modified example of one embodiment of the present invention. [Figure 10A] This is a circuit diagram showing a third modified form of one embodiment of the present invention. [Figure 10B] This is a circuit diagram showing a third modified form of one embodiment of the present invention. [Figure 11] This is a circuit diagram showing a fourth modified example of Embodiment 1. [Figure 12] This is a circuit diagram showing an example of a conventional switching regulator. [Modes for carrying out the invention]

[0011] Embodiments of the switching regulator control circuit of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiments described below.

[0012] <Configuration and basic operation of switching regulator control circuits> FIG. 1 shows a switching regulator control circuit 1 (hereinafter also simply referred to as "control circuit 1"), which is an example of a switching regulator control circuit according to an embodiment. The switching regulator 100 is composed of the control circuit 1, a transistor T connected to the output terminal 1a of the control circuit 1, a diode D and a smoothing circuit LC connected to the transistor T, and two voltage dividing resistors R1 and R2 connected to the smoothing circuit LC. The switching regulator 100 is a step-down switching regulator configured to output a target voltage lower than the voltage (input voltage Vin) input to its input terminal 101 as an output voltage Vout from the output terminal 102. The control circuit 1 controls a switching element (transistor T in the example of FIG. 1) that intermittently switches the conduction state between the input terminal 101 and the output terminal 102 of the switching regulator 100 using a negative feedback circuit 10.

[0013] The control circuit 1 includes an oscillation circuit 2, an error amplification circuit 3, a reference voltage generation circuit 31, a comparison circuit 4, and an output circuit 5. In the example of FIG. 1, the output of the oscillation circuit 2 is connected to the inverting input of the comparison circuit 4. The output of the error amplification circuit 3 is connected to the non-inverting input of the comparison circuit 4. A reference voltage Vref is input to the non-inverting input of the error amplification circuit 3, and a feedback voltage Vfb of the output voltage Vout of the switching regulator 100 is input to the inverting input of the error amplification circuit 3. The output of the comparison circuit 4 is input to the output circuit 5, and a control signal Sc output from the output circuit 5 is output from the output terminal 1a of the control circuit 1.

[0014] The output terminal 1a is connected to the control terminal of the transistor T (the gate in the example of FIG. 1), and one of the controlled terminals of the transistor T (the source in the example of FIG. 1) is connected to the input terminal 101 of the switching regulator 100 to input the input voltage Vin. The other controlled terminal of the transistor T (the drain in the example of FIG. 1) is connected to the cathode of a diode D whose anode is connected to GND. The smoothing circuit LC includes a coil L and a capacitor C connected in series. One end of the coil L is connected to the other controlled terminal of the transistor T and the cathode of the diode D, and one end of the capacitor C is connected to GND. The connection node between the coil L and the capacitor C is connected to the output terminal 102 of the switching regulator 100. A series circuit of voltage-dividing resistors R1 and R2 is connected between the output terminal 102 and GND, and the connection node between the voltage-dividing resistor R1 and the voltage-dividing resistor R2 is connected to the inverting input of the error amplification circuit 3.

[0015] The oscillation circuit 2 generates a periodic signal Sp in which the waveform of the signal level consisting of a voltage repeats the same form at a constant period. In particular, in the control circuit 1 of the embodiment, the oscillation circuit 2 generates a triangular wave signal or a sawtooth wave signal (hereinafter, also collectively referred to as a "ramp signal") including a period in which the signal level gradually changes with the passage of time as the periodic signal Sp. The periodic signal Sp may include a period in which it gradually changes across the signal level (error voltage Ver) of the error signal Ser output by the error amplification circuit 3. The oscillation circuit 2 is not particularly limited in its circuit configuration as long as it can generate a periodic signal such as a ramp signal. For example, the oscillation circuit 2 may be an integrated circuit device (IC) configured to generate such a periodic signal, or an oscillation circuit configured by a combination of individual semiconductor elements and passive components to generate a periodic signal. Also, the oscillation circuit 2 may be a so-called current-controlled oscillator or voltage-controlled oscillator whose oscillation frequency is variable depending on the current flowing inside or the voltage applied.

[0016] The reference voltage generation circuit 31 generates a reference voltage Vref, which is input to the non-inverting input of the error amplification circuit 3. While a constant voltage generation circuit such as a bandgap reference is exemplified as the reference voltage generation circuit 31, the reference voltage generation circuit 31 is not limited to a bandgap reference and can be composed of any circuit capable of generating a constant voltage. Preferably, the reference voltage generation circuit 31 generates a reference voltage Vref that is (r2 / (r1+r2)) times the target voltage required for the output voltage Vout of the switching regulator 100. Here, r1 and r2 are the resistance values ​​of the voltage divider resistors R1 and R2, respectively. In other words, the resistance values ​​of the voltage divider resistors R1 and R2 are selected such that (r2 / (r1+r2)) equals (reference voltage Vref) / (target voltage of the switching regulator 100). Note that the control circuit 1 does not necessarily have to include the reference voltage generation circuit 31, and the reference voltage Vref may be input from outside the control circuit 1.

[0017] The error amplification circuit 3 may be configured as an operational amplifier, as shown by the circuit symbol in Figure 1. The error amplification circuit 3 may be an integrated circuit (IC) that constitutes the operational amplifier, or it may be realized by a combination of discrete semiconductor elements and passive components. The error amplification circuit 3 configured as an operational amplifier outputs a voltage signal whose signal level increases or decreases depending on the difference between the voltage input to the non-inverting input and the voltage input to the inverting input. That is, the error amplification circuit 3 outputs an error signal Ser that indicates the difference between the voltage at the non-inverting input and the voltage at the inverting input. As mentioned above, a reference voltage Vref, which is (r2 / (r1+r2)) times the target voltage of the switching regulator 100, may be input to the non-inverting input of the error amplification circuit 3. On the other hand, a voltage that is (r2 / (r1+r2)) times the currently output output voltage Vout is input to the inverting input. Therefore, the error amplification circuit 3 outputs an error signal Ser that indicates the difference between the target voltage of the switching regulator 100 and the currently output output voltage Vout of the switching regulator 100. As shown in Figure 1, the error signal Ser consists of the output voltage Ver of the error amplification circuit 3.

[0018] The comparator circuit 4 may be composed of a comparator, as shown by the circuit symbol in Figure 1. The comparator circuit 4 may be an integrated circuit (IC) that constitutes a comparator, or it may be realized by a combination of discrete semiconductor elements and passive components. The comparator circuit 4 compares the periodic signal Sp input from the oscillator circuit 2 with the error signal Ser input from the error amplifier circuit 3 and outputs a signal (fundamental signal) Sb that indicates the comparison result.

[0019] In the example shown in Figure 1, the periodic signal Sp and the error signal Ser are input to the inverting and non-inverting input terminals of the comparator circuit 4, respectively. Therefore, in the example shown in Figure 1, the comparator circuit 4 outputs a basic signal Sb that is high level when the voltage of the error signal Ser (error voltage) Ver is greater than the voltage of the periodic signal Sp Vp, and low level when voltage Ver is less than voltage Vp. Thus, signal Sb contains a pulse (basic pulse) Pb that has a time width approximately the same as the duration of the state in which the voltage Ver of the error signal Ser is greater than the voltage Vp of the periodic signal Sp. In this way, the comparator circuit 4 outputs a basic pulse Pb that indicates the duration of a predetermined magnitude relationship between the voltage Ver of the error signal Ser and the voltage Vp of the periodic signal Sp, with that time width.

[0020] The "predetermined magnitude relationship" between voltage Ver and voltage Vp may be such that voltage Ver is greater than voltage Vp, or conversely, that voltage Ver is less than voltage Vp. In other words, a periodic signal Sp may be input to the non-inverting input of the comparator circuit 4, and an error signal Ser may be input to the inverting input. In that case, as will be described later, the configuration of the pulse shortening circuit 6 may be appropriately changed from the example in Figure 5.

[0021] The output circuit 5 outputs a control signal Sc indicating the conduction time of transistor T based on the basic pulse Pb input from the comparator circuit 4. The output terminal of the output circuit 5 is connected to the output terminal 1a of the control circuit 1, and the control signal Sc output from the output circuit 5 is output from the output terminal 1a as the output signal of the control circuit 1.

[0022] In this embodiment, the output circuit 5 includes a pulse shortening circuit 6. The pulse shortening circuit 6 generates and outputs a control pulse Pc that indicates the conduction time of transistor T. The pulse shortening circuit 6 generates the control pulse Pc by shortening the time width of the basic pulse Pb, as will be described later.

[0023] The output circuit 5 in the example in Figure 1 further includes a buffer circuit 51 that receives a control pulse Pc and outputs a control signal Sc. In the example in Figure 1, the buffer circuit 51 is composed of an inverter that inverts the high and low levels of the input signal and outputs them. Therefore, the control signal Sc includes a control pulse Pci, which is an inverted pulse of the control pulse Pc and has approximately the same time width as the control pulse Pc.

[0024] Note that the buffer circuit 51 does not necessarily have to be an inverter; in other words, it may be a non-inverting type buffer circuit. For example, as will be described later, the buffer circuit 51 may be a non-inverting type buffer circuit depending on the output signal of the pulse shortening circuit 6. Also, the output circuit 5 does not necessarily have a buffer circuit 51. For example, if the pulse shortening circuit 6 has sufficient driving capability for the transistor T, the buffer circuit 51 may not be provided.

[0025] The control terminal of transistor T, whose conduction state of two controlled terminals is controlled by control circuit 1, is connected to the output terminal 1a of control circuit 1. In the example in Figure 1, transistor T is a P-type FET. However, transistor T may also be an N-type FET. In that case, the output circuit 5 may not have a buffer circuit 51, or it may have a non-inverting buffer circuit. Also, transistor T may be a bipolar transistor.

[0026] The diode D, coil L, and capacitor C can be any diode, coil, and capacitor having characteristics and ratings suitable for the characteristics and ratings that the switching regulator 100 should possess. Furthermore, the voltage divider resistors R1 and R2 can be selected such that (r2 / (r1+r2)) for each resistance value r1 and r2 represents the ratio of the reference voltage Vref to the target voltage of the switching regulator 100.

[0027] The output voltage Vout of the switching regulator 100 is divided by voltage divider resistors R1 and R2 and input as a feedback voltage Vfb to the inverting input of the error amplifier circuit 3. That is, a negative feedback circuit 10 is formed that returns from the error amplifier circuit 3 to the error amplifier circuit 3 via the comparator circuit 4, output circuit 5, transistor T, smoothing circuit LC, and voltage divider resistor R1. Therefore, as described above, when the error amplifier circuit 3 operates, the error voltage Ver decreases / increases depending on whether the output voltage Vout is high or low relative to the target voltage of the switching regulator. Thus, the duty cycle of the basic signal Sb decreases / increases and the duty cycle of the control signal Sc increases / decreases, and consequently the conduction time of transistor T decreases / increases, causing the output voltage Vout to decrease / increase. As a result, an output voltage Vout close to the target voltage is continuously output.

[0028] The switching regulator 100 shown in Figure 1 differs from the conventional switching regulator shown in Figure 12 in that it includes a pulse shortening circuit 6 within the control circuit 1. Because the control circuit 1 includes the pulse shortening circuit 6, the switching regulator 100 can stably output a voltage with low ripple even when the conduction time of transistor T is considerably short relative to the period of the periodic signal Sp, that is, when the duty cycle of the switching regulator 100 is low, due to a large difference between the input voltage Vin and the target voltage (a small absolute value of the target voltage). The details are explained below. In the following explanation, the ratio simply referred to as "duty cycle" means the duty cycle of a switching regulator control circuit such as control circuit 1, or the duty cycle of a switching regulator such as switching regulator 100, i.e., the ratio between the input voltage Vin and the target voltage. The "duty cycle of the switching regulator" and the "duty cycle of the switching regulator control circuit" mean the ratio of the conduction time of the switching element that switches the conduction state between the input terminal and output terminal of a switching regulator such as transistor T, with respect to the period of the periodic signal Sp.

[0029] <Distortion of periodic signals> The upper panel of Figure 2A shows a magnified view of the waveform near the lower limit voltage of the periodic signal Sp generated by the oscillator circuit 2, along with error voltages Vera and Verb, which are compared with the voltage Vp of the periodic signal Sp. The lower panel shows the pulses P1 and P2 of the signal S generated in a conventional switching regulator control circuit as a result of this comparison. In an oscillator circuit that generates a ramp signal, such as oscillator circuit 2, signal waveform distortion, as shown in Figure 2A, can occur near the inversion value in the direction of voltage increase or decrease, such as the lower limit of the signal. Such waveform distortion can be caused, for example, by a capacitor within the oscillator circuit.

[0030] Figure 2B shows an example of the relationship between error voltage Ver and duty cycle in a conventional switching regulator control circuit when the periodic signal generated by the oscillator circuit is distorted as in the example in Figure 2A. Because the periodic signal is distorted, the ideal linear relationship shown by the dashed line between error voltage Ver and duty cycle cannot be obtained in the low duty cycle region, and the change in duty cycle in relation to the change in error voltage Ver increases.

[0031] If the periodic signal Sp generated by the oscillator circuit exhibits waveform distortion as shown in Figure 2A, and a considerably lower output voltage is required relative to the input voltage—that is, if low duty cycle operation is required and the error voltage Ver is located in the voltage region where the periodic signal Sp is distorted—the output voltage may not be properly controlled. For example, in Figure 2A, if the output voltage of the switching regulator is higher than the target voltage when the error voltage Vera is output and pulse P1 is generated as a result of comparison with the periodic signal Sp, a lower error voltage, such as error voltage Verb, will be output to reduce the duty cycle. When error voltage Verb is output, if there is no distortion in the periodic signal Sp, pulse Pt will be output and the duty cycle will decrease to a value corresponding to pulse Pt.

[0032] However, as shown in the example in Figure 2A, if distortion occurs in the periodic signal Sp, a pulse P2 with an even shorter time width than pulse Pt is generated, and the duty cycle may decrease to a value corresponding to pulse P2. As a result, the duty cycle is likely to fall below the desired duty cycle, and when it does, the error voltage Ver increases to increase the duty cycle, but because the change in pulse time width is large, pulses with a time width exceeding the desired duty cycle may be generated. As a result, the duty cycle of the switching regulator discretely fluctuates between the upper and lower ratios surrounding the desired duty cycle, and as a result, excessive ripple may occur in the output voltage of the switching regulator. To address these problems that can occur during operation at low duty cycles, in this embodiment, as shown in Figure 1, the control circuit 1 includes a pulse shortening circuit 6. As a result, a stable output voltage can be obtained even during operation at low duty cycles, as explained below.

[0033] <Function of pulse shortening circuit> Figure 3 shows the relationship Re1 between the error voltage Ver and the duty cycle in the control circuit 1, which includes the pulse shortening circuit 6, as a solid line. Figure 3 also shows the relationship between the error voltage Ver and the duty cycle when the pulse shortening circuit 6 is not present, i.e., the relationship Re2 shown in Figure 2B, as a dashed line. Since the duty cycle and output voltage Vout are proportional under a constant input voltage Vin, the relationships Re1 and Re2 shown in Figure 3 also show the relationship between the error voltage Ver and the output voltage Vout, as indicated by the second axis on the right side of Figure 3, which shows the output voltage Vout of the switching regulator.

[0034] As shown in Figure 3, in the control circuit 1 of this embodiment, which includes the pulse shortening circuit 6, the duty cycle with respect to the error voltage Ver is lower compared to a conventional switching regulator control circuit. Therefore, the relationship between the error voltage Ver and the duty cycle shifts from relationship Re2, shown by the dashed line, to relationship Re1, shown by the solid line, by the amount of decrease in the duty cycle ΔD corresponding to the amount of shortening of the basic pulse Pb by the pulse shortening circuit 6. For example, when the duty cycle D1 is required to output the output voltage Vo1, the error amplification circuit 3 (see Figure 1), which constitutes the negative feedback circuit 10 together with the pulse shortening circuit 6, outputs an error voltage Ver2 that is higher than the error voltage Ver1 by a voltage difference ΔV that compensates for the decrease in the duty cycle ΔD caused by the pulse shortening circuit 6, rather than the error voltage Ver1. For the error voltage Ver2, the comparison circuit 4 (see Figure 1) outputs a basic pulse Pb (see Figure 1) having a time width corresponding to the duty cycle D2, according to relationship Re2, shown by the dashed line. The duration of the basic pulse Pb is longer than the duration corresponding to the duty cycle D1 to be achieved by a time equal to the duty cycle reduction ΔD caused by the pulse shortening circuit 6. However, the duration of the basic pulse Pb is shortened by the pulse shortening circuit 6 by a time equal to the duty cycle reduction ΔD, so the duty cycle D1 to be achieved is realized.

[0035] The effect of this operation of the error amplifier circuit 3 in the control circuit 1 equipped with the pulse shortening circuit 6 will be explained with reference to Figure 4. Figure 4 shows, similar to Figure 2A, the periodic signal Sp, the error voltage Ver, and the pulses of the signal Sb generated as a result of comparing the periodic signal Sp and the error voltage Ver (basic pulse Pb, control pulse Pc). In operation at a low duty cycle where a conventional switching regulator control circuit should output, for example, the error amplifier circuit 3 of the control circuit 1 of this embodiment outputs an error voltage Ver2 that is ΔV higher than the error voltage Ver1 by a voltage difference ΔV that compensates for the decrease in duty cycle ΔD due to the pulse shortening circuit 6, rather than the error voltage Ver1. Due to this operation of the error amplifier 3, in operation at a low duty cycle where a conventional switching regulator control circuit would output the error voltage Ver1, in the control circuit 1 of this embodiment, the error voltage Ver2 is compared with the periodic signal Sp in a region where no waveform distortion is yet observed, rather than immediately near the lower limit of the periodic signal Sp. As a result of this comparison, a basic pulse Pb is output that has a time width longer by the amount of time width reduction Δt in the pulse shortening circuit 6 than the control pulse Pc that should be generated by comparing the distortion-free periodic signal Sp with the error voltage Ver1. The time width of the basic pulse Pb is shortened by Δt by the pulse shortening circuit 6, and the control pulse Pc is output from the pulse shortening circuit 6. Therefore, the voltage control operation of the switching regulator 100 is stabilized, and the desired output voltage with little ripple is obtained.

[0036] For example, even when operating at a duty cycle of approximately 0%, such as when an error voltage Ver3 is output in a conventional switching regulator, the voltage control operation can be made unstable by selecting the amount of pulse width reduction by the pulse shortening circuit 6 so that the error voltage output is located in a voltage region where there is no distortion in the waveform of the periodic signal Sp. Even without significantly reducing the pulse width, by appropriately reducing the pulse width, it is possible to lower the duty cycle at which control begins to become unstable at low duty cycles, thereby widening the stable operating range with respect to duty cycles.

[0037] <Example of a pulse shortening circuit> Figure 5 shows a specific example of the pulse shortening circuit 6 included in the control circuit 1 of this embodiment. Figure 6 also shows the voltage waveforms V60, Vn1, and V67 at the input terminal 60, node N1, and output terminal 67 of the pulse shortening circuit example in Figure 5, respectively.

[0038] The pulse shortening circuit 6 in the example of Figure 5 includes an inverting buffer 61 to which the output of the comparator circuit 4 in Figure 1 is input via its input terminal 60, a switching element 62, a current source 63, a capacitor 64, and inverting buffers 65 and 66. The output of the inverting buffer 61 is connected to the control terminal of the switching element 62, and one of the two controlled terminals of the switching element 62, the input of the inverting buffer 65, and one end of the capacitor 64 are connected at node N1. The other controlled terminal of the switching element 62 and the other end of the capacitor 64 are connected to GND. The output of the inverting buffer 65 and the input of the inverting buffer 66 are connected, and the output of the inverting buffer 66 is connected to the input of the buffer circuit 51 in Figure 1 via its output terminal 67. The current source 63 is connected via node N1 to one of the controlled terminals of the switching element 62, one end of the capacitor 64, and the input of the inverting buffer 65, and supplies a constant current to the capacitor 64 when the switching element 62 is in a non-conducting state.

[0039] In the example in Figure 5, the switching element 62 is an N-type FET, with its gate connected to the inverting buffer 61, its drain connected to node N1, and its source connected to GND. The switching element 62 may also be a P-type FET or a bipolar transistor. Depending on the conductivity type and characteristics of the transistor that is the switching element 62, and in cases where a periodic signal Sp is input to the non-inverting input of the comparator circuit 4 in Figure 1 and an error signal Ser is input to the inverting input, a non-inverting buffer may be provided instead of the inverting buffer 61, or the inverting buffer 61 may be omitted. Also, depending on the conductivity type and characteristics of the transistor T that is the switching element of the switching regulator 100, either or both of the inverting buffers 65 and 66 may be omitted, and may be replaced by the buffer circuit 51 shown in Figure 1. The current source 63 is not particularly limited in its configuration or internal circuitry, as long as it can supply a constant current to the capacitor 64. For example, the current source 63 may be configured by any circuit including a current mirror.

[0040] As shown in Figure 6, the basic pulse Pb output by the comparator circuit 4 is input to the input terminal 60 to which the output of the comparator circuit 4 in Figure 1 is connected. Until the basic pulse Pb is input, the voltage at the input terminal 60 is low, as shown by the voltage waveform V60, so the inverting buffer 61 outputs a high-level voltage, the switching element 62, which is an N-type FET, is in a conducting state, and the current supplied from the current source 63 flows into the switching element 62 instead of the capacitor 64, and at the same time the charge in the capacitor 64 is discharged via the switching element 62. Therefore, the voltage at node N1 is low, as shown by the voltage waveform Vn1, and the voltage at the output terminal 67 is also low, as shown by the voltage waveform V67.

[0041] When the basic pulse Pb is input to the inverting buffer 61 at time t1, the output of the inverting buffer 61 transitions to a low level in accordance with the rising edge of the basic pulse Pb, and the switching element 62, which was previously conducting, switches to a non-conducting state. The current from the current source 63 that was flowing through the switching element 62 begins to flow to the capacitor 64, and the capacitor 64 begins to charge, causing the voltage at node N1 to start rising. Then, at time t2, when the voltage at node N1 exceeds the input threshold Vt of the inverting buffer 65, the output of the inverting buffer 66 also inverts along with the output of the inverting buffer 65, and as a result, the voltage at the output terminal 67 rises as shown by the voltage waveform V67. After that, a high-level voltage is output from the output terminal 67 until the voltage at the input terminal 60 falls.

[0042] Subsequently, at time t3, when the input of the basic pulse Pb ends and the voltage at the input terminal 60 falls to a low level, a high-level voltage is output from the inverting buffer 61 and the switching element 62 transitions to a conduction state. The capacitor 64 is rapidly discharged and the voltage at node N1 transitions to a low level, and via the inversion of the output of the inverting buffer 65, the output of the inverting buffer 66, i.e., the voltage at the output terminal 67, also transitions to a low level, thus obtaining a control pulse Pc with a time width from time t2 to time t3. In this way, a control pulse Pc is generated and output in which the time width of the basic pulse Pb, which has a time width from time t1 to time t3, is shortened to a time width from time t2 to time t3.

[0043] As shown above, in the example of Figure 5, the pulse shortening circuit 6 includes a capacitor 64 configured to start charging when the basic pulse Pb rises. The pulse shortening circuit 6 in the example of Figure 5 is configured to shorten the time width of the basic pulse Pb by the length of time required from the start of charging of the capacitor 64 until the capacitor 64 reaches a predetermined charge state. The amount of shortening of the time width of the basic pulse Pb by the pulse shortening circuit 6 can be adjusted by any method. For example, the amount of shortening of the time width by the pulse shortening circuit 6 can be adjusted by adjusting the current value of the current source 63, the capacitance of the capacitor 64, and the resistance value of an electrical resistor (not shown) connected in series with the capacitor 64.

[0044] In the example in Figure 5, the inverting buffer 65 is a Schmitt trigger inverter with hysteresis in the input voltage threshold according to its internal state. The inverting buffer 65 does not necessarily have to be an inverting buffer with such hysteresis, but an inverting buffer with hysteresis in the input voltage threshold is sometimes preferable for a gradually rising voltage at node N1. That is, it may be possible to suppress chattering when the output of the inverting buffer 65 is inverted.

[0045] <Stability during operation at high duty cycles> As described above, by providing a pulse shortening circuit 6 as shown in the example in Figure 5, instability during operation at low duty cycles can be reduced. However, referring to Figure 3 again, when the relationship between error voltage and duty cycle shifts from relation Re2 to relation Re1 due to the action of the pulse shortening circuit 6, the region where the change in duty cycle becomes large in response to the change in error voltage Ver (hereinafter this region is also called the "nonlinear region") expands to the low duty cycle side, as shown in part A of Figure 3. Therefore, the output voltage of the switching regulator may become unstable when operating at extremely high duty cycles close to 100%. As mentioned above, switching regulators are required to operate at various duty cycles depending on the application and operating environment. Therefore, stable operation even at high duty cycles is desirable.

[0046] The nonlinear region is thought to expand as the shortening width of the basic pulse Pb by the pulse shortening circuit 6 increases. This is because, as a result of the pulse shortening circuit 6, a basic pulse Pb with a longer duration than the pulse that should be generated for the desired duty cycle is output from the comparator circuit 4. Therefore, as the duty cycle approaches 100%, the duty cycle of the basic pulse Pb approaches 100% first. For example, even if the duty cycle of the basic pulse Pb gradually increases to 100%, the duty cycle of the control pulse Pc output by the pulse shortening circuit 6 changes rapidly to 100% when the duty cycle of the basic pulse Pb reaches 100% because the discharge opportunity of the capacitor 64 in Figure 5 disappears. Also, even if the duty cycle of the basic pulse Pb does not reach 100%, as it approaches 100%, the discharge time of the capacitor 64 becomes insufficient, and the duty cycle of the control pulse Pc may increase in proportion to the change in the duty cycle of the basic pulse Pb.

[0047] Furthermore, the amount of change in the duty cycle brought about by the pulse shortening circuit 6 increases as the frequency of the periodic signal Sp (see Figure 1) increases. This is because, even if the amount of shortening of the time width of the basic pulse Pb by the pulse shortening circuit 6 is the same, the higher the frequency, the larger the ratio of the shortening amount to the period, and therefore the larger the change in the duty cycle.

[0048] In this embodiment, modifications to suppress instability in operation at high duty cycles are described below. First, a first modification that suppresses the increase in the amount of change in the duty cycle with respect to the error voltage, especially when the frequency of the periodic signal is high, is described.

[0049] <First variation> Figure 7 shows a circuit diagram of a first modified example of the control circuit 1 of this embodiment. In the example of Figure 7, the control circuit 1 includes an oscillator circuit 2 that generates a periodic signal Sp, similar to the example of Figure 1. The oscillator circuit 2 in the example of Figure 7 is configured to oscillate the periodic signal Sp at a frequency corresponding to the current (control current) flowing inside the oscillator circuit 2. Furthermore, in the example of Figure 7, the pulse shortening circuit 6 includes a second current source 63a that supplies current to the capacitor 64, in addition to the current source 63. External circuit elements attached to the control circuit 1, and the buffer circuit 51 in the example of Figure 1, are added in the example of Figure 7 in the same way as in the example of Figure 1. However, since these configurations may be the same as in the example of Figure 1, their illustration and description are omitted. The same applies to the drawings from Figure 8 onwards, which will be referenced later. Also, among the components shown in the drawings from Figure 7 onwards, components that are the same as those shown in Figure 1 or Figure 5 are either denoted by the same reference numerals as those in Figure 1 or Figure 5, or are omitted as appropriate, and the description of such similar components is omitted as appropriate.

[0050] Specifically, the oscillator circuit 2 in Figure 7 is configured to generate a periodic signal Sp having a frequency corresponding to the current I1 flowing through a resistor Rt, which is located outside the control circuit 1 and connected to the oscillator circuit 2 via terminal 2a. That is, the frequency of the periodic signal Sp is set by selecting the resistance value of resistor Rt. In the example in Figure 7, the current I1 is configured to flow through a current mirror circuit 21 within the oscillator circuit 2, and the mirror current corresponding to the current I1 flows into the signal generation circuit 22, which generates the periodic signal Sp. When the current I1 changes according to the resistance value of resistor Rt, for example, the charging and discharging time in the signal generation circuit 22 changes, and a periodic signal Sp having a frequency corresponding to the resistance value of resistor Rt is generated. For example, the larger the current I1, the higher the frequency of the periodic signal Sp that can be generated.

[0051] On the other hand, the second current source 63a is a variable current source configured to adjust the current supplied to the capacitor 64. In the example in Figure 7, the second current source 63a is configured to supply a current to the capacitor 64 corresponding to the resistance value of the resistor Rt when the switching element 62 is in a non-conductive state. Therefore, the second current source 63a can supply a current to the capacitor 64 corresponding to the frequency of the periodic signal Sp.

[0052] For example, when the current I1 increases, the frequency of the periodic signal Sp increases, and the current supplied from the second current source 63a also increases. As a result, the charging speed of the capacitor 64 increases. Conversely, when the frequency of the periodic signal Sp is low, the current supplied from the second current source 63a is small, and the charging speed of the capacitor 64 is slow. Therefore, the time shortening of the time width of the basic pulse Pb by the pulse width shortening circuit 6 can be adjusted according to the frequency of the periodic signal Sp.

[0053] The oscillation circuit 2 and the pulse shortening circuit 6 may be configured such that a current equivalent to current I1 is supplied to the capacitor 64. For example, the second current source 63a may be omitted, and two outputs of the current mirror circuit 21 in Figure 7 may be provided in parallel, with one of them connected to the capacitor 64 as shown in connection 2b by the dashed line in Figure 7, thereby supplying the mirror current of current I1 to the capacitor 64. In this way, the charging speed of the capacitor 64 can be adjusted according to the frequency of the periodic signal Sp, and thus the shortening time of the basic pulse Pb by the pulse width shortening circuit 6 can be adjusted.

[0054] Thus, the pulse shortening circuit 6 in the example of Figure 7 is configured to charge the capacitor 64 using a current based on a current I1 that can have a current value corresponding to the frequency of the periodic signal Sp. In this embodiment, the pulse shortening circuit 6 may be configured to change the shortening time of the time width of the basic pulse Pb according to the frequency of the periodic signal Sp.

[0055] Next, in this embodiment, in addition to adjusting the shortening amount according to the frequency of the periodic signal Sp, or in addition to that, several modifications that suppress instability of operation at high duty cycles are described below. In each of the modifications described below, the pulse shortening circuit 6 is configured to change the shortening time of the time width of the basic pulse Pb according to the duty cycle of the control pulse Pc with respect to the period of the periodic signal Sp, that is, according to the duty cycle of the control circuit 1.

[0056] <Second variation> Figure 8 shows a second modified example of the control circuit 1 of this embodiment. The pulse shortening circuit 6 in the example of Figure 8 includes a differential input circuit Din composed of a pair of transistors, a common current source Ics that supplies a constant current to the differential input circuit Din, a reference voltage generation circuit Vrs that generates a constant reference voltage Vr2, and a current mirror circuit CL1 to which the current flowing out from the differential input circuit Din is input, instead of the second current source 63a and the mechanism for adjusting its current in the example of Figure 7. The pulse shortening circuit 6 in the example of Figure 8 further includes a current mirror circuit CL2 connected between the current mirror circuit CL1 and the capacitor 64, which allows current flowing into the capacitor 64 to flow out when the switching element 62 is in a non-conductive state.

[0057] In other words, the pulse shortening circuit 6 in the example of Figure 8 consists of a common current source Ics, a differential input circuit Din, a reference voltage generation circuit Vrs, and current mirror circuits CL1 and CL2, and includes a current supply circuit that supplies current to the capacitor 64 when the capacitor 64 is being charged. This current supply circuit is configured to increase the current supplied to the capacitor 64 in response to an increase in the voltage of the periodic signal Sp, as will be described below.

[0058] One input Di1 of the differential input circuit Din receives the periodic signal Sp output from the oscillator circuit 2, while the other input Di2 receives the reference voltage Vr2 generated by the reference voltage generation circuit Vrs. The reference voltage generation circuit Vrs generates a reference voltage Vr2 that is, for example, any voltage between the lower limit and upper limit voltages of the periodic signal Sp. The current supplied from the common current source Ics is distributed between the transistors on the input Di1 side and the transistors on the input Di2 side according to the relative magnitudes of the voltages at input Di1 and input Di2 and the magnitude of the difference between them. The greater the voltage at input Di1 is than the voltage at input Di2, the less current flows through the transistors on the input Di1 side and the more current flows through the transistors on the input Di2 side.

[0059] The current flowing through the transistor on the input Di2 side flows into one of the two transistors in the current mirror circuit CL1, which is a diode-connected transistor (in Figure 8, the left transistor with its drain and gate connected). The other transistor in the current mirror circuit CL1 receives a current of a magnitude corresponding to the magnitude of the current flowing into the other transistor from the differential input circuit Din. This current flows into the other diode-connected transistor in the current mirror circuit CL2 (in Figure 8, the left transistor with its drain and gate connected). Therefore, the other transistor in the current mirror circuit CL2 receives a current of a magnitude corresponding to the current flowing from the current mirror circuit CL2 to the current mirror circuit CL1. This current is supplied to the capacitor 64 when the switching element 62 is in a non-conductive state.

[0060] In other words, a current of a magnitude corresponding to the voltage of the periodic signal Sp is supplied to the capacitor 64 when the switching element 62 is in a non-conducting state. The larger the voltage of the periodic signal Sp is relative to the reference voltage Vr2, the larger the current supplied to the capacitor 64 in addition to the current from the current source 63. In accordance with this increase in current, the charging speed of the capacitor 64 is increased, and as a result, the amount of shortening of the time width of the basic pulse Pb by the pulse shortening circuit 6 becomes smaller. Therefore, the amount of shortening of the time width of the basic pulse Pb by the pulse shortening circuit 6 can be adjusted by the voltage of the periodic signal Sp when the switching element 62 is in a non-conducting state, and the higher the voltage of the periodic signal Sp when the switching element 62 is in a non-conducting state, the smaller the amount of shortening of the time width of the basic pulse Pb can be.

[0061] In the example shown in Figure 8, the switching element 62 turns into a non-conducting state when the voltage of the error signal Ser exceeds the voltage of the periodic signal Sp. Therefore, the higher the voltage of the periodic signal Sp when the voltage of the error signal Ser exceeds the voltage of the periodic signal Sp, the greater the current supplied to the capacitor 64 when charging of the capacitor 64 begins. On the other hand, the voltage of the error signal Ser is larger when the difference between the input voltage and output voltage of the step-down switching regulator is small, and therefore the higher the duty cycle of the control circuit 1. Consequently, the higher the duty cycle of the control circuit 1, the greater the voltage of the periodic signal Sp when the voltage of the error signal Ser exceeds the voltage of the periodic signal Sp. Consequently, the higher the duty cycle of the control circuit 1, the greater the current supplied to the capacitor 64 when charging of the capacitor 64 begins, and the smaller the reduction in the time width of the basic pulse Pb.

[0062] Thus, the pulse shortening circuit 6 in the example of Figure 8 is configured to change the shortening time of the basic pulse Pb according to the voltage of the periodic signal Sp when the relative magnitudes of the voltage of the error signal Ser and the voltage of the periodic signal Sp switch. As in the example of Figure 8, by using the periodic signal Sp as one of the input voltages of the differential input circuit Din which is compared with the reference voltage Vrs, the shortening time of the basic pulse Pb can be changed according to the duty cycle of the control circuit 1.

[0063] In the example shown in Figure 8, the oscillator circuit 2 is configured to generate a triangular wave signal instead of a sawtooth wave signal as the periodic signal Sp. A triangular wave signal as the periodic signal Sp is preferable because the change in the voltage of the periodic signal Sp is gradual when the voltage of the error signal Ser exceeds the periodic signal Sp, i.e., when charging of the capacitor 64 begins, thus making it less likely for the shortening amount of the basic pulse Pb to become unstable.

[0064] <Third variation> Figure 9 shows a third modified example of the control circuit 1 of this embodiment. In the pulse shortening circuit 6 of the example in Figure 9, an error signal Ser is input to one of the inputs Di1 of the differential input circuit Din, instead of a periodic signal Sp. The oscillation circuit 2 may generate a triangular wave signal as the periodic signal Sp, but in the example in Figure 9, a sawtooth wave signal is generated. The other circuit configurations and components in the pulse shortening circuit 6 of the example in Figure 9 are the same as those in the pulse shortening circuit 6 of the example in Figure 8, so a repetitive explanation of them will be omitted.

[0065] The pulse shortening circuit 6 in the example of Figure 9 operates similarly to the pulse shortening circuit 6 in the example of Figure 8. However, in the example of Figure 9, the larger the voltage of the error signal Ser, the larger the current supplied to the capacitor 64 when the switching element 62 is not conducting, and the smaller the amount of shortening of the time width of the basic pulse Pb by the pulse shortening circuit 6. As mentioned above, the voltage of the error signal Ser is larger when the duty cycle of the control circuit 1 is high. Therefore, as in the example of Figure 9, by using the error signal Ser as one of the input voltages of the differential input circuit Din which is compared with the reference voltage Vrs, the shortening time of the time width of the basic pulse Pb can be changed according to the duty cycle of the control circuit 1. Thus, in the control circuit 1 of this embodiment, the pulse shortening circuit 6 may be configured to change the shortening time of the time width of the basic pulse Pb according to the voltage of the error signal Ser.

[0066] <Another form of the third variation> As shown in the example in Figure 9, when the amount of shortening by the pulse shortening circuit 6 is changed using an error signal Ser, the pulse shortening circuit 6 may be configured as in the alternative examples shown in Figures 10A and 10B. In the examples in Figures 10A and 10B, an operational amplifier OP to which the error signal Ser is input is provided, without the differential input circuit Din or current mirror circuit CL1 as in the example in Figure 9.

[0067] In the example in Figure 10A, the error signal Ser is input to the non-inverting input of the operational amplifier OP. The output of the operational amplifier OP is connected to the gate of the transistor Tr, the drain of transistor Tr is connected to a diode-connected transistor in the current mirror circuit CL2, and the source of transistor Tr is connected to the inverting input of the operational amplifier OP and one end of resistor Ro. The other end of resistor Ro is connected to GND.

[0068] In the example in Figure 10A, the higher the error signal Ser, the larger the voltage output by the operational amplifier OP to increase the voltage at the inverting input, reducing the drain-source resistance of the transistor Tr and increasing the current flowing through the transistor connected to transistor Tr, one of the two transistors in the current mirror circuit CL2. As a result, the current supplied to capacitor 64 also increases, and the amount of time width reduction of the fundamental pulse Pb by the pulse shortening circuit 6 decreases.

[0069] In the example in Figure 10B, the error signal Ser is input to the inverting input of the operational amplifier OP. The output of the operational amplifier OP is connected to the gates of the pair of transistors in the current mirror circuit CL2 that are connected to each other. The drain of the transistor that is not connected to capacitor 64 is connected to the non-inverting input of the operational amplifier OP and to one end of resistor Ro. The other end of resistor Ro is connected to GND.

[0070] In the example in Figure 10B, the higher the error signal Ser, the smaller the op-amp OP outputs to increase the voltage at the non-inverting input, thereby lowering the gate voltage of the pair of transistors in the current mirror circuit CL2. As a result, the current flowing through the transistor connected to resistor Ro increases, as does the current flowing through the transistor connected to capacitor 64. Consequently, the current supplied to capacitor 64 increases, and the amount of time width reduction of the basic pulse Pb by the pulse shortening circuit 6 decreases.

[0071] <Fourth variation> Figure 11 shows a fourth modified example of the control circuit 1 of this embodiment. In the pulse shortening circuit 6 of the example in Figure 11, one input Di1 of the differential input circuit Din is input to an output proportional voltage Voa proportional to the output voltage Vout of the switching regulator 100 (see Figure 1), and the other input Di2 is input to an input proportional voltage Via proportional to the input voltage Vin of the switching regulator 100 (see Figure 1). For example, the input voltage Vin and the output voltage Vout may be divided by a series resistor circuit and input to the differential input circuit Din, respectively. The other circuit configurations and components in the pulse shortening circuit 6 of the example in Figure 11 are the same as those in the pulse shortening circuit 6 of the example in Figure 9, so a repetitive explanation of them will be omitted.

[0072] The pulse shortening circuit 6 in the example of Figure 11 operates similarly to the pulse shortening circuit 6 in the example of Figure 9. However, in the example of Figure 11, the larger the ratio of the output proportional voltage Voa to the input proportional voltage Via, the more current flows to the transistor on the side to which the input proportional voltage Via is input. That is, a large current is supplied to the capacitor 64 when the switching element 62 is not conducting, so the amount of shortening of the time width of the basic pulse Pb by the pulse shortening circuit 6 is small. The ratio of the output proportional voltage Voa to the input proportional voltage Via, that is, the ratio of the output voltage Voa to the input voltage Via, is naturally larger when the duty cycle of the control circuit 1 is high. Therefore, as in the example of Figure 11, by applying the input proportional voltage Via and the output proportional voltage Voa to the respective inputs of the differential input circuit Din so that they can be compared with each other, the shortening time of the time width of the basic pulse Pb can be changed according to the duty cycle of the control circuit 1. Thus, in the control circuit 1 of this embodiment, the pulse shortening circuit 6 may be configured to change the shortening time of the time width of the basic pulse Pb according to the ratio of the input voltage Vin to the output voltage Vout.

[0073] Furthermore, the common current source Ics shown in the examples of Figures 8, 9, and 11 may be configured to allow adjustment of the magnitude of the supplied current, similar to the second current source 63a in the example of Figure 7. For example, similar to the second current source 63a in the example of Figure 7, a terminal for adjusting the current value in the common current source Ics may be connected to the oscillator circuit 2 to supply more current when the frequency of the periodic signal Sp is high. This reduces the amount of shortening of the time width of the basic pulse Pb during high duty cycle operation, and also reduces the amount of shortening of the time width of the basic pulse Pb when the frequency of the periodic signal Sp is high. [Explanation of Symbols]

[0074] 1. Switching regulator control circuit 10 Negative Feedback Circuit 100 Switching Regulator 101 Input Terminal 102 Output terminal 2. Oscillator Circuit 3. Error Amplifier Circuit 31. Reference voltage generation circuit 4 Comparison circuit 5 Output Circuit 6. Pulse shortening circuit 62 Switching elements (transistors) 63 Current source 63a 2nd current source 64 Capacitors I1 Current (Frequency setting current) Pb Basic Pulse Pc control pulse Sc control signal Sp periodic signal Ver, Ver1~3, Vera, Verb Error Voltage Vin Input Voltage Vout output voltage Vp is the voltage of the periodic signal. Vref Reference Voltage

Claims

1. A switching regulator control circuit that uses a negative feedback circuit to control a switching element that intermittently switches a conductive state between an input terminal and an output terminal of a switching regulator that is configured to output a target voltage equal to or lower than an input voltage, a comparator circuit which compares an error signal indicating the difference between a target voltage and the output voltage of the switching regulator with a periodic signal including a gradually changing period, and outputs a basic pulse indicating the duration of a predetermined magnitude relationship between the voltage of the error signal and the voltage of the periodic signal, and which constitutes a part of the negative feedback circuit; an output circuit that outputs a control signal indicating a conduction time of the switching element based on the basic pulse, The output circuit includes a pulse shortening circuit that shortens a time width of the basic pulse to generate a control pulse indicating the conduction time. Switching regulator control circuit.

2. The pulse shortening circuit comprises: a capacitor configured to begin charging at the rising edge of the basic pulse; 2. The switching regulator control circuit according to claim 1, wherein the time span is shortened by the length of time it takes for the capacitor to reach a predetermined charged state from the start of the charging.

3. further comprising an oscillator circuit for generating the periodic signal; the oscillator circuit is configured to oscillate the periodic signal at a frequency corresponding to a current flowing therethrough; The switching regulator control circuit of claim 2 , wherein the pulse shortening circuit is configured to charge the capacitor with a current based on the current.

4. 3. The switching regulator control circuit according to claim 1, wherein the pulse shortening circuit is configured to change the amount of time the pulse width is shortened in accordance with a frequency of the periodic signal.

5. 5. The switching regulator control circuit according to claim 1, wherein the pulse shortening circuit is configured to change the shortening time of the time width in accordance with a duty ratio of the control pulse with respect to a period of the periodic signal.

6. 6. The switching regulator control circuit according to claim 1, wherein the pulse shortening circuit is configured to change the shortening time of the time width in response to a voltage of the periodic signal when a magnitude relationship between the voltage of the error signal and the voltage of the periodic signal switches.

7. 6. The switching regulator control circuit according to claim 1, wherein the pulse shortening circuit is configured to change the amount of time the time width is shortened in response to a voltage of the error signal.

8. 6. The switching regulator control circuit according to claim 1, wherein the pulse shortening circuit is configured to change the shortening time of the time width in accordance with a ratio between the input voltage and the output voltage.

9. the pulse shortening circuit further includes a current supply circuit that supplies a current flowing through the capacitor when the capacitor is charged; 3. The switching regulator control circuit according to claim 2, wherein the current supply circuit is configured to increase the supply current in response to an increase in the voltage of the periodic signal.

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