Tetragonal system semimetal half-whistler compound

Abstract

To provide a magnetic resistance random access memory (MRAM) cell, capable of performing a scaling of a size by using a tetragonal system semimetal half-whistler compound (a tetragonal system is contributed to a PMA).SOLUTION: A MRAM cell contains a template layer (a non-limit chemical template layer). The template layer contains a binary alloy having an alternative layer lattice structure. The MRAM cell also contains a semimetal half-whistler layer containing a semimetal half-whistler material having a tetragonal system lattice structure. The semimetal half-whistler layer is positioned at an outer side of the template layer, and includes the number of half-whistler inner surface lattices different from the number of cubic-shaped inner surface lattices of the semimetal half-whistler material. In addition, the MRAM cell contains: a tunnel barrier positioned on the outer side of the semimetal half-whistler layer; and a magnetic layer positioned at the outer side of the tunnel barrier.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates generally to electrical, electronic and computer technologies, and more particularly to magnetoresistive random access memory (MRAM). [Background technology]

[0002] Currently, MRAM is a three-layer device that uses magnetic tunnel junctions (MTJs). These typically include a reference layer magnet, a tunnel barrier, and a storage or free magnetic layer. The magnetic layers can be ferromagnetic or ferrimagnetic. A current is passed through the device and the resistance is measured. The resistance varies depending on the magnetic orientation of the two magnetic layers, and the relative resistance change is called tunneling magnetoresistance (TMR), which is related to the spin polarization (i.e., higher spin polarization means higher TMR). High spin polarization, and therefore high TMR, is preferred (higher TMR means higher ON / OFF ratio). Low switching currents are also preferred. In a parallel arrangement, the magnetic layers have their magnetizations aligned with each other; in this state the resistance is usually lower compared to the antiparallel arrangement. In an antiparallel state, the magnetic layers have their magnetizations misaligned with each other; in this state the resistance is usually higher compared to the parallel arrangement. The magnetic state of the MTJ is changed by passing a current. Since the current transfers spin angular momentum, exceeding a threshold current switches the moment direction of the memory layer. Such MRAM devices are switched using spin transfer torque (STT), hence the name STT-MRAM. The magnitude of the required switching current is smaller when the magnetization of the electrodes is oriented perpendicular to the layers.

[0003] Current devices use alloys of cobalt, iron and boron in the magnetic layers, and such layers are ferromagnetic. Heusler compounds have a face-centered cubic (FCC) crystal structure and 2A magnetic intermetallic compound having the composition YZ (full Heuslers or simply "Heuslers"), where X and Y are transition metals and Z is in the p-block (or main group) of the periodic table. A half Heusler has the composition XYZ. References herein to Heusler or Heuslers without the term "half" are intended to refer to full Heuslers. A Heusler compound has four interpenetrating FCC sublattices (in the case of the half Heusler compound XYZ, one FCC sublattice is empty). Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a technology for using a tetragonal half metallic half-Heusler compound in an MRAM or the like. [Means for solving the problem]

[0005] In one aspect, each exemplary magnetoresistive random access memory cell includes a template layer including a binary alloy having an alternating layer lattice structure; a half-metallic half-Heusler layer including a half-metallic half-Heusler material having a tetragonal lattice structure, the half-metallic half-Heusler layer being located outside the template layer and having a half-Heusler in-plane lattice constant different from the in-plane lattice constant of a cube shape of the half-metallic half-Heusler material; a tunnel barrier outside the half-metallic half-Heusler layer; and a magnetic layer outside the tunnel barrier.

[0006] In yet another aspect, a magnetoresistive random access memory array of such magnetoresistive random access memory cells includes a plurality of bit lines and a plurality of complementary bit lines forming a plurality of bit line-complementary bit line pairs, a plurality of word lines intersecting the plurality of bit line pairs at a plurality of cell locations, and a respective plurality of magnetoresistive random access memory cells located at each of the respective plurality of cell locations, each magnetoresistive random access memory cell electrically connected to a corresponding bit line and selectively interconnected to a corresponding complementary bit line under control of a corresponding one of the word lines.

[0007] In yet another aspect, a method of operating such an array includes providing an array, applying signals to word lines such that a first subset of cells store logic 1s and a second subset of cells store logic 0s; and reading the stored logic 1s and 0s via the bit lines and complementary bit lines.

[0008] In a further aspect, a method of forming a magnetoresistive random access memory cell includes providing a template layer comprising a binary alloy having an alternating layer lattice structure and having an in-plane lattice constant of the template layer; epitaxially growing a half-metallic half-Heusler layer on the template layer, the half-metallic half-Heusler layer comprising a half-metallic half-Heusler material, the half-metallic half-Heusler layer grown on the template layer, the half-Heusler material having a tetragonal lattice structure and a half-Heusler in-plane lattice constant different from the in-plane lattice constant of a cubic shape of the half-metallic half-Heusler material and substantially matching the in-plane lattice constant of the template layer; forming an outer tunnel barrier of the half-metallic half-Heusler layer; and forming a magnetic layer outer of the tunnel barrier.

[0009] In yet another aspect, a hardware description language design construct is encoded in a machine-readable data storage medium, the HDL design construct including elements that, when processed by a computer-aided design system as described, generate a machine-executable representation of a magnetoresistive random access memory cell and / or array.

[0010] As used herein, "facilitating" an action includes performing an action, making an action easier, helping to perform an action, or having an action performed. Thus, as a non-limiting example, instructions performed at a step can facilitate an action performed by semiconductor processing equipment by sending appropriate data or instructions to cause or assist in the action being performed. When an actor facilitates an action in addition to performing the action, the action is performed by some entity or combination of entities.

[0011] The techniques disclosed herein may provide substantial advantageous technical effects. Some embodiments may not have such potential advantages, and such potential advantages are not necessarily required in all embodiments. By way of example and not of limitation, one or more embodiments may provide one or more of the following:

[0012] • MRAM devices whose cells exhibit high spin polarization (using a semi-metal whose spin polarization is 1) and therefore high TMR and high ON / OFF ratio.

[0013] • MRAM devices in which the cells exhibit low magnetization and low switching currents.

[0014] • MRAM devices in which the magnetic layer of the cell exhibits volume perpendicular magnetic anisotropy (PMA) and can be scaled to small dimensions using tetragonal half-metallic half-Heusler compounds (where the tetragonal crystal structure contributes to the PMA).

[0015] • A fabrication technique that uses an underlayer (e.g., CoAl) to allow epitaxial growth of tetragonal semimetallic half-Heusler compounds.

[0016] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying drawings. [Brief description of the drawings]

[0017] The following drawings are offered by way of example only, and not by way of limitation, and like reference numbers (when used) indicate corresponding elements throughout the several drawings. [Figure 1] 1 shows a half-Heusler compound for use in an embodiment of the present invention. [Diagram 2] 1 illustrates the growth of a Heusler compound on a template layer in accordance with an embodiment of the present invention (and is representative of the growth of a half-Heusler compound on a template layer in accordance with an embodiment of the present invention). [Figure 3a] 1 shows a table of half-metallic half-Heusler compounds that can be used in tetragonal form in MRAM according to an embodiment of the present invention. [Figure 3b] 1 shows a table of half-metallic half-Heusler compounds that can be used in tetragonal form in MRAM according to an embodiment of the present invention. [Figure 3c] 1 shows a table of half-metallic half-Heusler compounds that can be used in tetragonal form in MRAM according to an embodiment of the present invention. [Figure 4] 1 shows ferromagnetic and ferrimagnetic semimetallic half-Heusler compounds that can be used in MRAM according to an embodiment of the present invention - (the tetragonal unit cell shown in FIGS. 4 and 5 is rotated 45° about the z-axis with respect to the parent cubic structure shown in FIG. 1). [Diagram 5] 1 shows ferromagnetic and ferrimagnetic semimetallic half-Heusler compounds that can be used in MRAM according to an embodiment of the present invention - (the tetragonal unit cell shown in FIGS. 4 and 5 is rotated 45° about the z-axis with respect to the parent cubic structure shown in FIG. 1). [Figure 6] The density of states (DOS) for the compounds listed in FIG. [Figure 7] FIG. 5 shows the density of states (DOS) for the compounds listed. [Figure 8] FIG. 3A reproduces portions of FIGS. 3A-C for a selected list of compounds with strong PMA. [Figure 9] 1 provides non-limiting examples of chemical templating layers useful in one or more embodiments. [Figure 10]1 illustrates a first exemplary MRAM cell according to an embodiment of the present invention. [Figure 11] 4 illustrates a second exemplary MRAM cell according to an embodiment of the present invention. [Figure 12] 1 illustrates an array of MRAM cells according to an embodiment of the present invention. [Figure 13] 1 shows a flow diagram of a manufacturing method according to an embodiment of the present invention. [Figure 14] 1 illustrates a computer system that may be useful for implementing one or more aspects and / or elements of the present invention. [Figure 15] FIG. 1 is a flow diagram of a design process used in the design, manufacture and / or testing of semiconductors. It should be understood that elements in the drawings are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown in order to reduce clutter in the view of the illustrated embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The principles of the invention described herein are in the context of exemplary embodiments, and various modifications to the illustrated embodiments within the scope of the claims will be apparent to those skilled in the art from the teachings herein. That is, no limitations are intended or should be inferred with respect to the embodiments shown and described herein.

[0019] Tetragonal half-Heusler compounds have been found to be important in MRAM applications. Current MRAM devices use magnetic tunnel junctions (MTJs) as the storage element. A simple MTJ is a three-layer structure that includes two magnetic layers separated by a tunnel barrier layer. Current MTJs using cobalt iron boron (Co / Fe / B) can provide magnetic layers with magnetization perpendicular to the film surface (i.e., exhibiting a favorable perpendicular magnetic anisotropy (PMA)). The perpendicular magnetic anisotropy (PMA) of a Co-Fe-B layer arises from the interface between such a layer and the tunnel barrier and / or underlayer on which the Co-Fe-B layer is deposited. Thus, these layers must be thin enough so that the interface PMA arises from the magnetic volume and overcomes the magnetic erase energy, which increases in proportion to the magnetic volume of the Co-Fe-B layer. However, high moment requires high switching current. One or more embodiments advantageously provide a PMA, but with a lower moment and correspondingly reduced switching current compared to prior art devices.

[0020] It is preferable for magnetic materials to have volume PMA rather than surface (interface) PMA because this allows devices to be scaled to smaller sizes (typically smaller diameters). As device size decreases, the thermal stability of the device decreases. However, for elements with volume anisotropy, there is an advantage to increasing the thickness to compensate for the loss in thermal stability. The switching current is expressed as the product (M s VH k ), where M s is the saturation magnetization, V is the volume, H k is an anisotropic field. Low moments (i.e. low M s ) Half-Heusler compounds are k The increase in M s Therefore, a lower switching current is required as long as it does not overwhelm the

[0021] Therefore, for MRAM applications, it is preferred that all magnetic elements have moments perpendicular to the layer itself (i.e. magnetization perpendicular to the film plane - PMA occurring in the crystal structure). Low magnetization and low switching currents are preferred. We have found that one way to achieve PMA is through the use of half-Heusler compounds. Normally half-Heusler compounds tend to be cubic. Thus, the thin film is grown and the magnetic moments are in the plane of the layer. For MTJs for MRAM applications, it is highly preferred that the magnetic moments of the magnetic layers are perpendicular to the layer. The way to induce PMA from half-Heusler layers is to modify the compound from cubic to tetragonal. Instead of having all three unit cell axes be the same length, if one of the axes is a bit longer (or shorter), the magnetization can become perpendicular because the crystal symmetry is broken. It is worth noting that the parameter c' described elsewhere in this specification is appropriate because the unit cells of the half-Heusler materials described elsewhere in this specification in connection with Figures 4 and 5 are not simple crystals having only a single element (the simple relationship c=a for a cube does not apply to cells with multiple elements). In the tetragonal case, one of the axes is longer (or shorter) than in the cubic case.

[0022] Figure 1 shows the cubic half-Heusler compound and its in-plane lattice constant a cub 3 shows an embodiment of a PMA-based half-Heusler film. Bulk PMA is preferred because surface (interface) PMA is difficult to scale to small cells; our calculations show that bulk PMA can advantageously be scaled to smaller sizes. As explained elsewhere herein, in the tetragonal case, the Z (vertical) axis is "stretched" compared to the cubic case (alternative approaches could shrink it). Due to the bulk concentration, the magnetization tends to be perpendicular to the film (i.e., along the z-axis). If a half-Heusler layer is grown with the z-axis perpendicular to the (xy) plane with the appropriate template layer, it will have a moment perpendicular to the (xy) plane of the film.

[0023] Half-metallic (HM) magnetic materials have a Fermi energy E FSince the material has a band gap at , the DOS (spin 1,E F ) = 0, whereas the normal metallic DOS (spin 2,E F )>0 (DOS=density of states). Theoretically, such materials would provide infinite TMR if used as electrodes in MRAM devices. Unfortunately, all known half-metallic half-Heusler compounds are cubic with zero volume anisotropy (by symmetry); hence, they are not suitable for practical STT-MRAM devices. Using an appropriate template layer, half-Heusler compounds can be deformed in the in-plane direction, which can induce tetragonality in the half-Heusler compounds. Tetragonality implies the presence of PMA, suggesting suitability for use in vertical MTJs. It would be highly favorable if the half-metallicity of half-Heusler compounds could be made robust against in-plane deformation, as such vertical MTJs could have high TMR.

[0024] Also, all materials have up and down spins associated with semi-metallicity. If there is a band gap in one of the spin channels, only electrons of one spin will move when a current flows at the Fermi level. Semi-metals are very useful for achieving high TMR. One or more embodiments make the cubic compound tetragonal by epitaxy. The material is deposited on a template layer (in a non-limiting example, a chemical template layer) that forces the in-plane lattice constant to be different from the out-of-plane lattice constant. This results in tetragonality. One or more embodiments ensure that the semi-metallicity (i.e., having a band gap in one of the spin channels) is still maintained. It has been found that there are many half-Heusler compounds that are semi-metallic. There are about 3,000 half-Heusler compounds. Of these, 150 are semi-metallic. Only a few of these can be made tetragonal while still maintaining the semi-metallic properties, such that they have perpendicular magnetic anisotropy, i.e., the magnetization is perpendicular to the film. Of these, a few are advantageously used in MRAM and are likely to have high TMR.

[0025] A suitable aspect of one or more embodiments is the variation of the in-plane lattice constant of known semi-metallic cubic half-Heusler compounds by using a different template layer, such that such half-Heusler compounds become tetragonal with non-zero volume anisotropy. The template layer can be, for example, a non-magnetic binary compound (e.g., CoAl with in-plane lattice constant a=4.03 Å) and the half-metallic magnetic half-Heusler compound can be, for example, a known ternary compound (e.g., a cub RhCrGe with a = 4.07 Å, cub NiMnSi with a = 3.86 Å, cub RhFeSn with a = 4.28 Å, or cub = 4.15 Å). The ternary compound is modified when epitaxially grown on the CoAl layer. If the change in the in-plane lattice constant is not large (e.g., within 5% from the equilibrium cubic lattice constant), calculations indicate that the half-metallicity may remain intact for at least some half-Heusler compounds. Therefore, DFT (density-functional theory) calculations were used to determine tetragonal half-Heusler compounds that are still semimetallic with non-zero volume anisotropy. In this context, the half-metallic half-Heusler compounds themselves are also well known. However, all the half-metallic half-Heusler compounds known so far have shown a cubic crystal lattice structure and have not shown PMA. The inventors have found that half-metallic half-Heusler compounds with a tetragonal crystal lattice structure can obtain PMA by growth on a template layer. The inventors have found that growth on a template layer "squeezes" or "stretches" the lattice constant in one direction to obtain the desired tetragonal crystal lattice structure (e.g., "stretches" in z while "squeezing" in x and y) while maintaining semimetallic properties. High TMR is predicted for such compounds based on calculations with the template layer used as a base for epitaxial growth.

[0026] One or more embodiments favor tetragonal semimetallic half-Heusler compounds with non-zero anisotropy by using an underlayer (e.g., CoAl) with a different in-plane lattice constant (compared to the cubic geometry) to obtain a volume anisotropy that is opposite to the interface anisotropy. One or more embodiments use a half-Heusler semimetallic compound. In one or more embodiments, the half-Heusler semimetallic compound can be, for example, a nonmagnetic metal (e.g., CoAl) or a magnetic metal (e.g., cubic CoAl, which is also a half-metallic Heusler). 2 In one embodiment, the tetragonal half-metallic half-Heusler is grown on a common substrate, which may be a semiconductor barrier (e.g., MgO), and thus the tetragonal half-metallic half-Heusler becomes the bottom electrode of the MRAM cell. In another embodiment, the half-Heusler half-metallic compound is grown on a semiconductor barrier (e.g., MgO), and thus the tetragonal half-metallic half-Heusler becomes the top electrode of the MRAM cell.

[0027] See Figures 3a, 3b and 3c. The parameter a_cub is the in-plane cubic lattice constant (here a cub If this a_cub value can be altered, for example, to + / - 0.3 Å or + / - 10%, and the compound still maintains its semi-metallicity, then the compound is considered to exhibit strong semi-metallicity and can be grown with a template layer to achieve tetragonal crystallinity without losing its semi-metallicity.

[0028] It is noteworthy that semimetals are materials that act as conductors for electrons of one spin orientation, but as insulators or semiconductors for electrons of the opposite orientation. Known semimetals are ferromagnetic (or ferrimagnetic). In semimetals, the valence band for one spin orientation is partially filled, while there is a gap in the density of states for the other spin orientation. This results in conductive behavior only for electrons of the first spin orientation. In some semimetals, the majority of the spin channels are conductive, while in other semimetals, only a minority of the channels are conductive.

[0029] The inventors have determined that the in-plane lattice constant a corresponds to the lattice constant a cubWe identified 19 semimetallic half-Heuslers with PMA that maintain their semimetallicity when changed within 0.50 Å (or 5%) of the vicinity. cub It has extremely stable semi-metallic properties that are not easily destroyed by changes in lattice constant of less than 10%.

[0030] Referring again to FIG. 1, aspects of the chemical template layer will now be considered. 2 A half-Heusler compound XYZ, such as As, contains alternating layers of Mn-Mn and Mn-As atoms. In FIG. 1, atoms with shading 101 indicate As atoms (main group), atoms with shading 103 indicate Mn atoms at Y-positions of XYZ (tetrahedrally coordinated by Z), and atoms with shading 105 indicate element Mn atoms at X-positions of XYZ (octahedrally coordinated by Z). As is a transition metal and Ge is a main group of the periodic table. One of the alternating layers contains only transition metal atoms 103, and the other layer contains main group element atoms 101 along with transition metal atoms 105. Thus, a seed layer containing a single element that is lattice matched to the in-plane lattice constant does not promote the growth of aligned half-Heusler compounds at low temperatures, such as room temperature. An ideal seed layer contains a binary compound of a transition element and a main group element. This ideal seed layer also has an alternating layer structure containing these two elements. One layer contains only the transition metal. Other layers contain only main group metals (the "Z" in XYZ is also a main group metal). This binary compound has a CsCl-like (cesium chloride-like) structure (where each cesium ion is coordinated by eight chloride ions). Exemplary template layers include CoAl, CoGa, etc.

[0031] Referring now to FIG. 2, one or more embodiments use a CsCl-type chemical template layer (CTL) 401 (CoAl is an example of a good CsCl-type CTL) to promote the growth of aligned Heusler compounds at ultra-thin thicknesses and even at room temperature. "E" corresponds to Al, for example, and "A" corresponds to Co, for example. In FIG. 2, view 421 is a schematic diagram and view 423 is a transmission electron microscopy (TEM) image. In the example of FIG. 2, Mn 3A full-Heusler compound such as Sb403 is epitaxially grown on top of a CoAl layer 401; however, this example is equally valid for half-Heusler materials (as previously described, with one layer containing transition metal atoms and the other layer having an alternating layer structure with transition metal and main group atoms). The in-plane lattice constant of ultra-thin (<~25 Å) full-Heusler compounds is similar to the CoAl CTL. The full-Heusler (or half-Heusler) can be deformed to different degrees by choosing the appropriate CTL. It has been found that ternary full-Heusler or half-Heusler compounds can also be aligned with a CTL. As shown, Mn (generally X) is grown on Al and Ge (generally Z) is grown on Co. Note the atomic step 405. The full-Heusler (or half-Heusler) material can be deformed so that it adopts the in-plane lattice constant of the template material. One or more implementations impose the lattice constant of the template layer on the Heusler (or half-Heusler) layer. Note that in view 423, the CoAl(401) includes an Al layer 409 and a Co layer 411, and the MnSb includes an MnMn layer 413 and an MnSb layer 415. Note the MgO tunnel barrier 407.

[0032] We investigated 150 cubic half-Heusler compounds that are claimed in the literature to be (theoretically) half-metallic (HM). Using DFT / GGA (Generalized Gradient Approximation) and DFT / LDA (Local Density Approximation) methods for calculations accordingly, we found that some of these compounds are indeed HM, some are not HM but have large spin polarization, and some are not HM but have relatively small spin polarization. In particular, among the 150 compounds studied, we focused on 58 compounds with spin polarization = 100% (true semimetal), 51 compounds that are ferromagnetic, 25 compounds that exhibit PMA, and 19 compounds that remain half-metallic, as shown in Figures 3a, 3b, and 3c, where the in-plane lattice constant a is the same as the corresponding cubic lattice constant a cub The compound is changed by 0.50 Å near the cubThey have a very stable half-metallicity that is difficult to destroy by lattice parameter changes of less than 4% (in each direction) near the nucleus. The first column in Figures 3a, 3b and 3c lists related half-metallic Heusler compounds. All compounds shown in Figure 3 are ferromagnetic except for seven ferrimagnetic compounds (CoCrGe, CoMnGe, MnMnAs, FeCrAs, RuCrAs, CoCrAs and MnVAs). The second column lists

[0033]

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[0034]

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[0035] The inventors a cub We identified 56 compounds that maintain semimetallicity when a changes by 0.30 Å in the vicinity (all these compounds are highlighted in column 8 of Figures 3a-3c). cub They have a very stable semi-metallic nature that is not easily destroyed by lattice constant changes (in each direction) of less than 10% in the vicinity. According to the inventors' calculations, the most promising candidates for electrodes in MRAM devices are NaCsP, LiCaGe, LiSrGe, NaCaGe, KCaGe, RbTaGe, KCrTe, NaCaSn, KTaSn, KCaSn, RbNbSi, RbTaSi, NaCsAs, CsRbAs, CsBaC, CsSrC, CsRbN, RhFeGe, RhCrGe, CoCrGe, RhFeSn, NiVSn, RuCrAs, CoCrAs, and CsSrSn, which have the optimal in-plane lattice constant and anisotropy constant K v >0.19MJ / m 3The chemical ordering of RhFeGe, RhCrGe, CoCrGe, RhFeSn, NiVSn, RuCrAs, and CoCrAs containing transition and main group elements by the chemical templating layer is shown in FIG. 2. The other listed compounds contain other metal atoms or in some cases two metal atoms in place of the transition metal atom along with the main group element atom. The chemical templating layer must also promote chemical ordering in such compound sets.

[0036] K v It will be understood that it is appropriate for the value to be greater than 0, and the higher the value, the better. Therefore, the table shows that the value is ≥ 0.19 MJ / m 3 For all K v The values ​​are highlighted. In one or more embodiments, the spin polarization SP=1.

[0037] Reference is now made to Figures 4 and 5. Figure 4 shows an example of a ferromagnetic half-metallic half-Heusler, RhFeSn.

[0038] In Figure 4, note the vacancy (601), Fe (602), Sn (604) and Rh (605). Figure 5 shows an example of a ferromagnetic half-metallic half-Heusler, CoCrAs. In Figure 5, note the vacancy (601), Cr (612), As (613) and Co (611). In Figures 4 and 5, the arrows indicate the magnetic moments for the individual atoms. The tetragonal unit cell shown in Figures 4 and 5 is rotated 45° about the z-axis with respect to the parent cubic structure shown in Figure 1. (Note that only a portion of the atoms in Figure 1 are shown in Figures 4 and 5.) The lattice constant a of the cubic half-Heusler material is cub is shown in Figure 1, and the lattice constants a and c of the tetragonal half-Heusler material are shown in Figure 4. For a cubic structure, the in-plane lattice constants a shown in Figure 4 and a shown in Figure 1 cub The relationship between

[0039]

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[0040]

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[0041] As mentioned above, the tetragonal case can be produced by growth on a suitable template layer. To review, the template concept involves growing a template layer and then growing another layer (e.g., a Heusler or half-Heusler compound) on top of it. Template essentially means that the layer grown on the template layer will grow to the lattice constant, a, of the underlayer / seed layer. Similar to Poisson's ratio, changing a also changes c; decreasing a increases c (and vice versa). The lattice constant, a, of the semi-metallic half-Heusler layer is proportional to the lattice constant, a, of the template layer (a TL ), the template layer is rotated by 45° to accommodate the lattice match of the half-metallic half-Heusler layer. TL 'Sqrt(2)*a TLLet us define a half-Heusler of CoCrAs, grown on a CoAl template layer. c decreases as a decreases from 3.57 Å for the cubic shape to 4.04 Å for the tetragonal morphology. The material tries to maintain the unit cell volume. Referring again to FIG. 2, CoAl is a layered structure. In the Heusler compound 403 (also representing a half-Heusler), all the Mn layers contain only transition metals and therefore prefer to grow on the Al of the template layer, but also have main group elements and therefore prefer to grow on Co, thus obtaining ordering in the material 403. Atomic steps 405 are intrinsic to the template layer 401 but do not disturb the ordering of the Heusler material 403 (also representing a half-Heusler).

[0042] FIG. 8 shows a half-metallic half-Heusler compound having an optimal in-plane lattice constant for high PMA according to an embodiment of the present invention. v ≧0.19MJ / m 3 It should be noted that FIG. 8 reproduces portions of FIG. 3a-FIG. 3c for a selected list of compounds having the K v =0.19MJ / m 3 Instead of K v =0.2MJ / m 3 It should be noted that this includes CoCrGe, which is w hm For all such compounds, except for RhFeGe, where E = 0.20 Å, g >0.4eV and w hm ≧0.34 Å. Thus, these compounds have strong semimetallic character.

[0043] Figure 9 shows candidate CTL materials. The in-plane lattice constants a for several CTL materials are shown in Fig. 9. TL can be adjusted over a wide range of values. TLThe " value can be further adjusted by modification of the deformation ratio induced in the underlying seed layer and / or composition at the nominal 1:1 value. In one or more embodiments, different lattice constants can be "mixed and matched." For example, in connection with "mixing and matching," the lattice constant of CoAl is 2.86 Å and the lattice constant of RuAl is 2.95 Å. In principle, when a half-Heusler compound is grown on RuAl, it will stretch differently than if it were grown on CoAl because the half-Heusler compound will attempt to conform to the RuAl lattice constant. That is, the degree of tetragonal stretching will vary depending on what substrate the tetragonal half-Heusler material is grown on.

[0044] FIG. 10 illustrates an embodiment having a half-metallic half-Heusler compound as the preservation layer 1205 .

[0045] Seed layer 1203 typically includes a CTL and is located on substrate 1201. Substrate 1201 is typically silicon with CMOS circuitry such as transistors and access lines that allow for individual device selection. In addition to the novel cells described herein, conventional transistors, access lines, peripheral circuitry, etc. can be used (see description of FIG. 12 below). The CTL or even multi-layer CTL can be grown on a suitable surface, such as a seed layer deposited directly on or, more commonly, on the substrate, if possible. Non-limiting examples of seed layers include tantalum, tantalum-ruthenium, chromium, manganese, manganese nitride, etc. A semi-metallic half-Heusler layer 1205 is located on the CTL and can be formed, for example, by epitaxial growth on the CTL. A polarization enhancing layer 1207 is optionally located on the outside of layer 1205; if present, layer 1207 can include a thin layer of a magnetic material, such as cobalt. A tunnel barrier 1209 is located outside layer 1207 (if present) and otherwise outside layer 1205; the barrier 1209 may be, for example, MgO, MgAl 2 O 4etc. The magnetic layer 1211 may include conventional cobalt, iron, nickel or alloys, or may include Heusler or half-Heusler materials. If present, a synthetic antiferromagnet (SAF) layer 1213 is located outside layer 1211. Typically, the synthetic antiferromagnet (SAF) layer includes a Co / Pt multilayer (not shown) magnetically coupled to a base magnetic layer to achieve the required performance. A thin layer (not shown) of Ta or Ir or Ru (on the order of a few angstroms) may typically be interposed between the magnetic layer and the SAF layer. A cap layer 1215 is located outside layer 1213 (if present) or, if not, outside layer 1211. The cap layer may include Mo, W, Ta, Pt, Ru, or combinations thereof. In FIG. 10, double arrow 1221 indicates a storage layer whose magnetization can be changed, and single arrow 1223 indicates a reference layer whose magnetization is constant / fixed.

[0046] FIG. 11 shows an embodiment using a half-metallic half-Heusler compound as the reference layer.

[0047] A seed layer 1303 typically comprises a CTL and is located on the substrate 1301. A half-metallic half-Heusler layer 1205 is located on the CTL and can be formed, for example, by epitaxial growth on the CTL. A polarization enhancing layer 1307 is optionally located on the outside of layer 1305. A tunnel barrier 1309 is located on the outside of layer 1307 (if present) and otherwise on the outside of layer 1305. A magnetic layer 1311 may comprise conventional cobalt, iron, nickel or alloys and may also comprise Heusler or half-Heusler materials. A cap layer 1313 is located on the outside of layer 1311. In FIG. 11, double arrow 1323 indicates a storage layer whose magnetization can be changed and single arrow 1321 indicates a reference layer whose magnetization is constant / fixed. The material discussion of FIG. 10 is generally applicable to FIG. 11.

[0048] In both Figures 10 and 11, the Heusler layer is typically located on top of the template layer by epitaxial growth during fabrication.

[0049] Thus, we identified 45 half-metallic half-Heusler compounds with PMA that maintain their half-metallicity even when subjected to substantial in-plane lattice distortions of approximately 10% (the distortions are a cub (The nuclei vary by 0.50 Å around the nucleus.) These compounds are KCrTe, NaCsP, NaCsAs, CsRbAs, CsRbN, NaKP, CsRbP, KCaGe, RbCrTe, CsBaC, LiSrGe, RbSrGe, KCaSn, KCaSi, NaVSi, RbSrSi, RbSrB, NaCaGe, KSrB, KTaSn, RbTaGe, CsSrSn, and CsVS. , RbSrC, CsSrC, RbTaSi, KBaB, CoVSb, RbNbSn, RbNbSi, KMgGe, MnMnAs, RbCaB, CsSrGe, CoCrAs, LiBaGe, CoCrSb, NaCaSn, CoCrGe, RhVAs, CsNbSn, CsNbSi, CsNbGe, NiMnSi, and RhCrGe. These compounds have a very stable semi-metallic character that is not easily destroyed by changes in the lattice constant (in either direction). Experimentally, such transformations can be achieved by epitaxial growth of such compounds on CTLs such as CoAl.

[0050] According to the inventors' calculations, the most promising candidates for the electrodes of MRAM devices are KCrTe, NaCsP, NaCsAs, CsRbAs, KCaGe, CsBaC, LiSrGe, KCaSn, NaCaGe, KTaSn, RbTaGe, CsSrC, RbTaSi, RbNbSi, CoCrAs, NaCaSn, RhCrGe, LiCaGe, RhFeSn, NiVSn, CsRbN, RhFeGe, CoCrGe, RuCrAs, and CsSrSn, which have the optimal in-plane lattice constant and anisotropy constant K v >=0.19MJ / m 3 Of these 25 compounds, 23 are ferromagnetic. Of these 25 compounds, 21 have stable half-metallic properties that are not easily destroyed by changes in the lattice constant (the deformation rate is a cub (The lattice constant can vary up to 0.50 Å around the Mn 3 Ge(m=1.0μ B / form_unit, where form_unit stands for "formula unit"), with a low moment (m=1.0μ B / form_unit).

[0051] Thus, one or more embodiments include a device, again including a multi-layer structure (e.g., FIGS. 10 and 11). The multi-layer structure includes a first layer that is non-magnetic at room temperature, including a binary alloy having a CsCl structure with a target in-plane lattice constant (e.g., CTL of 1203, 1303). Also included is a second layer 1205, 1305 having a half-metallic half-Heusler compound with magnetization substantially perpendicular to the layer. As will be appreciated by those skilled in the art, typically the magnetization is not fixed, rather the magnetization precesses like a top at non-zero temperatures. This may vary with temperature. In terms of such precession, squareness as used herein refers to the squareness of the time integral / average of the magnetization path. The time integral / average of the magnetization path may be, for example, "exactly" perpendicular, perpendicular to within = / -5% or perpendicular to within + / -10%.

[0052] In some such cases, the half-metallic half-Heusler compound is selected from the group consisting of RhCrGe, RhFeSn, CoCrGe, NiVSn, CoCrAs, RhFeGe, or RuCrAs; in some such cases, the half-metallic half-Heusler layer has a thickness, for example, of less than 5 nm. In some such cases, the binary alloy template layer or chemical template layer is A 1-x E xwhere A is a transition metal element and E is a main group element. For example, A can include Co, E can include at least aluminum or gallium, and possibly trace amounts of other elements (e.g., Al or Ga; or alloys of Al with Ga, Ge, Sn, or any combination thereof, e.g., AlSn, AlGe, AlGaGe, AlGaSn, AlGeSn, and AlGaGeSn), and x can range from 0.42 to 0.55. In some such cases, the tunnel barrier 1209, 1309 is located in contact with the semi-metallic half-Heusler layer; the tunnel barrier can include, for example, MgO (magnesium aluminum oxide is Mg 1-z Al 2+(2 / 3)z O 4 Magnesium aluminum oxide having the form of a suitable alternative to MgO, where -0.5 <z<0.5である)。

[0053] In one or more embodiments, the half-metallic half-Heusler compound is selected from the group consisting of KCrTe, NaCsP, NaCsAs, CsRbAs, KCaGe, CsBaC, LiSrGe, KCaSn, NaCaGe, KTaSn, RbTaGe, CsSrC, RbTaSi, RbNbSi, CoCrAs, NaCaSn, RhCrGe, LiCaGe, RhFeSn, NiVSn, CsRbN, RhFeGe, CoCrGe, RuCrAs, and CsSrSn; the half-metallic half-Heusler layer has a thickness, for example, of less than 5 nm; and in some such cases, the binary alloy template layer or chemical template layer is A. 1-x E x where A is a transition metal element and E is a main group element. For example, A includes Co, E includes at least aluminum or gallium, and possibly trace amounts of other elements, and x is in the range of 0.42 to 0.55 as discussed above. In some such cases, the tunnel barrier 1209, 1309 is located in contact with the half-metallic half-Heusler layer; the tunnel barrier may include, for example, MgO (magnesium aluminum oxide is a suitable alternative to MgO).

[0054] It should be noted that semi-metallic half-Heusler compounds are represented by stoichiometric formulas, which do not exclude small variations of up to a few percent from the nominal value. The template layer can include any of the materials listed in FIG. 9, but is not limited to these materials.

[0055] Referring now to Figure 12, there is shown an array of MRAM devices 1202. Each cell 1202 (e.g., the embodiment of Figure 10 or Figure 11) is coupled to a respective transistor 1204 that controls reading and writing. Word lines 1206 provide data for writing to the cells 1202, and bit lines 1210 and bit line complements 1208 read data from the cells 1202. In this manner, large arrays of memory elements can be implemented on a single chip. Any number of cells 1202 can be used within the limitations of the manufacturing process and design specifications.

[0056] Recording data in cell 1202 involves passing a current through the cell. This current has the effect of switching the magnetization between parallel and anti-parallel states, switching between low and high resistance. This effect can be used to represent digital ones and zeros, so cell 1202 can be used as a non-volatile memory. Passing a current in one direction through cell 1202 causes the magnetization of the free layers 1205, 1311 to be parallel to the magnetization of the reference layers 1211, 1305, while passing a current in the other direction through cell 1202 causes the magnetization of the free layers 1205, 1311 to be anti-parallel to the reference layers 1211, 1305. Reading the bit stored in cell 1202 involves applying a voltage (lower than that used to record information) to cell 1202 to discover whether the cell offers a high resistance ("1") or a low resistance ("0") to the current.

[0057] The fabrication of semiconductor devices includes various stages of a device patterning process. For example, the fabrication of a semiconductor chip may begin with, for example, a number of computer aided design (CAD) generated device patterns, followed by efforts to replicate such device patterns onto a substrate. The replication process may include the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing processes. For example, in a photolithography process, a layer of photoresist material may first be applied on top of a substrate and then selectively exposed with a predetermined device pattern or patterns. Portions of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beam, x-rays, etc.) may undergo a slight change in solubility in certain solutions. The photoresist may then be developed in a developer to remove the unirradiated (in negative resist) or irradiated (in positive resist) portions of the resist layer to generate a photoresist pattern or photomask. The photoresist pattern or photomask may then be copied or transferred to the substrate beneath the photoresist pattern.

[0058] There are numerous techniques used by those skilled in the art to remove material at various stages in creating semiconductor structures. These processes are collectively referred to herein as "etching." For example, etching includes the techniques of wet etching, dry etching, chemical oxide removal (COR) etching, ion milling, and reactive ion etching (RIE), all of which are known techniques for removing selected materials when forming semiconductor structures. Standard Cleaning Solution 1 (SC1) contains a strong base, typically ammonium hydroxide and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. Because the techniques and applications of etching are well understood by those skilled in the art, a more detailed description of such processes is not provided herein.

[0059] Although the overall fabrication method, including the epitaxial growth of the semi-metallic half-Heusler material on the template layer and the structures formed thereby, are novel, certain individual processing steps required to embody the method may utilize conventional semiconductor manufacturing techniques and existing semiconductor manufacturing tooling. These techniques and tooling are already familiar to those skilled in the art of the relevant art taught herein. Additionally, one or more processing steps and tooling used to fabricate semiconductor devices are described in a number of readily available publications, including, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st. Edition, Prentice Hall, 2001 and PH Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, both of which are incorporated herein by reference. It is emphasized that while some individual processing steps are described herein, such steps are merely exemplary and one of ordinary skill in the art may be familiar with several equally suitable alternatives that may be applicable.

[0060] It should be understood that the various layers and / or regions illustrated in the accompanying figures may not be drawn to scale, and one or more semiconductor layers of the type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of illustration, and this does not imply that the semiconductor layers not explicitly shown are omitted in the actual integrated circuit device.

[0061] In light of the preceding discussion, it will be appreciated that a typical exemplary magnetoresistive random access memory cell includes a template layer (e.g., part of 1203 or 1303) that includes a binary alloy (e.g., 401) having an alternating layer lattice structure. Also included is a half-metallic half-Heusler layer 1205, 1305 that includes a half-metallic half-Heusler material (e.g., 403) having a tetragonal lattice structure. The half-metallic half-Heusler layer is located outside the template layer and has a half-Heusler in-plane lattice constant that is different from the in-plane lattice constant of the cube shape of the half-metallic half-Heusler material. See the description of Figures 4 and 5. The cell further includes a tunnel barrier 1209, 1309 outside the half-metallic half-Heusler layer and a magnetic layer 1211, 1311 outside the tunnel barrier. The magnetic layer can be, for example, a conventional material or a Heusler or half-Heusler material.

[0062] 10, in some cases, the half-metallic half-Heusler layer 1205 includes a retention layer and the magnetic layer 1211 includes a reference layer, while, referring specifically to FIG 11, in some cases, the half-metallic half-Heusler layer 1305 includes a reference layer and the magnetic layer 1311 includes a retention layer.

[0063] The half-metallic half-Heusler compound may be selected from the group consisting of KCrTe, NaCsP, NaCsAs, CsRbAs, KCaGe, CsBaC, LiSrGe, KCaSn, NaCaGe, KTaSn, RbTaGe, CsSrC, RbTaSi, RbNbSi, CoCrAs, NaCaSn, RhCrGe, LiCaGe, RhFeSn, NiVSn, CsRbN, RhFeGe, CoCrGe, RuCrAs, and CsSrSn. In some cases, the thickness of the half-metallic half-Heusler layer is less than 5 nm. An example material stack of Figure 10 can be Si substrate / 50 Å Ta / 3 Å Co20Fe60B20 / 200 Å Mn3N / 300 Å CoAl / 14 Å RhFeGe / 12 Å MgO / 11 Å Co20Fe60B20 / 3 Å Ta / [2.5 Å Co / 5 Å Pt]2 / 5 Å Co / 9 Å Ru / 5 Å Co / 5 Å Pt / [2.5 Å Co / 5 Å Pt]4 / 5 Å Pt / 100 Å Ru. An example material stack of Figure 11 can be Si substrate / 50 Å Ta / 3 Å Co20Fe60B20 / 200 Å Mn3N / 300 Å CoAl / 25 Å Mn2FeSb / 12 Å MgO / 11 Å Co20Fe60B20 / 100 Å Ru.

[0064] In some cases, the half-metallic half-Heusler compound is selected from the group consisting of RhCrGe, RhFeSn, CoCrGe, NiVSn, CoCrAs, RhFeGe, or RuCrAs; again, in some cases, the half-metallic half-Heusler layer has a thickness of less than 5 nm.

[0065] In one or more embodiments, the tunnel barriers 1209, 1309 are selected from the group consisting of magnesium oxide and magnesium aluminum oxide.

[0066] In one or more embodiments, the binary alloy of the template layer is represented by the formula A 1-x E x where A is a transition metal element, E is a main group element including at least one of aluminum and gallium, and x is in the range of 0.42 to 0.55.

[0067] In some cases, the alternating layer lattice structure of the template layer includes a cesium chloride structure.

[0068] In some cases, the template layer is non-magnetic at room temperature (ie, 20° C.).

[0069] In one or more embodiments, the template layer has an in-plane lattice constant of the template layer, and the half-Heusler in-plane lattice constant substantially matches the in-plane lattice constant of the template layer. As used herein, the half-Heusler in-plane lattice constant "substantially matches" the in-plane lattice constant of the template layer when it matches the in-plane lattice constant of the template layer, or when the in-plane lattice constant of the tetragonal half-Heusler material moves from the in-plane lattice constant of the cubic half-Heusler material toward the in-plane lattice constant of the template material. In some cases, the half-Heusler in-plane lattice constant matches the in-plane lattice constant of the template layer within + / - 10%. In some cases, the Heusler in-plane lattice constant matches the in-plane lattice constant of the template layer within + / - 10%. The half-metallic half-Heusler material has a magnetization that is substantially perpendicular to the half-metallic half-Heusler layer, for example.

[0070] In another embodiment, referring to FIG. 12, a magnetoresistive random access memory array includes a plurality of bit lines 1210 and a plurality of complementary bit lines 1208 forming a plurality of bit line-complementary bit line pairs. A plurality of word lines 1206 intersect the plurality of bit line pairs at a plurality of cell locations. A plurality of magnetoresistive random access memory cells 1202 are located at each of the plurality of cell locations. Each magnetoresistive random access memory cell 1202 is electrically connected to a corresponding bit line 1210 and selectively interconnected to a corresponding one of the complementary bit lines 1208 under the control of a corresponding one of the word lines 1206 (e.g., each transistor 1204 is field effect turned off or on by a signal from the word line 1206 applied to its gate, which controls reading and writing, and controls whether the cell is coupled to the complementary bit line).

[0071] Each of the plurality of magnetoresistive random access memory cells includes a template layer including a binary alloy having an alternating layer lattice structure, a half-metallic half-Heusler layer including a half-metallic half-Heusler material having a tetragonal lattice structure, the half-metallic half-Heusler layer being located outside the template layer and having a half-Heusler in-plane lattice constant different from the in-plane lattice constant of the cube shape of the half-metallic half-Heusler material, a tunnel barrier outside the half-metallic half-Heusler layer, and a magnetic layer outside the tunnel barrier, all of which are described elsewhere herein. Typically, the capping layer (1215 or 1313) of the devices shown in Figures 10 and 11 is coupled to a bit line 1210, while the layer (1203 or 1303) is coupled to a bit line complement 1208 via an access FET.

[0072] In yet another aspect, an exemplary method of operation includes providing an array as described above, applying signals to word lines 1206 such that a first subset of cells 1202 stores a logic 1 and a second subset of cells 1202 stores a logic 0; and reading the stored logic 1s and 0s via bit lines 1210 and complementary bit lines 1208.

[0073] In yet another embodiment, referring to FIG. 13, an exemplary method of forming a magnetoresistive random access memory cell (such as FIG. 10 or 11) includes providing a template layer (e.g., 1203 or part of 1303, see layer 401 of FIG. 2) according to step 1301. The template layer includes a binary alloy having an alternating layer lattice structure and has an in-plane lattice constant of the template layer. An additional step 1303 includes epitaxially growing a half-metallic half-Heusler layer (e.g., 1205 or 1305, see layer 403 of FIG. 2) on the template layer. The half-metallic half-Heusler layer includes a half-metallic half-Heusler material. The half-metallic half-Heusler layer is grown on the template layer, the half-Heusler material having a tetragonal lattice structure and a half-Heusler in-plane lattice constant different from the in-plane lattice constant of the cubic shape of the half-metallic half-Heusler material. The half-Heusler in-plane lattice constant substantially matches the in-plane lattice constant of the template layer. Additional steps include forming 1307 a tunnel barrier (e.g., 1209 or 1309, see layer 407 in FIG. 2) outside the semi-metallic half-Heusler layer; and forming 1307 a magnetic layer 1211, 1311 outside the tunnel barrier. The method may also include providing and / or forming the other elements shown in FIGS. 10 and 11 using techniques apparent to those skilled in the art from the teachings herein. The cells may be assembled into an array by forming multiple cells at the same time and interconnecting them with wires, transistors and peripheral circuitry in a manner apparent to those skilled in the art from the teachings herein.

[0074] Those skilled in the art will recognize that the exemplary structures described above may be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), bare die, packaged form, or integrated as part of intermediate or final products that benefit from tetragonal semi-metallic half-Heusler compounds, such as in MRAM.

[0075] Integrated circuits according to aspects of the present invention may be used in essentially any application and / or electronic system in which tetragonal semi-metallic half-Heusler compounds are beneficial, such as MRAM, etc. Given the teachings of the present disclosure content provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the embodiments disclosed herein.

[0076] Some aspects of the present invention or elements thereof may be realized in the form of an apparatus including a memory and at least one processor coupled to the memory and operative to perform exemplary method steps. Figure 14 illustrates a computer system useful in implementing one or more aspects and / or elements of the present invention; referred to herein as a cloud computing node, but also representative of servers, general purpose computers, etc., which may be provided as a cloud or locally. It is noted that such a computer may / can control the design and / or manufacture of semiconductors or may use, for example, the memory cells / arrays described herein.

[0077] Cloud computing node 10 has computer system / server 12 operating in numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments and / or configurations suitable for use with computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0078] The computer system / server 12 may be described in the general context of computer system executable instructions, such as program modules, executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system / server 12 may be practiced in a distributed cloud computing environment where work is performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0079] 14, computer system / server 12 of cloud computing node 10 is shown in the form of a general-purpose computing device. Components of computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18 coupling various system components including system memory 28 to processor 16.

[0080] Bus 18 may represent one or more of several types of bus structures including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or local bus using a variety of bus architectures, including, by way of example and not limitation, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0081] Computer system / server 12 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by computer system / server 12 and includes all volatile and nonvolatile media, removable and non-removable media.

[0082] The system memory 28 may include computer system readable media in the form of volatile memory such as random access memory (RAM) 30 and / or cache memory 32. The computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may provide a non-removable, non-volatile magnetic medium (not shown, commonly referred to as a "hard drive") for reading and writing. Although not shown in the drawings, a magnetic disk drive may be provided for reading and writing a removable, non-volatile magnetic disk (e.g., a "floppy disk") and an optical disk drive may be provided for reading and writing a removable, non-volatile optical disk, e.g., a CD-ROM, DVD-ROM, or other optical media. In such a case, each may be coupled to the bus 18 by one or more data media interfaces. As further shown and described below, the memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of embodiments of the present invention.

[0083] A program / utility 40 having a set (at least one) of program modules 42 may be stored in memory 28, including, by way of example and not limitation, an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, may include implementing a networking environment. The program modules 42 generally perform the functions and / or methodologies of embodiments of the present invention as described herein.

[0084] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, a pointing device, a display 24; one or more devices that allow a user to interact with the computer system / server 12; and / or any device (e.g., a network card, a modem, etc.) that allows the computer system / server 12 to communicate with one or more other computing devices. Such communication may occur via an input / output (I / O) interface 22. Still, the computer system / server 12 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet), via a network adapter 20. As shown, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. Although not shown in the drawings, it should be understood that other hardware and / or software components may be used with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data archive storage systems, etc.

[0085] Thus, one or more embodiments may employ software executed on a general purpose computer or workstation (e.g., for designing and / or manufacturing semiconductors). With reference to FIG. 14, such implementations may employ, for example, an input / output interface 22 to a processor 16, memory 28, and display 24, and external devices 14, such as a keyboard, pointing device, and the like. As used herein, the term "processor" is intended to include any processing device, such as one that includes a CPU (Central Processing Unit) and / or other forms of processing circuitry. The term "processor" also refers to one or more individual processors. The term "memory" is intended to include memory associated with a processor or CPU, such as RAM (Random Access Memory) 30, ROM (Read Only Memory), fixed memory elements (e.g., hard drive 34), removable memory elements (e.g., diskettes), flash memory, and the like. As used herein, the phrase "input / output interface" is also intended to contemplate an interface to one or more mechanisms for inputting data into, for example, a processing unit (e.g., a mouse) and one or more mechanisms for providing results associated with a processing device (e.g., a printer). The processor 16, memory 28 and input / output interface 22 may be interconnected via a bus 18, for example as part of the data processing device 12. For example, suitable interconnections via the bus 18 may also be provided to a network interface 20, such as a network card, which may be provided for interfacing with a computer network, and a media interface, such as a diskette or CD-ROM drive, which may be provided for interfacing with suitable media.

[0086] Thus, computer software containing instructions or code for carrying out the methodologies of the present invention as described herein can be stored in one or more of the associated memory elements (e.g., ROM, fixed or removable memory) and, when ready for use, loaded in part or in whole (e.g., RAM) and executed by the CPU. Such software can include, but is not limited to, firmware, resident software, microcode, etc.

[0087] A data processing system suitable for storing and / or executing program code includes at least one processor 16 coupled directly or indirectly to memory elements 28 via a system bus 18. The memory elements may include local memory used during the actual implementation of the program code, bulk storage, and a cache memory 32 that provides temporary storage of at least some of the program code to reduce the number of times the code must be retrieved from bulk storage during implementation.

[0088] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I / O controllers.

[0089] Network adapter 20 may also be coupled to the system to enable the data processing system to be coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems and Ethernet cards are just a few of the currently available types of network adapters.

[0090] As used herein, including in the claims, a "server" includes a physical data processing system that executes a server program (e.g., system 12 shown in FIG. 14). It should be understood that such a physical server may or may not include a display and keyboard.

[0091] Any of the methods described herein may include the additional step of providing a system including individual software modules implemented in a computer readable storage medium; the modules may include some or all of the appropriate elements shown in FIG. 15, for example. The method steps may then be performed using the individual software modules and / or sub-modules of the system as described herein executed on one or more hardware processors, such as 16. A computer program product may also include a computer readable storage medium having code adapted to be implemented to perform one or more method steps described herein, including providing a system having individual software modules. In one or more embodiments, the computer readable storage medium embodying the code and / or design structure is non-transitory.

[0092] One example of a user interface that may be used in some cases is hypertext markup language (HTML) code that is provided by a server or the like to a browser on a user's computing device. The HTML is parsed by the browser on the user's computing device to generate a graphical user interface (GUI).

[0093] An exemplary design process used in semiconductor design, manufacturing and / or testing One or more embodiments employ computer-aided semiconductor integrated circuit design simulation, testing, layout, and / or fabrication. In this regard, FIG. 15 illustrates a block diagram of an exemplary design flow 700 for use in, for example, semiconductor IC logic design, simulation, testing, layout, and fabrication. The design flow 700 includes processes, machines, and / or mechanisms for processing a design structure or device to generate a logically or functionally equivalent representation of the design structure and / or device that can be analyzed using techniques disclosed herein and elsewhere. The design structure processed and / or generated by the design flow 700 can be encoded on a machine-readable storage medium to include data and / or instructions that, when executed or processed on a data processing system, generate a logically, structurally, mechanically, or functionally equivalent representation of a hardware component, circuit, device, or system. Machines include, but are not limited to, any machine used in IC design processes, such as designing, fabricating, or simulating a circuit, component, device, or system. For example, the machines may include: lithography machines, machines and / or equipment for generating masks (e.g., e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or testing process or machines for programming a functionally equivalent representation of a design structure into a medium (e.g., a machine for programming a programmable gate array).

[0094] Design flow 700 may vary depending on the type of representation being designed. For example, a design flow 700 for building an application specific integrated circuit (ASIC) may differ from a design flow 700 for designing a standard component or for instantiating a design into a programmable array, such as a programmable gate array (PGA) or field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

[0095] FIG. 15 illustrates a number of such design structures, including an input design structure 720, which is preferably processed by the design process 710. The design structure 720 may be a logical simulation design structure that is generated and processed by the design process 710 to generate a logically equivalent functional representation of a hardware device. The design structure 720 may additionally or alternatively include data and / or program instructions that, when processed by the design process 710, generate a functional representation of the physical structure of the hardware device. Whether representing functional and / or structural design features, the design structure 720 may be generated using electronic computer-aided design (ECAD), as implemented by a core developer / designer. When encoded, such as in a gate array or storage medium, the design structure 720 may be accessed and processed by one or more hardware and / or software modules in the design process 710 to simulate or functionally represent an electronic component, circuit, electronic or logic module, device, apparatus or system. Thus, design structure 720 may include files or other data structures containing human and / or machine readable source code, compiled structures, and computer executable code structures that, when processed by a design or simulation data processing system, functionally simulate or otherwise represent the design of a circuit or other level of hardware logic. Such data structures may include Hardware Description Language (HDL) design entities or other data structures conforming to and / or compatible with lower level HDL design languages ​​such as Verilog and VHDL and / or higher level design languages ​​such as C or C++.

[0096] Design process 710 preferably uses and incorporates hardware and / or software modules to synthesize, transform or otherwise process design / simulation functional equivalents of components, circuits, devices or logic structures to generate netlist 780, which may include design structures such as design structure 720. Netlist 780 may include, for example, a compiled or processed data structure representing a list of wires, individual components, logic gates, control circuits, I / O devices, models, etc., describing connections to other elements and circuits in an integrated circuit design. Netlist 780 may be synthesized using an iterative process in which netlist 780 is resynthesized one or more times according to device design specifications and parameters. As with the other design structure types described herein, netlist 780 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash or other flash memory. Additionally or alternatively, the medium may be a system or cache memory, a buffer area or other suitable memory.

[0097] The design process 710 may include hardware and software modules for processing a variety of input data structure types, including netlist 780. Such data structure types may include, for example, a set of commonly used elements, circuits, and devices, including models, layouts, and code representations for a given manufacturing technology (e.g., various technology nodes, 32 nm, 45 nm, 90 nm, etc.), residing in library elements 730. The data structure types may further include design specifications 740, characterization data 750, verification data 760, design rules 770, test data files 785, which may include input test patterns, output test results, and other test information. The design process 710 may further include standard mechanical design processes, such as stress analysis, thermal analysis, machine event simulation, process simulation for operations such as casting, molding, and die pressing. Those skilled in the art of mechanical design may understand the extent of mechanical design tools and applications used in the design process 710 without departing from the scope and spirit of the present invention. Design process 710 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule verification, place-and-route operations, and the like.

[0098] The design process 710 employs and incorporates logic and physical design tools, such as HDL compilers and simulation model building tools, to process the design structure 720 together with some or all of the illustrated supporting data structures along with any additional mechanical designs or data (if applicable) to create a second design structure 790. The design structure 790 resides on a storage medium or programmable gate array in a data format used for data exchange of mechanical devices and structures (e.g., information stored in IGES, DXF, Parasolid XT, JT, DRG or other format suitable for storing or rendering such mechanical design structures). Like the design structure 720, the design structure 790 preferably includes one or more files, data structures, or other computer-encoded data or instructions that reside on a data storage medium and that, when processed by an ECAD system, generate a logically or otherwise functionally equivalent form, such as one or more IC designs. In one embodiment, the design structure 790 includes a compiled, executable HDL simulation model that functionally simulates the device being analyzed.

[0099] The design structure 790 may also employ data formats used to exchange integrated circuit layout data and / or symbolic data formats (e.g., information stored in GDSII (GDS2), GL1, OASIS, map files, or other suitable formats for storing such design data structures). The design structure 790 may include, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, metal levels, vias, shapes, routing data through a manufacturing line, and any other data required by a manufacturer or other designer / developer to manufacture a device or structure as described herein (e.g., .lib files). The design structure 790 may then proceed to stage 795, where, for example, the design structure 790 may proceed to tape-out, released for manufacturing, released to a mask house, sent to another design house, or sent back to the customer.

[0100] The illustrations of the embodiments described herein are intended to provide a general understanding of various embodiments, and are not intended to provide a complete description of all elements and features of devices and systems that can use the circuits and techniques described herein. Many other embodiments will be apparent to those skilled in the art from the teachings herein; other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of the present disclosure. It should also be noted that in some alternative embodiments, some of the steps of the exemplary method may occur out of the order shown in the figures. For example, two steps shown in succession may in fact be performed substantially simultaneously, or certain steps may be performed in the reverse order depending on the functionality involved. The figures are merely representational and are not drawn to scale. Thus, the specification and drawings should be considered as illustrative and not in a limiting sense.

[0101] The embodiments are referred to herein individually and / or collectively by the term "embodiment" merely for convenience and without any intention to limit the scope of the present application to any single embodiment or inventive concept when in fact more than one is illustrated. Thus, although specific embodiments have been illustrated and described herein, it should be understood that arrangements which achieve the same purpose are substituted for the specific embodiment illustrated; that is, the present disclosure is intended to cover any and all adaptations or variations of the various embodiments. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art from the teachings herein.

[0102] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly dictates otherwise. As used herein, the terms "comprise" or "comprising" shall be understood to specify the presence of a referenced feature, step, operation, element, and / or component, or combination thereof, but not to preclude the presence or addition of one or more other features, steps, operations, elements, and / or components, or combinations thereof. Terms such as "bottom," "top," "above," "over," "under," and "below" are used to indicate the relative location of elements or structures, but not relative heights. When a layer of a structure is described herein as "over" another layer, it will be understood that there may or may not be an intermediate element or layer intervening between the two particular layers. When a layer is described as "directly on" another layer, it indicates that the two layers are in direct contact. As used in this specification and the appended claims, the term "about" means within plus or minus 10%.

[0103] The equivalents of the relevant structures, materials, acts, and all means or step-function elements in the following claims are intended to include all structures, materials, or acts for performing functions in combination with other claimed elements as specifically claimed. The description of the various embodiments has been provided for purposes of illustration and description, but is not limited to or exclusive of the disclosed forms. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments have been selected and described to best explain the principles and practical applications and to enable those skilled in the art to understand the various embodiments with various modifications suitable for the particular use intended.

[0104] The Abstract is provided to comply with 37 C.FR § 1.76(b), which requires a summary that will enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. It will also be appreciated that in the foregoing detailed description, various features have been grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, claimed subject matter may include less than all features of a single embodiment. Accordingly, the following claims are incorporated into the detailed description, with each claim standing on its own as separately claimed subject matter.

[0105] Given the teachings provided herein, one skilled in the art will be able to contemplate other implementations and applications of the techniques and disclosed embodiments. Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the exemplary embodiments are not limited to such precise examples, and that various different changes and modifications may be made by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A template layer containing a binary alloy having an alternating layer lattice structure; A semimetallic half-Heusler layer comprising a semimetallic half-Heusler material having a tetragonal lattice structure, wherein the semimetallic half-Heusler layer is located outside the template layer and has a half-Heusler in-plane lattice constant different from the in-plane lattice constant of the cubic form of the semimetallic half-Heusler material; The tunnel barrier outside the semimetallic half-Heusler layer; and The magnetic layer on the outside of the tunnel barrier; A magnetoresistive random access memory cell, including one.

2. The aforementioned semimetallic half-Heusler layer includes a preservation layer, The magnetoresistive random access memory cell according to claim 1, wherein the magnetic layer includes a reference layer.

3. The aforementioned semimetallic half-Heusler material comprises a semimetallic half-Heusler compound. The magnetoresistive random access memory cell according to claim 2, wherein the semimetallic half-Heusler compound is selected from the group consisting of RhCrGe, RhFeSn, NiVSn, NaCsP, LiCaGe, LiSrGe, NaCaGe, KCaGe, RbTaGe, KCrTe, NaCaSn, KTaSn, KCaSn, RbNbSi, RbTaSi, NaCsAs, CsRbAs, CsBaC, CsSrC, CsRbN, RhFeGe, CoCrGe, RuCrAs, CoCrAs, and CsSrSn.

4. The magnetoresistive random access memory cell according to claim 3, wherein the semimetallic half-Heusler layer has a thickness of less than 5 nm.

5. The magnetoresistive random access memory cell according to claim 3, wherein the semimetallic half-Heusler compound is selected from the group consisting of RhCrGe, RhFeSn, CoCrGe, NiVSn, CoCrAs, RhFeGe, or RuCrAs.

6. The magnetoresistive random access memory cell according to claim 5, wherein the semimetallic half-Heusler layer has a thickness of less than 5 nm.

7. The magnetoresistive random access memory cell according to claim 2, wherein the tunnel barrier is selected from the group consisting of magnesium oxide and aluminum magnesium oxide.

8. The aforementioned binary alloy is A １－ｘ E ｘ The magnetoresistive random access memory cell according to claim 2, wherein the cell is represented as follows, where A is a transition metal element, E is a main group element comprising at least one of aluminum and gallium, and x is in the range of 0.42 to 0.

55.

9. The aforementioned semimetallic half-Heusler layer includes a base layer, The magnetoresistive random access memory cell according to claim 1, wherein the magnetic layer includes a storage layer.

10. The aforementioned semimetallic half-Heusler material comprises a semimetallic half-Heusler compound. The semimetallic half-Heusler compound is selected from the group consisting of RhCrGe, RhFeSn, NiVSn, NaCsP, LiCaGe, LiSrGe, NaCaGe, KCaGe, RbTaGe, KCrTe, NaCaSn, KTaSn, KCaSn, RbNbSi, RbTaSi, NaCsAs, CsRbAs, CsBaC, CsSrC, CsRbN, RhFeGe, CoCrGe, RuCrAs, CoCrAs, and CsSrSn, as described in claim 9, a magnetoresistive random access memory cell.

11. The magnetoresistive random access memory cell according to claim 10, wherein the semimetallic half-Heusler layer has a thickness of less than 5 nm.

12. The magnetoresistive random access memory cell according to claim 10, wherein the semimetallic half-Heusler compound is selected from the group consisting of RhCrGe, RhFeSn, CoCrGe, NiVSn, CoCrAs, RhFeGe, or RuCrAs.

13. The magnetoresistive random access memory cell according to claim 12, wherein the semimetallic half-Heusler layer has a thickness of less than 5 nm.

14. The magnetoresistive random access memory cell according to claim 1, wherein the alternating layer lattice structure of the template layer includes a cesium chloride structure.

15. The magnetoresistive random access memory cell according to claim 1, wherein the template layer is nonmagnetic at room temperature.

16. The template layer has an in-plane lattice constant, The magnetoresistive random access memory cell according to claim 1, wherein the Half-Heusler in-plane lattice constant substantially matches the in-plane lattice constant of the template layer.

17. The magnetoresistive random access memory cell according to claim 16, wherein the semimetallic half-Heusler material has a magnetization substantially perpendicular to the semimetallic half-Heusler material.

18. Multiple bit lines and multiple complementary bit lines forming a pair of complementary bit lines; Multiple word lines that intersect the multiple bit line-complementary bit line pairs at multiple cell locations; A plurality of magnetoresistive random access memory cells, each of which is arranged at each of the plurality of cell locations, wherein each of the magnetoresistive random access memory cells is electrically connected to a corresponding bit line and selectively interconnected to a corresponding complementary bit line under the control of a corresponding word line; Includes, Each of the plurality of magnetoresistive random access memory cells is A template layer containing a binary alloy having an alternating layer lattice structure, A semimetallic half-Heusler layer comprising a semimetallic half-Heusler material having a tetragonal lattice structure, wherein the semimetallic half-Heusler layer is located outside the template layer and has a half-Heusler in-plane lattice constant different from the in-plane lattice constant of the cubic semimetallic half-Heusler material, The tunnel barrier on the outside of the aforementioned semimetallic half-Heusler layer, The magnetic layer on the outside of the tunnel barrier, A magnetoresistive random access memory array, including one.

19. The aforementioned semimetallic half-Heusler layer includes a preservation layer, The magnetoresistive random access memory array according to claim 18, wherein the magnetic layer includes a reference layer.

20. The aforementioned semimetallic half-Heusler material comprises a semimetallic half-Heusler compound. The magnetoresistive random access memory array according to claim 19, wherein the semimetallic half-Heusler compound is selected from the group consisting of RhCrGe, RhFeSn, NiVSn, NaCsP, LiCaGe, LiSrGe, NaCaGe, KCaGe, RbTaGe, KCrTe, NaCaSn, KTaSn, KCaSn, RbNbSi, RbTaSi, NaCsAs, CsRbAs, CsBaC, CsSrC, CsRbN, RhFeGe, CoCrGe, RuCrAs, CoCrAs, and CsSrSn.

21. The semimetallic half-Heusler layer has a base layer, The magnetoresistive random access memory array according to claim 18, wherein the magnetic layer has a recording layer.

22. The magnetoresistive random access memory array according to claim 21, wherein the semimetallic half-Heusler compound is selected from the group consisting of RhCrGe, RhFeSn, NiVSn, NaCsP, LiCaGe, LiSrGe, NaCaGe, KCaGe, RbTaGe, KCrTe, NaCaSn, KTaSn, KCaSn, RbNbSi, RbTaSi, NaCsAs, CsRbAs, CsBaC, CsSrC, CsRbN, RhFeGe, CoCrGe, RuCrAs, CoCrAs, and CsSrSn.

23. A method for operating a magnetoresistive random access memory array, The step of providing a magnetoresistive random access memory array, The aforementioned array is Multiple bit lines and multiple complementary bit lines that form multiple bit line-complementary bit line pairs, Multiple word lines intersect with the multiple bit line pairs at multiple cell locations, A plurality of magnetoresistive random access memory cells, each of which is arranged at each of the plurality of cell locations, wherein each of the magnetoresistive random access memory cells is electrically connected to a corresponding bit line and selectively interconnected to a corresponding complementary bit line under the control of one of the corresponding word lines, It has, Each of the plurality of magnetoresistive random access memory cells is A template layer containing a binary alloy having an alternating layer lattice structure, A semimetallic half-Heusler layer comprising a semimetallic half-Heusler material having a tetragonal lattice structure, wherein the semimetallic half-Heusler layer is positioned outside the template layer and has a half-Heusler in-plane lattice constant different from the in-plane lattice constant of the cubic semimetallic half-Heusler material, The tunnel barrier on the outside of the aforementioned semimetallic half-Heusler layer, The magnetic layer on the outside of the tunnel barrier, Includes, This method further, Steps include: applying a signal to the word line, storing logic 1 in a first subset of the cell, and storing logic 0 in a second subset of the cell; The steps include reading the stored logic 1 and 0 via the bit line and the complementary bit line, A method having.

24. A method for forming a magnetoresistive random access memory cell, The steps include providing a template layer containing a binary alloy having an alternating layer lattice structure and having an in-plane lattice constant for the template layer, A step of epitaxially growing a semimetallic half-Heusler layer on the template layer, wherein the semimetallic half-Heusler layer comprises a semimetallic half-Heusler material, and is grown on the template layer such that the semimetallic half-Heusler material has a tetragonal lattice structure and has a half-Heusler in-plane lattice constant different from the in-plane lattice constant of the cubic semimetallic half-Heusler material, and the half-Heusler in-plane lattice constant substantially matches the in-plane lattice constant of the template layer. The steps include forming a tunnel barrier on the outside of the semimetallic half-Heusler layer, The steps include forming a magnetic layer on the outside of the tunnel barrier, A method having.

25. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, The HDL design structure, when processed in a computer-aided design system, includes elements that generate a machine-executable representation of a magnetoresistive random-access memory cell. The HDL design structure is, A template layer containing a binary alloy having an alternating layer lattice structure, A semimetallic half-Heusler layer comprising a semimetallic half-Heusler material having a tetragonal lattice structure, wherein the semimetallic half-Heusler layer is located outside the template layer and has a semimetallic half-Heusler in-plane lattice constant different from the in-plane lattice constant of the cubic semimetallic half-Heusler material, The tunnel barrier on the outside of the aforementioned semimetallic half-Heusler layer, The magnetic layer on the outside of the tunnel barrier, An HDL design structure having [this feature].

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