FAN-OUT STRUCTURE FOR LIGHT EMITTING DIODE DEVICES AND LIGHTING SYSTEMS - Patent application

Abstract

An LED lighting system and a vehicle headlamp system are described. The LED lighting system includes a silicon backplane having a top surface, a bottom surface, and a side surface, and a substrate surrounding the side surface of the silicon backplane, the substrate having a top surface, a bottom surface, and a side surface. A first redistribution layer is provided on the top surface of the silicon backplane and the top surface of the substrate. A second redistribution layer is provided on the bottom surface of the silicon backplane and the bottom surface of the substrate. At least one via extends through the substrate between the first redistribution layer and the second redistribution layer and is filled with a metal material.

Description

Technical Field

[0001] (Reference to Related Applications) This application claims the benefit of U.S. Non-Provisional Application No. 16 / 750,809, filed on January 23, 2020, European Patent Application No. 20157985.1, filed on February 18, 2020, U.S. Provisional Application No. 62 / 951,601, filed on December 20, 2019, and U.S. Provisional Application No. 62 / 937,629, filed on November 19, 2019, the contents of which are hereby incorporated by reference.

Background Art

[0002] Precision control lighting applications may require the production and manufacture of small addressable light emitting diode (LED) lighting systems. Such systems of smaller size may require non-conventional components and manufacturing processes.

Summary of the Invention

[0003] An LED lighting system, a vehicle headlamp system, and a manufacturing method are described. The LED lighting system includes a silicon backplane having a top surface, a bottom surface, and side surfaces, and a substrate surrounding the side surfaces of the silicon backplane, the substrate having a top surface, a bottom surface, and side surfaces. A first redistribution layer is provided on the top surface of the silicon backplane and the top surface of the substrate. A second redistribution layer is provided on the bottom surface of the silicon backplane and the bottom surface of the substrate. At least one via extends through the substrate between the first redistribution layer and the second redistribution layer and is filled with a metallic material.

[0004] A more detailed understanding can be obtained from the following description given by way of example in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0005] [Figure 1A] It is a top view of an exemplary LED array.

[0006] [Figure 1B] This is a cross-sectional view of an exemplary LED lighting system.

[0007] [Figure 1C] Figure 1B is a top view of an exemplary LED lighting system.

[0008] [Figure 1D] Figure 1B is a bottom view of an exemplary LED lighting system.

[0009] [Figure 2] Figure 1B is a cross-sectional view of an exemplary application system incorporating an LED lighting system.

[0010] [Figure 3] Figure 1B shows an example vehicle headlamp system incorporating the LED lighting system.

[0011] [Figure 4] This is a diagram illustrating another example of a vehicle headlamp system.

[0012] [Figure 5] This is a flowchart illustrating an exemplary method for manufacturing an LED lighting system, such as the LED lighting system shown in Figure 1B.

[0013] [Figure 6A] These are cross-sectional views of an LED lighting system at various stages in its manufacturing process. [Figure 6B] These are cross-sectional views of an LED lighting system at various stages in its manufacturing process. [Figure 6C] These are cross-sectional views of an LED lighting system at various stages in its manufacturing process. [Figure 6D] These are cross-sectional views of an LED lighting system at various stages in its manufacturing process. [Figure 6E] These are cross-sectional views of an LED lighting system at various stages in its manufacturing process. [Figure 6F] These are cross-sectional views of an LED lighting system at various stages in a manufacturing method. [Figure 6G] These are cross-sectional views of an LED lighting system at various stages in a manufacturing method. [Figure 6H] These are cross-sectional views of an LED lighting system at various stages in a manufacturing method. [Figure 6I] These are cross-sectional views of an LED lighting system at various stages in a manufacturing method. [Figure 6J] These are cross-sectional views of an LED lighting system at various stages in a manufacturing method.

[0014] [Figure 7] This is a bottom view representing the bottom surface of the LED lighting system of FIG. 6E.

Embodiments for Carrying Out the Invention

[0015] Examples of different lighting systems and / or light-emitting diodes ("LEDs") are described more fully below with reference to the accompanying drawings. These examples are not mutually exclusive, and the configurations found in one example may be combined with the configurations found in one or more other examples to achieve additional implementations. Accordingly, it will be understood that the examples shown in the accompanying drawings are provided for illustrative purposes only and are not intended to limit the present disclosure in any way. Like numbers refer to like elements throughout.

[0016] Terms such as first, second, third, etc., may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms may be used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and a second element may be referred to as a first element. When used herein, the term "and / or" may include any combination of one or more items of the related enumerated items.

[0017] When an element such as a layer, region, or substrate is said to be "on" or "onto" another element, it will be understood that it may be directly on or directly extending onto the other element, or that intervening elements may be present. In contrast, when an element is said to be "directly on" or "directly onto" another element, there may be no intervening elements. When an element is said to be "connected" or "coupled" to another element, it will be understood that it may be directly connected or coupled to the other element, and / or connected or coupled to the other element via one or more intervening elements. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements between that element and the other element. It will be understood that these terms are intended to encompass different orientations of elements, in addition to any orientation shown in the diagram.

[0018] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as illustrated. It will be understood that these terms are intended to encompass different orientations of the device, in addition to the orientation shown in the illustration.

[0019] Furthermore, whether LEDs, LED arrays, electrical components, and / or electronic components are housed on one, two, or more electronic boards may also depend on design constraints and / or applications.

[0020] Optical power emitting devices, such as semiconductor light-emitting devices (LEDs) or devices that emit ultraviolet (UV) or infrared (IR) light power, are among the most efficient light sources currently available. These devices (hereinafter "LEDs") may include light-emitting diodes, resonant cavity light-emitting diodes, vertical cavity laser diodes, edge-emitting lasers, or equivalents. For example, due to their compact size and lower power requirements, LEDs can be attractive candidates for many different applications. For example, they may be used as light sources for handheld battery-powered devices such as cameras and mobile phones (e.g., flashlights and camera flashes). They may also be used for automotive lighting, head-up display (HUD) lighting, garden lighting, streetlights, video torches, general lighting (e.g., home, shop, office, studio lighting, theater / stage lighting, and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, backlights for displays, and IR spectroscopy. A single LED may not provide light brighter than an incandescent light source; therefore, for applications where greater brightness is desired or required, multi-junction devices or arrays of LEDs (such as monolithic LED arrays or micro-LED arrays) may be used.

[0021] Figure 1A is a top view of an exemplary LED array 102. In the example shown in Figure 1A, the LED array 102 is an array of emitters 120. LED arrays can be used for any application, such as those requiring precise control of LED array emitters. The emitters 120 in the LED array 102 may be individually addressable or addressable within a group / subset.

[0022] An exploded view of a 3x3 section of the LED array 102 is also shown in Figure 1A. As shown in the exploded view of the 3x3 section, the LED array 102 may include emitters 120, each having a width w1. In embodiments, the width w1 may be about 100 μm or less (e.g., 40 μm). The lanes 122 between the emitters 120 may have a width w2. In embodiments, the width w2 may be about 20 μm or less (e.g., 5 μm). The lanes 122 may provide an air gap between adjacent emitters or may contain other materials. The distance d1 from the center of one emitter 120 to the center of the adjacent emitter 120 may be about 120 μm or less (e.g., 45 μm). It will be understood that the widths and distances provided herein are illustrative only and actual widths and / or dimensions may vary.

[0023] While Figure 1A shows rectangular emitters arranged in a symmetric matrix, it will be understood that emitters of any shape and arrangement may be applied to the embodiments described herein. For example, the LED array 102 in Figure 1A may contain more than 20,000 emitters in any applicable configuration, such as a 200 × 100 matrix, a symmetric matrix, an asymmetric matrix, or equivalent. It will also be understood that multiple sets of emitters, matrices, and / or substrates may be arranged in any applicable format to implement the embodiments described herein.

[0024] As described above, an LED array like LED array 102 may contain up to 20,000 or more emitters. Such arrays may have a surface area of ​​90 mm² or more and may require significant power, such as 60 watts or more, to power them. Such LED arrays may be referred to as micro-LED arrays or simply micro-LEDs. A micro-LED may consist of an array of individual emitters mounted on a substrate, or it may be a single silicon wafer or die divided into segments that form emitters. The latter type of micro-LED may be referred to as a monolithic LED.

[0025] To individually drive or control each LED within the array, a silicon backplane may be positioned close to the LED array, which can become extremely hot during operation. Therefore, heat dissipation can be challenging for such devices. Several solutions are known for heat dissipation in semiconductor devices, and these solutions often involve structures that dissipate heat through the top of the device. However, due to light emission, LED arrays like the LED array 102 in Figure 1A may not be able to dissipate heat through the top of the device.

[0026] In addition, LED arrays like LED array 102 may include passive elements such as resistors and capacitors that may form drivers, controllers, and other circuits, and may be used in applications such as vehicle headlamp systems. It may be desirable to package at least some of the passive elements into the LED array.

[0027] Embodiments described herein may provide a low-profile LED array package that may house one or more passive elements and may allow for the dissipation of heat generated by the silicon backplane and the LED array.

[0028] Figure 1B is a cross-sectional view of an exemplary LED lighting system 100. In the example shown in Figure 1B, the LED lighting system 100 includes a silicon backplane 104. The silicon backplane 104 has a top surface 101, a bottom surface 103, and a side surface 105. The side surface 105 of the silicon backplane 104 is surrounded by a substrate 106 formed from a molding material. The substrate 106 has a top surface 107, a bottom surface 109, and a side surface 190. One or more metal layers 110 or redistribution layers (RDLs) (as shown in an alternative embodiment in Figure 6E) are provided on the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106. The RDLs 117 may be formed on at least a portion of the top surface 101 of the silicon backplane 104 and the top surface 107 of the substrate 106. In the example shown in Figure 1B, the RDL117 includes two layers 116a and 116b of dielectric material 116 and a single metal layer 112. One or more vias 108 may extend through the substrate 106 and may be filled with the metal material. Thus, the vias may form continuous electrical connections between the silicon backplane 104, the RDL117, and the metallization / RDL110. An LED array, such as the LED array 102 in Figure 1A, may be mounted on the top surface 101 of the silicon backplane 104 and electrically coupled to it via an array of metal connectors (not shown in Figure 1B). In an embodiment, an electronic component 114 may be mounted on the RDL117 and electrically coupled to the LED lighting system 100 via the metal layer 112.

[0029] The LED array 102 may be a micro-LED as described above with respect to Figure 1A. The LED array 102 may have a depth d1. In this embodiment, the depth d1 may be, for example, between 5 and 250 μm.

[0030] The silicon backplane 104 may include circuits and connectors that provide individually addressable connections to the emitters in the LED array 102. In embodiments, the silicon backplane may be a complementary metal-oxide semiconductor (CMOS) integrated circuit, which in embodiments may be an application-specific integrated circuit (ASIC). The silicon backplane 104 may have a depth d3. In embodiments, the depth d3 may be, for example, 100 μm to 1 mm.

[0031] The structure, consisting of a silicon backplane 104, a substrate 106, metallization / RDL 110, RDL 117, and vias 108, may have a depth d2. In embodiments, the depth d2 may be, for example, 100 μm to 1 mm. Since the silicon backplane 104 is integrated with the substrate and the LED array 102 is located on top of the silicon backplane 104, the LED lighting system 100 may have a lower profile than a system in which one or more of these elements are stacked vertically.

[0032] In the example shown in Figure 1B, the RDL 117 includes two layers 116a and 116b of dielectric material 116 and a single metal layer 112. The first layer 116a of the two layers of dielectric material 116 may be on the top surface 107 of the substrate 106 and at least a portion of the top surface 101 of the silicon backplane 104. The metal layer 112 may be patterned on the first layer 116a of dielectric material 116, for example, by copper plating and copper etching. The second layer 116b of dielectric material 116 may be on the top of the patterned metal layer 112 and the exposed portion of the first layer 116a of dielectric material 116. Although an RDL consisting of two layers of dielectric material and a single metal layer is shown in Figure 1B, those skilled in the art will recognize that the RDL 117 may include more or fewer layers of dielectric material and / or many metal layers, depending on design constraints. The dielectric material 116 may be any suitable dielectric material. In an embodiment, the dielectric material may be a polymer dielectric material such as polyimide.

[0033] RDL117 may extend from the peripheral region of the silicon backplane 104 toward the side surface 190 of the substrate 106. This may house an LED array 102 mounted on the top surface 101 of the silicon backplane 104 in the central region, and may also help dissipate heat by housing dielectric material that further insulates the LED lighting system 100 away from the hottest central region of the LED lighting system 100. The metal layer 112 may have portions exposed from the dielectric material 116 to form bond pads. The metal layer 112 may include portions extending between the peripheral region of the silicon backplane 104 and the bond pads, creating a continuous electrical connection between them. The bond pads may be electrically coupled to vias 108 to form a continuous electrical connection between the top and bottom surfaces of the LED lighting system 100. The bond pads may be located in the peripheral region of the substrate, or (for example, as shown in Figure 1C) spaced away from the LED array, but closer to the LED array.

[0034] The metallization / RDL110 may be formed in a number of different ways. In the example shown in Figure 1B, the metallization / RDL110 is a metallic layer comprising a first portion electrically and thermally coupled to the bottom surface 103 of the silicon backplane 104 in a central region, and a second portion fanning out from the peripheral region of the silicon backplane 104 toward the side surface 190 of the substrate 106. In embodiments, the first and second portions may be electrically insulated from each other. Although not visible in Figure 1B, the second portion may extend from the silicon backplane 104 and bond to individual vias 108 with bond pads to electrically couple the silicon backplane 104 to the metallic layer 112 at the top surface. Both the first and second portions of the metallic layer 110 may be coupled to an external circuit board (not shown), for example, by soldering. This may allow for a direct connection between the LED lighting system 100 and an external circuit board, which provides an improved heat sink through the bottom of the LED lighting system. In addition, this structure may allow for communication between the silicon backplane 104, the LED array 102, the passive components 114 on the substrate 106, and any electronic components on the external circuit board.

[0035] In another example, which will be described in detail later with respect to Figures 6E and 7, the metallization / RDL 110 may be a combination of a metal layer and an RDL. Similar to the embodiment shown in Figure 1B, the metal layer may be electrically and thermally coupled to the bottom surface 103 of the silicon backplane 104 in the central region. However, fan-out may be achieved using an RDL instead of a metal layer. In such embodiments, the LED lighting device 100 may have RDLs on both the top and bottom surfaces.

[0036] In both cases, the metallization / RDL110 may be thinner than conventional silicon device packages and may contain significantly less dielectric material than conventional silicon device packages. For example, the metal layer 100 in the embodiment shown in Figure 1B may be a single metal layer, and the RDL may contain as few dielectric layers as possible. This improves the efficiency of heat dissipation in such packages and enables packaging for micro-LEDs and CMOS backplanes that may radiate substantial heat.

[0037] In the LED lighting system 100 shown in Figure 1B, the top surface 101 of the silicon backplane 104 and the top surface 107 of the substrate 106 are in the same plane. Similarly, the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106 are in the same plane. This configuration may allow for the smallest possible ease of packaging and manufacturing. However, those skilled in the art will understand that since the substrate 106 is molded, it may take any shape, for example, if the substrate 106 has a top surface 107 that is higher than the top surface 101 of the silicon backplane 104, in order to further distance the electronic component 114 from the high-temperature region of the LED lighting system 100. Thus, in embodiments, these surfaces may not be in the same plane.

[0038] Figure 1C is a top view showing the top surface 130 of the exemplary LED lighting system 100 of Figure 1B. In the example shown in Figure 1C, the top surface 130 of the LED lighting system includes the uppermost layer 116b of the dielectric material 116 within the RDL 117. The electronic component 114 is electrically coupled to the metal 112 within the RDL and exposed from the dielectric material 116. In embodiments, the electronic component 114 may not be electrically coupled to all areas of the metal 112, and therefore, the top surface 130 may also include some areas of the metal 112 exposed from the dielectric material 116 in embodiments. The top surface of at least a portion of the silicon backplane 104 is shown in Figure 1C, including the portion of the silicon backplane 104's top surface that is not covered by the LED array 102 or the dielectric material 116. The top surface of the LED array 102 is also shown mounted on the top surface of the silicon backplane 104.

[0039] As shown in Figure 1C, the LED lighting system 100 has a length l1 and a width w1. In an embodiment, the length l1 may be about 20 mm and the width w1 may be about 15 mm. The silicon backplane 104 may have a length l2 and a width w2. In an embodiment, the length l2 may be about 15.5 mm and the width w2 may be about 6.5 mm. The LED array 102 may have a length l3 and a width w3. In an embodiment, the length l3 may be about 11 mm and the width w3 may be about 4.4 mm.

[0040] Given these exemplary dimensions, (in the above example, approximately 100 mm) 2 A relatively large surface area (300 mm in the above example) that is not occupied by the LED array (having a surface area of ​​a relatively large amount) 2 LED array packages with ) may be provided. Therefore, this design provides sufficient space for mounting electronic components on the LED array package.

[0041] Figure 1D is a bottom view showing the bottom surface 140 of the exemplary LED lighting system 100 of Figure 1B. In the example shown in Figure 1D, the bottom surface 140 includes a region of the substrate 106 and a region of metal 110 exposed from the molding material 106 or solder pads bonded thereto. In some embodiments, several regions of the substrate may be covered by RDL portions and / or metallization interconnecting the silicon backplane and the bond pads, these of which are not shown in Figure 1D. In some embodiments, the interconnecting metal regions and / or RDL may be covered by dielectric materials or other encapsulating or protective materials (not shown in Figure 1D).

[0042] Figure 2 is a cross-sectional view of an application system 200 incorporating the LED lighting system 100 of Figure 1B. The application system 200 may include a circuit board 150 having a number of bond pads 152. In the example shown in Figure 2, the exposed metal areas / bond pads of the RDL / metallization 110 of the LED lighting system 100 are directly bonded to the bond pads 152 of the circuit board 150. As described above, the direct bonding between the metal layer 110 on the bottom surface of the silicon backplane 104 and the circuit board 150 allows for efficient heat transfer from the LED lighting system 100 to the circuit board 150 for heat sink purposes without requiring, for example, an additional heat dissipation structure on the top of the LED lighting system 100 (or elsewhere) which might otherwise block light emission from the LED array 102. The circuit board 150 may be part of a larger system used in a specific application such as vehicle lighting or flashing applications (an exemplary vehicle lighting system is described below with respect to Figures 3 and 4). In such a system, some of the passive components used in the application may be component 114, which may be provided directly on the LED lighting system 100 before being mounted on the circuit board 150. The circuit board 150 may include a heat sink as well as other circuit elements required for a larger system. RDL 117, RDL / metallization 110, and via 108 may provide continuous electrical connections between component 114, the silicon backplane 104, and the circuit board 150.

[0043] Figure 3 is a diagram of an exemplary vehicle headlamp system 300 that may incorporate the LED lighting system 100 of Figure 1B. The exemplary vehicle headlamp system 300 shown in Figure 3 includes a power line 302, a data bus 304, an input filter and protection module 306, a bus transceiver 308, a sensor module 310, an LED DC / DC (direct current to direct current) module 312, a logic low dropout (LDO) module 314, a microcontroller 316, and an active headlamp 318. In embodiments, the active headlamp 318 may include an LED lighting system, such as the LED lighting system 100 of Figure 1B. As described above, the LED lighting system 100 provides sufficient space and bond pads on the top surface of the substrate so that one, more, or all of the modules shown in Figure 3 may be housed on the top surface of the LED lighting system 100. Modules not located on the top surface of the LED lighting system 100 may be located on the circuit board 150 (as shown in Figure 2). In some embodiments, some or all of the electronic components of the modules within the vehicle lighting system 300 may be housed on the top surface of the LED lighting system 100, and some may be provided on the circuit board 150 (shown in Figure 2).

[0044] The power line 302 may have an input that receives power from the vehicle, and the data bus 304 may have inputs / outputs that may exchange data between the vehicle and the vehicle headlamp system 300. For example, the vehicle headlamp system 300 may receive commands from other locations in the vehicle, such as commands to turn on turn signal transmission or commands to turn on the headlamps, and may send feedback to other locations in the vehicle if desired. The sensor module 310 may be communicatively coupled to the data bus 304 and may provide additional data to the vehicle headlamp system 300 or other locations in the vehicle, for example, in relation to environmental conditions (e.g., time, rain, fog, or ambient light level), vehicle status (e.g., parked, moving, speed, or direction of movement), and the presence / location of other objects (e.g., vehicles or pedestrians). A headlamp controller, separate from any vehicle controller communicatively coupled to the vehicle data bus, may also be included in the vehicle headlamp system 300. In Figure 3, the headlamp controller may be a microcontroller, such as a microcontroller (μc) 316. The microcontroller 316 may be communicatively coupled to the data bus 304.

[0045] The input filter and protection module 306 may be electrically coupled to the power line 302 and may, for example, support various filters that reduce conducted emission and provide power immunity. In addition, the input filter and protection module 306 may provide electrostatic discharge (ESD) protection, load-dump protection, alternator field decay protection, and / or reverse polarity protection.

[0046] The LED DC / DC module 312 may be coupled between the filter and protection module 306 and the active headlamp 318 to receive filtered power and provide a drive current to power the LEDs in the LED array within the active headlamp 318. The LED DC / DC module 312 may have an input voltage between 7 and 18 volts with a nominal voltage of approximately 13.2 volts (determined, for example, by factors or local calibration and adjustment of operating conditions due to load, temperature or other factors) and an output voltage that may be slightly higher than the maximum voltage of the LED array (e.g., 0.3 volts).

[0047] The logic LDO module 314 may be coupled to the input filter and protection module 306 to receive filtered power. The logic LDO module 314 may also be coupled to the microcontroller 314 and / or the active headlamp 318 to supply power to the silicon backplane (e.g., CMOS logic) within the microcontroller 314 and / or the active headlamp 318.

[0048] The bus transceiver 308 may have, for example, a universal asynchronous receiver transmitter (UART) or a serial peripheral interface (SPI) interface and may be coupled to the microcontroller 316. The microcontroller 316 may translate vehicle inputs based on or containing data from the sensor module 310. The translated vehicle inputs may include video signals transferable to an image buffer in the active headlamp module 318. In addition, the microcontroller 316 may load a default image frame and test open / short pixels during startup. In embodiments, the SPI interface may load the image buffer in CMOS. The image frame may be a full frame, a difference frame, or a partial frame. Other configurations of the microcontroller 316 may include control interface monitoring of CMOS states, including die temperature, and logic LDO outputs. In embodiments, the LED DC / DC output may be dynamically controlled to minimize headroom. In addition to providing image frame data, other headlamp functions may also be controlled, such as complementary use in conjunction with side markers or turn signal lights, and / or activation (startup) of daytime running lights.

[0049] Figure 4 shows another exemplary vehicle headlamp system 400. The exemplary vehicle headlamp system 400 shown in Figure 4 includes an application platform 402, two LED lighting systems 406 and 408, and optical systems 410 and 412. The two LED lighting systems 406 and 408 may be LED lighting systems such as the LED lighting system 100 in Figure 1B, or the LED lighting system 100 may be included in addition to some or all of the other modules in the vehicle headlamp system 300 in Figure 3. In the latter embodiment, the LED lighting systems 406 and 408 may be a vehicle headlamp subsystem.

[0050] The LED lighting system 408 may emit a light beam 414 (shown between arrows 414a and 414b in Figure 4). The LED lighting system 406 may emit a light beam 416 (shown between arrows 416a and 416b in Figure 4). In the embodiment shown in Figure 4, a secondary optical system 410 is adjacent to the LED lighting system 408, and light emitted from the LED lighting system 408 passes through the secondary optical system 410. Similarly, a secondary optical system 412 is adjacent to the LED lighting system 412, and light emitted from the LED lighting system 412 passes through the secondary optical system 412. In an alternative embodiment, the secondary optical systems 410 / 412 are not provided in the vehicle headlamp system.

[0051] If a secondary optical system 410 / 412 is included, the secondary optical system 410 / 412 may consist of one or more optical guides, or may include one or more optical guides. One or more optical guides may be edge-lit, or may have internal apertures that define the internal edges of the optical guides. LED lighting systems 408 and 406 (or active headlamps of a vehicle headlamp subsystem) may be inserted into the internal apertures of one or more optical guides so that they inject light into the internal edges (internal aperture optical guides) or external edges (edge-lit optical guides) of one or more optical guides. In embodiments, one or more optical guides may shape the light emitted by the LED lighting systems 408 and 406 in a desired manner, such as using a gradient, chamfered distribution, narrow distribution, wide distribution, or angular distribution.

[0052] The application platform 402 may provide power and / or data to the LED lighting systems 406 and / or 408 via a line 404 which may include one or more of the power line 302 and data bus 304 shown in Figure 3. One or more sensors (which may be sensors in system 300 or other additional sensors) may be located inside or outside the housing of the application platform 402. Alternatively or additionally, as shown in the exemplary LED lighting system 300 in Figure 3, each LED lighting system 408 and 406 may include its own sensor module, connectivity and control module, power module, and / or LED array.

[0053] In an embodiment, the vehicle headlamp system 400 may represent an automobile having an operable light beam that selectively activates LEDs to provide controllable light. For example, an array of LEDs (e.g., LED array 102) may be used to define or project shapes or patterns, or to illuminate only selective sections of the road. In an exemplary embodiment, infrared cameras or detector pixels within the LED systems 406 and 408 may be sensors (similar to the sensors in sensor module 310 in Figure 3) that identify portions of a scene requiring illumination (e.g., a road or pedestrian crossing).

[0054] Figure 5 is a flowchart of an exemplary method 500 for manufacturing an LED lighting system, such as the LED lighting system 100 in Figure 1B. Figures 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I, and 6J are cross-sectional views of the LED lighting system at various stages of the manufacturing method. In embodiments, the method 500 may manufacture a high-density LED lighting system mounted at the panel level.

[0055] In the exemplary method 500 shown in Figure 5, a silicon backplane may be attached to a first carrier (502) to form a first structure. In embodiments, the silicon backplane may be attached to a temporary (e.g., plastic) carrier via an adhesive material such as tape or temporary adhesive. An example of a first structure 600A is shown in Figure 6A and includes a silicon backplane 104, a first carrier 602, and an optional adhesive material 604.

[0056] A second structure may be formed by molding (504) a silicon backplane attached to a first carrier. An example of a second structure 600B is shown in Figure 6B and includes the first structure 600A of Figure 6A having molding material surrounding the sides of the silicon backplane 104. The molding material forms a substrate 106 having the embedded silicon backplane 104. In an embodiment, a mold may be placed on the structure 600A, filled with molding material, and cured. If necessary, excess molding material may be removed from the top surface of the silicon backplane. In an embodiment, the molding may be panel-level molding, the molding material may be a polymer material, and the second structure 600B may be a plastic substrate having a silicon backplane embedded on a temporary substrate.

[0057] A third structure may be formed by forming one or more vias through the substrate (506). In embodiments, one or more vias may be formed using a laser or a drill. An example of a third structure 600C is shown in Figure 6C, which includes a silicon backplane 104 embedded in a substrate 106, with two vias 108 formed through them. At this stage, the silicon backplane 104 with the vias 108 and the substrate 106 may remain attached to the first temporary carrier 602. The vias 108 may be filled with a metallic material.

[0058] At least one metal layer may be formed on the silicon backplane and on one surface of the substrate (508). This may be done in a number of different ways.

[0059] In some embodiments, a fourth structure may be formed by patterning or plating a metal layer onto a silicon backplane and one surface of the substrate. Figure 6D shows an example 600D of a fourth structure, which includes a third structure having a metal layer 110. As shown in Figure 6D, the metal layer 110 forms bond pads on regions extending from the peripheral region of the silicon backplane 104 and on vias. A metal layer is also provided in the central region of one surface of the silicon backplane 104. The bottom view of the LED lighting system 100 shown in Figure 1D illustrates this example.

[0060] In other embodiments, a metal layer may be formed on one surface of the silicon backplane within a central region, and a redistribution layer may be formed on one surface of the substrate and silicon backplane adjacent to a single metal layer to form a fifth structure. Figure 6E shows an example 600E of the fifth structure, which includes a third structure having a single metal layer 618 and a redistribution layer 616. In the example shown in Figure 6E, the redistribution layer 616 includes a layer of dielectric material 614 and a metal layer 612. Although three metal layers are shown in Figure 6E, more than one, two, or three metal layers may be used as needed due to design constraints. The redistribution layer may be formed, for example, by alternating deposition of layers of dielectric material, selective removal of portions of dielectric material (as needed), and patterning of the metal layer on top. As can be seen from Figure 6E, the metal layer 612 begins in a peripheral region of one surface of the silicon backplane and extends toward the side of the substrate. The metal layer 612 is electrically coupled between the silicon backplane 104 and the vias. A portion of the metal layer 612 may be exposed from the dielectric material 614 to form a solder pad, or a separate solder pad may be formed on the outermost surface of the outermost dielectric layer.

[0061] Figure 7 is a bottom view representing the bottom surface 700 of the LED lighting system of Figure 6E. Line 702 represents the outermost perimeter of the substrate. Line 104 represents the outermost perimeter of the region occupied by the silicon backplane 104 relative to the outermost perimeter of the substrate. The dashed line 704 indicates the boundary of the region between line 704 and the outermost perimeter of the silicon backplane 104, which may be referred to herein as the peripheral region of the silicon backplane 104. The metal layer 612 of the redistribution layer 616 may begin in the peripheral region and extend toward the side of the substrate (bounded by line 702). There is a gap between the boundary 704 of the peripheral region of the silicon backplane and a single metal layer 618 formed on one surface of the silicon backplane. This gap may be filled with dielectric material, for example, as reflected in Figure 6E.

[0062] The structure formed as a result of 508 (e.g., the fourth or fifth structure) may be inverted and attached to the second carrier (510) to form the sixth structure. In embodiments, the structure (e.g., the fourth or fifth structure) may be attached to a temporary (e.g., plastic) carrier via an adhesive material such as tape or temporary adhesive. The structure may be placed adjacent to the second carrier with at least one metal layer. An example of the sixth structure 600G is shown in Figure 6G and includes the second carrier 608 and an optional adhesive material 606. Once the structure is attached to the second carrier, the first carrier may be removed (512) to form the seventh structure. An example of the seventh structure 600G is shown in Figure 6G.

[0063] An eighth structure may be formed by forming a redistribution layer and an array of metal connectors on the surface exposed by the removal of the second carrier (514). In embodiments, the array of metal connectors may be formed by plating or otherwise patterning or forming an array of copper pillar bumps on the surface. An example of the eighth structure 600H is shown in Figure 6H and includes a metal connector 640 and a redistribution layer 117, comprising at least one metal layer 112 and dielectric material 116. As described above with respect to Figure 6E, the redistribution layer may be formed by alternating deposition of layers of dielectric material, selective removal of portions of dielectric material (if necessary), and patterning a metal layer on top. In embodiments, more than 20,000 (e.g., about 28,000) metal connectors may be formed on the surface.

[0064] The LED array may be mounted to a silicon backplane via electrical connectors (516) to form a ninth structure. In embodiments, this may be done by aligning the silicon backplane with the electrical connectors and heating it to reflow the solder copper material within the copper pillar bumps. Reflow may create an underfill beneath the LED array. In embodiments, the LED array may be a monolithic LED array. An example of the ninth structure 600I is shown in Figure 6I and includes an LED array 102 and an underfill.

[0065] The LED array may undergo a laser liftoff (LLO) process and phosphor integration (518). A tenth structure may be formed by mounting any passive components on the exposed metal region within the redistribution layer 117. An example of the tenth structure 600J is shown in Figure 600J and includes an LED array 102 having a phosphor material 610 and a passive component 114.

[0066] Optionally, a tenth structure, which may be an LED lighting system such as the LED lighting system 100 in Figure 1B, may be mounted on an external circuit board, for example, to integrate the LED lighting system 100 into a vehicle headlamp or other application system (520).

[0067] While embodiments have been described in detail, those skilled in the art will understand that, given this disclosure, modifications may be made to the embodiments described herein without departing from the spirit of the inventive concept. Therefore, the scope of the invention is not intended to be limited to the specific embodiments shown and described.

Claims

1. a silicon backplane having a top surface, a bottom surface, and a side surface; an array of metal connectors on the top surface of the silicon backplane; a substrate surrounding the side of the silicon backplane and having a top surface, a bottom surface, and a side surface; a first redistribution layer overlying the top surface of the silicon backplane and the top surface of the substrate; a second redistribution layer overlying the bottom surface of the silicon backplane and the bottom surface of the substrate; at least one via extending through the substrate between the first redistribution layer and the second redistribution layer and filled with a metallic material; system.

2. The first redistribution layer comprises: at least one first dielectric layer; at least one first metal layer; the at least one first metal layer extends from a peripheral region of the silicon backplane toward the side of the substrate and has at least a portion exposed from the at least one dielectric layer to form at least one bond pad; The system of claim 1 .

3. The system of claim 2 , further comprising at least one passive component electrically coupled to the at least one bond pad.

4. The second redistribution layer comprises: at least one second dielectric layer; at least one second metal layer; the at least one second metal layer extends from a peripheral region of the silicon backplane toward the side of the substrate and has at least a portion exposed from the at least one dielectric layer to form at least one bond pad. The system of claim 1 .

5. The system of claim 4 , further comprising a metal layer electrically and thermally coupled to the bottom surface of the silicon backplane in a central region, the metal layer being spaced apart from the second redistribution layer.

6. The system of claim 1 , wherein the array of metal connectors is an array of copper pillar bumps.

7. The system of claim 1 further comprising a light emitting diode (LED) array electrically coupled to the array of metallic connectors.

8. The system of claim 7 , wherein the LED array is a monolithic LED array.

9. 10. The system of claim 8, wherein the monolithic LED array includes a plurality of emitters, each of the plurality of emitters having a width of 100 μm or less.

10. 10. The system of claim 9, wherein the plurality of emitters are arranged in rows and columns, and lanes between adjacent rows and columns have a width of 20 μm or less.

11. The system of claim 1 , wherein the substrate comprises a molding material.

12. The system of claim 1 , wherein the silicon backplane is a complementary metal-oxide semiconductor (CMOS) integrated circuit.

13. The system of claim 1 , wherein the silicon backplane is an application specific integrated circuit (ASIC).

14. at least one sensor; a controller communicatively coupled to the at least one sensor; a light emitting diode (LED) driver; an active headlamp communicatively coupled to the controller and electrically coupled to the LED driver, the active headlamp comprising: a silicon backplane having a top surface, a bottom surface, and a side surface; a substrate surrounding the side of the silicon backplane and having a top surface, a bottom surface, and a side surface; a redistribution layer overlying the top surface of the silicon backplane and the top surface of the substrate, the redistribution layer including at least one dielectric layer and at least one metal layer, the at least one metal layer extending from a peripheral region of the silicon backplane toward the side surface of the substrate and having at least a portion exposed from the at least one dielectric layer to form at least one bond pad; an LED array on the top surface of the silicon backplane; Vehicle headlamp system.

15. 15. The vehicle headlamp system of claim 14, wherein at least one of the at least one sensor, the controller, and the LED driver includes at least one passive component, the at least one passive component being electrically coupled to the at least one bond pad.

16. The active headlamp further includes a metal layer electrically and thermally coupled to the bottom surface of the silicon backplane; The vehicle headlamp system further includes a circuit board electrically and thermally coupled to the metal layer.

15. The vehicle headlamp system of claim 14.

17. 17. The vehicle headlamp system of claim 16, wherein the at least one passive component comprises a plurality of passive components, at least one of the plurality of passive components being on the circuit board.

18. 15. The vehicle headlamp system of claim 14, wherein the LED array is a monolithic LED array including a plurality of emitters, each of the plurality of emitters having a width of 100 [mu]m or less.

19. 20. The vehicle headlamp system of claim 18, wherein the plurality of emitters are arranged in rows and columns, with lanes between adjacent rows and columns having a width of 20 μm or less.

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