Image sensor

Abstract

To provide an image sensor which enables clear image quality.SOLUTION: Provided is an image sensor. The image sensor includes: a substrate, having a first surface and a second surface opposite thereto, which includes first to third pixels aligned in a first direction; a first pixel separation part, disposed in the substrate, which is interposed between the first pixel and the second pixel so as to separate them from each other; and a second pixel separation part, disposed in the substrate, which is interposed between the second pixel and the third pixel so as to separate them from each other. The first pixel separation part includes a first separation insulation pattern which covers a first conductive pattern and its lateral wall. The second pixel separation part includes a second separation insulation pattern which covers a second conductive pattern and its lateral wall. The first conductive pattern has a first width in the first direction, and the second conductive pattern has, in the first direction, a second width smaller than the first width.SELECTED DRAWING: Figure 5A

Description

[Technical field]

[0001] The present invention relates to an image sensor. [Background technology]

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. The image sensor can be classified into a charge coupled device (CCD) type and a complementary metal oxide semiconductor (CMOS) type. The CMOS type image sensor is abbreviated as a CMOS image sensor (CIS). The CIS has a plurality of pixels arranged two-dimensionally. Each pixel includes a photodiode (PD). The photodiode serves to convert incident light into an electrical signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,991,742B2 Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide an image sensor capable of realizing clear image quality.

[0005] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] To achieve the above object, an image sensor according to an embodiment of the present invention includes a substrate having a second surface opposite to a first surface, the substrate including first to third pixels arranged in a first direction; a first pixel isolation portion disposed within the substrate and interposed between the first pixel and the second pixel to isolate the first pixel and the second pixel; and a second pixel isolation portion disposed within the substrate and interposed between the second pixel and the third pixel to isolate the second pixel and the third pixel, the first pixel isolation portion including a first isolation insulating pattern covering a first conductive pattern and a sidewall thereof, the second pixel isolation portion including a second isolation insulating pattern covering a second conductive pattern and a sidewall thereof, the first conductive pattern having a first width in the first direction, and the second conductive pattern having a second width in the first direction that is smaller than the first width.

[0007] According to an embodiment of the present invention, there is provided an image sensor comprising: a substrate having a second surface opposite to a first surface, the substrate including first to third pixels arranged in a first direction; a first pixel isolation portion disposed within the substrate and interposed between the first pixel and the second pixel to isolate the first pixel from the second pixel; and a second pixel isolation portion disposed within the substrate and interposed between the second pixel and the third pixel to isolate the second pixel from the third pixel, the first pixel isolation portion including a first isolation insulating pattern covering a first conductive pattern and a sidewall thereof, the second pixel isolation portion including a second isolation insulating pattern excluding the first conductive pattern, the first pixel isolation portion having a first width in the first direction, and the second pixel isolation portion having a second width smaller than the first width in the first direction.

[0008] According to another embodiment of the present invention, there is provided an image sensor including a substrate having a second surface opposite to a first surface, the substrate including first to third pixels arranged in a first direction, a transfer gate arranged on the first surface of the substrate in each of the first to third pixels, a first interlayer insulating film covering the first surface of the substrate, a first pixel isolation portion arranged in the substrate and interposed between the first pixel and the second pixel to isolate the first pixel and the second pixel, a second pixel isolation portion arranged in the substrate and interposed between the second pixel and the third pixel to isolate the second pixel and the third pixel, a first light-shielding pattern arranged on the second surface of the substrate and overlapping with the first pixel isolation portion, and a second light-shielding pattern arranged on the second surface of the substrate and overlapping the first pixel isolation portion. and a second light-shielding pattern overlapping with a pixel separation portion, the first pixel separation portion including a first conductive pattern, a first isolation insulating pattern covering a sidewall thereof, and a first buried insulating pattern between the first conductive pattern and the first interlayer insulating film, the second pixel separation portion including a second conductive pattern, a second isolation insulating pattern covering a sidewall thereof, and a second buried insulating pattern between the second conductive pattern and the first interlayer insulating film, the first pixel separation portion having a first width in the first direction, the second pixel separation portion having a second width in the first direction that is smaller than the first width, the first light-shielding pattern having a third width in the first direction, and the second light-shielding pattern having a fourth width in the first direction that is smaller than the third width. Effect of the Invention

[0009] In the image sensor of the present invention, the second pixel isolation portion isolating unit pixels constituting one pixel group, and includes relatively less conductive patterns made of light-absorbing polysilicon than the first pixel isolation portion isolating pixel groups, or the conductive patterns are eliminated, thereby reducing or preventing light loss caused by absorption of incident light by polysilicon. This increases the amount of received light and photosensitivity, thereby realizing clear image quality. In addition, the second pixel isolation portion is relatively narrow, and therefore the overall size of the image sensor can be reduced, enabling high integration.

[0010] In the image sensor of the present invention, the second light blocking pattern located on the second pixel separating portion separating unit pixels constituting one pixel group has a width smaller than that of the first light blocking pattern located on the first pixel separating portion separating the pixel groups, so that the amount of light incident on the unit pixels constituting one pixel group can be relatively increased, thereby increasing the amount of received light and achieving clear image quality. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention; [Diagram 2] 1 is a circuit diagram of an active pixel sensor array of an image sensor according to an embodiment of the present invention. [Diagram 3] 1 is a plan view of an image sensor including a low refraction pattern according to an embodiment of the present invention; [Figure 4] 1 is a plan view of an image sensor including a pixel separator according to an embodiment of the present invention; [Figure 5A] FIG. 5 is a cross-sectional view taken along line AA' of FIG. 3 and / or FIG. 4 according to an embodiment of the present invention. [Figure 5B] 4 is a cross-sectional view taken along line AA' of FIG. 3 according to an embodiment of the present invention. [Figure 6] 1 is a plan view of an image sensor including a pixel separator according to an embodiment of the present invention; [Figure 7A] FIG. 7 is a cross-sectional view taken along line AA' of FIG. 6 according to an embodiment of the present invention. [Figure 7B] FIG. 7 is a cross-sectional view taken along line BB' of FIG. 6 according to an embodiment of the present invention. [Figure 8A] 5B is a diagram sequentially illustrating a process for manufacturing an image sensor having the cross-section of FIG. 5A. [Figure 8B] 5B is a diagram sequentially illustrating a process for manufacturing an image sensor having the cross-section of FIG. 5A. [Figure 9] FIG. 2 is a plan view of an image sensor according to an embodiment of the present invention. [Figure 10] FIG. 2 is a plan view of an image sensor according to an embodiment of the present invention. [Figure 11] 11 is a cross-sectional view taken along line AA' in FIG. 10. [Figure 12A] 1 is a plan view of an image sensor having a low refraction pattern according to an embodiment of the present invention; [Figure 12B] 1 is a plan view of an image sensor having a pixel separator according to an embodiment of the present invention; [Figure 13A] 1 is a plan view of an image sensor having a low refraction pattern according to an embodiment of the present invention; [Figure 13B] 1 is a plan view of an image sensor having a low refraction pattern according to an embodiment of the present invention; [Figure 14] 1 is a cross-sectional view of an image sensor according to an embodiment of the present invention. [Figure 15] 1 is a cross-sectional view of an image sensor according to an embodiment of the present invention. [Figure 16] 1 is a cross-sectional view of an image sensor according to an embodiment of the present invention. [Figure 17] 1 is a cross-sectional view of an image sensor according to an embodiment of the present invention. [Figure 18] 1 is a cross-sectional view of an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In order to more specifically explain the present invention, embodiments of the present invention will be described in more detail below with reference to the accompanying drawings.

[0013] FIG. 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention.

[0014] Referring to FIG. 1, the image sensor may include an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a correlated double sampler (CDS) 1006, an analog to digital converter (ADC) 1007, and an input / output buffer 1008.

[0015] The active pixel sensor array 1001 includes a plurality of unit pixels arranged two-dimensionally, and can convert an optical signal into an electrical signal. The active pixel sensor array 1001 can be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, from a row driver 1003. The converted electrical signal can be provided to a correlated double sampler 1006.

[0016] The row driver 1003 can provide a number of driving signals to the active pixel sensor array 1001 for driving a number of unit pixels according to the result decoded by the row decoder 1002. When the unit pixels are arranged in a matrix, a driving signal can be provided for each row.

[0017] A timing generator 1005 may provide timing and control signals to the row decoder 1002 and the column decoder 1004 .

[0018] The correlated double sampler (CDS) 1006 may receive, hold, and sample an electrical signal generated by the active pixel sensor array 1001. The correlated double sampler 1006 may double sample a specific noise level and a signal level according to an electrical signal, and output a difference level corresponding to the difference between the noise level and the signal level.

[0019] An analog-to-digital converter (ADC) 1007 can convert an analog signal corresponding to the difference level output from the correlated double sampler 1006 into a digital signal and output the digital signal.

[0020] The input / output buffer 1008 latches digital signals, and the latched signals can be sequentially output to a video signal processor (not shown) according to the results of decoding by the column decoder 1004 .

[0021] FIG. 2 is a circuit diagram of an active pixel sensor array of an image sensor according to an embodiment of the present invention.

[0022] 1 and 2, the sensor array 1001 includes a plurality of unit pixels UP, and the unit pixels UP may be arranged in a matrix shape. Each unit pixel UP may include a transfer transistor TX. Each unit pixel UP may further include logic transistors RX, SX, and DX. The logic transistor may be a reset transistor RX, a selection transistor SX, or a source follower transistor DX. The transfer transistor TX may include a transfer gate TG. Each unit pixel UP may further include a photoelectric conversion part PD and a floating diffusion region FD. The logic transistors RX, SX, and DX may be shared among the plurality of unit pixels UP.

[0023] The photoelectric conversion unit PD can generate and accumulate photocharges in proportion to the amount of light incident from the outside. The photoelectric conversion unit PD can include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX can transfer the charge generated in the photoelectric conversion unit PD to the floating diffusion region FD. The floating diffusion region FD can transfer and cumulatively store the charge generated in the photoelectric conversion unit PD. The source follower transistor DX can be controlled according to the amount of photocharges accumulated in the floating diffusion region FD.

[0024] The reset transistor RX can periodically reset the charge accumulated in the floating diffusion region FD. The drain electrode of the reset transistor RX can be connected to the floating diffusion region FD, and the source electrode can be connected to a power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX can be applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charge accumulated in the floating diffusion region FD can be discharged, and the floating diffusion region FD can be reset.

[0025] The source follower transistor DX including the source follower gate electrode SF can act as a source follower buffer amplifier. The source follower transistor DX can amplify the potential change at the floating diffusion region FD and output it to the output line Vout.

[0026] A selection transistor SX including a selection gate electrode SEL can select a unit pixel UP to be read out in a row unit. When the selection transistor SX is turned on, a power supply voltage VDD can be applied to a drain electrode of the source follower transistor DX.

[0027] Fig. 3 is a plan view of an image sensor including a low refraction pattern according to an embodiment of the present invention. Fig. 4 is a plan view of an image sensor including a pixel separator according to an embodiment of the present invention. Fig. 5A is a cross-sectional view taken along line A-A' in Fig. 3 and / or Fig. 4 according to an embodiment of the present invention.

[0028] 3, 4, and 5A, an image sensor 500 according to an embodiment of the present invention includes a first substrate 1. The first substrate 1 may be, for example, a silicon single crystal wafer, a silicon epitaxial layer, or a silicon on insulator (SOI) substrate. The first substrate 1 may be doped with impurities of a first conductivity type. For example, the first conductivity type may be P-type. The first substrate 1 includes a first surface 1a and a second surface 1b that are opposite to each other. The first substrate 1 may include a pixel array region APS and an edge region EG. The pixel array region APS may include a plurality of unit pixels UP. The edge region EG may correspond to a part of a connection region CNR of FIG. 14.

[0029] Pixel separators DTI1 and DTI2 may be disposed on the first substrate 1 to separate / limit the unit pixels UP in the pixel array region APS. The pixel separators DTI1 and DTI2 may be extended to the edge region EG. Four unit pixels UP adjacent to each other and arranged in two rows and two columns in the unit pixel UP may constitute one pixel group GP. The unit pixel UP may include first to fourth unit pixels UP(1) to UP(4) adjacent to each other in a clockwise direction. The first to fourth unit pixels UP(1) to UP(4) adjacent to each other may constitute first to fourth pixel groups GP(1) to GP(4). The first to fourth pixel groups GP(1) to GP(4) may be adjacent to each other in a clockwise direction. The first and second pixels UP(1) and UP(2) may be arranged along a first direction X. The fourth and third pixels UP(4) and UP(3) may be arranged along the first direction X. The fourth and first pixels UP(4), UP(1) may be arranged along a second direction Y intersecting the first direction X. The third and second pixels UP(3), UP(2) may be arranged along the second direction Y.

[0030] The pixel isolation parts DTI1 and DTI2 may include first and second pixel isolation parts DTI1 and DTI2. The first pixel isolation part DTI1 may surround the first to fourth pixel groups GP(1) to GP(4), respectively. The first pixel isolation part DTI1 may have a mesh shape in a plan view. As an example, referring to FIGS. 4 and 5A, the first pixel isolation part DTI1 is interposed between the third unit pixel UP(3) of the first pixel group GP(1) and the fourth unit pixel UP(4) of the second pixel group GP(2). The second pixel isolation part DTI2 is interposed between the fourth unit pixel UP(4) of the second pixel group GP(2) and the third unit pixel UP(3).

[0031] The second pixel isolation part DTI2 may protrude from a sidewall of the first pixel isolation part DTI1 and may be interposed between the first to fourth unit pixels UP(1) to UP(4). The second pixel isolation part DTI2 may have a cross shape in a plan view.

[0032] In the unit pixel UP, a photoelectric conversion unit PD may be disposed in the first substrate 1. The photoelectric conversion unit PD may be doped with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type may be, for example, N type. The N type impurities doped in the photoelectric conversion unit PD may form a PN junction with P type impurities doped in the surrounding first substrate 1 to provide a photodiode.

[0033] An isolation portion STI adjacent to the first surface 1a may be disposed in the first substrate 1. The isolation portion STI may be penetrated by the first and second pixel isolation portions DTI1 and DTI2. The isolation portion STI may define an active region ACT adjacent to the first surface 1a in each unit pixel UP. The active region ACT may be provided for the transistors TX, RX, DX, and SX of FIG. 2.

[0034] A transfer gate TG may be disposed on the first surface 1a of the first substrate 1 in each unit pixel UP. A portion of the transfer gate TG may be extended into the first substrate 1. The transfer gate TG may be a vertical type. Alternatively, the transfer gate TG may be a planar type that is not extended into the first substrate 1 and has a flat shape. A gate insulating film Gox may be interposed between the transfer gate TG and the first substrate 1. A floating diffusion region FD may be disposed in the first substrate 1 on one side of the transfer gate TG. The floating diffusion region FD may be doped with, for example, impurities of the second conductive type.

[0035] The image sensor 500 may be a rear light receiving image sensor. Light may be incident into the first substrate 1 through the second surface 1b of the first substrate 1. Electron-hole pairs may be generated at the PN junction by the incident light. The generated electrons may be transferred to the photoelectric conversion unit PD. When a voltage is applied to the transmission gate TG, the electrons may be transferred to the floating diffusion region FD.

[0036] In one unit pixel UP(3), UP(4), a reset gate RG may be disposed adjacent to the transmission gate TG on the first surface 1a. In another unit pixel UP(1), UP(2), a source follower gate SF and a selection gate SEL may be disposed adjacent to the transmission gate TG on the first surface 1a. The gates TG, RG, SF, and SEL may correspond to the gates of the transistors TX, RX, DX, and SX in FIG. 2, respectively. The gates TG, RG, SF, and SEL may overlap with the active region ACT. In this example, the reset transistor RX, selection transistor SX, and source follower transistor DX may be shared between two adjacent unit pixels UP.

[0037] The first surface 1a may be covered with a first interlayer insulating film IL. The first interlayer insulating film IL may be formed of a multi-layer film of at least one film selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a porous low dielectric film. A first wiring 15 may be disposed between or within the first interlayer insulating film IL. The floating diffusion region FD may be connected to the first wiring 15 by a first contact plug 17. The first contact plug 17 may penetrate a first interlayer insulating film IL that is closest (lowest layer) to the first surface 1a among the first interlayer insulating films IL in the pixel array region APS.

[0038] The first pixel isolation part DTI1 is located in a first trench 22a formed from the first surface 1a toward the second surface 1b. The second pixel isolation part DTI2 is located in a second trench 22b formed from the first surface 1a toward the second surface 1b. From the cross-section of FIG. 5A, the first pixel isolation part DTI1 and the first trench 22a may each have a first width W1 in the first direction X. The second pixel isolation part DTI2 and the second trench 22b may each have a second width W2 in the first direction X. The second width W2 is smaller than the first width W1. Since the second pixel isolation part DTI2 has the relatively narrow second width W2, the size of the image sensor can be reduced. Therefore, a highly integrated image sensor can be provided.

[0039] The first pixel isolation part DTI1 may include a first buried insulation pattern 12a, a first isolated insulation pattern 14a, and a first conductive pattern 16a. The first buried insulation pattern 12a may be interposed between the first conductive pattern 16a and the first interlayer insulating film IL. The first isolated insulation pattern 14a may be interposed between the first conductive pattern 16a and the first substrate 1 and between the first buried insulation pattern 12a and the first substrate 1.

[0040] The second pixel isolation part DTI2 may include a second buried insulation pattern 12b, a second isolated insulation pattern 14b, and a second conductive pattern 16b. The second buried insulation pattern 12b may be interposed between the second conductive pattern 16b and the first interlayer insulating film IL. The second isolated insulation pattern 14b may be interposed between the second conductive pattern 16b and the first substrate 1 and between the second buried insulation pattern 12b and the first substrate 1.

[0041] The buried insulating pattern 12x includes a first buried insulating pattern 12a and a second buried insulating pattern 12b. The isolated insulating pattern 14x includes a first isolated insulating pattern 14a and a second isolated insulating pattern 14b. The conductive pattern 16x includes a first conductive pattern 16a and a second conductive pattern 16b.

[0042] The second embedded insulating pattern 12b, the second isolated insulating pattern 14b, and the second conductive pattern 16b of the second pixel isolation part DTI2 associated with a given pixel group GP may include portions of the embedded insulating pattern 12x, the isolated insulating pattern 14x, and the conductive pattern 16x located within an area G defined in the first direction X and the second direction Y by the outermost boundary (e.g., the outermost sidewall) of the unit pixel UP of the given group.

[0043] The first buried insulating pattern 12a, the first isolated insulating pattern 14a, the second buried insulating pattern 12b, and the second isolated insulating pattern 14b may be formed of an insulating material having a refractive index different from that of the first substrate 1. The first buried insulating pattern 12a, the first isolated insulating pattern 14a, the second buried insulating pattern 12b, and the second isolated insulating pattern 14b may include, for example, silicon oxide. The first conductive pattern 16a and the second conductive pattern 16b may be separated from the first substrate 1. The first conductive pattern 16a and the second conductive pattern 16b may include a polysilicon film or a silicon germanium film doped with impurities. The impurities doped into the polysilicon or silicon germanium film may be, for example, one of boron, phosphorus, and arsenic. Alternatively, the first conductive pattern 16a and the second conductive pattern 16b may include a metal film.

[0044] In the cross section of Fig. 5A, the first isolated insulating pattern 14a may have the same first thickness T1 as the second isolated insulating pattern 14b. In the plan view of Fig. 4, the first thickness T1 of each of the first isolated insulating pattern 14a and the second isolated insulating pattern 14b may be constant regardless of position.

[0045] The first conductive pattern 16a may have a third width W3 in the first direction X. The second conductive pattern 16b may have a fourth width W4 in the first direction X. The fourth width W4 is smaller than the third width W3. If the first conductive pattern 16a and the second conductive pattern 16b are made of polysilicon, the polysilicon may absorb light. In the present invention, the second conductive pattern 16b having a relatively small fourth width W4 is interposed between the first to fourth unit pixels UP(1) to UP(4) constituting one pixel group GP, so that absorption of light incident within one pixel group GP can be prevented / minimized / reduced. Therefore, the amount of light received by the image sensor can be increased, and the quantum efficiency (QE) can be increased, and the light sensitivity can be improved. In addition, the autofocus function can be improved. Therefore, clear image quality can be realized.

[0046] The first buried insulating pattern 12a may have a third width W3 in the first direction X. The second buried insulating pattern 12b may have a fourth width W4 in the first direction X.

[0047] In the plane of FIG. 4, the first and third unit pixels UP(1) and UP(3) may be arranged side by side in a third direction Z that intersects with the first and second directions X and Y at the same time. The second pixel isolation part DTI2 may further include a third conductive pattern 16p disposed between the first and third unit pixels UP(1) and UP(3). The third conductive pattern 16p may be disposed between the second and fourth unit pixels UP(2) and UP(4). That is, the third conductive pattern 16p is disposed at the center of each pixel group GP. The third conductive pattern 16p may have a diagonal shape in a plane. The third conductive pattern 16p is disposed between the second conductive patterns 16b and connects them. The third conductive pattern 16p may have a ninth width (W9 in FIG. 4) in the third direction Z. The ninth width W9 may be equal to or greater than the fourth width W4.

[0048] A first fixed charge layer 24 is disposed on the second surface 1b of the first substrate 1. The first fixed charge layer 24 may be in contact with the second surface 1b of the first substrate 1. The first fixed charge layer 24 may be a single layer or multiple layers of a metal oxide layer or a metal fluoride layer containing oxygen or fluorine in an amount less than the stoichiometric ratio. Thus, the fixed charge layer may have a negative fixed charge. The first fixed charge layer 24 may be a single layer or multiple layers of a metal oxide or a metal fluoride containing at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides. As a specific example, the first fixed charge layer 24 may include a hafnium oxide layer and / or an aluminum oxide layer. The first fixed charge layer 24 may improve dark current and white spots.

[0049] A second fixed charge film 42 and a first protective film 44 may be sequentially stacked on the first fixed charge film 24. The second fixed charge film 42 may include a single film or multiple films of a metal oxide film or a metal fluoride film. The second fixed charge film 42 may include, for example, a hafnium oxide film and / or an aluminum oxide film. The second fixed charge film 42 may reinforce the first fixed charge film 24 or function as an adhesive film. The first protective film 44 may be formed of a material such as PETEOS, SiOC, SiO 2 , SiN The first protective film 44 can function as an anti-reflection film and / or a planarization film.

[0050] 4 and 5A, in the edge region EG, the connection contact BCA may penetrate the first passivation layer 44, the second fixed charge layer 42, the first fixed charge layer 24, and a portion of the first substrate 1 to contact the first conductive pattern 16a and the first isolation insulating pattern 14a. The connection contact BCA may be located in the third trench 46. The connection contact BCA may include a diffusion barrier pattern 48g conformally covering the inner sidewall and bottom surface of the third trench 46, a first metal pattern 52 on the diffusion barrier pattern 48g, and a second metal pattern 54 filling the third trench 46. The diffusion barrier pattern 48g may include, for example, titanium. The first metal pattern 52 may include, for example, tungsten. The second metal pattern 54 may include, for example, aluminum. The diffusion barrier pattern 48g and the first metal pattern 52 may be extended onto the first passivation layer 44 to be electrically connected to other wiring or via / contact.

[0051] In the pixel array region APS, first and second light-shielding patterns 48a and 48b may be disposed on the first passivation layer 44. First and second low refraction patterns 50a and 50b may be disposed on the first and second light-shielding patterns 48a and 48b, respectively. The first light-shielding pattern 48a and the first low refraction pattern 50a may overlap the first pixel isolation part DTI1 and have the same shape as the first pixel isolation part DTI1 in a plan view. That is, the first light-shielding pattern 48a and the first low refraction pattern 50a may surround the pixel groups GP(1) to GP(4) in a plan view. The second light-shielding pattern 48b and the second low refraction pattern 50b may overlap the second pixel isolation part DTI2 and have the same shape as the second pixel isolation part DTI2 in a plan view. The second light blocking patterns 48b and the second low refraction patterns 50b may be interposed between the first to fourth unit pixels UP(1) to UP(4) in each of the pixel groups GP(1) to GP(4).

[0052] The sidewalls of the first light blocking pattern 48a and the first low refraction pattern 50a may be aligned with each other. The first light blocking pattern 48a and the first low refraction pattern 50a may each have a fifth width W5 in the first direction X. The sidewalls of the second light blocking pattern 48b and the second low refraction pattern 50b may be aligned with each other. The second light blocking pattern 48b and the second low refraction pattern 50b may each have a sixth width W6 in the first direction X. The sixth width W6 may be equal to or smaller than the fifth width W5. When the sixth width W6 is smaller than the fifth width W5, the amount of light incident into the first to fourth unit pixels UP(1) to UP(4) constituting one pixel group GP may be relatively increased. Therefore, the amount of light received by the image sensor may be increased, and the quantum efficiency (QE) may be increased, thereby improving the photosensitivity.

[0053] The first and second light-shielding patterns 48a and 48b may have the same material and thickness as the diffusion prevention pattern 48g. The first and second light-shielding patterns 48a and 48b may include, for example, titanium.

[0054] The first and second low refraction patterns 50a and 50b may have the same thickness and may include the same organic material. The first and second low refraction patterns 50a and 50b may have a refractive index smaller than that of the color filters CF1 and CF2. For example, the first and second low refraction patterns 50a and 50b may have a refractive index of about 1.3 or less. The light blocking patterns 48a and 48b and the low refraction patterns 50a and 50b may prevent crosstalk between adjacent unit pixels UP.

[0055] A second protective layer 56 is stacked on the first protective layer 44. The second protective layer 56 may conformally cover the light blocking patterns 48a, 48b, the low refraction patterns 50a, 50b, and the connecting contact BCA. Color filters CF1, CF2 may be disposed between the low refraction patterns 50a, 50b in the pixel array region APS. Each of the color filters CF1, CF2 may have one of blue, green, and red. As another example, the color filters CAF1, CF2 may include other colors such as cyan, magenta, or yellow.

[0056] In this example, one color filter may be arranged on one pixel group GP. In the image sensor according to this example, the color filters CF1 and CF2 may be arranged in a 2x2 Tetra pattern. That is, a first color filter CF1 may be arranged on the second pixel group GP(2). A second color filter CF2 may be arranged on the first, third, or fourth pixel group GP(1), GP(3), or GP(4).

[0057] A first optical black pattern CFB may be disposed on the second passivation film 56 in the edge region EG. The first optical black pattern CFB may include, for example, the same material as a blue color filter.

[0058] In the pixel array region APS, a microlens ML may be disposed on the color filters CF1 and CF2. Edges of the microlenses ML may be in contact with each other and connected. In this example, one microlens ML may be disposed in one pixel group GP. That is, one microlens ML may cover the first to fourth unit pixels UP(1) to UP(4) that are disposed adjacent to each other. In the plan view of FIG. 4, the second pixel isolation part DTI2 may cross the center of the microlens ML.

[0059] A lens residual layer MLR may be disposed on the first optical black pattern CFB in the edge region EG. The lens residual layer MLR may include the same material as the microlenses ML. The image sensor 500 may be an autofocus image sensor.

[0060] A negative bias voltage may be applied to the first and second conductive patterns 16a and 16b through the connecting contact BCA. The first and second conductive patterns 16a and 16b may serve as a common bias line. Therefore, holes that may be present on the surface of the first substrate 1 in contact with the first and second pixel isolation parts DTI1 and DTI2 may be captured to improve dark current characteristics.

[0061] FIG. 5B is a cross-sectional view taken along line AA' of FIG. 3 according to an embodiment of the present invention.

[0062] 3 and 5B, in the image sensor 501 according to the present embodiment, the second pixel isolation part DTI2 may exclude the second conductive pattern 16b and the second buried insulating pattern 12b of FIG. 5A. The second pixel isolation part DTI2 may further include a third conductive pattern 16p as shown in FIG. 6, and in this case, the third conductive pattern 16p may be isolated without being connected to the second conductive pattern 16b. The second pixel isolation part DTI2 may include a void region VD located in the second isolated insulating pattern 14b. The second isolated insulating pattern 14b may include at least one inner surface 14bs defining the void region VD within the region of the second isolated insulating pattern 14b. The void region VD may be a seam. The void region VD may have a maximum fourth width W4. The fourth width W4 may be smaller than the third width W3 of the first conductive pattern 16a of the first pixel isolation part DTI1. At a point where the void region VD has a maximum width W4, the second isolation insulating pattern 14b may have a first thickness T1. The first thickness T1 may be the same as the thickness of the first isolation insulating pattern 14a of the first pixel isolation portion DTI1. The planar shape of the void region VD may be the same as or similar to the second conductive pattern 16b of Fig. 4. Other structures may be the same as or similar to those described with reference to Figs. 3 to 5A.

[0063] In the image sensor 501 of Fig. 5B, since there is no second conductive pattern 16b between the first to fourth unit pixels UP(1) to UP(4) constituting one pixel group GP, it is possible to prevent the light incident on one pixel group GP from being absorbed by the second conductive pattern 16b. Therefore, the amount of light received by the image sensor is increased, the QE (Quantum Efficiency) is increased, and the light sensitivity is improved. In addition, the autofocus function can be improved.

[0064] Fig. 6 is a plan view of an image sensor including a pixel separator according to an embodiment of the present invention. Fig. 7A is a cross-sectional view taken along line A-A' in Fig. 6 according to an embodiment of the present invention. Fig. 7B is a cross-sectional view taken along line B-B' in Fig. 6 according to an embodiment of the present invention.

[0065] 6, 7A, and 7B, in the image sensor 502 according to the present embodiment, the second pixel isolation part DTI2 may be formed only by the second isolation insulating pattern 14b. In this case, the second thickness T2 of the second isolation insulating pattern 14b may be the same as the second width W2 of the second pixel isolation part DTI or the second trench 22b. The second thickness T2 may be greater than the first thickness T1 of the first isolation insulating pattern 14a of the first pixel isolation part DTI1. The second pixel isolation part DTI2 may further include a third conductive pattern 16p, and in this case, the third conductive pattern 16p may be surrounded and isolated by the second isolation insulating pattern 14b. A sidewall of the first pixel isolation part DTI may have a concave-convex structure. In the cross section of FIG. 7A, the first conductive pattern 16a of the first pixel isolation part DTI may have a third width W3 in the first direction X. In the cross section of FIG. 7B, the first conductive pattern 16a of the first pixel isolation unit DTI may have a seventh width W7 in the first direction X. The seventh width W7 may be greater than the third width W3. In the cross section of FIG. 7B, the first conductive pattern 16a of the first pixel isolation unit DTI may have a seventh width W7 in the first direction X. The seventh width W7 may be greater than the third width W3. In the cross section of FIG. 7B, the third conductive pattern 16p may have an eighth width W8. The eighth width W8 may be less than the seventh width W7.

[0066] The second pixel isolation part DTI2 may further include a third buried insulation pattern 12p on the third conductive pattern 16p. The third buried insulation pattern 12p may include the same material as the first buried insulation pattern 12a. The third buried insulation pattern 12p may have a rhombic shape in a plan view. The third buried insulation pattern 12p may have an eighth width W8. Other structures may be the same / similar to those described with reference to FIGS. 3 to 5A.

[0067] In the image sensor 502 of Fig. 7A, since there is no second conductive pattern 16b between the first to fourth unit pixels UP(1) to UP(4) constituting one pixel group GP, it is possible to prevent the light incident within one pixel group GP from being absorbed by the second conductive pattern 16b. Therefore, the amount of light received by the image sensor is increased, the QE (Quantum Efficiency) is increased, and the light sensitivity is improved. In addition, the autofocus function can be improved.

[0068] 8A and 8B are views sequentially illustrating a process for manufacturing an image sensor having the cross section of FIG. 5A.

[0069] Referring to FIG. 8A, a first substrate 1 including a pixel array region APS and an edge region EG is prepared. An ion implantation process or the like is performed on the first substrate 1 to form a photoelectric conversion unit PD. An isolation unit STI is formed on a first surface 1a of the first substrate 1 to define an active region. The isolation unit STI may be formed by a shallow trench isolation process. A first mask pattern MK1 is formed on the first surface 1a of the first substrate 1. The isolation unit STI and a portion of the first substrate 1 are etched using the first mask pattern MK1 as an etching mask to form first and second trenches 22a and 22b. At this time, the first trench 22a may be formed to have a first width W1. The second trench 22b may be formed to have a second width W2 narrower than the first width W1.

[0070] An isolation insulating film 14 is conformally formed on the first surface 1a of the first substrate 1 with a first thickness T1. Thus, the isolation insulating film 14 may have the first thickness T1 in the first and second trenches 22a and 22b as well. The first thickness T1 may be smaller than 1 / 2 the second width W2. A conductive film 16 is deposited on the isolation insulating film 14 to fill the first and second trenches 22a and 22b. The conductive film 16 has a third width W3 in the first trench 22a. The conductive film 16 has a fourth width W4 in the second trench 22b.

[0071] Referring to FIG. 8B, an etch-back process is performed on the conductive film 16 to remove the conductive film 16 on the first surface 1a of the first substrate 1, and first and second conductive patterns 16a and 16b are formed in the first and second trenches 22a and 22b, respectively. In the etch-back process, the top surfaces of the first and second conductive patterns 16a and 16b are formed lower than the first surface 1a of the first substrate 1. Then, a buried insulating film is stacked to fill the tops of the first and second trenches 22a and 22b. Then, a polishing process is performed to remove the isolation insulating film 14 and the buried insulating film on the first surface 1a of the first substrate 1, and first and second isolation insulating patterns 14a and 14b and first and second buried insulating patterns 12a and 12b are formed in the first and second trenches 22a and 22b, respectively. Thus, first and second pixel isolation parts DTI1 and DTI2 can be formed.

[0072] Thereafter, other components may be formed through a normal process with reference to Figures 3 to 5A, except that the widths W5 and W6 of the first and second light blocking patterns 48a and 48b and the first and second low refraction patterns 50a and 50b may be formed to be different from each other as shown in Figure 5A.

[0073] In another example, since the second width W2 is narrow in the step of Fig. 8A, the isolation insulating film 14 can block the entrance of the second trench 22b. In this case, a void region VD can be formed in the second trench 22b as shown in Fig. 5B, or the second trench 22b can be filled only with the isolation insulating film 14 without the void region VD as shown in Fig. 7A. In this case, the conductive film 16 cannot enter the second trench 22b. Therefore, the image sensor of Fig. 5B or Fig. 7A can be formed.

[0074] Since polysilicon constituting the conductive pattern absorbs light, the greater the amount of polysilicon, the more the incident light is absorbed by the polysilicon, resulting in light loss and possibly reducing the sensitivity of the image sensor. If the first and second pixel isolation portions are all replaced with insulating film structures to prevent this, it becomes difficult to improve the dark current characteristics because a negative voltage cannot be applied to the conductive pattern.

[0075] In the present invention, the widths of the first and second pixel isolation parts are dualized to be different from each other, so that the structure / composition ratio of the first and second pixel isolation parts can be different. That is, the second pixel isolation part overlapping one microlens reduces or eliminates polysilicon to improve light sensitivity, and the first pixel isolation part DTI1 located at the boundary between the microlenses has a relatively wide polysilicon (first conductive pattern) and a negative voltage is applied thereto to improve dark current characteristics.

[0076] FIG. 9 is a plan view of an image sensor according to an embodiment of the present invention.

[0077] 9, the second pixel isolation part DTI2 of the image sensor 503 according to the present embodiment does not include the third conductive pattern 16p. That is, the third conductive pattern 16p is not disposed at the center of each of the pixel groups GP. A floating diffusion region FD is disposed in the first substrate 1 at the center of each of the pixel groups GP. The second pixel isolation part DTI2 does not exist at the center of each of the pixel groups GP. A transfer gate TG is disposed in the first to fourth unit pixels UP(1) to UP(4) in each of the pixel groups GP to surround the floating diffusion region FD. In each of the pixel groups GP, the first to fourth unit pixels UP(1) to UP(4) share one floating diffusion region FD. The other structures may be the same / similar to those described with reference to FIGS. 3 to 5A.

[0078] 10 is a plan view of an image sensor according to an embodiment of the present invention, and FIG 11 is a cross-sectional view taken along line AA' in FIG 10.

[0079] 10 and 11, in the image sensor 504 according to the present embodiment, microlenses ML may be disposed on unit pixels UP in a 1:1 ratio. That is, one microlens ML is disposed on one unit pixel UP. Also, color filters CF1 and CF2 may be disposed on unit pixels UP in a 1:1 ratio. That is, one color filter CF1 or CF2 is disposed on one unit pixel UP. The rest of the structure may be the same / similar to that described with reference to FIGS. 3 to 7B.

[0080] 12A and 12B are plan views of an image sensor having a low refraction pattern and a pixel separator according to an embodiment of the present invention.

[0081] 12A and 12B, in the image sensor 505 according to the present embodiment, one pixel group GP may include nine unit pixels UP(1) to UP(9) arranged in three rows and three columns. One microlens ML may be disposed on one pixel group GP. That is, one microlens ML may simultaneously cover nine unit pixels UP(1) to UP(9) arranged in three rows and three columns. One color filter CF1 or CF2 may be disposed on one pixel group GP. In the image sensor according to the present embodiment, the color filters CF1 and CF2 may be arranged in a Nona pattern shape of a 3x3 shape. The first pixel isolation part DTI1 may surround the pixel group GP. The second pixel isolation part DTI2 may be extended from a sidewall of the first pixel isolation part DTI1 and interposed between the unit pixels UP(1) to UP(9). In FIG. 12B, four third conductive patterns 16p may be disposed in one pixel group GP. The sixth width W6 of the second light blocking pattern 48b and the second low refraction pattern 50b overlapping the second pixel isolation portion DTI2 is smaller than the fifth width W5 of the first light blocking pattern 48a and the first low refraction pattern 50a overlapping the first pixel isolation portion DTI1. The rest of the configuration is the same / similar to that described above.

[0082] 13A and 13B are plan views of an image sensor having a low refraction pattern according to an embodiment of the present invention.

[0083] Referring to Fig. 13A, the image sensor 506 according to the present embodiment may include a super microlens SML. Specifically, the planar / sectional shapes of the first and second pixel isolation parts DTI1 and DTI2, the first light blocking pattern 48a, the first low refraction pattern 50a, the second light blocking pattern 48b, and the second low refraction pattern 50b may be the same / similar to those described with reference to Figs. 3 to 7B. The microlenses ML may be disposed on the first to fourth unit pixels UP(1) to UP(4), respectively. However, the third unit pixel UP(3) of the first pixel group GP(1) and the fourth unit pixel UP(4) of the second pixel group GP(2) adjacent thereto may be simultaneously covered by one super microlens SML. In a planar view, a first pixel isolation part DTI1, a first light shielding pattern 48a and / or a first low refraction pattern 50a may be arranged between the third unit pixel UP(3) of the first pixel group GP1 and the adjacent fourth unit pixel UP(4) of the second pixel group GP(2).

[0084] The third unit pixel UP(3) of the first pixel group GP1 covered with the super microlens SML and the fourth unit pixel UP(4) of the second pixel group GP(2) adjacent thereto may be used as an auto-focus (AF) pixel for an auto-focus function. The other first to fourth unit pixels UP(1) to UP(4) may be used as image pixels for image sensing. The other configurations are the same / similar to those described above.

[0085] 13B, in the image sensor 507 according to the present embodiment, the super microlens SML simultaneously covers the third and fourth unit pixels UP(3) and UP(4) of the first pixel group GP(1). In a plan view, the second pixel isolation part DTI2, the second light blocking pattern 48b, and / or the second low refraction pattern 50b may be disposed between the third and fourth unit pixels UP(3) and UP(4) of the first pixel group GP(1). The third and fourth unit pixels UP(3) and UP(4) of the first pixel group GP(1) covered by the super microlens SML may be used as AF (Auto-focus) pixels for an auto-focus function. The other first to fourth unit pixels UP(1) to UP(4) may be used as image pixels for image sensing. The other configurations may be the same / similar to those described in FIG. 13A.

[0086] FIG. 14 is a cross-sectional view of an image sensor according to an embodiment of the present invention.

[0087] 14, the image sensor 508 according to the present embodiment may have a structure in which a first sub-chip CH1 and a second sub-chip CH2 are bonded together. The first sub-chip CH1 may preferably perform an image sensing function. The second sub-chip CH2 may preferably include a circuit for driving the first sub-chip CH1 or storing an electrical signal generated by the first sub-chip CH1.

[0088] The second sub-chip CH2 may include a second substrate 100, a plurality of transistors TR disposed on the second substrate 100, a second interlayer insulating film 110 covering the second substrate 100, and a second wiring 112 disposed in the second interlayer insulating film 110. The second interlayer insulating film 110 may have a single layer or a multi-layer structure of at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous insulating film. The first sub-chip CH1 and the second sub-chip CH2 are bonded. Thus, the first interlayer insulating film IL and the second interlayer insulating film 110 may be in contact with each other.

[0089] The first sub-chip CH1 includes a first substrate 1 including a pad region PAD, a connection region CNR, an optical black region OB, and a pixel array region APS. The pixel array region APS and a part of the connection region CNR of the first sub-chip CH1 may have the same / similar structure as described with reference to FIGS. 3 to 13B. That is, the pixel array region APS may include a plurality of unit pixels UP. In the pixel array region APS, first and second pixel isolation parts DTI1 and DTI2 may be disposed on the first substrate 1 to isolate the unit pixels UP. The first substrate 1 may have an element isolation part STI disposed adjacent to a first surface 1a. In each of the unit pixels UP, a photoelectric conversion part PD may be disposed within the first substrate 1. In each of the unit pixels UP, a transfer gate TG may be disposed on the first surface 1a of the first substrate 1. A floating diffusion region FD may be disposed within the first substrate 1 on one side of the transfer gate TG. The first surface 1a may be covered with a first interlayer insulating film IL.

[0090] The optical black area OB may not be incident on the substrate 1. The first and second pixel separators DTI1 and DTI2 may be extended to the optical black area OB to separate the first black pixel UPO1 from the second black pixel UPO2. In the first black pixel UPO1, a photoelectric conversion unit PD may be disposed in the first substrate 1. In the second black pixel UPO2, no photoelectric conversion unit PD exists in the first substrate 1. A transmission gate TG and a floating diffusion region FD may be disposed in both the first black pixel UPO1 and the second black pixel UPO2. The first black pixel UPO1 may sense an amount of charge that may be generated from the photoelectric conversion unit PD when light is blocked, and provide a first reference amount of charge. The first reference amount of charge may be a relative reference value when calculating an amount of charge generated from the unit pixel UP. The second black pixel UPO2 may sense an amount of charge that may be generated in the absence of the photoelectric conversion unit PD, and provide a second reference amount of charge. The second reference charge amount can be used as information for removing process noise.

[0091] The first fixed charge layer 24, the second fixed charge layer 42, the first protective layer 44, and the second protective layer 56 may also be extended onto the second surface 1b on the optical black area OB, the connection area CNR, and the pad area PAD. The edge area EG described with reference to Figures 3 to 13B may correspond to a part of the connection area CNR in Figure 14.

[0092] In the connection region CNR, the connection contact BCA may penetrate the first passivation layer 44, the second fixed charge layer 42, the first fixed charge layer 24, and a portion of the first substrate 1 to contact the first conductive pattern 16a of the first pixel isolation part DTI1. The connection contact BCA may be located in a third trench 46. The connection contact BCA may include a first diffusion prevention pattern 48g conformally covering an inner sidewall and a bottom surface of the third trench 46, a first metal pattern 52 on the first diffusion prevention pattern 48g, and a second metal pattern 54 filling the third trench 36.

[0093] A portion of the first diffusion prevention pattern 48g may be extended onto the first protective film 44 on the optical black area OB to provide a third optical black pattern 48c. A portion of the first metal pattern 52 may be extended onto the first optical black pattern 48c on the optical black area OB to provide a second optical black pattern 52a. The second optical black pattern 52a and the connection contact BCA may be covered with a second protective film 56. A first optical black pattern CFB may be located on the protective film 56 in the optical black area OB and the connection area CNR.

[0094] A first via V1 may be disposed beside the connection contact BCA in the connection region CNR. The first via V1 may also be referred to as a back bias stack via. The first via V1 may penetrate the first passivation layer 44, the second fixed charge layer 42, the first fixed charge layer 24, the first substrate 1, the first interlayer insulating layer IL, and a portion of the second interlayer insulating layer 110 to contact a portion of the first wiring 15 and a portion of the second wiring 112 at the same time.

[0095] The first via V1 may be disposed within a first via hole H1. The first via V1 may include a second diffusion prevention pattern 48d and a first via pattern 52b on the second diffusion prevention pattern 48d. The second diffusion prevention pattern 48d may be connected to the first diffusion prevention pattern 48g. The first via pattern 52b may be connected to the first metal pattern 52. The connection contact BCA may be connected to a portion of the first wiring 15 and a portion of the second wiring 112 through the first via V1.

[0096] The second diffusion barrier pattern 48d and the first via pattern 52b may conformally cover the inner wall of the first via hole H1. The second diffusion barrier pattern 48d and the first via pattern 52b may not completely fill the first via hole H1. A first low refractive index residual film 50g may fill the first via hole H1. A color filter residual film CFR may be disposed on the first low refractive index residual film 50g.

[0097] An external connection pad 62 and a second via V2 connected to each other may be disposed in the pad area PAD. The external connection pad 62 may penetrate the first passivation layer 44, the second fixed charge layer 44, the first fixed charge layer 24, and a portion of the first substrate 1. The external connection pad 62 may be disposed in a fourth trench 60. The external connection pad 62 may include the third diffusion prevention pattern 48e and a first pad pattern 52c conformally covering an inner wall and a bottom surface of the fourth trench 60 in this order, and a second pad pattern 54a filling the fourth trench 60.

[0098] The second via V2 may penetrate the first passivation layer 44, the second fixed charge layer 42, the first fixed charge layer 24, the first substrate 1, the first interlayer insulating layer IL, and a portion of the second interlayer insulating layer 110 to contact a portion of the second wiring 112. The external connection pad 62 may be connected to a portion of the second wiring 112 through the second via V2. The second via V2 may be disposed in a second via hole H2. The second via V2 may include a fourth diffusion prevention pattern 48f and a second via pattern 52d conformally covering an inner wall and a bottom surface of the second via hole H2 in that order. The fourth diffusion prevention pattern 48f and the second via pattern 52d may not completely fill the second via hole H2. A second low refractive index residual film 50c may fill the second via hole H2. A color filter residual film CFR may be disposed on the second low refractive index residual film 50c.

[0099] The first and second light blocking patterns 48a, 48b, the first diffusion prevention pattern 48g, the first optical black pattern 48c, and the second to fourth diffusion prevention patterns 48d to 48f may have the same thickness and the same material (e.g., titanium). The first metal pattern 52, the second optical black pattern 52a, the first via pattern 52b, the first pad pattern 52c, and the second via pattern 52d may have the same thickness and the same material (e.g., tungsten). The second metal pattern 54 and the second pad pattern 54a may have the same material (e.g., aluminum).

[0100] The first and second low refraction patterns 50a and 50b, the first low refraction residual film 50g, and the second low refraction residual film 50c may have the same material as each other. The color filter residual film CFR may have the same color and material as one of the color filters CF1 and CF2.

[0101] The second passivation layer 56 may extend to the pad area PAD and have an opening exposing the second pad pattern 54a. A microlens residual layer MLR may cover the optical black area OB, the connection area CNR, and the pad area PAD. The microlens residual layer MLR may have an opening 35 exposing the second pad pattern 54a in the pad area PAD.

[0102] FIG. 15 is a cross-sectional view of an image sensor according to an embodiment of the present invention.

[0103] Referring to FIG. 15, an image sensor 509 according to the present embodiment may have a structure in which first to third sub-chips CH1 to CH3 are bonded in sequence. The first sub-chip CH1 may preferably perform an image sensing function. The first sub-chip CH1 may be the same / similar to that described with reference to FIGS. 3 to 13B. The first sub-chip CH1 may include a transfer gate TG and a first interlayer insulating film IL1 covering the transfer gate TG on a first surface 1a of a first substrate 1. A first device isolation part STI1 is disposed in the first substrate 1 to define an active region. A first conductive pad CP1 may be disposed in the first interlayer insulating film IL1 at the bottom layer. The first conductive pad CP1 may include copper.

[0104] The second sub-chip CH2 may include a second substrate 200, a selection gate SEL, a source follower gate SF, and a reset gate (not shown) disposed thereon, and a second interlayer insulating film IL2 covering them. A second device isolation part STI2 is disposed on the second substrate 200 to define an active region. A second contact 217 and a second wiring 215 may be disposed in the second interlayer insulating film IL2. A second conductive pad CP2 may be disposed in the uppermost second interlayer insulating film IL2. The second conductive pad CP2 may include copper. The second conductive pad CP2 may be in contact with the first conductive pad CP1. The source follower gate SF may be connected to a floating diffusion region FD of the first sub-chip CH1, respectively.

[0105] The third sub chip CH3 may include a third substrate 300, a peripheral transistor PTR disposed thereon, and a third interlayer insulating film IL3 covering the third substrate 300. A third isolation part STI3 is disposed in the third substrate 300 to define an active region. A third contact 317 and a third wiring 315 may be disposed in the third interlayer insulating film IL3. The uppermost third interlayer insulating film IL3 contacts the second substrate 200. The through electrode TSV may connect the second wiring 215 and the third wiring 315 by penetrating the second interlayer insulating film IL2, the second isolation part STI2, the second substrate 200, and the third interlayer insulating film IL3. A sidewall of the through electrode TSV may be surrounded by a via insulating film TVL. The third sub chip CH3 may include a circuit for driving the first and / or second sub chips CH1 and CH2 or storing an electrical signal generated in the first and / or second sub chips CH1 and CH2.

[0106] FIG. 16 is a cross-sectional view of an image sensor according to an embodiment of the present invention.

[0107] 16, in an image sensor 510 according to this embodiment, the first light blocking pattern 48a and the first low refraction pattern 50a may each have a fifth width W5 in the first direction X. The second light blocking pattern 48b and the second low refraction pattern 50b may each have a sixth width W6 in the first direction X. The sixth width W6 may be equal to the fifth width W5.

[0108] The first pixel isolation part DTI1 and the first trench 22a may each have a first width W1 in the first direction X. The second pixel isolation part DTI2 and the second trench 22b may each have a second width W2 in the first direction X. The second width W2 is smaller than the first width W1. The sixth width W6 may be the same as or different from the second width W2. The sixth width W6 may be larger than the second width W2. The rest of the structure may be the same as that described with reference to FIG. 5A.

[0109] FIG. 17 is a cross-sectional view of an image sensor according to an embodiment of the present invention.

[0110] 17, an image sensor 511 according to this embodiment does not include or can eliminate the first light-shielding pattern 48a and the second light-shielding pattern 48b of FIG. 5A. That is, the bottom surfaces of the first low refraction pattern 50a and the second low refraction pattern 50b can be in direct contact with the first passivation film 44. The rest of the structure can be the same as that described with reference to FIG. 5A.

[0111] FIG. 18 is a cross-sectional view of an image sensor according to an embodiment of the present invention.

[0112] 18, the image sensor 512 according to this embodiment may not include a connecting contact BCA. In FIG. 18, an edge region EG is not shown. However, in the edge region EG, a first contact plug 17 may penetrate the first buried insulating pattern 12a and contact the first conductive pattern 16a of the first pixel isolation part DTI1. A negative bias voltage may be applied to the first and second conductive patterns 16a and 16b through the first contact plug 17. The other structures may be the same as those described with reference to FIG. 5A.

[0113] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. The embodiments of Figures 3 to 15 can be combined with each other. [Explanation of symbols]

[0114] 1 Board 12a, 12b, 12x buried insulating patterns 14a, 14b, 14x Separate insulating patterns 16a, 16b, 16x Conductive patterns 17 Contact plug 24, 42 Fixed charge membrane 44, 56 Protective film 500 Image Sensor ACT active region APS pixel array area BCA Connecting Contact DTI1, DTI2 pixel separation section EG Border Area FD Floating diffusion area Gox Gate Insulator GP Pixel Group IL Interlayer insulating film PD Photoelectric conversion unit RG Reset Gate SEL Select Gate SF Source Follower Gate STI element isolation section TG Transmission Gate UP unit pixel

Claims

1. An image sensor, wherein the image sensor is A substrate having, in a plan view, a first surface, a second surface opposite to the first surface, a pixel array region, and an optical black region adjacent to the pixel array region, The optical black pattern on the aforementioned optical black region, A first pixel group within the pixel array region includes first to fourth pixels arranged in a first 2x2 matrix, A second pixel group within the pixel array region, including fifth to eighth pixels arranged in a second 2x2 matrix, A first microlens covering the first to fourth pixels, A second microlens covering the fifth to eighth pixels, A first trench is provided within the substrate, and in a plan view, surrounds the first pixel group and the second pixel group, The substrate includes a second trench comprising a first portion located between the first and second pixels in a plan view, a second portion located between the second and third pixels, a third portion located between the third and fourth pixels, and a fourth portion located between the first and fourth pixels. The first to fourth pixels are arranged in a 2x2 matrix and are sequentially arranged in a clockwise direction. The first part is spaced apart from the third part in a first direction in a plan view, The second portion is spaced apart from the fourth portion in a second direction perpendicular to the first direction in the plan view, The width of the first trench in the first direction between the first pixel group and the second pixel group on the second surface is different from the width of the first portion on the second surface in the first direction. The image sensor is configured to receive light from the second surface. Image sensor.

2. The image sensor according to claim 1, wherein each of the first and second trenches penetrates the substrate.

3. A first embedded insulating pattern provided in the first trench and in contact with the second surface, The image sensor according to claim 2, further comprising a second embedded insulating pattern provided in the second trench and in contact with the second surface.

4. The first embedded insulating pattern is spaced apart from the first surface, The image sensor according to claim 3, wherein the second embedded insulating pattern is spaced apart from the first surface.

5. Further comprising a floating diffusion region shared by the first to fourth pixels, The image sensor according to claim 4, wherein the width of the floating diffusion region in the first direction in the plan view is greater than the width of the first portion in the first direction in the plan view.

6. Further comprising a floating diffusion region shared by the first to fourth pixels, The image sensor according to claim 4, wherein the width of the floating diffusion region in the second direction in the plan view is greater than the width of the fourth portion in the second direction in the plan view.

7. A first color filter covering the first to fourth pixels, The image sensor according to claim 5, further comprising a second color filter covering the fifth to eighth pixels.

8. The image sensor according to claim 7, wherein the floating diffusion region is located in the center of the first pixel group in the plan view.

9. An image sensor, wherein the image sensor is A substrate having, in a plan view, a first surface, a second surface opposite to the first surface, a pixel array region, and an optical black region adjacent to the pixel array region, The optical black pattern on the aforementioned optical black region, A first pixel group within the pixel array region includes first to fourth pixels arranged in a first 2x2 matrix, A second pixel group within the pixel array region, including fifth to eighth pixels arranged in a second 2x2 matrix, A first color filter covering the first to fourth pixels, A second color filter covering the fifth to eighth pixels, A first trench is provided within the substrate, and in a plan view, surrounds the first pixel group and the second pixel group, The substrate includes a second trench having a first portion positioned between the first and second pixels in a plan view, a second portion positioned between the second and third pixels, a third portion positioned between the third and fourth pixels, and a fourth portion positioned between the first and fourth pixels. The first to fourth pixels are arranged in a 2x2 matrix and are sequentially arranged in a clockwise direction. The first part is spaced apart from the third part in a first direction in a plan view, The second portion is spaced apart from the fourth portion in a second direction perpendicular to the first direction in the plan view, The width in the first direction of the first trench between the first pixel group and the second pixel group on the second surface is different from the width in the first direction of the first portion on the second surface. The image sensor is configured to receive light from the second surface. Image sensor.

10. A first pattern for embedding the second trench, In a vertical view, the second pattern is positioned between the side wall of the second trench and the first pattern, The present invention further includes a third pattern positioned between the first pattern and the first surface, The first pattern is in contact with the second surface, The image sensor according to claim 9, wherein the third pattern is in contact with the first surface.

11. The image sensor according to claim 10, wherein the second pattern and the third pattern include silicon oxide.

12. The image sensor according to claim 10, wherein the first pattern includes a metal layer.

13. Further comprising a floating diffusion region shared by the first to fourth pixels, The image sensor according to claim 11, wherein the width of the floating diffusion region in the first direction in the plan view is greater than the width of the first portion in the first direction in the plan view.

14. Further comprising a floating diffusion region shared by the first to fourth pixels, The image sensor according to claim 11, wherein the width of the floating diffusion region in the second direction in the plan view is greater than the width of the fourth portion in the second direction in the plan view.

15. A first microlens covering the first to fourth pixels, The image sensor according to claim 13, further comprising a second microlens covering the fifth to eighth pixels.

16. A fourth pattern for embedding the first trench, In the aforementioned vertical view, a fifth pattern is positioned between the side wall of the first trench and the fourth pattern, The present invention further includes a sixth pattern positioned between the fourth pattern and the first surface, The fourth pattern is in contact with the second surface, The sixth pattern is in contact with the first surface, as described in claim 13.

17. The image sensor according to claim 1, wherein the width in the first direction of the first trench between the first pixel group and the second pixel group on the second surface is different from the width in the first direction of the first trench on the first surface.

18. The image sensor according to claim 17, wherein each of the first trench and the second trench penetrates the substrate.

19. The image sensor according to claim 17, wherein the floating diffusion region is located in the center of the first pixel group in the plan view.

20. An image sensor, wherein the image sensor is A substrate having, in a plan view, a first surface, a second surface opposite to the first surface, a pixel array region, and an optical black region adjacent to the pixel array region, The optical black pattern on the aforementioned optical black region, A first pixel group within the pixel array region includes first to fourth pixels arranged in a first 2x2 matrix, A second pixel group within the pixel array region, including fifth to eighth pixels arranged in a second 2x2 matrix, A first microlens covering the first to fourth pixels, A second microlens covering the fifth to eighth pixels, A first trench is provided within the substrate, and in a plan view, surrounds the first pixel group and the second pixel group, The substrate is provided and includes a second trench comprising: a first portion positioned between the first and second pixels in a plan view; a second portion positioned between the second and third pixels; a third portion positioned between the third and fourth pixels; and a fourth portion positioned between the first and fourth pixels. The first to fourth pixels are arranged in a 2x2 matrix and are sequentially arranged in a clockwise direction. The first part is spaced apart from the third part in a first direction in a plan view, The second portion is spaced apart from the fourth portion in a second direction perpendicular to the first direction in the plan view, The width of the first trench in the first direction between the first pixel group and the second pixel group on the second surface is different from the width of the first portion on the second surface in the first direction. The width of the first trench in the first direction between the first pixel group and the second pixel group on the second surface is different from the width of the first trench in the first direction on the first surface. Each of the first and second trenches is filled with a metal layer. The image sensor is configured to receive light from the second surface. Image sensor.

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