Semiconductor package and drive apparatus

Abstract

To decrease the effect of offset in a semiconductor package having Hall elements built therein.SOLUTION: A semiconductor package 100 includes a semiconductor chip having a plurality of Hall elements 111 built therein, and a plurality of external terminals 102 arranged on one surface side of the semiconductor chip. A Hall element 111S1 belonging to a first group and a Hall element 111S2 belonging to a second group are arranged to be point-symmetrical with respect to a center point P of the semiconductor package in a plan view. The Hall element 111S1 is at least partially covered by an external terminal 102A1 among the plurality of external terminals in a plan view, and the Hall element 111S2 is at least partially covered by an external terminal 102B1 among the plurality of external terminals in a plan view. A region R1 covered by the external terminal 102A1 of the Hall element 111S1 in a plan view and a region R2 covered by the external terminal 102B1 of the Hall element 111S2 in a plan view are point-symmetrical with respect to the center point P of the semiconductor package in a plan view.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a semiconductor package and a drive device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor package having terminals arranged in a staggered pattern along the longitudinal direction. Patent Document 2 discloses a method and device for compensating a Hall sensor for both temperature and mechanical stress. Patent Document 3 discloses reducing offset by switching the direction of the drive current of the Hall element. [Prior art document] [Patent documents] [Patent Document 1] Patent No. 6826088 [Patent Document 2] Patent No. 6371338 [Patent Document 3] Patent No. 5658715 Summary of the Invention [Problem to be solved by the invention]

[0003] It is desirable to reduce the effect of offset in a semiconductor package incorporating a Hall element. [Means for solving the problem]

[0004] A semiconductor package according to an aspect of the present invention may include a semiconductor chip having a plurality of Hall elements built therein and a plurality of external terminals arranged on one surface side of the semiconductor chip. The semiconductor package may be rectangular extending in a first direction in a plan view. The plurality of external terminals may include a plurality of first external terminals included in a first row along the first direction, and a plurality of second external terminals facing the first row across the center of the semiconductor package and included in a second row along the first direction. The centers of gravity of the plurality of first external terminals may not overlap with the centers of gravity of the plurality of second external terminals in the first direction and in a second direction intersecting the first direction. The plurality of Hall elements may include a first Hall element and a second Hall element. The first Hall element and the second Hall element may be arranged point-symmetrically with respect to a center point of the semiconductor package in a plan view. The first Hall element may be at least partially covered by the first external terminal of the plurality of first external terminals in a plan view. The second Hall element may be at least partially covered by a second external terminal of the plurality of second external terminals in a plan view. A first region of the first Hall element covered by the first external terminal in a plan view and a second region of the second Hall element covered by the second external terminal in a plan view may be point-symmetric with respect to the point at the center of the semiconductor package in a plan view.

[0005] In the semiconductor package, the Hall elements may include the first Hall element and the third Hall element belonging to a first group, and the second Hall element and the fourth Hall element belonging to a second group. The third Hall element and the fourth Hall element may be arranged point-symmetrically with respect to the point at the center of the semiconductor package in a plan view.

[0006] In any of the semiconductor packages, when the semiconductor package is divided into a first event area, a second event area, a third event area, and a fourth event area in a planar view with a first axis along the first direction and a second axis along the second direction passing through the center of the semiconductor package, the first Hall element and the third Hall element may be arranged on the first event area, and the second Hall element and the fourth Hall element may be arranged on the third event area, or the first Hall element and the third Hall element may be arranged on the second event area, and the second Hall element and the fourth Hall element may be arranged on the fourth event area.

[0007] In any of the semiconductor packages, the semiconductor chip may further incorporate a control circuit that outputs a drive signal to control a drive unit that changes the position or attitude of a magnet relatively to the semiconductor package based on the sum of outputs indicating the magnitude of a magnetic field output from the first Hall element, the second Hall element, the third Hall element, and the fourth Hall element.

[0008] In any of the semiconductor packages, the control circuit may include an amplifier circuit that amplifies the sum of the outputs.

[0009] In any of the semiconductor packages, the control circuit may control the drive unit further based on a difference between a sum of outputs indicating the magnitude of a magnetic field output from the first Hall element and the third Hall element and a sum of outputs indicating the magnitude of a magnetic field output from the second Hall element and the fourth Hall element.

[0010] In any of the semiconductor packages, the control circuit may include an amplifier circuit that amplifies a ratio of the sum of outputs indicating the magnitude of the magnetic field output from the first Hall element, the second Hall element, the third Hall element, and the fourth Hall element to the difference.

[0011] In any of the semiconductor packages, the plurality of external terminals may include a pair of power supply terminals for supplying power to the semiconductor package, a pair of drive terminals for outputting a drive signal from the control circuit to the drive unit, and a pair of communication terminals for communicating with the outside. The first external terminal and the second external terminal may be one of the pair of drive terminals and one of the pair of power supply terminals.

[0012] In any of the semiconductor packages, the third Hall element and the fourth Hall element may not overlap any of the plurality of external terminals in a plan view.

[0013] In any one of the semiconductor packages, the first Hall element may be entirely covered by the first external terminal in a planar view, and the second Hall element may be entirely covered by the second external terminal in a planar view.

[0014] In any of the semiconductor packages, the first Hall element and the third Hall element may be entirely covered by the first external terminal in a plan view, and the second Hall element and the fourth Hall element may be entirely covered by the second external terminal in a plan view.

[0015] In any of the semiconductor packages, the first Hall element and the second Hall element may have a pair of first electrodes facing each other in the first direction and a pair of second electrodes facing each other in a second direction intersecting the first direction. In the first Hall element, the pair of first electrodes may be output electrodes. In the second Hall element, the pair of second electrodes may be output electrodes.

[0016] In any of the semiconductor packages, the first Hall element may be entirely covered by the first external terminal in a planar view. The second Hall element may be entirely covered by the second external terminal in a planar view. The third Hall element may be partially covered by the first external terminal in a planar view. The fourth Hall element may be partially covered by the second external terminal in a planar view.

[0017] In any of the semiconductor packages, the third Hall element and the fourth Hall element may have a pair of first electrodes facing each other in the first direction and a pair of second electrodes facing each other in a second direction intersecting the first direction. In the third Hall element, the pair of second electrodes may be output electrodes. In the fourth Hall element, the pair of first electrodes may be output electrodes.

[0018] In any one of the semiconductor packages, each of the first external terminal and the second external terminal may be an external terminal that is located closest to the point at the center of the semiconductor package in a plan view among the plurality of external terminals.

[0019] In any of the semiconductor packages, the first external terminal and the second external terminal may be point-symmetric with respect to the point at the center of the semiconductor package in a plan view.

[0020] In any of the semiconductor packages, the first Hall element and the third Hall element may be arranged in a line along the first direction, and the second Hall element and the fourth Hall element may be arranged in a line along the first direction.

[0021] In any of the semiconductor packages, the third Hall element and the fourth Hall element may be arranged in a row along a second direction intersecting the first direction.

[0022] In any one of the semiconductor packages, a width of the semiconductor package in the first direction may be greater than a width of the semiconductor package in a second direction intersecting the first direction.

[0023] In any one of the semiconductor packages, the width in the first direction may be 1.65 times or more longer than the width in the second direction.

[0024] In any one of the semiconductor packages, the width in the first direction may be 2.5 times or more longer than the width in the second direction.

[0025] In any one of the semiconductor packages, the total area of ​​the plurality of external terminals in a planar view may be 14% or more of the area of ​​the semiconductor package in a planar view.

[0026] In any one of the semiconductor packages, the total area of ​​the plurality of external terminals in a planar view may be 19% or more of the area of ​​the semiconductor package in a planar view.

[0027] In any one of the semiconductor packages, the external terminals may be arranged in two rows along the first direction.

[0028] The semiconductor package may further include a redistribution layer disposed above the semiconductor chip and electrically connected to the semiconductor chip, and a sealing material disposed above the redistribution layer, and the plurality of external terminals may be electrically connected to the redistribution layer via the sealing material.

[0029] In any of the semiconductor packages, the redistribution layer may include wiring that extends 100 μm or more along the first direction from at least one of the plurality of external terminals and is electrically connected to the semiconductor chip.

[0030] In any one of the semiconductor packages, the wiring may have a portion that extends on a line along the first direction that passes through a center of the at least one external terminal in a plan view.

[0031] In any one of the semiconductor packages, the redistribution layer may include wiring that extends 100 μm or more along the second direction from at least one of the plurality of external terminals and is electrically connected to the semiconductor chip.

[0032] A wafer level chip size package (WL-CSP) may be used.

[0033] A driving device according to an aspect of the present invention may include a first portion that holds a magnet. The driving device may include a second portion that holds any one of the semiconductor packages so as to face the magnet, the second portion being held by the first portion such that a position or attitude of the second portion can be changed relative to the first portion. The driving device may include a driving unit that changes a position or attitude of the second portion relative to the first portion. The semiconductor package may output a driving signal to the driving unit based on outputs from the multiple Hall elements.

[0034] In the driving device, the first portion may further hold a lens portion, and the second portion may further hold an imaging element that captures an image formed through the lens portion.

[0035] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0036] [Figure 1] FIG. 2 is an exploded perspective view of the camera module. [Diagram 2] FIG. 2 is a diagram illustrating an example of a circuit configuration of a semiconductor package. [Diagram 3] 11 is a diagram showing how the offset amount increases by amplifying the output signal of a magnetic sensor; [Figure 4] FIG. 2 is a plan view of the conductor package as viewed from the external terminal side. [Diagram 5] FIG. 5 is a diagram showing a schematic cross section taken along the line AA in FIG. [Figure 6] 6 is a diagram showing the relationship between the moving distance of the lens unit and the magnitude of the magnetic field detected by the magnetic sensor. [Figure 7] FIG. 4 is a diagram showing an example of an arrangement of a plurality of Hall elements; [Figure 8] FIG. 4 is a diagram showing an example of an arrangement of a plurality of Hall elements; [Figure 9] FIG. 4 is a diagram showing an example of an arrangement of a plurality of Hall elements; [Figure 10] FIG. 4 is a diagram showing an example of an arrangement of a plurality of Hall elements; [Figure 11] FIG. 4 is a diagram showing an example of an arrangement of a plurality of Hall elements; [Figure 12] FIG. 4 is a diagram showing an example of an arrangement of a plurality of Hall elements; [Figure 13] FIG. 4 is a diagram showing an example of an arrangement of a plurality of Hall elements; [Figure 14] FIG. 4 is a diagram showing an example of an arrangement of a plurality of Hall elements; [Figure 15] FIG. 2 is a diagram showing an equivalent circuit of a Hall element. [Figure 16A] FIG. 2 is a diagram showing an equivalent circuit of a Hall element 111S1. [Figure 16B] FIG. 13 is a diagram showing an equivalent circuit of a Hall element 111S2. [Figure 16C] FIG. 13 is a diagram showing an equivalent circuit of a Hall element 111S3. [Figure 16D] FIG. 13 is a diagram showing an equivalent circuit of a Hall element 111S4. [Figure 17] 2 is a diagram for explaining the function of each external terminal. FIG. [Figure 18] FIG. 2 is a diagram showing a wiring state in a rewiring layer of a semiconductor package. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0038] 1 shows an exploded perspective view of a camera module 10 according to this embodiment. The camera module 10 includes a substrate 300, a base 20, a holding frame 30, and a lens unit 40. An image sensor 302 is disposed on the substrate 300. The image sensor 302 may be configured with a CCD or CMOS. The image sensor 302 outputs image data of an optical image formed via the lens unit 40.

[0039] The holding frame 30 holds the lens unit 40 inside. A magnet 32 ​​is arranged on the outer surface of the holding frame 30. The base 20 holds the holding frame 30 together with the lens unit 40 so as to be movable in the optical axis direction (Z-axis direction) of the lens unit 40 and in directions intersecting the optical axis (X-axis and Y-axis directions). A coil 200 and a semiconductor package 100 are arranged on the side of the base 20. The coil 200 is arranged in a position facing the magnet 32. The coil 200 may be an air-core coil.

[0040] The magnet 32 ​​and the coil 200 function as a VCM (voice coil motor) that is a drive source that moves or rotates the holding frame 30 relative to the base 20. The holding frame 30 is an example of a first part, and the base 20 is an example of a second part.

[0041] When a current is passed through the coil 200 in the magnetic field of the magnet 32, a force is generated in the coil 200 in a direction perpendicular to the magnetic field. This applies a thrust along the X or Y direction to the holding frame 30. The arrangement of the coil 200 or the direction of the magnetic field of the magnet 32 ​​may be designed so that a thrust along the Z direction is applied to the holding frame 30 by passing a current through the coil 200.

[0042] The semiconductor package 100 is disposed in the air-core portion of the coil 200. The semiconductor package 100 may function as a position sensor that detects the position or posture of the holding frame 30 relative to the base 20. The position sensor may be a magnetic sensor including a Hall element. The position sensor may output a voltage with a magnitude according to a change in the magnetic field. When the holding frame 30 moves, the positional relationship between the semiconductor package 100 and the magnet 32 ​​changes, and the magnitude of the magnetic field detected at the position changes. As a result, the position sensor detects the position of the magnet 32 ​​relative to the semiconductor package 100, that is, the position of the holding frame 30 relative to the base 20. In this embodiment, as the magnetic sensor, a magnetic sensor including a Hall element that applies the Hall effect and detects a change in an external magnetic field from the generated electromotive force will be described as an example. However, the magnetic sensor is not limited to a form having a Hall element. The magnetic sensor may have an electromagnetic conversion element other than a Hall element. The magnetic sensor may be any of various sensors capable of detecting a magnetic field, such as a spin-valve type magnetoresistance effect element (GMR element, TMR element, etc.) whose resistance changes in response to a change in an external magnetic field, or may be a combination of such various sensors. The magnetic sensor may also be composed of a sensor element group consisting of a plurality of magnetic sensor elements.

[0043] The semiconductor package 100 supplies a current to the coil 200 so as to bring the position or attitude of the holding frame 30 to a target position or attitude depending on the position or attitude of the holding frame 30 with respect to the base 20. The semiconductor package 100 may be provided outside the coil 200. Furthermore, the holding frame 30 may include the semiconductor package 100 and the coil 200, and the base 20 may include the magnet 32.

[0044] In the camera module 10 configured in this manner, the magnet 32 ​​and the coil 200 are used as driving sources, and the semiconductor package 100 passes a current through the coil 200 so that the position or attitude of the lens unit 40 relative to the imaging surface of the imaging element 302 becomes a desired position or attitude. This causes the lens unit 40 to function as a zoom lens or a focus lens. Alternatively, the semiconductor package 100 performs image blur correction by passing a current through the coil 200 so that the position or attitude of the lens unit 40 is changed in a direction that cancels image blur. In this embodiment, a VCM (voice coil motor) is used as an example of a driving source that drives the lens unit 40. However, the driving source is not limited to a VCM. The camera module 10 may have a microelectromechanical system (MEMS), a shape memory alloy (SMA), a polymer actuator (EAP), a bimetal actuator, or a piezoelectric element, in addition to a VMC, as a driving source that drives the lens unit 40.

[0045] 2 is a diagram showing an example of a circuit configuration of the semiconductor package 100. The semiconductor package 100 includes a magnetic sensor 112, an amplifier 113, an A / D converter 114, a PID control unit 115, a D / A converter 116, and an output driver 117. The magnetic sensor 112, the amplifier 113, the A / D converter 114, the PID control unit 115, the D / A converter 116, and the output driver 117 may be built into a semiconductor chip.

[0046] The magnetic sensor 112 has a plurality of Hall elements, and outputs a voltage or current whose magnitude corresponds to the magnitude of the magnetic field as a position signal indicating the position of the lens unit 40. The amplifier 113 amplifies the position signal output from the magnetic sensor 112. The A / D converter 114 converts the analog signal, which is the position signal amplified by the amplifier 113, into a digital signal.

[0047] PID control unit 115 outputs a drive signal to control the position of lens unit 40 to the target position by PID control, based on the position of lens unit 40 indicated in the digital signal output from A / D converter 114 and the target position of lens unit 40 output from position command generation unit 210. A control unit such as a microprocessor such as a CPU or MPU, or a microcontroller such as an MCU that controls imaging of camera module 10 may include the position command generation unit 210.

[0048] The D / A converter 116 converts the drive signal from a digital signal to an analog signal and outputs the signal to the output driver 117. The output driver 117 outputs to the coil 200 a current corresponding to the drive signal.

[0049] 3, the signal output from the magnetic sensor 112 contains a certain amount of noise. The amplifier 113 downstream of the magnetic sensor 112 amplifies the signal containing the noise as is. If the noise is large, that is, if the offset amount is large, even if an attempt is made to increase the amplification factor of the amplifier 113, there are cases in which signals other than noise cannot be appropriately amplified because there is a limit to the size of the signal that can be input to the A / D converter 114. By reducing the offset amount contained in the signal output from the magnetic sensor 112, the amplification factor can be increased, and as a result, the S / N ratio can be improved.

[0050] 4 is a plan view of the semiconductor package 100 as viewed from the side of the external terminals 102. The semiconductor package 100 has a plurality of external terminals 102. The semiconductor package 100 has six external terminals 102.

[0051] The semiconductor package 100 has a rectangular shape extending in a first direction (X-axis direction) in a plan view. Here, the rectangular shape is a concept that includes an approximately rectangular shape. The approximately rectangular shape is a concept that includes a quadrangle with four corners other than 90°, a quadrangle with four corners within a range of 90°±5°, or a rounded quadrangle with four corners. The semiconductor package 100 may be a rectangle whose width in the first direction (X-axis direction) is longer than its width in the second direction (Z-axis direction) in a plan view. The multiple external terminals 102 may be arranged in two rows along the first direction. The multiple external terminals 102 include multiple external terminals 102A1, 102A2, and 102A3 included in a first row along the first direction (X-axis direction), and multiple external terminals 102B1, 102B2, and 102B3 that face the first row across the center P of the semiconductor package 100 and are included in a second row along the first direction (X-axis direction). The centers of gravity of the external terminals 102A1, 102A2, and 102A3 do not overlap with the centers of gravity of the external terminals 102B1, 102B2, and 102B3 in the first direction (X-axis direction) and in the second direction (Z-axis direction) intersecting the first direction. That is, the external terminals 102A1, 102A2, and 102A3 and the external terminals 102B1, 102B2, and 102B3 are arranged in a staggered pattern along the first direction.

[0052] The intervals in the first direction between the external terminals 102A1, 102A2, and 102A3 are the same as the intervals in the first direction between the external terminals 102B1, 102B2, and 102B3, and the external terminals 102A1, 102A2, and 102A3 are shifted from the external terminals 102B1, 102B2, and 102B3 in the first direction. The external terminals 102A1, 102A2, and 102A3 are also shifted from the external terminals 102B1, 102B2, and 102B3 in the second direction. Here, the term "same" includes the concept of "approximately the same." In other words, the intervals in the first direction between each of the multiple external terminals 102A1, 102A2, and 102A3 and the intervals in the first direction between each of the multiple external terminals 102B1, 102B2, and 102B3 do not have to be completely the same.

[0053] As ICs such as the semiconductor package 100 become smaller, the proportion of external terminals in the surface area of ​​the IC increases. In addition, when the semiconductor package 100 is disposed in the air-core portion of the coil 200, the gap in the air-core portion is narrow, so that the shape of the semiconductor package 100 is preferably an elongated rectangular shape. By disposing the multiple external terminals 102 in a staggered manner along the first direction on the surface of such an elongated semiconductor package 100 as shown in FIG. 4, the width of the semiconductor package 100 in the second direction can be narrowed. By disposing the multiple external terminals 102B1, 102B2, and 102B3 so that each of the multiple external terminals 102B1, 102B2, and 102B3 overlaps only partially with each of the multiple external terminals 102B1, 102B2, and 102B3 in the second direction, the width of the semiconductor package 100 in the second direction can be narrowed. By disposing the multiple external terminals 102 in a staggered manner, the semiconductor package 100 can be made smaller in the second direction (width direction) while keeping the terminal shape or number of terminals the same. Therefore, even if the semiconductor package 100 is made smaller in size in the width direction, it is possible to prevent a decrease in stability during mounting.

[0054] The width of the semiconductor package 100 in the first direction may be 1.65 times or more longer than the width in the second direction. The width of the semiconductor package 100 in the first direction may be 2.5 times or more longer than the width in the second direction. The total area of ​​the multiple external terminals 102 in a planar view may be 14% or more of the area of ​​the semiconductor package 100 in a planar view. The total area of ​​the multiple external terminals 102 in a planar view may be 19% or more of the area of ​​the semiconductor package 100 in a planar view.

[0055] FIG. 5 is a schematic diagram of the AA cross section shown in FIG. 4. In this embodiment, the semiconductor package 100 is described as a wafer-level chip size package (WL-CSP) type semiconductor package. However, the semiconductor package 100 may be a fan-out wafer-level package (FO-WLP) type semiconductor package. The semiconductor package 100 includes a silicon substrate 110, a redistribution layer 120 disposed on a first surface side of the silicon substrate 110, and a sealing material 130 disposed at least on a surface of the redistribution layer 120 opposite to the surface on the silicon substrate 110 side. The silicon substrate 110 incorporates a semiconductor chip. The semiconductor chip may include a magnetic sensor 112, an amplifier 113, an A / D converter 114, a PID control unit 115, a D / A converter 116, and an output driver 117.

[0056] In the camera module 10 including such a semiconductor package 100, the lens unit 40 is becoming heavier as the pixel count increases. As the pixel count increases, the image sensor 302 becomes larger, and the image sensor 302 tends to become hot. In addition, when the lens unit 40 becomes heavier, the current required to drive the lens unit 40 increases, and the temperature increases with the increase in current. Such a temperature increase also affects the magnetic sensor 112 built into the semiconductor package 100. That is, the offset amount of the magnetic sensor 112 increases with the increase in temperature. If the offset amount of the magnetic sensor 112 increases, the S / N ratio decreases. When the camera module 10 controls the lens unit 40 using the magnetic sensor 112 with poor temperature characteristics and low S / N ratio, the noise suppression performance deteriorates, the error between the actual position of the lens unit 40 and the target position increases, and the position of the lens unit 40 cannot be controlled with high accuracy. Therefore, it is difficult to realize high-precision image blur correction.

[0057] FIG. 6 shows the relationship between the moving distance of the lens unit 40 and the magnitude of the magnetic field detected by the magnetic sensor 112. The straight line A1 shows the relationship between the moving distance of the lens unit 40 in the case of a normal camera and the magnitude of the magnetic field detected by the magnetic sensor 112. The straight line A2 shows the relationship between the moving distance of the lens unit 40 in the case of a high-performance camera with high pixel count and the magnitude of the magnetic field detected by the magnetic sensor 112. As shown in FIG. 6, the moving distance of the lens unit 40 in response to the change in the magnitude of the magnetic field in the case of a high-performance camera is longer than the moving distance of the lens unit 40 in response to the change in the magnitude of the magnetic field in the case of a normal camera. That is, even if the error of the signal detected by the magnetic sensor 112 is the same, the position error of the lens unit 40 in the high-performance camera is larger than the position error of the lens unit 40 in the normal camera. With the increase in pixel count, the position error of the lens unit 40 is significantly manifested as image blur. That is, the decrease in the S / N ratio of the magnetic sensor 112 has a more significant effect on the high-performance camera, such as the inability to perform high-precision image blur correction. Therefore, it is more desirable to reduce the effect of the offset amount of the magnetic sensor 112.

[0058] 7, when the multiple Hall elements 111 constituting the magnetic sensor 112 are arranged in a line in each of the first direction (X-axis direction) and the second direction (Z-axis direction), the multiple external terminals 102 are arranged in a staggered manner, which causes variations in the size of the overlapping area where the Hall elements 111 and the external terminals 102 overlap in a plan view. If the size of the overlapping area differs, the change in the magnitude of the stress applied to the Hall element 111 caused by the change in the temperature or humidity around the semiconductor package 100 also differs. If the stress applied to the Hall element 111 changes, the offset amount included in the signal output from the Hall element 111 also changes.

[0059] Therefore, in this embodiment, in order to offset the change in the offset amount, a plurality of Hall elements 111 are arranged point-symmetrically with respect to the center P of the semiconductor package 100 in a plan view, as shown in FIG.

[0060] The Hall element 111S1 and the Hall element 111S2 are disposed symmetrically with respect to the center P. The Hall element 111S3 and the Hall element 111S4 are disposed symmetrically with respect to the center P.

[0061] When the semiconductor package 100 is divided into a first event region, a second event region, a third event region, and a fourth event region by a first axis L1 along a first direction (X-axis direction) passing through the center P and a second axis L2 along a second direction (Z-axis direction) in a plan view, the Hall element 111S1 and the Hall element 111S3 may be arranged on the first event region. The Hall element 111S2 and the Hall element 111S4 may be arranged on a third event region that is point-symmetrical with the first event region with respect to the center P. Alternatively, the Hall element 111S1 and the Hall element 111S3 may be arranged on the second event region. The Hall element 111S2 and the Hall element 111S4 may be arranged on a fourth event region that is point-symmetrical with the second event region with respect to the center P.

[0062] 8, the Hall elements 111S1 and 111S3 are arranged side by side in a first row along the first direction. The Hall elements 111S2 and 111S4 are arranged side by side in a second row on the opposite side of the first row with respect to the center P along the first direction. The Hall elements 111S1 and 111S3 do not overlap with the Hall elements 111S2 and 111S4 in the second direction.

[0063] In FIG. 9, the Hall elements 111S1 and 111S3 are arranged side by side in a first row along the first direction. The Hall elements 111S2 and 111S4 are arranged side by side in a second row on the opposite side of the first row with the center P in between along the first direction. The Hall element 111S1 does not overlap the Hall elements 111S2 and 111S4 in the second direction. The Hall element 111S2 does not overlap the Hall elements 111S1 and 111S3 in the second direction. On the other hand, the Hall element 111S3 overlaps the Hall element 111S4 in the second direction. That is, the Hall elements 111S3 and 111S4 are arranged side by side along the second direction.

[0064] Here, assuming that the output of the Hall element 111S1 is S1, the output of the Hall element 111S2 is S2, the output of the Hall element 111S3 is S3, and the output of the Hall element 111S4 is S4, the magnetic sensor 112 outputs the result of sum / difference calculation or sum calculation of S1, S2, S3, and S4 as a signal indicating the magnitude of the magnetic field. That is, the magnetic sensor 112 outputs (S1+S2+S3+S4) / ((S1+S3)-(S2+S4)) or (S1+S2+S3+S4) as a signal indicating the magnitude of the magnetic field. By arranging each pair of the Hall elements 111 point-symmetrically with respect to the center P, and adding up the outputs of each pair of the Hall elements 111, the noise included in the output of each Hall element 111, i.e., the offset amount, can be offset.

[0065] The PID control unit 115 may output a drive signal for controlling the coil 200 that functions as a drive unit that changes the position or attitude of the magnet 32 ​​relatively to the semiconductor package 100, based on the sum of outputs (S1+S2+S3+S4) indicating the magnitude of the magnetic fields output from the Hall elements 111S1, 111S2, 111S3, and 111S4. The amplifier 113 may amplify the sum of the outputs (S1+S2+S3+S4) and provide the sum of the outputs to the PID control unit 115 via the A / D converter 114.

[0066] The PID control unit 115 may output a drive signal further based on the difference ((S1+S3)-(S2+S4)) between the sum (S1+S3) of outputs indicating the magnitude of the magnetic field output from Hall element 111S1 and Hall element 111S3 and the sum (S2+S4) of outputs indicating the magnitude of the magnetic field output from Hall element 111S2 and Hall element 111S4.

[0067] The PID control unit 115 may output a drive signal based on a ratio (S1+S2+S3+S4) / ((S1+S3)-(S2+S4)) of the sum (S1+S2+S3+S4) of outputs indicating the magnitude of the magnetic field output from the Hall elements 111S1, 111S2, 111S3, and 111S4 to the difference ((S1+S3)-(S2+S4)). The amplifier 113 may amplify the ratio (S1+S2+S3+S4) / ((S1+S3)-(S2+S4)) and provide the sum of the outputs to the PID control unit 115 via the A / D converter 114.

[0068] 10, the multiple Hall elements 111 include a Hall element 111S1 and a Hall element S3 belonging to a first group, and a Hall element 111S2 and a Hall element 111S4 belonging to a second group. The Hall element 111S1 may be at least partially covered in a plan view by the external terminal 102A1 of the multiple external terminals 102A1, 102A2, and 102A3. The Hall element 111S2 may be at least partially covered in a plan view by the external terminal 102B1 of the multiple external terminals 102B1, 102B2, and 102B3. A region R1 covered in a plan view by the external terminal 102A1 of the Hall element 111S1 and a region R2 covered in a plan view by the external terminal 102B1 of the Hall element 111S2 are point-symmetrical with respect to the center P of the semiconductor package 100 in a plan view. The Hall element 111S3 and the Hall element 111S4 are disposed point-symmetrically with respect to the center P of the semiconductor package 100 in a plan view.

[0069] 11, the Hall elements 111S1 and 111S may be completely covered by the external terminal 102A1 in a plan view, and the Hall elements 111S2 and 111S4 may be completely covered by the external terminal 102B1 in a plan view.

[0070] 12, the Hall element 111S1 may be completely covered by the external terminal 102A1 in a planar view. The Hall element 111S2 may be completely covered by the external terminal B1 in a planar view. On the other hand, the Hall elements 111S3 and 111S4 may not be partially covered by any of the multiple external terminals 102. In other words, the Hall elements 111S3 and 111S4 may not overlap any of the multiple external terminals 102 in a planar view.

[0071] 13, the Hall element 111S1 may be partially covered by the external terminal 102A1 in a planar view. The Hall element 111S2 may be partially covered by the external terminal B1 in a planar view. On the other hand, the Hall elements 111S3 and 111S4 may not be partially covered by any of the multiple external terminals 102. In other words, the Hall elements 111S3 and 111S4 may not overlap any of the multiple external terminals 102 in a planar view.

[0072] 14, the Hall element 111S1 may be entirely covered by the external terminal 102A1 in a planar view. The Hall element 111S2 may be entirely covered by the external terminal 102B1 in a planar view. The Hall element 111S3 may be partially covered by the external terminal 102A1 in a planar view. The Hall element 111S4 may be partially covered by the external terminal 102B1 in a planar view.

[0073] 15, the Hall element 111 can be represented by an equivalent circuit in which four resistors R1, R2, R3, and R4, each having a resistance value R, are bridge-connected. The Hall element 111 has a pair of electrodes D1 and D2 opposed to each other in a first direction, and a pair of electrodes D3 and D4 opposed to each other in a second direction.

[0074] The four resistors R1, R2, R3, and R4 have the same resistance value R. However, when the stresses applied to the four resistors R1, R2, R3, and R4 are different, the resistance values ​​of the four resistors R1, R2, R3, and R4 vary. As a result, the offset amount included in the signal output from the Hall element 111 changes.

[0075] In order to reduce such fluctuations in the offset amount, it is possible to switch a pair of electrodes output from the Hall element 111 and add up the two outputs. That is, at a first timing, a signal Sa according to the magnitude of the magnetic field is output from a pair of electrodes D1 and D2 of the Hall element 111, and at a second timing following the first timing, a signal Sb according to the magnitude of the magnetic field is output from a pair of electrodes D3 and D4 of the Hall element 111, and the offset amount is reduced by adding up the signals Sa and Sb. However, time is required to switch the electrodes to be output, which slows down the response. For example, when focusing or image blur correction is performed by moving the lens unit 40, such a delay in response may cause a delay in focusing or may prevent high-precision image blur correction.

[0076] Therefore, the output electrodes of the Hall elements 111 arranged point symmetrically are set to a pair of electrodes in different directions. By adding the outputs of those Hall elements 111, the offset amount can be reduced, as in the case of switching the electrodes. Furthermore, no response delay occurs due to switching the electrodes. By reducing the offset amount in this way, not only can the response delay be suppressed, but the magnetic sensor 112 can calculate S1+S2 and S1+S3 sequentially in a time-division manner, and therefore can calculate the output of each Hall element 111 without sacrificing the AD range.

[0077] 14, the Hall elements 111S1, 111S2, 111S3, and 111S4 have a pair of electrodes D1 and D2 facing each other in a first direction, and a pair of electrodes D3 and D4 facing each other in a second direction intersecting the first direction. In the Hall elements 111S1 and 111S4, the pair of electrodes D1 and D2 are output electrodes. On the other hand, in the Hall elements 111S2 and 111S3, the pair of electrodes D3 and D4 are output electrodes.

[0078] In the configuration shown in FIG. 14, the Hall element 111S1 is only partially covered by the external terminal 102A1 in a plan view. As a result, the stress applied to the Hall element 111S1 varies. FIG. 16A shows an equivalent circuit of the Hall element 111S1. As shown in FIG. 16A, in the Hall element 111S1, among the four bridge-connected resistors R1, R2, R3, and R4, the resistance value of the resistor R1 is R+r, and the resistance values ​​of the other three resistors R2, R3, and R4 are R. That is, the resistance value of the resistor R1 is different from the resistance values ​​of the resistors R2, R3, and R4.

[0079] FIG. 16B shows an equivalent circuit of the Hall element 111S2. The Hall element 111S2 is only partially covered by the external terminal 102B1 in a plan view, similar to the Hall element 111S1. As a result, the stress applied to the Hall element 111S2 varies. However, the position of the area of ​​the Hall element 111S2 covered by the external terminal 102B1 in a plan view is different from the position of the area of ​​the Hall element 111S1 covered by the external terminal 102A1 in a plan view. The area of ​​the Hall element 111S2 covered by the external terminal 102B1 in a plan view is point-symmetrical with the area of ​​the Hall element 111S1 covered by the external terminal 102A1 in a plan view with respect to the center P. Therefore, in the Hall element 111S2, the resistance value of the resistor R3 among the four bridge-connected resistors R1, R2, R3, and R4 is R+r, and the resistance values ​​of the other three resistors R1, R2, and R4 are R. That is, the resistance value of the resistor R3 is different from the resistance values ​​of the resistors R1, R2, and R4.

[0080] Fig. 16C shows an equivalent circuit of the Hall element 111S3, and Fig. 16D shows an equivalent circuit of the Hall element 111S4. The Hall element 111S3 is completely covered by the external terminal 102A1 in a plan view, and the Hall element 111S4 is completely covered by the external terminal 102B1 in a plan view. As a result, there is no variation in the stress applied to the Hall elements 111S3 and 111S4. Therefore, in the Hall elements 111S3 and 111S4, the resistance values ​​of the four bridge-connected resistors R1, R2, R3, and R4 are the same.

[0081] In the equivalent circuit of the Hall element 111S1 shown in FIG. 16A, an offset voltage V offset_1 is defined by equation (1). V offset_1 =V 1_1 -V 2_1 =((R+r) / (2R+r)-1 / 2)×V in =r / (2×(2R+r)) (1)

[0082] In the equivalent circuit of the Hall element 111S2 shown in FIG. 16B, an offset voltage V offset_1 is defined by equation (2). V offset_1 =V 1_2 -V 2_2 =((R / (2R+r))-1 / 2)×V in =-r / (2×(2R+r)) (2)

[0083] In the equivalent circuit of the Hall element 111S3 shown in FIG. 16C, an offset voltage V offset_3 is defined by equation (3). V offset_3 =V 1_3 -V 2_3 =0 (3)

[0084] In the equivalent circuit of the Hall element 111S4 shown in FIG. 16D, the offset voltage V offset_4 is defined by equation (4). V offset_3 =V 1_4 -V 2_4 =0 (4)

[0085] From the above, when the outputs of the Hall elements 111S1, 111S2, 111S3, and 111S4 are all added together, an offset voltage V corresponding to the offset amount output from the magnetic sensor 112 is obtained. offset is defined by the formula (5), and the offset amounts occurring in the Hall elements 111S1 and 111S2 are cancelled out and become zero. V offset =V offset_1 +V offset_2 +V offset_3 +V offset_4 =r / (2×(2R+r))-r / (2×(2R+r))=0···(5)

[0086] 17 shows the function of each external terminal 102 of the semiconductor package 100. In a plan view, the external terminal 102A1 and the external terminal 102A3 arranged in the second event region are a pair of power supply terminals. The external terminal 102B2 arranged in the third event region and the external terminal 102B1 arranged in the fourth event region are a pair of drive terminals that output a drive signal for the coil 200. The external terminal 102A2 arranged in the first event region and the external terminal 102B3 arranged in the fourth event region are a pair of communication terminals for communicating with the control unit of the camera module 10.

[0087] The Hall element 111S1 may at least partially overlap with the external terminal 102A1, which is one of a pair of power supply terminals, in a plan view, and the Hall element 111S2 may at least partially overlap with the external terminal 102B1, which is one of a pair of drive terminals, in a plan view. In this way, the Hall element 111 may overlap with an external terminal other than the pair of communication terminals in a plan view. However, it is preferable that the Hall element 111 does not overlap with the pair of communication terminals in a plan view. If the Hall element 111 overlaps with one of the pair of communication terminals in a plan view, the Hall element 111 and the pair of communication terminals are affected by noise on each other, which increases the adverse effect.

[0088] Each of the external terminals 102A1 and 102B1 that at least partially overlap with the Hall element 111 in a planar view is preferably an external terminal that is located closest to the center P of the semiconductor package 100 in a planar view among the multiple external terminals 102.

[0089] As long as the external terminals 102A1 and 102B1, which at least partially overlap with the Hall element 111 in a plan view, are point-symmetric with respect to the center P of the semiconductor package 100 in a plan view, the shape of the external terminals 102A1 and 102B1 in a plan view does not have to be circular.

[0090] FIG. 18 shows the wiring state in the redistribution layer 120 of the semiconductor package 100. By arranging the multiple external terminals 102 in a staggered manner along the first direction, there is space in the areas of each external terminal 102 facing the first and second directions. Therefore, the wiring for electrically connecting from the external terminal 102 to the semiconductor chip can be extended relatively long in the first and second directions. For example, the redistribution layer 120 may include a wiring LB1 that extends from the external terminal 102B1 along the first direction by 100 μm or more and is electrically connected to the semiconductor chip. That is, the portion kb1 of the wiring LB1 that extends along the first direction may be 100 μm or more. Similarly, the redistribution layer 120 may include a wiring LB3 that extends from the external terminal 102B3 along the first direction by 100 μm or more and is electrically connected to the semiconductor chip. That is, the portion kb3 of the wiring LB3 that extends along the first direction may be 100 μm or more. By wiring in the eleventh direction or the second direction in this manner, wiring can be achieved through the shortest route, and therefore the area of ​​the semiconductor package 100 in plan view can be reduced.

[0091] Moreover, the wiring LB1 includes a portion kb1 that extends on a line in the first direction that passes through the center of the external terminal 102B1. The wiring LB3 includes a portion kb3 that extends on a line in the first direction that passes through the center of the external terminal 102B3.

[0092] The redistribution layer 120 may include a wiring LB2 that extends 100 μm or more from the external terminal 102B2 along the second direction and is electrically connected to the semiconductor chip. The wiring LB2 includes a portion kb2 that extends on a line along the second direction that passes through the center of the external terminal 102B2.

[0093] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0094] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0095] 10 Camera Module 20 base 30 Holding Frame 32 Magnet 40 Lens unit 100 Semiconductor Packages 102 External terminal 110 Silicon substrate 111 Hall element 112 Magnetic Sensor 113 Amplifier 114 A / D Converter 115 PID control unit 116 D / A Converter 117 Output Driver 120 Redistribution layer 130 Encapsulating material 200 Coil 210 Position command generation section 300 Substrates 302 Image sensor

Claims

1. A semiconductor package having at least a first hole element and a second hole element, and a plurality of external terminals provided on a first surface of the semiconductor chip, the semiconductor package having a rectangular shape extending in a first direction in a plan view, wherein the first hole element and the second hole element are arranged point-symmetrically with respect to a central point of the semiconductor package in a plan view, the plurality of external terminals include a plurality of first external terminals included in a first row along the first direction and a plurality of second external terminals included in a second row along the first direction, in a plan view, the plurality of first external terminals and the plurality of second external terminals are arranged in a staggered pattern on the first surface, in a plan view, the first hole element is arranged along the first row and the second hole element is arranged along the second row, the semiconductor package.

2. The plurality of first external terminals or the plurality of second external terminals include a pair of communication terminals for the outside of the semiconductor package, in a plan view, the first hole element and the second hole element are arranged so as not to overlap with the pair of communication terminals, the semiconductor package according to claim 1.

3. The semiconductor chip has a plurality of hole elements including the first hole element and the second hole element, the plurality of hole elements include the first hole element and the third hole element belonging to a first group, and the second hole element and the fourth hole element belonging to a second group, the third hole element and the fourth hole element are arranged point-symmetrically with respect to the point at the center of the semiconductor package in a plan view, the semiconductor package according to claim 2.

4. In a plan view, the third hole element and the fourth hole element are arranged so as not to overlap with the pair of communication terminals, the semiconductor package according to claim 3.

5. In a plan view, the first hole element and the third hole element belonging to the first group are arranged along the first row, and the second hole element and the fourth hole element belonging to the second group are arranged along the second row, the semiconductor package according to claim 4.

6. The width of the semiconductor package in the first direction is longer than the width in a second direction intersecting the first direction of the semiconductor package, the semiconductor package according to claim 5.

7. The width in the first direction is 1.65 times or more longer than the width in the second direction, the semiconductor package according to claim 6.

8. The semiconductor package according to claim 6, wherein the width in the first direction is 2.5 times or more longer than the width in the second direction.

9. The semiconductor package according to claim 7 or 8, wherein the total area of the plurality of external terminals in a plan view is 14% or more of the area of the semiconductor package in a plan view.

10. The semiconductor package according to claim 7 or 8, wherein the total area of the plurality of external terminals in a plan view is 19% or more of the area of the semiconductor package in a plan view.

11. The external terminals belonging to the first row and the external terminals belonging to the second row, which are located closest to the center of the semiconductor package in a plan view, are point-symmetrical with respect to the center of the semiconductor package in a plan view. The semiconductor package according to claim 5.

12. It includes a redistribution layer laminated on the first surface side of the semiconductor chip and electrically connected to the semiconductor chip. The semiconductor package according to any one of claims 1 to 5, wherein at least one of the plurality of external terminals is electrically connected to the first hole element and the second hole element via the redistribution layer.

13. The semiconductor package according to claim 12, wherein the redistribution layer includes a wiring that extends 100 μm or more along the first direction from at least one of the plurality of external terminals and is electrically connected to the semiconductor chip.

14. The semiconductor package according to claim 13, wherein the wiring has a portion that extends along a line in the first direction passing through the center of the at least one external terminal in a plan view.

15. The semiconductor package according to claim 12, wherein the redistribution layer includes a wiring that extends 100 μm or more along a second direction intersecting the first direction from at least one of the plurality of external terminals and is electrically connected to the semiconductor chip.

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