Solid-state image pickup device and signal processing method

Abstract

To provide a solid-state image pickup device that can be increased in lifetime, and a signal processing method.SOLUTION: A solid-state image pickup device 1 comprises a signal processing part 90. Signal processing of the signal processing part 90 includes: processing of adding a first signal S1 corresponding to electric charges from a first light reception part 5 and a second signal S2 corresponding to electric charges from a second light reception part 6 together to generate an addition signal S3; processing og subtracting the second signal S2 from the first signal S1 to generate a subtraction signal S4; and processing of correcting the addition signal S3 based upon the subtraction signal S4 and then outputting the resulting signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a solid-state imaging device and a signal processing method. [Background technology]

[0002] Patent Document 1 describes an imaging device. This imaging device includes a horizontal transfer unit that transfers charges generated by two-dimensionally arranged photoelectric conversion elements horizontally line by line and converts them into an imaging signal, a transfer control gate unit that controls the supply of charges to the horizontal transfer unit, a drive unit that drives the horizontal transfer unit and the transfer control gate unit, and a signal correction unit that generates a correction signal using an imaging signal output from the horizontal transfer unit and corrects the imaging signal subsequently output from the horizontal transfer unit using the correction signal. The drive unit also uses the transfer control gate unit to stop the supply of charges to the horizontal transfer unit, and the signal correction unit generates the correction signal using the imaging signal output from the horizontal transfer unit when the supply of charges to the horizontal transfer unit is stopped. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-005328 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in imaging devices such as those described above, white spots (hereinafter referred to as "WS") with a high signal level may occur after shipment even when no light is incident. One cause of WS is thought to be alpha rays from the imaging device's packaging and other materials, or neutron rays from cosmic rays, which form defects or cause damage in the crystalline structure of the semiconductor (e.g., silicon) in the imaging device's light-receiving section. Because alpha rays are emitted from materials close to the light-receiving section, it is difficult to provide a shield for the light-receiving section, making them difficult to block. Neutron rays coming from the outside world are also difficult to block because neutrons are not charged particles. Therefore, it is difficult to prevent WS from occurring in the first place.

[0005] Therefore, if WS occurs after shipment, it is conceivable to continue using the imaging device while correcting the output signal to remove noise caused by WS. However, such correction has been difficult with conventional imaging devices due to reasons such as the risk of WS increasing over time and the possibility that the output signal may change like an RTS (Random Telegraph Signal). Therefore, it is desirable to enable output signal correction and extend the life of imaging devices.

[0006] An object of the present disclosure is to provide a solid-state imaging device and a signal processing method that can achieve a longer life. [Means for solving the problem]

[0007] A solid-state imaging device according to the present disclosure includes: [1] "a first light receiving section and a second light receiving section that generate charges in response to incidence of light; an output section that outputs a first signal in response to the charges generated in the first light receiving section and a second signal in response to the charges generated in the second light receiving section; and a signal processing section that processes the signal output from the output section, wherein the first light receiving section has a first pixel region configured by a plurality of first pixels arranged along a first direction or a plurality of first pixel areas that are pixel areas including one first pixel, and the first pixel region is configured by a plurality of second pixels arranged along the first direction or a plurality of second pixel areas that are pixel areas including one second pixel, and the second light receiving section has a first pixel region configured by a plurality of second pixels arranged along the first direction or a plurality of second pixel areas that are pixel areas including one second pixel, and the second pixel region is ... second direction." a first pixel area and a second pixel area configured to be arranged in a first direction such that when the first pixel area and the second pixel area are arranged along the first direction such that ends of the first pixel area and the second pixel area in the second direction coincide with each other, each of the plurality of first pixel areas and each of the plurality of second pixel areas are associated with each other so that they line up along the first direction; and the signal processing by the signal processing unit includes an addition signal generation process of adding the first signal and the second signal to generate an addition signal, a subtraction signal generation process of subtracting the second signal from the first signal to generate a subtraction signal, and a correction process of correcting the addition signal based on the subtraction signal and outputting the addition signal.

[0008] This solid-state imaging device includes a first light receiving section and a second light receiving section that generate electric charges in response to incident light. The first light receiving section has a first pixel region configured by first pixel areas including one or more first pixels arranged along a second direction, and the second light receiving section similarly has a second pixel region configured by second pixel areas including one or more second pixels arranged along the second direction. In the first light receiving section and the second light receiving section, electric charges are generated in the first pixels and the second pixels respectively in response to incident light.

[0009] When the first pixel area and the second pixel area are arranged along the first direction so that the ends of the first pixel area and the second pixel area in the second direction of the first pixel area and the second pixel area are aligned (whether they are actually arranged in this manner or not), each of the plurality of first pixel areas and each of the plurality of second pixel areas are associated with each other so that they are lined up along the first direction. Therefore, in this solid-state imaging device, by irradiating the first light receiving section (first pixel area) and the second light receiving section (second pixel area) with the same or corresponding light, a correspondence relationship is generated between a first signal corresponding to the charge from the first light receiving section and a second signal corresponding to the charge from the second light receiving section.

[0010] Therefore, by generating a subtraction signal between the first signal and the second signal by the signal processing unit, information regarding the output value due to WS, which may occur regardless of the correspondence between the first signal and the second signal (for example, the position of the pixel area that generates the output value due to WS, or the signal itself containing the output value) can be obtained. Therefore, by correcting the sum signal (output signal before correction) of the first signal and the second signal generated by the signal processing unit based on this subtraction signal, it is possible to remove the output value due to WS. Therefore, even if WS occurs over time, its effects can be suppressed and continued use is possible. In other words, the life of the solid-state imaging device is extended.

[0011] The solid-state imaging device according to the present disclosure may be [2] "the solid-state imaging device according to the above [1], wherein, in the correction process, the signal processing unit generates a correction signal based on the subtraction signal and corrects the sum signal by subtracting the correction signal from the sum signal, and when a white dot area, which is a pixel area exhibiting an output value below a negative threshold, is detected in the correction signal, the sign of the output value of the white dot area is changed to positive." In this case, by subtracting the correction signal from the sum signal, it is possible to remove the output value due to WS (the output value of the white dot area) from the sum signal.

[0012] The solid-state imaging device according to the present disclosure may be [3] "the solid-state imaging device according to the above [2], wherein, in the correction process, the signal processing unit generates the correction signal in all the first pixel areas and all the second pixel areas, and corrects the sum signal by subtracting the correction signal from the sum signal." In this case, it is possible to remove the output value caused by WS from the sum signal without identifying the position of the white dot area.

[0013] The solid-state imaging device according to the present disclosure may be [4] "the solid-state imaging device according to the above [1], wherein, in the correction process, the signal processing unit generates a correction signal based on the subtraction signal and corrects the sum signal by adding the correction signal to the sum signal, and when a white dot area, which is a pixel area exhibiting an output value exceeding a positive threshold, is detected in the correction signal, the sign of the output value of the white dot area is changed to negative." In this case, adding the correction signal to the sum signal makes it possible to remove the output value due to WS (the output value of the white dot area) from the sum signal.

[0014] The solid-state imaging device according to the present disclosure may be [5] "the solid-state imaging device according to the above [4], wherein, in the correction process, the signal processing unit generates the correction signals in all of the first pixel areas and all of the second pixel areas, and corrects the sum signal by adding the correction signals to the sum signal." In this case, it is possible to remove output values ​​caused by WS from the sum signal without identifying the positions of white dot areas.

[0015] The solid-state imaging device according to the present disclosure may be [6] "the solid-state imaging device according to any one of [2] to [5] above, wherein, in the correction process, the signal processing unit sets the output value of the pixel area that indicates an output value between a positive threshold and a negative threshold in the correction signal to 0." In this case, superimposition of noise due to subtraction or addition of the correction signal is suppressed.

[0016] The solid-state imaging device according to the present disclosure may be the solid-state imaging device according to [7] above, wherein "in the correction process, when a white dot area is detected in the subtraction signal, the signal processing unit replaces the output value of the white dot area in the sum signal with an output value obtained by doubling the output value of the second pixel area at the position of the white dot area in the second signal, and when a white dot area is detected in the subtraction signal, the signal processing unit replaces the output value of the white dot area in the sum signal with an output value obtained by doubling the output value of the first pixel area at the position of the white dot area in the first signal." In this case, subtraction and addition of a correction signal are not necessary when removing the output value due to WS from the sum signal.

[0017] The solid-state imaging device according to the present disclosure may be [8] "the solid-state imaging device according to any one of [1] to [7] above, wherein the signal processing unit performs the correction process when at least one of a white dot area, which is the pixel area exhibiting an output value above a positive threshold, and a white dot area, which is the pixel area exhibiting an output value below a negative threshold, is detected in the subtraction signal." In this case, if a white dot area is not detected, the execution of the correction process can be omitted.

[0018] The solid-state imaging device according to the present disclosure may be [9] "the solid-state imaging device according to any one of [1] to [8] above, including a first transfer gate unit for transferring charges from each of the first pixel areas, a second transfer gate unit for transferring charges from each of the second pixel areas, a first horizontal transfer CCD unit for transferring the charges transferred by the first transfer gate unit to the output unit, and a second horizontal transfer CCD unit for transferring the charges transferred by the second transfer gate unit to the output unit." In this case, it is possible to extend the life of the solid-state imaging device configured to include a CCD (Charge Coupled Device).

[0019] The solid-state imaging device according to the present disclosure may be

[10] "the solid-state imaging device according to the above [9], wherein the first pixel region and the second pixel region are arranged in the first direction such that each of the first pixel areas and each of the second pixel areas are aligned along the first direction." In this case, it is easy to cause the same or corresponding light to be incident on the first pixel region and the second pixel region.

[0020] The solid-state imaging device according to the present disclosure may be

[11] "the solid-state imaging device according to the above

[10] , wherein the first pixel region, the first transfer gate unit, and the first horizontal transfer CCD unit are arranged in order toward one side of the first direction, and the second pixel region, the second transfer gate unit, and the second horizontal transfer CCD unit are arranged in order toward the opposite side of the first direction." In this case, it is possible to appropriately arrange the first horizontal transfer CCD unit, the second horizontal transfer CCD unit, the first transfer gate unit, and the second transfer gate unit with respect to the first pixel region and the second pixel region, which are arranged in an arrangement that facilitates the incidence of the same or corresponding light.

[0021] The solid-state imaging device according to the present disclosure may be

[12] "the solid-state imaging device according to any one of the above [1] to

[11] , wherein the output section includes a first output section for receiving charges generated in the first light receiving section and outputting the first signal, and a second output section for receiving charges generated in the second light receiving section and outputting the second signal." In this case, by providing output sections corresponding to the first light receiving section and the second light receiving section, respectively, the processing speed can be improved.

[0022] The solid-state imaging device according to the present disclosure is,

[13] "the solid-state imaging device according to any one of the above [1] to

[12] , wherein the first pixel area includes a plurality of first pixels arranged along the first direction, and the second pixel area includes a plurality of second pixels arranged along the first direction. In this case, binning becomes possible, and the signal-to-noise ratio of the output signal becomes good.

[0023] The solid-state imaging device according to the present disclosure may be

[14] "the solid-state imaging device according to any one of the above [1] to

[13] , wherein the first pixel region and the second pixel region are arranged adjacent to each other." In this case, by arranging the first pixel region and the second pixel region close to each other, the characteristics between the regions become similar, and more appropriate correction can be performed.

[0024] The signal processing method according to the present disclosure is

[15] "a signal processing method for a solid-state imaging device including a first light receiving section and a second light receiving section for generating charges in response to incidence of light, and an output section for outputting a first signal in response to the charges generated in the first light receiving section and a second signal in response to the charges generated in the second light receiving section, the method comprising: an addition signal generating step of generating an addition signal by adding the first signal and the second signal; a subtraction signal generating step of generating a subtraction signal by subtracting the second signal from the first signal; and a correction step of correcting and outputting the addition signal based on the subtraction signal, wherein the first light receiving section is a plurality of first pixels arranged along a first direction, or a pixel area including one first pixel. the second light receiving unit has a second pixel region configured by arranging a plurality of second pixels along the first direction or a plurality of second pixel areas, which are pixel areas including one second pixel, along the second direction, and the first pixel area and the second pixel area are associated such that when the first pixel area and the second pixel area are arranged along the first direction so that ends of the first pixel area and the second pixel area in the second direction coincide with each other, each of the plurality of first pixel areas and each of the plurality of second pixel areas are aligned along the first direction.

[0025] According to this signal processing method, the life of the solid-state imaging device can be extended for the same reasons as above. [Effects of the Invention]

[0026] According to the present disclosure, it is possible to provide a solid-state imaging device and a signal processing method that can achieve a longer life. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a schematic plan view showing an example of a solid-state imaging device according to this embodiment. [Figure 2] FIG. 2 is a partial schematic cross-sectional view taken along line II-II in FIG. 1, and a schematic diagram showing the potential in the cross-section. [Figure 3] FIG. 3 is a schematic plan view showing another example of the solid-state imaging device according to the present embodiment. [Figure 4] FIG. 4 is a partial schematic cross-sectional view taken along line IV-IV in FIG. 3, and a schematic diagram showing the potential in the cross-section. [Figure 5] FIG. 5 is a graph showing various signals. [Figure 6] FIG. 6 is a graph showing various signals. [Figure 7] FIG. 7 is a flowchart showing an example of a signal processing method according to this embodiment. [Figure 8] FIG. 8 is a flowchart showing another example of the signal processing method according to this embodiment. [Figure 9] FIG. 9 is a flowchart showing yet another example of the signal processing method according to this embodiment. [Figure 10] FIG. 10 is a schematic plan view showing a first modified example of a solid-state imaging device. [Figure 11] FIG. 11 is a partial schematic cross-sectional view taken along line XI-XI in FIG. 10, and a schematic diagram showing the potential in the cross-section. [Figure 12] FIG. 12 is a schematic plan view showing another aspect of the solid-state imaging device of the first modified example. [Figure 13] FIG. 13 is a partial schematic cross-sectional view taken along line XIII-XIII in FIG. 12, and a schematic diagram showing the potential in the cross-section. [Figure 14]FIG. 14 is a schematic plan view showing a second modified example of the solid-state imaging device. [Figure 15] FIG. 15 is a schematic plan view showing an enlarged portion of FIG. [Figure 16] FIG. 16 is a partial schematic cross-sectional view taken along line XVI-XVI in FIGS. 14 and 15, and a schematic diagram showing the potential in the cross-section. DETAILED DESCRIPTION OF THE INVENTION

[0028] An embodiment will be described below with reference to the drawings. In the description of each drawing, the same or corresponding parts are denoted by the same reference numerals, and redundant description may be omitted. Each drawing may also show a Cartesian coordinate system consisting of a first axis defining a first direction D1, a second axis defining a second direction D2 intersecting (orthogonal to) the first direction D1, and a third axis defining a third direction D3 intersecting (orthogonal to) the first direction D1 and the second direction D2. [Configuration of solid-state imaging device]

[0029] FIG. 1 is a schematic plan view showing an example of a solid-state imaging device according to this embodiment. FIG. 2 is a partial schematic cross-sectional view taken along line II-II in FIG. 1, and a schematic diagram showing the potential at the cross-section. The cross-sectional view taken along line II-II (without hatching) is shown in the upper part of FIG. 2, and the potential V at the cross-section is shown in the lower part of FIG. 2. The solid-state imaging device 1 shown in FIGS. 1 and 2 is, for example, a CCD image sensor. The solid-state imaging device 1 includes a first pixel region 10 and a second pixel region 20.

[0030] The first pixel region 10 has a plurality of first pixel areas 11 arranged along the second direction D2. Each of the first pixel areas 11 includes a plurality of first pixels 12 arranged along the first direction D1. The first pixels 12 generate electric charges in response to incident light. Therefore, the first pixel region 10 constitutes a first light receiving section 5 that generates electric charges in response to incident light. Here, the first light receiving section 5 is formed in a shape that is elongated in the second direction D2 compared to the first direction D1, depending on the number of first pixels 12 arranged in each of the first direction D1 and the second direction D2. In other words, here, the number of first pixels 12 arranged in the second direction D2 is greater than the number of first pixels 12 arranged in the first direction D1.

[0031] The second pixel region 20 has a plurality of second pixel areas 21 arranged along the second direction D2. Each second pixel area 21 includes a plurality of second pixels 22 arranged along the first direction D1. The second pixels 22 generate electric charges in response to incident light. Therefore, the second pixel region 20 constitutes a second light receiving section 6 that generates electric charges in response to incident light. Here, the second light receiving section 6 is formed in a shape that is elongated in the second direction D2 compared to the first direction D1, depending on the number of second pixels 22 arranged in each of the first direction D1 and the second direction D2. That is, here, the number of second pixels 22 arranged in the second direction D2 is greater than the number of second pixels 22 arranged in the first direction D1.

[0032] In this embodiment, the number of first pixels 12 arranged in the first pixel region 10 and the number of second pixels 22 arranged in the second pixel region 20 are the same in each of the first direction D1 and the second direction D2. That is, the first pixel region 10 and the second pixel region 20 have the same area. Therefore, here, the number of first pixels 12 included in the first pixel area 11 and the number of second pixels 22 included in the second pixel area 21 are also the same, and the number of first pixel areas 11 and the number of second pixel areas 21 are also the same. That is, in this embodiment, the first pixel region 10 and the second pixel region 20 have the same shape in a plane including the first direction D1 and the second direction D2.

[0033] The first pixel area 11 and the second pixel area 21 are associated with each other such that when the first pixel region 10 and the second pixel region 20 are arranged along the first direction D1 such that the ends of the first pixel region 10 and the second pixel region 20 in the second direction D2 coincide with each other, each of the multiple first pixel areas 11 and each of the multiple second pixel areas 21 are aligned along the first direction D1. In this embodiment, the first pixel region 10 and the second pixel region 20 are actually arranged such that the ends of the first pixel region 10 and the second pixel region 20 in the second direction D2 coincide with each other, so that each of the multiple first pixel areas 11 and each of the multiple (the same number as the first pixel areas 11) second pixel areas 21 are aligned in the first direction D1.

[0034] The first light receiving section 5 (first pixel region 10) and second light receiving section 6 (second pixel region 20) are configured on a semiconductor substrate 2. That is, the solid-state imaging device 1 includes the semiconductor substrate 2, a semiconductor layer 3 stacked on the semiconductor substrate 2, an insulating film F1 formed on the surface of the semiconductor layer 3 opposite to the semiconductor substrate 2, and a plurality of transfer electrodes F2 formed on the insulating film F1. The semiconductor substrate 2 and the semiconductor layer 3 include, for example, silicon. The semiconductor substrate 2 has a first conductivity type (here, P type).

[0035] The semiconductor layer 3 includes a pair of first and second regions 3A and 3B arranged on the semiconductor substrate 2 along a first direction D1. The first regions 3A each have a second conductivity type (N type in this example) different from the first conductivity type. The second region 3B is formed between the pair of first regions 3A and has a first conductivity type (P type in this example). + One of the pair of first regions 3A and a region of the semiconductor substrate 2 directly below the first region 3A constitutes a first light receiving section 5, and the other first region 3A and a region of the semiconductor substrate 2 directly below the first region 3A constitutes a second light receiving section 6. In addition, individual first pixels 12 and second pixels 22 are defined according to the arrangement of the transfer electrodes F2.

[0036] The second region 3B provides a potential barrier against the charge e generated in each of the first light receiving section 5 and the second light receiving section 6. This forms an element isolation section between the first light receiving section 5 and the second light receiving section 6. As a result, the first light receiving section 5 (first pixel region 10) and the second light receiving section 6 (second pixel region 20) are disposed adjacent to each other in the first direction D1 with the element isolation section interposed therebetween. On the other hand, as shown in FIGS. 3 and 4, the first conductivity type second region 3B may not be provided in the semiconductor layer 3, so that the first light receiving section 5 (first pixel region 10) and the second light receiving section 6 (second pixel region 20) may be disposed adjacent to each other in the first direction D1 without an element isolation section interposed therebetween.

[0037] When an element isolation section is provided between the first pixel region 10 and the second pixel region 20 (as in FIGS. 1 and 2), blooming is suppressed. On the other hand, when an element isolation section is not provided between the first pixel region 10 and the second pixel region 20 and the first pixel region 10 and the second pixel region 20 are arranged closer to each other (as in FIGS. 3 and 4), the dead region is reduced. FIG. 3 is a schematic plan view showing another example of a solid-state imaging device according to this embodiment. FIG. 4 is a partial schematic cross-sectional view taken along line IV-IV in FIG. 3 and a schematic diagram showing the potential at the cross-section. The cross-sectional view taken along line IV-IV (without hatching) is shown in the upper part of FIG. 4, and the potential V at the cross-section is shown in the lower part of FIG. 4.

[0038] As shown in Figures 1 and 3, the solid-state imaging device 1 further includes a first transfer gate section 30, a second transfer gate section 40, a first horizontal transfer CCD section 50, a second horizontal transfer CCD section 60, a first output section (output section) 70, a second output section (output section) 80, and a signal processing section 90.

[0039] The first transfer gate unit 30 is disposed on the opposite side of the first pixel region 10 from the second pixel region 20 in the first direction D1, and is for transferring charges from each of the first pixel areas 11 along the first direction D1. The second transfer gate unit 40 is disposed on the opposite side of the second pixel region 20 from the first pixel region 10 in the first direction D1, and is for transferring charges from each of the second pixel areas 21 along the first direction D1.

[0040] The first horizontal transfer CCD unit 50 is arranged on the opposite side of the first pixel region 10 in the first direction D1, with the first transfer gate unit 30 sandwiched between them. That is, the first pixel region 10, the first transfer gate unit 30, and the first horizontal transfer CCD unit 50 are arranged in this order on one side (here, the positive side) of the first direction D1. The first horizontal transfer CCD unit 50 receives the charges transferred by the first transfer gate unit 30 and transfers the charges to the first output unit 70 along the second direction D2. The second horizontal transfer CCD unit 60 is arranged on the opposite side of the second pixel region 20 in the first direction D1, with the second transfer gate unit 40 sandwiched between them. That is, the second pixel region 20, the second transfer gate unit 40, and the second horizontal transfer CCD unit 60 are arranged in this order on the other side (here, the negative side) of the first direction D1. The second horizontal transfer CCD section 60 receives the charges transferred by the second transfer gate section 40 and transfers the charges to the second output section 80 along the second direction D2.

[0041] The first output section 70 is disposed at one end of the first horizontal transfer CCD section 50 in the second direction D2. The first output section 70 is a first amplifier section that receives charges generated in the first light receiving section (first pixel region 10) and transferred by the first transfer gate section 30 and the first horizontal transfer CCD section 50, converts the charges into a voltage, and generates and outputs a first signal S1. The second output section 80 is disposed at one end of the second horizontal transfer CCD section 60 in the second direction D2 (the same side as the first output section 70). The second output section 80 is a second amplifier section that receives charges generated in the second light receiving section (second pixel region 20) and transferred by the second transfer gate section 40 and the second horizontal transfer CCD section 60, converts the charges into a voltage, and generates and outputs a second signal S2.

[0042] The signal processing unit 90 receives an input of a first signal S1 from the first output unit 70 and an input of a second signal S2 from the second output unit 80. The signal processing unit 90 appropriately processes the first signal S1 and the second signal S2 to generate and output an output signal So. In the solid-state imaging device 1, the first transfer gate unit 30, the second transfer gate unit 40, the first horizontal transfer CCD unit 50, the second horizontal transfer CCD unit 60, the first output unit 70, the second output unit 80, and the signal processing unit 90 may be configured on the semiconductor substrate 2, or some of them may be configured outside the semiconductor substrate 2. In the solid-state imaging device 1, the first light receiving unit 5 and the second light receiving unit 6 may be formed on different semiconductor substrates and arranged as described above. [Specific examples of signal processing]

[0043] Next, specific signal processing that can be performed by the signal processing unit 90 will be described. Figures 5 and 6 are graphs showing various signals. The horizontal axis of each graph indicates the position of the first pixel area 11 or the second pixel area 21 in the second direction D2, and the vertical axis of each graph indicates the output value (voltage value).

[0044] In the following description, it is assumed that light is equally incident on the first pixel region 10 and the second pixel region 20. Equal incident light on the first pixel region 10 and the second pixel region 20 can be achieved, for example, by positioning the center of spread of incident light at the boundary between the first pixel region 10 and the second pixel region 20. For example, when an element isolation section (second region 3B) is interposed between the first pixel region 10 and the second pixel region 20 as shown in FIGS. 1 and 2, the boundary between the first pixel region 10 and the second pixel region 20 is the center of the element isolation section in the first direction D1. Furthermore, when the first pixel region 10 and the second pixel region 20 are in direct contact with each other as shown in FIGS. 3 and 4, the boundary is the actual boundary between the first pixel region 10 and the second pixel region 20.

[0045] 5(a) shows the first signal S1 input to the signal processing unit 90, and FIG. 5(b) shows the second signal S2 input to the signal processing unit 90. Here, in the first signal S1, WS occurs in one of the multiple first pixel areas 11, resulting in a relatively high output value V1. The first pixel area 11 exhibiting this output value V1 is referred to as the WS area (white dot area) 11a. In the second signal S2, WS occurs in one of the multiple second pixel areas 21, resulting in a relatively high output value V2. The second pixel area 21 exhibiting this output value V2 is referred to as the WS area 21a. The position of the WS area 11a in the second direction D2 and the position of the WS area 21a in the second direction D2 are different from each other.

[0046] As shown in FIG. 5C, the signal processing of the signal processor 90 includes a signal summing process for generating a signal summing process by adding the first signal S1 and the second signal S2 to generate a signal summing process. The signal summing process is performed by adding together the peaks of the output values ​​of the first signal S1 and the second signal S2, which correspond to the incident light images in the first pixel region 10 and the second pixel region 20, and increasing the peaks (e.g., by a factor of two). The signal summing process also includes an output value V1a corresponding to the output value V1 of the WS area 11a of the first signal S1 and an output value V2a corresponding to the output value V2 of the WS area 21a of the second signal S2. The output value V1a corresponding to the output value V1 is the sum of the output value V1 and the output value of the second pixel area 21 of the second signal S2, which corresponds to the WS area 11a of the first signal S1. The output value V2a corresponding to the output value V2 is the sum of the output value V2 and the output value of the first pixel area 11 of the first signal S1, which corresponds to the WS area 21a of the second signal S2.

[0047] 6A, the signal processing by the signal processor 90 includes a subtraction signal generation process in which the second signal S2 is subtracted from the first signal S1 to generate a subtraction signal S4. In the subtraction signal S4, the peaks of the output values ​​of the first signal S1 and the second signal S2, which correspond to the incident light images in the first pixel region 10 and the second pixel region 20, are subtracted from each other and removed. However, the output value V1b corresponding to the output value V1 in the WS area 11a of the first signal S1 and the output value V2b corresponding to the output value V2 in the WS area 21a of the second signal S2 are not removed and remain because they occur at positions that do not correspond to each other. The output value V1b corresponding to the output value V1 is the value obtained by subtracting the output value of the second pixel area 21 of the second signal S2, which corresponds to the WS area 11a of the first signal S1, from the output value V1. Furthermore, the output value V2b corresponding to the output value V2 is the value obtained by subtracting the output value V2 from the output value of the first pixel area 11 of the first signal S1 corresponding to the WS area 21a of the second signal S2, and is a negative value.

[0048] As shown in FIG. 6B, the signal processing by the signal processing unit 90 includes a correction signal generation process in which the sign of the output value V2b of the WS area 21a in the subtraction signal S4 is converted to positive to generate the output value V2c, and the correction signal S5 is generated. The signal processing by the signal processing unit 90 may also generate the correction signal S5 by converting the sign of the output value V1b of the WS area 11a in the subtraction signal S4 to negative. The signal processing unit 90 may further perform a noise removal process in which the output values ​​of the pixel areas (the first pixel area 11 and the second pixel area 21) that exhibit output values ​​between the positive threshold Tp and the negative threshold Tn in the correction signal S5 are set to 0. The timing of the noise removal process is arbitrary, and the noise removal process may be performed before the process inverting the sign of the output value V2b (or the output value V1b), or after or simultaneously with the process inverting the sign of the output value V2b (or the output value V1b).

[0049] As a result, noise other than that caused by WS is removed from the correction signal S5, leaving only the output values ​​V1b and V2c caused by WS (or the output value V1b with its negative sign and the output value V2b). The threshold values ​​Tp and Tn may be the same or different from each other, and may be set to any value that can remove noise.

[0050] As shown in FIG. 6(c), the signal processing by the signal processing unit 90 includes a correction process in which the sum signal S3 is corrected by subtracting the correction signal S5 generated from the subtraction signal S4 from the sum signal S3 to generate the output signal So. As a result, in the output signal So, only the output values ​​V1a and V2a are removed from the sum signal S3. In this way, the correction process by the signal processing unit 90 corrects the sum signal S3 based on the subtraction signal S4 and outputs the corrected sum signal S3. Note that if the signal processing unit 90 generates the correction signal S5 by changing the sign of the output value V1b of the WS area 11a in the subtraction signal S4 to negative, the signal processing unit 90 may add the correction signal S5 to the sum signal S3 to correct the sum signal S3 and generate the output signal So. This also removes only the output values ​​V1a and V2a from the sum signal S3. [Example of signal processing method]

[0051] Next, an example of a signal processing method for the solid-state imaging device 1 by the signal processing unit 90 will be described. FIG. 7 is a flowchart showing an example of a signal processing method according to this embodiment. As shown in FIG. 7, in the signal processing method according to this embodiment, first, imaging is performed (step S101). In step S101, imaging is performed by equally irradiating light to the first pixel region 10 and the second pixel region 20 (allowing similar light to be incident). In step S101, a first signal S1 and a second signal S2 corresponding to charges generated in the first pixel region 10 and the second pixel region 20 are generated and input to the signal processing unit 90.

[0052] Subsequently, the signal processing unit 90 adds the images (step S102: addition signal generation process, addition signal generation step). More specifically, in step S102, the signal processing unit 90 adds the first signal S1 (image captured in the first pixel region 10) and the second signal S2 (image captured in the second pixel region 20) to generate the addition signal S3.

[0053] At the same time, in the following step S103, the signal processing unit 90 performs image subtraction (step S103: subtraction signal generation processing, subtraction signal generation step). More specifically, in step S103, the signal processing unit 90 subtracts the second signal S2 from the first signal S1 to generate a subtraction signal S4. Note that the order of steps S102 and S103 does not matter.

[0054] Next, the signal processing unit 90 determines whether or not WS exists based on the subtraction signal S4 (step S104). More specifically, in step S104, the signal processing unit 90 sets a positive threshold Tp and a negative threshold Tn for the subtraction signal S4, and determines whether or not there is a pixel area (first pixel area 11) whose output value exceeds the positive threshold Tp and whether or not there is a pixel area (second pixel area 21) whose output value is below the negative threshold Tn in the subtraction signal S4.

[0055] If the result of the determination in step S104 is that WS is not detected in the subtraction signal S4 (step S104: No), the signal processing unit 90 outputs the addition signal S3 (image) as the output signal So (step S108) and ends the processing. In other words, if WS is not present in the subtraction signal S4, the signal processing unit 90 does not perform correction processing.

[0056] On the other hand, if the result of the judgment in step S104 is that WS is detected in the subtraction signal S4 (step S104: Yes), that is, if at least one of WS area 11a, which is a pixel area showing an output value V1 that exceeds the positive threshold value Tp, and WS area 21a, which is a pixel area showing an output value V2 that is below the negative threshold value Tn, is detected in the subtraction signal S4, the signal processing unit 90 performs image processing (step S105: correction processing, correction step).

[0057] More specifically, in step S105, when the signal processing unit 90 detects a WS area 21a that is a pixel area exhibiting an output value V2b that is below the negative threshold value Tn in the subtraction signal S4, the signal processing unit 90 changes the sign of the output value V2b of the WS area 21a in the subtraction signal S4 to positive to generate the correction signal S5. At this time, the signal processing unit 90 can set the output value of the pixel area exhibiting an output value between the positive threshold value Tp and the negative threshold value Tn in the correction signal S5 to 0.

[0058] Next, the signal processing unit 90 corrects the sum signal S3 by subtracting the correction signal S5 from the sum signal S3 to generate an output signal S0 (step S106: correction processing, correction step). This removes the output values ​​V1a and V2a caused by WS from the sum signal S3. In this way, in steps S105 and S106, the signal processing unit 90 corrects the sum signal S3 based on the subtraction signal S4. Note that in step S106, the signal processing unit 90 can correct the sum signal S3 by generating correction signals S5 in all first pixel areas 11 and all second pixel areas 21 and subtracting them from the sum signal S3.

[0059] After the above, the signal processing unit 90 outputs the corrected signal S5 as the output signal So (image) (step S107), and the process ends.

[0060] In step S105, when the signal processing unit 90 detects a WS area 11a that is a pixel area exhibiting an output value V1b that exceeds the positive threshold value Tp in the subtraction signal S4, the signal processing unit 90 may change the sign of the output value V1b of the WS area 11a in the subtraction signal S4 to negative to generate the correction signal S5. In this case, too, the signal processing unit 90 can set the output value of a pixel area that exhibits an output value between the positive threshold value Tp and the negative threshold value Tn in the correction signal S5 to 0.

[0061] In this case, in step S106, the signal processing unit 90 can correct the sum signal S3 by adding the correction signal S5 to the sum signal S3 to generate the output signal S0. This removes the output values ​​V1a and V2a caused by WS from the sum signal S3. Note that in this case as well, in step S106, the signal processing unit 90 may correct the sum signal S3 by generating the correction signal S5 in all the first pixel areas 11 and all the second pixel areas 21 and adding it to the sum signal S3. [Another example of a signal processing method]

[0062] Next, another example of the signal processing method of the solid-state imaging device 1 by the signal processing unit 90 will be described. Fig. 8 is a flowchart showing another example of the signal processing method according to this embodiment. As shown in Fig. 8, the signal processing method according to this example differs from the signal processing method of the example in Fig. 7 only in that step S106 of determining the presence or absence of WS is not performed.

[0063] That is, after generating the addition signal S3 and the subtraction signal S4 in steps S102 and S103, the signal processing unit 90 performs image processing in step S105 and image subtraction (or addition) in step S106, regardless of whether or not WS is present in the subtraction signal S4. This eliminates the need for processing to determine whether or not WS is present. [Another example of a signal processing method]

[0064] Next, another example of a signal processing method for the solid-state imaging device 1 by the signal processing unit 90 will be described. FIG. 9 is a flowchart showing another example of the signal processing method according to the present embodiment. As shown in FIG. 9, in the signal processing method according to this example, similar to the signal processing method of the example of FIG. 7, steps S101, S102, and S103 are performed to generate an addition signal S3 and a subtraction signal S4, and step S104 is performed to determine whether or not WS exists in the subtraction signal S4. Note that the subtraction signal S4 is generated by subtracting the second signal S2 from the first signal S1. Therefore, when a WS area 11a, which is a pixel area exhibiting an output value V1b exceeding a positive threshold Tp, is detected in the subtraction signal S4, this indicates that the first signal S1 contains an output value V1 corresponding to WS. When a WS area 21a, which is a pixel area exhibiting an output value V2b below a negative threshold Tn, is detected in the subtraction signal S4, this indicates that the second signal S2 contains an output value V2 corresponding to WS.

[0065] Thereafter, if the result of the judgment in step S104 is that WS is detected in the subtraction signal S4 (step S104: Yes), that is, if at least one of a WS area 11a, which is a pixel area showing an output value V1b that exceeds the positive threshold Tp, and a WS area 21a, which is a pixel area showing an output value V2b that is below the negative threshold Tn, is detected in the subtraction signal S4, the signal processing unit 90 extracts the position in the second direction D2 of the detected WS area 11a and / or WS area 21a (step S205).

[0066] Next, the signal processing unit 90 performs image processing on the sum signal S3 based on the information about the WS position extracted in step S205 (step S206: correction processing, correction step). More specifically, in step S206, if the WS area 11a is detected, the signal processing unit 90 replaces the output value V1a of the WS area 11a in the sum signal S3 with an output value obtained by doubling the output value of the second pixel area 21 at the position of the WS area 11a in the second signal S2.

[0067] Alternatively, in step S206, when the WS area 21a is detected, the signal processing unit 90 replaces the output value V2a of the WS area 21a in the sum signal S3 with an output value obtained by doubling the output value of the first pixel area 11 at the position of the WS area 21a in the first signal S1. This allows the output value V1a caused by WS, which is included in the sum signal S3, to be corrected to a normal value corresponding to the output value of the second signal S2, and the output value V2a caused by WS, which is included in the sum signal S3, to be corrected to a normal value corresponding to the output value of the first signal S1.

[0068] Thus, in step S206, if the subtraction signal S4 detects a WS area 11a, which is a pixel area exhibiting an output value V1b exceeding the positive threshold Tp, the signal processing unit 90 replaces the output value V1a of the WS area 11a in the sum signal S3 with an output value obtained by doubling the output value of the second pixel area 21 at the position of the WS area 11a in the second signal S2. Also, if the subtraction signal S4 detects a WS area 21a, which is a pixel area exhibiting an output value below the negative threshold Tn, the signal processing unit 90 replaces the output value V2a of the WS area 21a in the sum signal S3 with an output value obtained by doubling the output value of the first pixel area 11 at the position of the WS area 21a in the first signal S1. This removes the output values ​​V1a and V2a attributable to WS from the sum signal S3. Subsequent processing is similar to that in the example of FIG. 7.

[0069] In step S206, when replacing the output values ​​V1a and V2a of the sum signal S3 with the output values ​​of the first signal S1 and the second signal S2, the signal processing unit 90 may determine whether the output values ​​used for the replacement are appropriate. As an example of this case, the signal processing unit 90 may use a predetermined positive threshold Tpa that is set to be equal to or greater than the maximum output value of a pixel area where WS does not occur and equal to or less than an output value obtained by superimposing WS on an output value (noise) in the absence of incident light, to determine whether the output value used for the replacement is a value between 0 and the threshold Tpa. If the result of this determination shows that the output value used for the replacement is a value between 0 and the threshold Tpat, the replacement can be performed.

[0070] That is, in step S206, when a WS area 11a, which is a pixel area that exhibits an output value V1b that exceeds a positive threshold value Tp, is detected in the subtraction signal S4, and the output value of the second pixel area 21 at the position of the WS area 11a in the second signal S2 is a value between 0 and the threshold value Tpa, the signal processing unit 90 can replace the output value V1a of the WS area 11a in the addition signal S3 with an output value that is twice the output value of the second pixel area 21 at the position of the WS area 11a in the second signal S2.

[0071] Furthermore, in step S206, if a WS area 21a, which is a pixel area exhibiting an output value below the negative threshold Tn, is detected in the subtraction signal S4, and the output value of the first pixel area 11 at the position of the WS area 21a in the first signal S1 is a value between 0 and the threshold Tpa, the signal processing unit 90 can replace the output value V2a of the WS area 21a in the addition signal S3 with an output value obtained by doubling the output value of the first pixel area 11 at the position of the WS area 21a in the first signal S1. Note that the positive threshold Tpa used here may be a value different from the positive threshold Tp used to determine the presence or absence of WS in the subtraction signal S4 in step S104. [Actions and Effects]

[0072] As described above, the solid-state imaging device 1 according to this embodiment is provided with a first light receiving section 5 and a second light receiving section 6 that generate electric charges in response to incident light. The first light receiving section 5 has a first pixel region 10 configured by first pixel areas 11 including a plurality of first pixels 12 arranged along the second direction D2, and the second light receiving section 6 similarly has a second pixel region 20 configured by second pixel areas 21 including a plurality of second pixels 22 arranged along the second direction D2. In the first light receiving section 5 and the second light receiving section 6, electric charges are generated in the first pixels 12 and the second pixels 22, respectively, in response to incident light.

[0073] When the first pixel area 11 and the second pixel area 20 are arranged along the first direction D1 so that the ends of the first pixel area 10 and the second pixel area 20 in the second direction D2 coincide with each other (they are actually arranged in this manner in the present embodiment), each of the multiple first pixel areas 11 corresponds to each of the multiple second pixel areas 21 so that they are lined up along the first direction D1. Therefore, in the solid-state imaging device 1, by irradiating the first light receiving section 5 (first pixel region 10) and the second light receiving section 6 (second pixel region 20) with the same or corresponding light, a correspondence is generated between a first signal S1 corresponding to the charge from the first light receiving section 5 and a second signal S2 corresponding to the charge from the second light receiving section 6.

[0074] Therefore, by generating a subtraction signal S4 between the first signal S1 and the second signal S2, the signal processing unit 90 obtains information about output values ​​V1 and V2 due to WS, which may occur regardless of the correspondence between the first signal S1 and the second signal S2 (e.g., information about the position of the pixel area that generates the output values ​​V1 and V2 due to WS, or the signal itself including the output values ​​V1 and V2). Therefore, by correcting the addition signal S3 (the output signal So before correction) of the first signal S1 and the second signal S2 generated by the signal processing unit 90 based on this subtraction signal S4, it is possible to remove the output values ​​V1a and V2a due to WS. Therefore, even if WS occurs over time, its influence can be suppressed and continuous use is possible. In other words, the life of the solid-state imaging device 1 is extended.

[0075] Furthermore, in the solid-state imaging device 1 according to this embodiment, in the correction process, the signal processing unit 90 generates a correction signal S5 based on the subtraction signal S4 and corrects the sum signal S3 by subtracting the correction signal S5 from the sum signal S3. At this time, if the correction signal S5 identifies a WS area 21a, which is a pixel area exhibiting an output value V2b below the negative threshold Tn, the sign of the output value V2b in the WS area 21a is changed to positive. Therefore, by subtracting the correction signal S5 from the sum signal S3, the output values ​​V1a and V2a due to WS can be removed from the sum signal S3 to generate the output signal So.

[0076] Furthermore, in the solid-state imaging device 1 according to this embodiment, in the correction process, the signal processing unit 90 can set the output value of a pixel area that exhibits an output value between the positive threshold Tp and the negative threshold Tn in the correction signal S5 to 0. This prevents noise from being superimposed due to the subtraction of the correction signal S5.

[0077] Furthermore, in the solid-state imaging device 1 according to this embodiment, in the correction process, the signal processing unit 90 generates correction signals S5 in all of the first pixel areas 11 and all of the second pixel areas 21, and corrects the sum signal S3 by subtracting the correction signals S5 from the sum signal S3. This makes it possible to remove the output values ​​V1a and V2a caused by WS from the sum signal S3 without specifying the position of the WS area.

[0078] In the solid-state imaging device 1 according to this embodiment, the signal processing unit 90 may, in the correction process, generate a correction signal S5 based on the subtraction signal S4 and add the correction signal S5 to the sum signal S3 to correct the sum signal S3. In this case, if the correction signal S5 identifies a WS area 11a, which is a pixel area exhibiting an output value V1b that exceeds a positive threshold Tp, the sign of the output value V1b in the WS area 11a may be changed to negative. In this case, adding the correction signal S5 to the sum signal S3 makes it possible to remove the output values ​​V1a and V2a due to WS from the sum signal S3.

[0079] In this case, the signal processing unit 90 may correct the sum signal S3 by generating correction signals S5 in all first pixel areas 11 and all second pixel areas 21 and adding the correction signals S5 to the sum signal S3 in the correction process. In this case, it is possible to remove the output values ​​V1a and V2a caused by WS from the sum signal S3 without specifying the position of the WS area.

[0080] Furthermore, in the solid-state imaging device 1 according to the present embodiment, in the correction process, when the signal processing unit 90 detects in the subtraction signal S4 at least one of a WS area 11a exhibiting an output value V1b exceeding a positive threshold Tp and a WS area 21a exhibiting an output value V2b below a negative threshold Tn, the signal processing unit 90 can replace the output values ​​V1a and V2a of the WS areas 11a and 21a in the sum signal S3 with an output value obtained by doubling the output value of a pixel area in the first pixel area 11 at the position of the WS area 11a and 21a in the first signal S1 and the second pixel area 21 at the position of the WS area 11a and 21a in the second signal S2, the output value of which is between the positive threshold Tpa and 0. Therefore, subtraction and addition of the correction signal S5 are not necessary when removing the output values ​​V1a and V2a due to WS from the sum signal S3.

[0081] Furthermore, in the solid-state imaging device 1 according to this embodiment, the signal processing unit 90 can execute the correction process when at least one of a WS area 11a indicating an output value V1b exceeding a positive threshold Tp and a WS area 21a indicating an output value V2b below a negative threshold Tn is detected in the subtraction signal S4. Therefore, when a WS area is not detected, the execution of the correction process can be omitted.

[0082] The solid-state imaging device 1 according to this embodiment also includes a first transfer gate section 30 for transferring charges from each of the first pixel areas 11, a second transfer gate section 40 for transferring charges from each of the second pixel areas 21, a first horizontal transfer CCD section 50 for transferring the charges transferred by the first transfer gate section 30 to the first output section 70, and a second horizontal transfer CCD section 60 for transferring the charges transferred by the second transfer gate section 40 to the second output section 80. This makes it possible to extend the life of the solid-state imaging device 1 including a CCD.

[0083] Furthermore, in the solid-state imaging device 1 according to this embodiment, the first pixel region 10 and the second pixel region 20 are arranged in the first direction D1 such that each of the first pixel areas 11 and each of the second pixel areas 21 are aligned along the first direction D1. This makes it easy to cause the same or corresponding light to be incident on the first pixel region 10 and the second pixel region 20.

[0084] Furthermore, in the solid-state imaging device 1 according to this embodiment, the first pixel region 10, the first transfer gate unit 30, and the first horizontal transfer CCD unit 50 are arranged in order toward one side of the first direction D1, and the second pixel region 20, the second transfer gate unit 40, and the second horizontal transfer CCD unit 60 are arranged in order toward the opposite side of the first direction D1. This makes it possible to appropriately arrange the first horizontal transfer CCD unit 50, the second horizontal transfer CCD unit 60, the first transfer gate unit 30, and the second transfer gate unit 40 with respect to the first pixel region 10 and the second pixel region 20, which are arranged in a manner that facilitates the incidence of the same or corresponding light.

[0085] The solid-state imaging device 1 according to this embodiment also includes a first output section 70 for receiving charges generated in the first light receiving section 5 and outputting a first signal S1, and a second output section 80 for receiving charges generated in the second light receiving section 6 and outputting a second signal S2. By providing output sections corresponding to the first light receiving section 5 and the second light receiving section 6 in this way, the processing speed can be improved.

[0086] In the solid-state imaging device 1 according to this embodiment, the first pixel area 11 includes a plurality of first pixels 12 arranged along the first direction D1, and the second pixel area 21 includes a plurality of second pixels 22 arranged along the first direction D1. This enables binning, resulting in a good signal-to-noise ratio of the output signal So.

[0087] Furthermore, in the solid-state imaging device 1 according to this embodiment, the first pixel region 10 and the second pixel region 20 are arranged adjacent to each other (with an element isolation portion interposed in some cases). Therefore, by arranging the first pixel region 10 and the second pixel region 20 closely, the characteristics between the regions become similar, and more appropriate correction can be performed.

[0088] Furthermore, the signal processing method according to this embodiment also contributes to extending the life of the solid-state imaging device 1 for the same reasons as above.

[0089] The above embodiment has described one aspect of the present invention. Therefore, the present invention is not limited to the above embodiment, and the aspects shown in the above embodiment may be modified in any manner. Next, modifications will be described. [First Modification]

[0090] Fig. 10 is a schematic plan view showing a first modified example of a solid-state imaging device. Fig. 11 is a partial schematic cross-sectional view taken along line XI-XI in Fig. 10, and a schematic diagram showing the potential in the cross-section. The cross-sectional view taken along line XI-XI (without hatching) is shown in the upper part of Fig. 11, and the potential V in the cross-section is shown in the lower part of Fig. 11.

[0091] 10 and 11 differs from the solid-state imaging device 1 according to the embodiment in that the solid-state imaging device 1A is a resistive gate CCD, whereas the solid-state imaging device 1 according to the embodiment is a binning CCD. Specifically, the solid-state imaging device 1A differs from the solid-state imaging device 1 in that the solid-state imaging device 1A includes a first pixel region 10A instead of the first pixel region 10, and a second pixel region 20A instead of the second pixel region 20.

[0092] The first pixel region 10A has a plurality of first pixel areas 11A arranged along the second direction D2. Each of the first pixel areas 11A includes one first pixel 12A extending along the first direction D1. The first pixel 12A generates charges in response to incident light. Therefore, the first pixel region 10A constitutes a first light receiving section 5 that generates charges in response to incident light.

[0093] The second pixel region 20A has a plurality of second pixel areas 21A arranged along the second direction D2. Each second pixel area 21A includes one second pixel 22A extending along the first direction D1. The second pixel 22A generates charges in response to incident light. Therefore, the second pixel region 20A constitutes a second light receiving section 6 that generates charges in response to incident light.

[0094] Here too, the first pixel region 10A and the second pixel region 20A are arranged so that their ends in the second direction D2 coincide, so that each of the multiple first pixel areas 11A and each of the multiple (same number as the first pixel areas 11A) second pixel areas 21A are arranged in the first direction D1.

[0095] The cross-sectional structure of the solid-state imaging device 1A is the same as that of the solid-state imaging device 1, and includes a semiconductor substrate 2 and a semiconductor layer 3, but also includes a high-resistance electrode F2A constituting a resistive gate structure on an insulating film F1. The high-resistance electrodes F2A are provided on a pair of first regions 3A of the semiconductor layer 3, respectively, and define individual first pixels 12A (first pixel areas 11A) and second pixels 22A (second pixel areas 21A). In the solid-state imaging device 1A, a potential slope is formed by applying different voltages to both ends of the high-resistance electrode F2A, and charge e is transferred. This enables high-speed transfer and enables readout with minimal unread residue even when the pixel height is large.

[0096] In the example of Figures 10 and 11, an element separation portion formed by the second region 3B is interposed between the first light receiving portion 5 (first pixel region 10A) and the second light receiving portion 6 (second pixel region 20A). However, as shown in Figures 12 and 13, by not providing the second region 3B of the first conductivity type in the semiconductor layer 3, the first light receiving portion 5 (first pixel region 10A) and the second light receiving portion 6 (second pixel region 20A) may be arranged adjacent to each other in the first direction D1 without an element separation portion therebetween.

[0097] Fig. 12 is a schematic plan view showing another example of a solid-state imaging device according to a modified example. Fig. 13 is a partial schematic cross-sectional view taken along line XIII-XIII in Fig. 12, and a schematic diagram showing the potential at the cross-section. The cross-sectional view taken along line XIII-XIII (without hatching) is shown in the upper part of Fig. 13, and the potential V at the cross-section is shown in the lower part of Fig. 13. [Second Modification]

[0098] Fig. 14 is a schematic plan view showing a second modified example of a solid-state imaging device. Fig. 15 is a schematic plan view showing an enlarged portion of Fig. 14. Fig. 16 is a partial schematic cross-sectional view taken along line XVI-XVI in Figs. 14 and 15, and a schematic diagram showing the potential at the cross-section. The cross-sectional view taken along line XVI-XVI (without hatching) is shown in the upper part of Fig. 16, and the potential V at the cross-section is shown in the lower part of Fig. 16.

[0099] 14 to 16 differs from the solid-state imaging device 1 according to the embodiment in that the solid-state imaging device 1B is a buried PD (Photodiode) CCD, whereas the solid-state imaging device 1 according to the embodiment is a binning CCD. Specifically, the solid-state imaging device 1B differs from the solid-state imaging device 1 in that the first pixel region 10 is replaced with a first pixel region 10B, and the second pixel region 20 is replaced with a second pixel region 20B.

[0100] The first pixel region 10B has a plurality of first pixel areas 11B arranged along the second direction D2. Each of the first pixel areas 11B includes one first pixel 12B extending along the first direction D1. The first pixel 12B generates charges in response to incident light. Therefore, the first pixel region 10B constitutes a first light receiving section 5 that generates charges in response to incident light.

[0101] The second pixel region 20B has a plurality of second pixel areas 21B arranged along the second direction D2. Each second pixel area 21B includes one second pixel 22B extending along the first direction D1. The second pixel 22B generates charges in response to incident light. Therefore, the second pixel region 20B constitutes a second light receiving section 6 that generates charges in response to incident light.

[0102] Here too, the first pixel region 10B and the second pixel region 20B are arranged so that their ends in the second direction D2 coincide, so that each of the multiple first pixel areas 11B and each of the multiple (same number as the first pixel areas 11B) second pixel areas 21B are arranged in the first direction D1.

[0103] The cross-sectional structure of the solid-state imaging device 1B is the same as that of the solid-state imaging device 1, and includes a semiconductor substrate 2 and a semiconductor layer 3, but a first conductivity type (here, P + As a result, a P type semiconductor layer 4 is formed on the front surface side of the first light receiving section 5 and the second light receiving section 6. + P with a diffusion layer (semiconductor layer 4) + N + P structure is formed.

[0104] In addition, the semiconductor layer 3 includes, in a region corresponding to the first region 3A of the semiconductor layer 3 of the solid-state imaging device 1, a channel portion 3Ab of a second conductivity type (N type in this case) and a second conductivity type (N type in this case) having a higher impurity concentration than the channel portion 3Ab. + The channel additional injection portion 3Aa is formed so as to widen toward the first transfer gate portion 30 and the second transfer gate portion 40, respectively. This forms a potential slope to transfer the charge e. With this structure, no transfer electrode is formed, and high quantum efficiency is achieved even in a front-illuminated type. [Other variations]

[0105] The above-described solid-state imaging device 1 (and solid-state imaging devices 1A, 1B (same below)) is configured as a CCD image sensor having a transfer gate and a horizontal transfer gate CCD section, but may also be configured as a CMOS image sensor instead of a CCD image sensor.

[0106] Furthermore, in the solid-state imaging device 1, the first pixel region 10 and the second pixel region 20 are arranged so that their ends in the second direction D2 coincide with each other, so that each of the multiple first pixel areas 11 and each of the multiple (same number as the first pixel areas 11) second pixel areas 21 are arranged in the first direction D1. However, when the first pixel region 10 and the second pixel region 20 are arranged along the first direction D1 so that their ends in the second direction D2 coincide with each other, it is only necessary that each of the multiple first pixel areas 11 and each of the multiple second pixel areas 21 are associated with each other so that they are lined up along the first direction D1.

[0107] That is, the first pixel region 10 and the second pixel region 20 may be arranged along the first direction D1 with their ends in the second direction D2 misaligned (shifted in the second direction D2) from each other. In this case, the first pixel area 11, which is a part of the first pixel region 10, and the second pixel area 21, which is a part of the second pixel region 20, are aligned so as to overlap in the first direction. Alternatively, the first pixel region 10 and the second pixel region 20 may be arranged along the second direction D2 without having any overlapping portions in the first direction D1.

[0108] Furthermore, the positional relationships between the first pixel region 10 and the second pixel region 20, the first transfer gate unit 30 and the second transfer gate unit 40, and the first horizontal transfer CCD unit 50 and the second horizontal transfer CCD unit 60 are not limited to the above-described form and may be modified as desired. For example, the respective units may be arranged in the following order from one side to the other in the first direction D1: second pixel region 20, second transfer gate unit 40, second horizontal transfer CCD unit 60, first pixel region 10, first transfer gate unit 30, first horizontal transfer CCD unit 50.

[0109] Although the solid-state imaging device 1 includes the first output section 70 and the second output section 80 as output sections, it may include only one output section. Furthermore, a gap other than the element isolation section may be formed between the first pixel region 10 and the second pixel region 20, so that the first pixel region 10 and the second pixel region 20 are spaced apart from each other.

[0110] Furthermore, while the solid-state imaging device 1 has two pixel regions, the first pixel region 10 and the second pixel region 20, the number of pixel regions is not limited to two and may be any number n. When there are three or more pixel regions, correction for removing output values ​​caused by WS can be performed more reliably than when there are two pixel regions. That is, when there are three or more pixel regions, even if WS occurs in pixel areas at the same position corresponding to each other in two of the pixel regions, the same correction as above can be performed using signals from the remaining pixel regions.

[0111] When there are two or more pixel regions (n), first, two pixel regions are selected from the n pixel regions, and the correction signal S5 is generated or the position of the WS area is extracted in the same manner as described above. This is then performed for all combinations of pixel regions. Next, the correction signals S5 or the position information of the WS area obtained from all combinations are combined to complete the correction signal S5 or position information. Then, the obtained correction signal S5 is subtracted from the sum signal S3 of the signals from all pixel regions, or the output value is replaced according to the position information, to generate the output signal So.

[0112] Furthermore, the invention is not limited to equally incident light on the first pixel region 10 and the second pixel region 20, and light having a known correspondence may be incident on each of them. As an example, light having a known correspondence is a state in which, when one light is split and incident on the first pixel region 10 and the second pixel region 20, the light intensities of the first pixel region 10 and the second pixel region 20 are in a known ratio. [Explanation of symbols]

[0113] 1, 1A, 1B... solid-state imaging device, 5... first light receiving section, 6... second light receiving section, 10, 10A, 10B... first pixel region, 11, 11A, 11B... first pixel area, 12, 12A, 12B... first pixel, 20, 20A, 20B... second pixel region, 21, 21A, 21B... second pixel area, 22, 22A, 22B... second pixel, 30... first transfer gate section, 40... second transfer gate section, 50... first horizontal transfer CCD section, 60... second horizontal transfer CCD section, 70... first output section (output section), 80... second output section, 90... signal processing section, S1... first signal, S2... second signal, S3... addition signal, S4... subtraction signal, S5... correction signal, So... output signal.

Claims

1. a first light receiving section and a second light receiving section that generate electric charges in response to incidence of light; an output section for outputting a first signal corresponding to the charge generated in the first light receiving section and a second signal corresponding to the charge generated in the second light receiving section; a signal processing unit for processing the signal output from the output unit; Equipped with the first light receiving unit has a first pixel region configured by arranging a plurality of first pixels arranged along a first direction or a plurality of first pixel areas, which are pixel areas including one first pixel, along a second direction intersecting the first direction; the second light receiving unit has a second pixel region configured by arranging a plurality of second pixels arranged along the first direction or a plurality of second pixel areas, each of which is a pixel area including one second pixel, along the second direction; the first pixel areas and the second pixel areas are associated with each other such that, when the first pixel areas and the second pixel areas are arranged along the first direction such that end portions of the first pixel areas and the second pixel areas in the second direction coincide with each other, each of the first pixel areas and each of the second pixel areas are aligned along the first direction; The signal processing by the signal processing unit is an addition signal generation process of generating an addition signal by adding the first signal and the second signal; a subtraction signal generation process for generating a subtraction signal by subtracting the second signal from the first signal; a correction process for correcting the addition signal based on the subtraction signal and outputting the corrected addition signal; Including, Solid-state imaging device.

2. the signal processing unit, in the correction processing, generates a correction signal based on the subtraction signal, and corrects the addition signal by subtracting the correction signal from the addition signal; In the correction signal, when a white point area, which is the pixel area exhibiting an output value below a negative threshold, is recognized, the sign of the output value of the white point area is changed to positive. The solid-state imaging device according to claim 1 .

3. In the correction process, the signal processing unit generates the correction signal in all of the first pixel areas and all of the second pixel areas, and corrects the sum signal by subtracting the correction signal from the sum signal. The solid-state imaging device according to claim 2 .

4. the signal processing unit, in the correction processing, generates a correction signal based on the subtraction signal, and corrects the addition signal by adding the correction signal to the addition signal; In the correction signal, when a white point area, which is the pixel area exhibiting an output value exceeding a positive threshold, is detected, the sign of the output value of the white point area is changed to negative. The solid-state imaging device according to claim 1 .

5. In the correction process, the signal processing unit generates the correction signals in all of the first pixel areas and all of the second pixel areas, and corrects the sum signal by adding the correction signals to the sum signal. The solid-state imaging device according to claim 4 .

6. In the correction process, the signal processing unit sets an output value of the pixel area that indicates an output value between a positive threshold and a negative threshold in the correction signal to 0.

6. The solid-state imaging device according to claim 2.

7. In the correction process, when a white dot area, which is the pixel area exhibiting an output value greater than a positive threshold, is detected in the subtraction signal, the signal processing unit replaces the output value of the white dot area in the addition signal with an output value obtained by doubling the output value of the second pixel area at the position of the white dot area in the second signal, and when a white dot area, which is the pixel area exhibiting an output value less than a negative threshold, is detected in the subtraction signal, the signal processing unit replaces the output value of the white dot area in the addition signal with an output value obtained by doubling the output value of the first pixel area at the position of the white dot area in the first signal. The solid-state imaging device according to claim 1 .

8. the signal processing unit executes the correction process when at least one of a white dot area, which is the pixel area exhibiting an output value greater than a positive threshold, and a white dot area, which is the pixel area exhibiting an output value less than a negative threshold, is detected in the subtraction signal. The solid-state imaging device according to claim 1 .

9. a first transfer gate portion for transferring charges from each of the first pixel areas; a second transfer gate portion for transferring charges from each of the second pixel areas; a first horizontal transfer CCD unit for transferring the charges transferred by the first transfer gate unit to the output unit; a second horizontal transfer CCD unit for transferring the charges transferred by the second transfer gate unit to the output unit; The solid-state imaging device according to claim 1 .

10. the first pixel regions and the second pixel regions are arranged in the first direction such that each of the first pixel areas and each of the second pixel areas are aligned along the first direction; The solid-state imaging device according to claim 9 .

11. the first pixel region, the first transfer gate unit, and the first horizontal transfer CCD unit are sequentially arranged toward one side in the first direction, the second pixel region, the second transfer gate unit, and the second horizontal transfer CCD unit are sequentially arranged toward an opposite side of the first direction; The solid-state imaging device according to claim 10.

12. The output unit a first output section for receiving the charge generated in the first light receiving section and outputting the first signal; a second output section for receiving the charge generated in the second light receiving section and outputting the second signal; The solid-state imaging device according to claim 1 ,

13. the first pixel area includes a plurality of first pixels arranged along the first direction; the second pixel area includes a plurality of second pixels arranged along the first direction; The solid-state imaging device according to claim 1 .

14. The first pixel region and the second pixel region are disposed adjacent to each other. The solid-state imaging device according to claim 1 .

15. A signal processing method for a solid-state imaging device including a first light receiving section and a second light receiving section for generating charges in response to incidence of light, and an output section for outputting a first signal in response to the charges generated in the first light receiving section and a second signal in response to the charges generated in the second light receiving section, an addition signal generating step of generating an addition signal by adding the first signal and the second signal; a subtraction signal generating step of subtracting the second signal from the first signal to generate a subtraction signal; a correction step of correcting the addition signal based on the subtraction signal and outputting the corrected addition signal; Equipped with the first light receiving unit has a first pixel region configured by arranging a plurality of first pixels arranged along a first direction or a plurality of first pixel areas, which are pixel areas including one first pixel, along a second direction intersecting the first direction; the second light receiving unit has a second pixel region configured by arranging a plurality of second pixels arranged along the first direction or a plurality of second pixel areas, each of which is a pixel area including one second pixel, along the second direction; the first pixel areas and the second pixel areas are associated with each other such that, when the first pixel areas and the second pixel areas are arranged along the first direction such that end portions of the first pixel areas and the second pixel areas in the second direction coincide with each other, each of the first pixel areas and each of the second pixel areas is aligned along the first direction; Signal processing methods.

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