Charge / discharge control device and battery device equipped with the same

Abstract

To provide a cell number determination device with a small circuit scale, a charge / discharge control device and a battery device.SOLUTION: A device includes: a plurality of differential amplifiers provided in accordance with a plurality of cells which can be increased or decreased in a battery pack mounting a plurality of cells connected in series; and a plurality of output circuits provided in accordance with the plurality of differential amplifiers. An input differential pair of the differential amplifiers is constituted by different pole gate NMOS transistor and NMOS transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a charge / discharge control device and a battery device that are provided with a cell number determination circuit. [Background technology]

[0002] A cell number determination device is disclosed that includes a voltage measurement unit that selects an i-th cell from a plurality of serially connected cells that constitute a battery, and measures the voltage value between the terminal to which the selected cell is connected and the (i-1)th cell one level above, and ground potential, a voltage comparison unit that compares the voltage value of the (i+1)th cell one level below the i-th cell with the voltage value of the i-th cell to determine the presence or absence of the i-th cell, and a cell number determination unit that determines the number of cells installed in the battery based on the comparison result of the voltage comparison unit (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-233359 A Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional cell number determination devices have a problem in that the circuit scale of the voltage measurement unit and voltage comparison unit is large.

[0005] The present invention has been made in consideration of the above problems, and has an object to provide a cell number determination device, a charge / discharge control device, and a battery device that have small circuit scales. [Means for solving the problem]

[0006] In order to solve the above problems, the cell number determination circuit of the present invention is a cell number determination circuit that determines the cell number of a battery pack having a plurality of cells connected in series, and is characterized in that it comprises a plurality of differential amplifiers provided corresponding to a plurality of cells that can be increased or decreased in the battery pack, and a plurality of output circuits provided corresponding to the plurality of differential amplifiers, and an input differential pair of the differential amplifiers is composed of an opposite-gate NMOS transistor and an NMOS transistor. Also, a charge / discharge control device and a battery device each including the cell number determination circuit. Effect of the Invention

[0007] According to the charge / discharge control device of the present invention, since the input differential pair of the differential amplifier of the cell detection circuit is composed of opposite polarity gate NMOS transistors and NMOS transistors, it is possible to provide a cell number determination device, a charge / discharge control device, and a battery device with small circuit scale. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a charge / discharge control device and a battery device equipped with a cell number determination circuit according to an embodiment of the present invention; [Diagram 2] 1 is a block diagram showing an example in which a battery having a reduced number of cells is connected to the battery device of the present embodiment; [Diagram 3] FIG. 4 is a block diagram showing another example of the charge / discharge control device of the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] FIG. 1 is a block diagram showing a charge / discharge control device and a battery device equipped with a cell number determination circuit of this embodiment.

[0010] The battery device 1 includes a charge / discharge control device 3, a battery pack 2 of 6 series cells, a discharge control FET 4, a charge control FET 5, and external terminals P+ and P-. The battery pack 2 includes cells 21 to 26 connected in series.

[0011] The charge / discharge control device 3 includes a charge / discharge control circuit 30, PMOS transistors PM1 to PM6, different gate NMOS transistors NM1 and NM3, NMOS transistors NM2 and NM4, constant current sources I1 to I4, power supply terminals VDD, a ground terminal VSS, input terminals VC1 to VC6, and output terminals CO and DO. The PMOS transistors PM1 to PM6, the different gate NMOS transistors NM1 and NM3, the NMOS transistors NM2 and NM4, and the constant current sources I1 to I4 configure a cell number determination circuit.

[0012] The battery pack 2, the discharge control FET 4, and the charge control FET 5 are connected in series between the external terminal P+ and the external terminal P-. The cells 21-26 of the battery pack 2 are connected to the power supply terminal VDD, the input terminals VC1-VC6, and the ground terminal VSS of the charge / discharge control device 3, respectively. The gate of the discharge control FET 4 is connected to the output terminal DO of the charge / discharge control device 3. The gate of the charge control FET 5 is connected to the output terminal CO of the charge / discharge control device 3.

[0013] The cell number determination circuit is composed of a first cell detection circuit which detects the presence or absence of cell 22, i.e., whether it is a 4-series cell, and a second cell detection circuit which detects the presence or absence of cell 21, i.e., whether it is a 5-series cell.

[0014] The first cell detection circuit includes PMOS transistors PM1, PM2, and PM3, a different polarity gate NMOS transistor NM1, an NMOS transistor NM2, and constant current sources I1 and I3. The PMOS transistors PM1 and PM2, the NMOS transistors NM1 and NM2 with different gates, and the constant current source I1 constitute a differential amplifier. The PMOS transistor PM3 and the constant current source I3 constitute an output circuit.

[0015] The gate of the opposite-gate NMOS transistor NM1 is connected to the input terminal VC1 and receives the voltage VDD. The gate of the NMOS transistor NM2 is connected to the input terminal VC5 and receives the voltage VC5 of the input terminal VC5.

[0016] The input differential pair of the differential amplifier is composed of opposite gate NMOS transistor NM1 and NMOS transistor NM2. The threshold Vth of the opposite gate NMOS transistor NM1 is 1.7V, and the threshold Vth of the NMOS transistor NM2 is 0.7V. These transistors have the same configuration except for the gate polarity, so they have the same temperature characteristics and offset, and the tendency of the threshold Vth to vary is also the same. Therefore, the difference in threshold Vth of these transistors can be set to 1.0V with high accuracy. In other words, the differential amplifier can detect a difference of input voltage within 1.0V without providing an offset to the input differential pair.

[0017] The second cell detection circuit includes PMOS transistors PM4, PM5, and PM6, a different polarity gate NMOS transistor NM3, an NMOS transistor NM4, and constant current sources I2 and I4. The PMOS transistors PM4 and PM5, the NMOS transistors NM3 and NM4, and the constant current source I2 constitute a differential amplifier. The PMOS transistor PM6 and the constant current source I4 constitute an output circuit.

[0018] The gate of the opposite-gate NMOS transistor NM3 is connected to the input terminal VC1 and receives the voltage VDD. The gate of the NMOS transistor NM4 is connected to the input terminal VC6 and receives the voltage VC6 of the input terminal VC6.

[0019] The input differential pair of the differential amplifier is composed of opposite gate NMOS transistor NM3 and NMOS transistor NM4. The threshold Vth of the opposite gate NMOS transistor NM3 is 1.7V, and the threshold Vth of the NMOS transistor NM4 is 0.7V. These transistors have the same configuration except for the gate polarity, so they have the same temperature characteristics and offset, and the tendency of the threshold Vth to vary is also the same. Therefore, the difference in threshold Vth of these transistors can be set to 1.0V with high accuracy. In other words, the differential amplifier can detect a difference of input voltage within 1.0V without providing an offset to the input differential pair.

[0020] The charge / discharge control circuit 30 has first to sixth input terminals connected to input terminals VC1 to VC6, receives the respective terminal voltages, and monitors the voltage of each cell. The charge / discharge control circuit 30 also has a first cell number detection terminal connected to the output terminal of a first cell detection circuit, and a second cell number detection terminal connected to the output terminal of a second cell detection circuit, detecting the number of cells in the battery pack.

[0021] 2 is a block diagram showing an example in which a battery pack 2 in which the number of cells of the battery device of this embodiment is reduced to four is connected. Since the configuration is the same as that of FIG. 1 except for the connection between the battery pack 2 and the charge / discharge control device 3, a description thereof will be omitted.

[0022] Since the cells 21 and 22 are eliminated from the battery pack 2, the output terminals of each are connected to the positive terminal of the cell 26, and therefore the voltage VDD is output. The charge / discharge control device 3 has the voltage VDD input to the input terminals VC5 and VC6, and therefore the voltage VDD is input to the gates of the NMOS transistors NM2 and NM4.

[0023] The operation of the cell number determination circuit of the charge / discharge control device 3 of this embodiment will be described below. Here, the voltage of each cell is assumed to be 3V.

[0024] First, a case where a battery pack 2 having 6 series cells is connected to a charge / discharge control device 3 as shown in FIG. 1 will be described.

[0025] The gate of the opposite-gate NMOS transistor NM1 of the first cell detection circuit is supplied with the voltage VDD, and the gate of the NMOS transistor NM2 is supplied with the voltage VC5 of the input terminal VC5. The voltage VDD is 18V, and the voltage VC5 is 6V. Therefore, the first cell detection circuit outputs an L-level signal from its output terminal, indicating that a cell is connected. Similarly, the second cell detection circuit also outputs an L-level signal from its output terminal.

[0026] Since the L level signals are input to the first cell number detection terminal and the second cell number detection terminal, the charge / discharge control circuit 30 determines that the connected battery pack 2 is a 6-series cell battery.

[0027] Next, a case where a battery pack 2 having four series cells is connected to a charge / discharge control device 3 as shown in FIG. 2 will be described.

[0028] The voltage VDD is input to the gates of the opposite gate NMOS transistor NM1 and the NMOS transistor NM2 of the first cell detection circuit. At this time, the threshold Vth of the opposite gate NMOS transistor NM1 is 1.7 V, and the threshold Vth of the NMOS transistor NM2 is 0.7 V. The same voltage VDD is input to the input differential pair, but due to the difference in threshold Vth, the current flowing through the NMOS transistor NM2 is greater than the current flowing through the PMOS transistor PM2.

[0029] Therefore, the first cell detection circuit outputs an H-level signal from its output terminal, indicating that no cell is connected. Similarly, the second cell detection circuit also outputs an H-level signal from its output terminal.

[0030] Since the H level signals are input to the first cell number detection terminal and the second cell number detection terminal, the charge / discharge control circuit 30 determines that the connected battery pack 2 is a 4-series cell battery.

[0031] As described above, in the cell number determination circuit of this embodiment, the input differential pair of the differential amplifier of the cell detection circuit is configured with opposite gate NMOS transistors and NMOS transistors, so that the cell number determination circuit can accurately detect the presence or absence of cells despite the simple circuitry.

[0032] FIG. 3 is a block diagram showing another example of the charge / discharge control device 3 of the present embodiment. The charge / discharge control device 3 in FIG. 3 has a configuration in which the PMOS transistor PM4, opposite gate NMOS transistor NM3, and constant current source I2 of the second cell detection circuit are shared with the PMOS transistor PM1, opposite gate NMOS transistor NM1, and constant current source I3 of the first cell detection circuit, i.e., the MOS transistor and constant current source on the opposite gate NMOS transistor NM3 side are shared, thereby reducing the number of elements.

[0033] The operation of the circuit is similar to that of the charge / discharge control device 3 in FIG. The charge / discharge control device 3 configured in this way can be configured with a minimum increase in elements even when the number of cell number detection circuits is increased.

[0034] Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention. For example, a configuration has been described in which a first cell detection circuit and a second cell detection circuit are provided for a battery pack with 6 series cells to 4 series cells, but the number of cells in the battery pack and the number of cells that can be increased or decreased are not limited to this, and therefore the number of cell detection circuits that make up the cell number determination circuit is also not limited. [Explanation of symbols]

[0035] 1 Battery device 2 Battery pack 3. Charge / discharge control device 4 Discharge control FET 5 Charge control FET 30 Charge / discharge control circuit PM1, PM2, PM3, PM4, PM5, PM6 PMOS transistors NM1, NM3 Different gate NMOS transistors NM2, NM4 NMOS transistors I1, I2, I3, I4 Constant current source

Claims

1. A cell number determination circuit for determining the number of cells in a battery pack equipped with a plurality of cells connected in series, a plurality of differential amplifiers provided corresponding to a plurality of cells that can be increased or decreased in the battery pack; a plurality of output circuits provided corresponding to the plurality of differential amplifiers; Equipped with The input differential pair of the differential amplifier is composed of an NMOS transistor and a different polarity gate NMOS transistor having a gate polarity different from that of the NMOS transistor. A cell number determination circuit comprising:

2. The input differential pair of the differential amplifier has the opposite gate NMOS transistor connected to the highest potential terminal of the battery pack, and the NMOS transistor connected to a terminal to which the variable cell is connected.

2. The cell number determination circuit according to claim 1.

3. The plurality of differential amplifiers are configured such that the MOS transistors on the opposite polarity gate NMOS transistor side and the constant current source are commonly used.

3. The cell number determination circuit according to claim 2.

4. a plurality of input terminals to which a plurality of terminals of the battery pack are connected; a cell number determination circuit according to any one of claims 1 to 3, which determines the number of cells in the battery pack based on the voltages of terminals corresponding to a number of cells that can be increased or decreased among the plurality of input terminals and the highest potential terminal of the battery pack; a charge / discharge control circuit that controls charging / discharging of the battery pack based on the voltages of the plurality of input terminals and the output signal of the cell number determination circuit; A charge / discharge control device comprising:

5. a battery pack including a plurality of cells connected in series; The charge / discharge control device according to claim 4 ; a charge / discharge control FET connected in series with the battery pack between the external terminals; A battery device comprising:

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