Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device with less shape variation and stable electric characteristics.SOLUTION: A semiconductor device includes a gate electrode, a gate insulating layer on the gate electrode, a metal oxide layer on the gate insulating layer, an oxide semiconductor layer with a polycrystalline structure on the metal oxide layer, a source electrode and a drain electrode on the oxide semiconductor layer, and an interlayer insulating layer covering the source electrode and the drain electrode and being in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a first region overlapping with the source electrode or the drain electrode, and a second region in contact with the interlayer insulating layer. The difference between the film thickness of the first region and the film thickness of the second region is 5 nm or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a semiconductor device. In particular, an embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel. Also, an embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, development of semiconductor devices using oxide semiconductors for the channel instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon has been progressing (for example, Patent Documents 1 to 6). Like semiconductor devices using amorphous silicon for the channel, semiconductor devices using oxide semiconductors for the channel have a simple structure and can be formed by a low-temperature process. It is known that semiconductor devices using oxide semiconductors for the channel have higher mobility than semiconductor devices using amorphous silicon for the channel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-141338 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-099601 [Patent Document 3] Japanese Patent Publication No. 2021-153196 [Patent Document 4] Japanese Patent Application Publication No. 2018-006730 [Patent Document 5] Japanese Patent Application Laid-Open No. 2016-184771 [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional semiconductor devices including an oxide semiconductor layer, the oxide semiconductor layer has low etching resistance, making it difficult to control the shape of the oxide semiconductor layer. In particular, in semiconductor devices manufactured using large-area substrates, variations in the shape of the oxide semiconductor layer cause variations in the electrical properties of the semiconductor device within the surface, resulting in reduced yields.

[0005] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in shape and stable electrical characteristics. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with reduced manufacturing variation and improved yield. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a gate electrode, a gate insulating layer on the gate electrode, a metal oxide layer on the gate insulating layer, an oxide semiconductor layer having a polycrystalline structure on the metal oxide layer, a source electrode and a drain electrode on the oxide semiconductor layer, and an interlayer insulating layer covering the source electrode and the drain electrode and in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer includes a first region overlapping with the source electrode or the drain electrode and a second region in contact with the interlayer insulating layer, and the difference in thickness between the first region and the second region is 5 nm or less.

[0007] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming a gate electrode, forming a gate insulating layer on the gate electrode, forming a metal oxide film on the gate insulating layer, forming an oxide semiconductor layer having a polycrystalline structure on the metal oxide film, etching the metal oxide film using the oxide semiconductor layer as a mask to form the metal oxide layer, depositing a conductive film on the oxide semiconductor layer, patterning the conductive film by etching to form source and drain electrodes, and forming an interlayer insulating layer that covers the source and drain electrodes and is in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer includes a first region overlapping with the source or drain electrode and a second region in contact with the interlayer insulating layer, and the difference in thickness between the first region and the second region is 5 nm or less. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 3] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 13] 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Figure 14] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. [Figure 15] 1 is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention. [Figure 16] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. [Figure 17]1 is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention. [Figure 18] FIG. 1 is a diagram showing the electrical characteristics of Sample A, Sample B, and Sample C. [Figure 19] FIG. 10 is a diagram showing the electrical characteristics of Sample D and Sample F. [Figure 20] FIG. 10 is a diagram showing the electrical characteristics of Sample G, Sample E, and Sample H. [Figure 21] FIG. 10 is a diagram showing the electrical characteristics of Sample I. [Figure 22] FIG. 10 is a diagram showing the electrical characteristics of Sample J. DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily arrive at by appropriately modifying the configuration of the embodiments while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, film thickness, shape, etc. of each part more schematically than the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] The term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are examples of semiconductor devices. The semiconductor device of the following embodiments may be, for example, a display device, an integrated circuit (IC) such as a microprocessor (micro-processing unit: MPU), or a transistor used in a memory circuit.

[0011] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0012] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downper." For convenience of explanation, the terms "up" and "downper" are used in the description. However, for example, the hierarchical relationship between the substrate and the oxide semiconductor layer may be reversed from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the hierarchical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When a pixel electrode is referred to as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is referred to as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view. Note that a "planar view" refers to a view perpendicular to the surface of the substrate.

[0013] In this specification and the like, the terms "film" and "layer" can be used interchangeably in some cases.

[0014] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0015] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0016] First Embodiment A semiconductor device 10 according to one embodiment of the present invention will be described with reference to FIGS.

[0017] [Configuration of semiconductor device 10] The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view showing an overview of the semiconductor device 10 according to one embodiment of the present invention. Figure 2 is a plan view showing an overview of the semiconductor device 10 according to one embodiment of the present invention. The cross-sectional view shown in Figure 1 corresponds to a cross section taken along line A1-A2 shown in Figure 2.

[0018] As shown in FIG. 1, the semiconductor device 10 is provided on a substrate 11. The semiconductor device 10 includes a gate electrode 12GE, gate insulating layers 14 and 16, a metal oxide layer 28, an oxide semiconductor layer 26, a source electrode 32S, a drain electrode 32D, and interlayer insulating layers 34 and 38. When the source electrode 32S and the drain electrode 32D are not particularly distinguished from each other, they may be collectively referred to as the source electrode and the drain electrode 32. Furthermore, the gate electrode 12GE, the gate insulating layers 14 and 16, the metal oxide layer 28, and the oxide semiconductor layer 26 may be collectively referred to as a transistor. In this embodiment, a bottom-gate transistor in which the gate electrode 12GE is provided below the oxide semiconductor layer 26 will be described.

[0019] In this embodiment, a bottom-gate transistor is exemplified as the semiconductor device 10, but the semiconductor device 10 is not limited to a bottom-gate transistor. For example, the semiconductor device 10 may be a dual-gate transistor in which gate electrodes are provided above and below the oxide semiconductor layer 26.

[0020] The gate electrode 12GE is provided on the substrate 11. Gate insulating layers 14 and 16 are provided on the substrate 11 and the gate electrode 12GE. The gate insulating layers 14 and 16 have a stacked structure. A metal oxide layer 28 is provided on the gate insulating layer 16. An oxide semiconductor layer 26 is provided on the metal oxide layer 28. A source electrode 32S and a drain electrode 32D are provided on the oxide semiconductor layer 26. Interlayer insulating layers 34 and 38 are provided on the oxide semiconductor layer 26 and the source electrode 32S and the drain electrode 32D. The interlayer insulating layers 34 and 38 have a stacked structure, with the interlayer insulating layer 38 being provided on the interlayer insulating layer 34. That is, the interlayer insulating layers 34 and 38 cover the source electrode 32S and the drain electrode 32D, and the interlayer insulating layer 34 is in contact with the oxide semiconductor layer 26.

[0021] As shown in FIG. 2, in a plan view, the oxide semiconductor layer 26 overlaps with the gate electrode 12GE. The D1 direction is a direction connecting the source electrode 32S and the drain electrode 32D, and the D2 direction is a direction perpendicular to the D1 direction. In the semiconductor device 10, the channel length L corresponds to the length of a region (channel region) of the oxide semiconductor layer 26 between the source electrode 32S and the drain electrode 32D in the D1 direction, and the channel width W corresponds to the width of the channel region in the D2 direction. In a plan view, the region of the oxide semiconductor layer 26 overlapping with the source electrode 32S is the source region, and the region of the oxide semiconductor layer 26 overlapping with the drain electrode 32D is the drain region. That is, the channel region is located between the source region and the drain region.

[0022] 2, in a plan view, the plane pattern of the metal oxide layer 28 is substantially the same as the plane pattern of the oxide semiconductor layer 26. In other words, the end of the metal oxide layer 28 and the end of the oxide semiconductor layer 26 are substantially aligned. With reference to FIGS. 1 and 2, the lower surface of the oxide semiconductor layer 26 is covered with the metal oxide layer 28. In particular, in the semiconductor device 10 according to this embodiment, the entire lower surface of the oxide semiconductor layer 26 is covered with the metal oxide layer 28.

[0023] The wiring 12W and the wiring 32W function as gate wiring. The wiring 32W is electrically connected to the wiring 12W via a contact hole 15. As will be described in detail later, the wiring 12W is formed in the same layer as the gate electrode 12GE. The wiring 32W is also formed in the same layer as the source electrode 32S and the drain electrode 32D. Note that the wiring 32W may not be provided on the wiring 12W.

[0024] The oxide semiconductor layer 26 is transparent and has a polycrystalline structure including a plurality of crystal grains. As will be described in detail later, the oxide semiconductor layer 26 having a polycrystalline structure can be formed by using a Poly-OS (Polycrystalline Oxide Semiconductor) technique. Therefore, hereinafter, the oxide semiconductor included in the oxide semiconductor layer 26 may be described as Poly-OS.

[0025] The crystal grains contained in the Poly-OS have a crystal grain size of 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The crystal grain size of the crystal grains can be obtained by, for example, cross-sectional SEM observation, cross-sectional TEM observation, or electron backscattered diffraction (EBSD) method.

[0026] As described above, the crystal grains contained in the Poly-OS have a grain size of 0.1 μm or more, and therefore, in the oxide semiconductor layer 26 having a thickness of 10 nm to 30 nm, there is a region along the film thickness direction that contains only one crystal grain.

[0027] Poly-OS has excellent etching resistance. As will be described in detail later, Poly-OS has excellent etching resistance against the etching solution or etching gas used in forming the source electrode 32S and the drain electrode 32D. Therefore, the oxide semiconductor layer 26 is hardly etched during the formation of the source electrode 32S and the drain electrode 32D. Therefore, the thickness of the first region (i.e., source region or drain region) of the oxide semiconductor layer 26 overlapping with the source electrode 32S or the drain electrode 32D is substantially the same as the thickness of the second region (i.e., channel region) of the oxide semiconductor layer 26 not overlapping with the source electrode 32S or the drain electrode 32D. In other words, the difference in thickness between the first region and the second region is 5 nm or less, preferably 3 nm or less, and more preferably 1 nm or less.

[0028] The film thickness of the channel region affects the electrical characteristics of the semiconductor device. If the film thickness of the channel region varies greatly, it is not possible to provide a semiconductor device with stable electrical characteristics. In other words, the yield of the semiconductor device decreases. On the other hand, in the semiconductor device 10, the film thickness of the channel region of the oxide semiconductor layer 26 can be controlled, so the semiconductor device 10 has stable electrical characteristics. For example, in the semiconductor device 10, when the channel length L of the channel region is in the range of 2 μm to 4 μm and the channel width of the channel region is in the range of 2 μm to 25 μm, the mobility is 20 cm 2 / Vs or more, even 30cm 2 A field-effect mobility (field-effect mobility in the linear region) of 1 / Vs or more can be obtained.

[0029] [Method of Manufacturing the Semiconductor Device 10] 3 to 11, a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described. Fig. 3 is a flowchart for explaining a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. Figs. 4 to 11 are schematic cross-sectional views showing a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. Each step of the flowchart shown in Fig. 3 will be described in order below.

[0030] In step S1001 ("GE formation") of FIG. 3, a gate electrode 12GE is formed on the substrate 11 (see FIG. 4).

[0031] The substrate 11 may be a rigid substrate having optical transparency, such as a glass substrate, a quartz substrate, or a sapphire substrate. When the substrate 11 needs to be flexible, a polyimide substrate, an acrylic substrate, a siloxane substrate, a fluororesin substrate, or a substrate containing a resin may be used. When a substrate containing a resin is used as the substrate 11, an impurity element may be introduced into the resin to improve the heat resistance of the substrate 11. In particular, when the semiconductor device 10 is a top-emission display, the substrate 11 does not need to be transparent, and therefore an impurity that reduces the transmittance of the substrate 11 may be used. When the semiconductor device 10 is used in an integrated circuit other than a display device, the substrate 11 may be a non-optically transparent substrate, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate.

[0032] The gate electrode 12GE is formed by processing a conductive film formed by sputtering. A common metal material is used as the metal material of the gate electrode 12GE. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used as the gate electrode 12GE. The above metal materials may be used as a single layer or a stacked layer.

[0033] In step S1002 ("GI formation") of FIG. 3, gate insulating layers 14 and 16 are formed on the gate electrode 12GE (see FIG. 4). The gate insulating layers 14 and 16 are formed by a CVD (Chemical Vapor Deposition) method or a sputtering method. An insulating material is used for the gate insulating layers 14 and 16. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ) and other inorganic insulating materials are used. x N y is a silicon compound containing a smaller proportion of nitrogen (N) than oxygen (O) (x>y). SiN x O y is a silicon compound containing a smaller proportion of oxygen than nitrogen (x>y).

[0034] Preferably, a gate insulating layer 14 made of a nitrogen-containing insulating material and a gate insulating layer 16 made of an oxygen-containing insulating material are sequentially formed on the substrate 11. By using a nitrogen-containing insulating material as the gate insulating layer 14, impurities diffusing from the substrate 11 toward the oxide semiconductor layer 26 can be blocked. Furthermore, by using an oxygen-containing insulating material as the gate insulating layer 16, oxygen can be released by heat treatment. The heat treatment temperature at which the oxygen-containing insulating material releases oxygen is, for example, 500°C or less, 450°C or less, or 400°C or less. Note that the oxygen-containing insulating material may release oxygen when heated in any step of the manufacturing process of the semiconductor device 10.

[0035] The thickness of the gate insulating layer 14 is preferably larger than the thickness of the gate insulating layer 16. In this embodiment, for example, silicon nitride having a thickness of 300 nm is formed as the gate insulating layer 14. For example, silicon oxide having a thickness of 100 nm is formed as the gate insulating layer 16.

[0036] 3, a metal oxide film 18 is formed on the gate insulating layers 14 and 16. The metal oxide film 18 is formed by sputtering or atomic layer deposition (ALD).

[0037] A metal oxide containing aluminum as a main component is used as the metal oxide film 18. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x ) is used. A metal oxide layer containing aluminum as a main component means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide film 18. The ratio of aluminum contained in the metal oxide film 18 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide film 18. The above ratio may be a mass ratio or a weight ratio.

[0038] The thickness of the metal oxide film 18 is, for example, 1 nm or more and 10 nm or less, preferably 1 nm or more and 5 nm or less. In this embodiment, aluminum oxide is used as the metal oxide film 18. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. In other words, barrier properties refer to the function of preventing gases such as oxygen and hydrogen from permeating aluminum oxide. In other words, barrier properties mean that even if gases such as oxygen and hydrogen exist from a layer provided below the aluminum oxide film, they are prevented from migrating to a layer provided above the aluminum oxide film. Alternatively, even if gases such as oxygen and hydrogen exist from a layer provided above the aluminum oxide film, they are prevented from migrating to a layer provided below the aluminum oxide film.

[0039] In step S1004 ("OS film formation") of FIG. 3, an oxide semiconductor film 22 is formed on the metal oxide film 18 (see FIG. 5). The oxide semiconductor film 22 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 22 is 10 nm to 50 nm, preferably 10 nm to 40 nm, and more preferably 10 nm to 30 nm.

[0040] The oxide semiconductor film 22 may be made of a metal oxide having semiconductor properties. For example, the oxide semiconductor film 22 may be made of an oxide semiconductor containing two or more metals including indium (In). The ratio of indium to the two or more metals is 50% or more. The oxide semiconductor film 22 may be made of, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or a lanthanoid element. The oxide semiconductor film 22 preferably contains a Group 13 element. Elements other than those mentioned above may also be used for the oxide semiconductor film 22.

[0041] When the oxide semiconductor film 22 is crystallized by OS annealing, which will be described later, the oxide semiconductor film 22 is preferably amorphous (having a small amount of crystalline components in the oxide semiconductor) after deposition and before OS annealing. That is, the oxide semiconductor film 22 is preferably formed under conditions that minimize crystallization of the oxide semiconductor film 22 immediately after deposition. For example, when the oxide semiconductor film 22 is formed by sputtering, the oxide semiconductor film 22 is formed while controlling the temperature of the object to be formed (the substrate 11 and a structure formed thereon).

[0042] When a film is formed on a target by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target, causing the temperature of the target to rise during the film formation process. If the temperature of the target rises during the film formation process, the oxide semiconductor film 22 contains microcrystals immediately after film formation. If the oxide semiconductor film 22 contains microcrystals, the crystal grain size cannot be increased by subsequent OS annealing. To control the temperature of the target, for example, the target can be cooled during film formation. For example, the target can be cooled from the side opposite the target surface so that the temperature of the target surface (hereinafter referred to as the "film formation temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. In particular, the film formation temperature of the oxide semiconductor film 22 is preferably 50°C or less. By forming the oxide semiconductor film 22 while cooling the substrate 11, it is possible to obtain an oxide semiconductor film 22 with a small amount of crystalline components immediately after the film formation.

[0043] In the sputtering process, the oxide semiconductor film 22 having an amorphous structure is formed under conditions of an oxygen partial pressure of 10% or less. If the oxygen partial pressure is high, the oxide semiconductor film 22 contains excess oxygen, which causes microcrystals to be included in the oxide semiconductor film 22 immediately after deposition. Therefore, it is preferable to form the oxide semiconductor film 22 under conditions of a low oxygen partial pressure. The oxygen partial pressure is, for example, 1% to 5%, and preferably 2% to 4%. Under conditions of an oxygen partial pressure of less than 1%, the oxygen distribution in the film formation apparatus tends to become non-uniform. As a result, the oxygen composition in the oxide semiconductor layer also becomes non-uniform, resulting in the formation of an oxide semiconductor layer containing many microcrystals or an oxide semiconductor layer that does not crystallize even after subsequent OS annealing treatment.

[0044] In step S1005 ("OS pattern formation") of FIG. 3, a pattern of the oxide semiconductor layer 24 is formed (see FIG. 6). The pattern of the oxide semiconductor layer 24 is formed using photolithography. For example, a resist mask (not shown) is formed on the oxide semiconductor film 22, and the oxide semiconductor film 22 is etched using the resist mask. The oxide semiconductor film 22 may be etched by wet etching or dry etching. Wet etching can be performed using an acidic etching solution. Examples of the etching solution that can be used include oxalic acid, PAN, sulfuric acid, hydrogen peroxide solution, and hydrofluoric acid. This allows the oxide semiconductor layer 24 to have a predetermined pattern. Thereafter, the resist mask is removed.

[0045] The formation of the oxide semiconductor layer 24 having a predetermined pattern (i.e., patterning of the oxide semiconductor film 22) is preferably performed before OS annealing. The Poly-OS after OS annealing has high etching resistance, making it difficult to pattern the oxide semiconductor layer 24 by etching. Furthermore, by performing OS annealing after the formation of the oxide semiconductor layer 24, damage (e.g., oxygen defects in the oxide semiconductor layer 24) that occurs during the formation of the oxide semiconductor layer 24 can be repaired by the OS annealing.

[0046] In step S1006 ("OS anneal") of FIG. 3, after the oxide semiconductor layer 24 is formed, the oxide semiconductor layer 24 is subjected to a heat treatment (OS anneal) to form the oxide semiconductor layer 26 (see FIG. 7). In the OS anneal, the oxide semiconductor layer 24 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300°C or higher and 500°C or lower, preferably 350°C or higher and 450°C or lower. The holding time at the temperature is 15 minutes or higher and 120 minutes or lower, preferably 30 minutes or higher and 60 minutes or lower. By performing the OS anneal, the oxide semiconductor layer 24 having an amorphous structure is crystallized to form the oxide semiconductor layer 26 having a polycrystalline structure. That is, the oxide semiconductor layer 26 including Poly-OS is formed by the OS anneal.

[0047] In thin film transistors, the field-effect mobility tends to be increased by reducing the thickness of the oxide semiconductor layer, which increases the number of carriers and reduces the influence of the back channel. That is, in thin film transistors, the field-effect mobility tends to be increased as the thickness of the region functioning as a channel in the oxide semiconductor layer is reduced. Therefore, the thinner the oxide semiconductor layer, the better. However, even if an oxide semiconductor layer is formed to a thickness of 10 nm or less and then subjected to heat treatment, the oxide semiconductor layer is not sufficiently crystallized. If the oxide semiconductor layer is not sufficiently crystallized, the oxide semiconductor layer and the metal oxide layer will be lost during a later etching process for patterning the metal oxide layer using the oxide semiconductor layer as a mask.

[0048] Furthermore, in a thin-film transistor, the crystallinity of the oxide semiconductor layer 26 contributes to improving the field-effect mobility. Therefore, it is preferable that the oxide semiconductor layer 26 has a polycrystalline structure. However, if microcrystals are contained in the oxide semiconductor film 22 during its formation, the crystal grain size of the polycrystalline structure cannot be increased even if a heat treatment is subsequently performed. Thus, it is difficult to achieve both a thin oxide semiconductor layer and good crystallization.

[0049] When the oxide semiconductor film 22 is formed by a sputtering method, it is formed at a low oxygen partial pressure of 3% or more and 5% or less. By forming the oxide semiconductor film 22 under the condition of a low oxygen partial pressure, it is possible to prevent the oxide semiconductor film 22 from containing excessive oxygen and to prevent the oxide semiconductor film 22 from containing microcrystals immediately after deposition. This makes it possible to prevent crystals from growing from the microcrystals during heat treatment of the oxide semiconductor layer 24. Therefore, even when the oxide semiconductor film 22 is formed to a thin thickness of more than 10 nm and not more than 30 nm, it is possible to increase the crystal grain size of the crystal grains in the polycrystalline structure of the oxide semiconductor layer 26.

[0050] As shown in step S1007 of FIG. 3, the metal oxide film 18 is patterned to form a metal oxide layer 28 (see FIG. 8). The oxide semiconductor layer 26 that has been sufficiently crystallized by the heat treatment has high etching resistance. Therefore, when the metal oxide film 18 is patterned using the crystallized oxide semiconductor layer 26 as a mask, it is possible to prevent the oxide semiconductor layer 26 from being lost. The metal oxide film 18 is etched using the oxide semiconductor layer 26 patterned in the above process as a mask. The metal oxide film 18 may be etched by wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used for wet etching. By etching the metal oxide film 18 using the oxide semiconductor layer 26 as a mask, the photolithography process can be omitted.

[0051] In step S1008 ("contact hole formation") of FIG. 3, contact holes 15 are formed in the gate insulating layers 14 and 16 (see FIG. 8). This exposes the upper surface of the wiring 12W. Note that if there is no need to connect the wiring 32W and the wiring 12W, the process of step S1008 does not need to be performed.

[0052] In step S1009 ("SD formation") of FIG. 3, the source electrode 32S, the drain electrode 32D, and the wiring 32W are formed (see FIG. 9). The source electrode 32S, the drain electrode 32D, and the wiring 32W are formed by patterning a conductive film formed by sputtering through etching. The wiring 32W can be connected to the wiring 12W through a contact hole 15. The source electrode 32S and the drain electrode 32D are made of the same conductive material as the gate electrode 12GE. The source electrode 32S, the drain electrode 32D, and the wiring 32W may be made of a single-layer or multi-layer conductive material. In this embodiment, a multi-layer structure of MoW alloy, Al, and MoW alloy (MoW / Al / MoW structure), a single-layer structure of MoW alloy (MoW structure), a single-layer structure of Ti (Ti structure), and a multi-layer structure of Ti, Al, and Ti (Ti / Al / Ti structure) are exemplified.

[0053] The source electrode 32S, the drain electrode 32D, and the wiring 32W are formed by patterning using wet etching or dry etching. In wet etching, an etching solution is used. For example, a solution containing at least two selected from the group consisting of phosphoric acid, acetic acid, nitric acid, hydrofluoric acid, hydrochloric acid, sulfuric acid, and oxalic acid can be used as the etching solution. Specifically, a mixed acid etching solution containing phosphoric acid, acetic acid, and nitric acid as its main components can be used as the etching solution. Alternatively, a mixed solution of hydrogen peroxide and ammonia water (hereinafter referred to as "H2O2 / NH3 solution") can also be used as the etching solution. In dry etching, an etching gas is used. For example, a fluorine-containing gas such as sulfur hexafluoride gas (SF6) or a chlorine-containing gas such as chlorine gas (Cl2) can be used as the etching gas.

[0054] Poly-OS has excellent etching resistance. Specifically, it has a very small etching rate with respect to the etching solution or etching gas used to form the source electrode 32S and the drain electrode 32D. This means that Poly-OS is hardly etched by the etching solution or etching gas. Therefore, in the semiconductor device 10, even if a conductive film is formed directly on the oxide semiconductor layer 26 and then patterned to form the source electrode 32S and the drain electrode 32D, the channel region of the oxide semiconductor layer 26 is hardly etched.

[0055] For example, the etching rate of the oxide semiconductor layer 26 with the etching solution used in forming the source electrode 32S and the drain electrode 32D is 0.1 nm / sec or less, or 0.01 nm / sec or less. The etching rate of the oxide semiconductor layer 26 with the etching gas used in forming the source electrode 32S and the drain electrode 32D is 0.5 nm / sec or less, or 0.1 nm / sec or less. For example, the etching rate of the oxide semiconductor layer 26 with the chlorine-based gas used in forming the source electrode 32S and the drain electrode 32D is 0.3 nm / sec or less. For example, the etching rate of the oxide semiconductor layer 26 with the fluorine-based gas used in forming the source electrode 32S and the drain electrode 32D is 0.1 nm / sec or less. The etching rate of the chlorine-based gas used in etching the source electrode 32S and the drain electrode 32D is slightly higher than that of etching with an etching solution or a fluorine-based gas. When etching is performed with a chlorine-based gas, the source electrode 32S and the drain electrode 32D can be more easily processed than when etching is performed with an etching solution. Therefore, an etching solution or etching gas may be selected appropriately depending on the structure of the conductive film for forming the source electrode 32S and the drain electrode 32D.

[0056] In semiconductor devices using oxide semiconductors without a polycrystalline structure, such as IGZO, as the oxide semiconductor layer, when source and drain electrodes are formed on the oxide semiconductor, the oxide semiconductor layer is also etched by etching the source and drain electrodes. Specifically, the etching rate of IGZO in chlorine-containing gases is 1.0 mm / sec. Considering that the channel region will be etched at this etching rate, the oxide semiconductor layer must be deposited thick in advance. For example, to manufacture a semiconductor device with a channel region thickness of 40 nm or less, an oxide semiconductor layer with a thickness of approximately 65 nm must be deposited, and the etching time for forming the source and drain electrodes must be adjusted so that the channel region thickness is 40 nm or less. However, controlling the channel region thickness by controlling the etching time is difficult. Furthermore, when the etching rate is high, precise control of the channel region thickness by controlling the etching time is difficult. In this case, the channel region thickness varies greatly.

[0057] Furthermore, if the film thickness of the channel region is significantly reduced, a recess is formed on the upper surface of the oxide semiconductor layer. The interlayer insulating layer provided on the oxide semiconductor layer is formed so as to cover the recess, but if the recess is deep, the interlayer insulating layer cannot sufficiently cover the recess. In other words, gaps may occur between the oxide semiconductor layer and the interlayer insulating layer, or between the source electrode and the drain electrode and the interlayer insulating layer. This can cause variations in not only the electrical characteristics but also the reliability of the semiconductor device.

[0058] In contrast, the oxide semiconductor layer 26 having a polycrystalline structure can be etched at an etching rate of 0.00 nm / sec to 0.1 nm / sec, preferably 0.00 nm / sec to 0.06 nm / sec, regardless of whether wet etching or dry etching is used. That is, the oxide semiconductor layer 26 having a polycrystalline structure has a lower etching rate and higher etching resistance than an oxide semiconductor layer using IGZO. Therefore, etching-induced film loss does not need to be considered, and controllability is good. Therefore, the oxide semiconductor layer can be formed to a thin film thickness of more than 10 nm to 30 nm or less. Furthermore, the selectivity of conductive materials that can be used for the source electrode 32S, drain electrode 32D, and wiring 32W is improved. For example, even when a conductive film using a MoW / Al / MoW stacked structure or a single-layer MoW alloy structure is processed by wet etching to form the source electrode 32S and drain electrode 32D, film loss of the oxide semiconductor layer 26 can be suppressed.

[0059] As described above, the etching rate of the oxide semiconductor layer 26 with respect to the etching solution used in forming the source electrode 32S and the drain electrode 32D is very small. Therefore, the film thickness of the first region (i.e., the source region or the drain region) of the oxide semiconductor layer 26 overlapping with the source electrode 32S or the drain electrode 32D is substantially the same as the film thickness of the second region (i.e., the channel region) of the oxide semiconductor layer 26 not overlapping with the source electrode 32S or the drain electrode 32D. In other words, the difference between the film thickness of the first region and the film thickness of the second region can be controlled to 5 nm or less, preferably 3 nm or less, and more preferably 1 nm or less. That is, variation in the film thickness of the channel region is suppressed.

[0060] In step S1010 ("SiOx formation") of FIG. 3, an interlayer insulating layer 34 is formed on the oxide semiconductor layer 26, the source electrode 32S, and the drain electrode 32D. The interlayer insulating layer 34 is preferably made of an insulating material containing oxygen. For example, the interlayer insulating layer 34 may be made of silicon oxide (SiO x ) or silicon oxynitride (SiOx N y ) is used. It is also preferable to use an insulating layer with few defects as the interlayer insulating layer 34. For example, when the oxygen composition ratio in the interlayer insulating layer 34 is compared with the oxygen composition ratio in an insulating layer having the same composition as the interlayer insulating layer 34 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the interlayer insulating layer 34 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. For example, when silicon oxide (SiO x When the gate insulating layer 16 is used, the interlayer insulating layer 34 has a composition ratio closer to the stoichiometric ratio of silicon oxide (SiO2) than the gate insulating layer 16. The interlayer insulating layer 34 may be a layer in which no defects are observed when evaluated by electron spin resonance (ESR).

[0061] The interlayer insulating layer 34 can be formed using the same film formation method as the gate insulating layers 14, 16. In order to increase the oxygen composition ratio in the interlayer insulating layer 34, the film may be formed at a relatively low temperature (for example, a film formation temperature of less than 350°C). In addition, in order to form an insulating layer with few defects as the interlayer insulating layer 34, the interlayer insulating layer 34 may be formed at a film formation temperature of 350°C or higher. Furthermore, after forming the interlayer insulating layer 34, a process of implanting oxygen into a part of the interlayer insulating layer 34 may be performed.

[0062] The thickness of the interlayer insulating layer 34 is 50 nm or more and 300 nm or less, 60 nm or more and 200 nm or less, or 70 nm or more and 150 nm or less.

[0063] 3, a metal oxide film 36 is formed on the interlayer insulating layer 34 (see FIG. 10). The metal oxide film 36 is formed by sputtering or atomic layer deposition (ALD).

[0064] A metal oxide containing aluminum as a main component is used as the metal oxide film 36. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlOx N y ), aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x ) is used. A metal oxide layer containing aluminum as a main component means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide film 36. The ratio of aluminum contained in the metal oxide film 36 may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide film 36. The above ratio may be a mass ratio or a weight ratio.

[0065] The thickness of the metal oxide film 36 is 1 nm or more and 50 nm or less, preferably 1 nm or more and 30 nm or less. Aluminum oxide is preferably used as the metal oxide film 36. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. Here, barrier properties refer to the function of suppressing the permeation of gases such as oxygen and hydrogen through aluminum oxide. In other words, this means that gases such as oxygen and hydrogen in a layer provided below the aluminum oxide film are prevented from migrating to a layer provided above the aluminum oxide film. Alternatively, this means that gases such as oxygen and hydrogen in a layer provided above the aluminum oxide film are prevented from migrating to a layer provided below the aluminum oxide film.

[0066] Note that a metal oxide containing a metal other than aluminum as a main component may be used as the metal oxide film 36. For example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like may be used as the metal oxide film 36.

[0067] 3 ("oxidation annealing"), a heat treatment is performed on the oxide semiconductor layer 26 with the interlayer insulating layer 34 and the metal oxide film 36 formed thereon (see FIG. 10). Here, the oxidation annealing may be performed at, for example, 300°C to 450°C. This allows oxygen released from the interlayer insulating layer 34 to be supplied to the oxide semiconductor layer 26. By providing the metal oxide film 36 so as to cover the substrate 11, it is possible to prevent oxygen released from the interlayer insulating layer 34 from being released outside the metal oxide film 36.

[0068] During the process from when the oxide semiconductor layer 26 is formed until when the interlayer insulating layer 34 is formed on the oxide semiconductor layer 26, many oxygen defects occur in the oxide semiconductor layer 26. However, by the oxidation annealing in step S1012, oxygen released from the interlayer insulating layer 34 is supplied to the oxide semiconductor layer 26, and the oxygen defects are repaired.

[0069] 3, the metal oxide film 36 is removed (see FIG. 11). For example, the metal oxide film 36 may be removed using diluted hydrofluoric acid (DHF).

[0070] 3, an interlayer insulating layer 38 is formed on the interlayer insulating layer 34. It is preferable to use an insulating material containing nitrogen for the interlayer insulating layer 38. For example, silicon nitride SiN x ) or silicon oxynitride (SiN x O y The interlayer insulating layer 38 can be formed using the same film forming method as that for the gate insulating layers 14 and 16.

[0071] Through the steps described above, the semiconductor device 10 shown in FIG. 1 can be manufactured.

[0072] In the semiconductor device 10 manufactured by the above manufacturing method, when the channel length L of the channel region is in the range of 2 μm to 4 μm and the channel width of the channel region is in the range of 2 μm to 25 μm, the mobility is 20 cm 2 / Vs or more, even 30cm 2 Excellent electrical characteristics of at least / Vs can be obtained.

[0073] Furthermore, by providing the metal oxide layer 28 under the oxide semiconductor layer 26, the metal oxide layer 28 can effectively reduce the film thickness of the region of the oxide semiconductor layer 26 that functions as a channel. This increases the density of carriers accumulated in the channel, thereby improving the mobility of the semiconductor device 10. The metal oxide film 18 has gas barrier properties against oxygen and hydrogen. However, unless oxygen is supplied to the oxide semiconductor layer 26 from the gate insulating layers 14 and 16 through the metal oxide layer 28, oxygen defects on the back surface of the oxide semiconductor layer 26 cannot be repaired. Therefore, by setting the film thickness of the metal oxide film 18 to be 1 nm or more and 10 nm or less, preferably 1 nm or more and 5 nm or less, oxygen contained in the gate insulating layer 16 can be appropriately supplied to the back surface of the oxide semiconductor layer 26.

[0074] Furthermore, even when the semiconductor device 10 is manufactured using a large-area substrate, it is possible to suppress variations in the shape of the oxide semiconductor layer 26. As a result, it is possible to suppress variations in the electrical properties of the semiconductor device 10 within the surface, thereby improving the yield.

[0075] Second Embodiment 12 to 15, a display device 20 using the semiconductor device 10 according to one embodiment of the present invention will be described. In the following embodiment, a configuration in which the semiconductor device 10 described in the first embodiment is applied to the circuitry of a liquid crystal display device will be described.

[0076] [Outline of the display device 20] Fig. 12 is a plan view showing an overview of a display device 20 according to one embodiment of the present invention. As shown in Fig. 12, the display device 20 has an array substrate 300, a seal portion 310, a counter substrate 320, a flexible printed circuit board 330 (FPC 330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the seal portion 310. A plurality of pixel circuits 301 are arranged in a matrix in a liquid crystal region 220 surrounded by the seal portion 310. The liquid crystal region 220 is an area that overlaps with a liquid crystal element 311, which will be described later, in a plan view.

[0077] The sealing region 240 in which the sealing portion 310 is provided is the region surrounding the liquid crystal region 220. The FPC 330 is provided in the terminal region 260. The terminal region 260 is the region in which the array substrate 300 is exposed from the counter substrate 320, and is provided outside the sealing region 240. The outside of the sealing region 240 means the outside of the region in which the sealing portion 310 is provided and the region surrounded by the sealing portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies signals to drive each pixel circuit 301.

[0078] [Circuit configuration of display device 20] Fig. 13 is a block diagram showing the circuit configuration of a display device 20 according to one embodiment of the present invention. As shown in Fig. 13, a source driver circuit 302 is provided at a position adjacent to the liquid crystal region 220 in the second direction D2 (column direction) in which the pixel circuits 301 are arranged, and a gate driver circuit 303 is provided at a position adjacent to the liquid crystal region 220 in the first direction D1 (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the sealing region 240. However, the region in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the sealing region 240, and may be any region outside the region in which the pixel circuits 301 are provided.

[0079] A source wiring 304 extends from the source driver circuit 302 in the second direction D2 and is connected to the plurality of pixel circuits 301 arranged in the second direction D2. A gate electrode 12GE extends from the gate driver circuit 303 in the first direction D1 and is connected to the plurality of pixel circuits 301 arranged in the first direction D1.

[0080] A terminal section 306 is provided in the terminal region 260. The terminal section 306 and the source driver circuit 302 are connected by a connection wiring 307. Similarly, the terminal section 306 and the gate driver circuit 303 are connected by a connection wiring 307. When the FPC 330 is connected to the terminal section 306, the external device to which the FPC 330 is connected is connected to the display device 20, and each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device.

[0081] The semiconductor device 10 shown in the first embodiment is used as a transistor included in a pixel circuit 301, a source driver circuit 302, and a gate driver circuit 303.

[0082] [Pixel circuit 301 of display device 20] 14 is a circuit diagram showing a pixel circuit 301 of a display device 20 according to one embodiment of the present invention. As shown in FIG. 14, the pixel circuit 301 includes elements such as a semiconductor device 10, a storage capacitor 350, and a liquid crystal element 311. The semiconductor device 10 has a gate electrode 12GE, an oxide semiconductor layer 26, a source electrode 32S, and a drain electrode 32D. The gate electrode 12GE is connected to a gate wiring 305. The source electrode 32S is connected to a source wiring 304. The drain electrode 32D is connected to the storage capacitor 350 and the liquid crystal element 311.

[0083] [Configuration of display device 20] 15 is a cross-sectional view of a display device 20 according to one embodiment of the present invention. The display device 20 shown in FIG.

[0084] 15, a gate electrode 12GE is provided on a substrate 11. Furthermore, a metal oxide layer 28 and an oxide semiconductor layer 26 are provided on the gate electrode 12GE with gate insulating layers 14 and 16 interposed therebetween. A source electrode 32S and a drain electrode 32D are provided on the oxide semiconductor layer 26.

[0085] Interlayer insulating layers 34 and 38 are provided on the source electrode 32S and the drain electrode 32D. An insulating layer 39 is provided on the interlayer insulating layers 34 and 38. The insulating layer 39 is provided to reduce unevenness caused by the semiconductor device 10. A contact hole is formed in the interlayer insulating layers 34 and 38 and the insulating layer 39 to expose the upper surface of the source electrode 32S. A common electrode 42C, which is provided in common to multiple pixels, is provided on the insulating layer 39. An insulating layer 44 is provided on the common electrode 42C. The insulating layer 44 is provided inside the contact hole. By forming the insulating layer 44 from a silicon nitride film, it is possible to prevent moisture from entering from the contact hole through the insulating layer 44. A pixel electrode 46P is provided on the insulating layer 44 and inside the contact hole. The pixel electrode 46P is connected to the drain electrode 32D.

[0086] Furthermore, a wiring 12C is provided on the substrate 11 and is connected to a wiring 32C through a contact hole provided in the gate insulating layers 14 and 16. The wiring 12C and the wiring 32C function as capacitance wiring. Furthermore, an electrode 46C is provided on the insulating layer 39 and inside the opening. The common electrode 42C, the insulating layer 44, and the electrode 46C form a storage capacitor 350.

[0087] In this embodiment, a configuration in which the semiconductor device 10 is used in the pixel circuit 301 is exemplified, but the semiconductor device 10 may also be used in a peripheral circuit including a source driver circuit 302 and a gate driver circuit 303.

[0088] Third Embodiment A display device 20 using a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 16 and 17. In this embodiment, a configuration in which the semiconductor device 10 described in the first embodiment is applied to the circuit of an organic EL display device will be described. The outline and circuit configuration of the display device 20 are similar to those shown in Figures 16 and 17, and therefore description thereof will be omitted.

[0089] [Pixel circuit 301 of display device 20] FIG. 16 is a circuit diagram showing a pixel circuit of a display device 20 according to one embodiment of the present invention. As shown in FIG. 16, a pixel circuit 301 includes elements such as a drive transistor 110, a selection transistor 120, a storage capacitor 210, and a light-emitting element DO. The drive transistor 110 and the selection transistor 120 have the same configuration as those of the semiconductor device 10. The source electrode of the selection transistor 120 is connected to a signal line 211, and the gate electrode of the selection transistor 120 is connected to a gate line 212. The source electrode of the drive transistor 110 is connected to an anode power line 213, and the drain electrode of the drive transistor 110 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to a cathode power line 214. The gate electrode of the drive transistor 110 is connected to the drain electrode of the selection transistor 120. The storage capacitor 210 is connected to the gate electrode and drain electrode of the drive transistor 110. A grayscale signal that determines the light-emitting intensity of the light-emitting element DO is supplied to the signal line 211. A signal that selects a pixel row to which the above grayscale signal is written is supplied to the gate line 212.

[0090] [Cross-sectional structure of the display device 20] Fig. 17 is a schematic cross-sectional view showing the configuration of a display device 20 according to one embodiment of the present invention. The configuration of the display device 20 shown in Fig. 17 is similar to that of the display device 20 shown in Fig. 15, but the structure above the insulating layer 39 of the display device 20 shown in Fig. 17 is different from the structure above the insulating layer 39 of the display device 20 shown in Fig. 15. Below, a description of the configuration of the display device 20 shown in Fig. 17 that is similar to that of the display device 20 shown in Fig. 15 will be omitted, and only the differences between the two will be described.

[0091] As shown in FIG. 17 , the display device 20 has a pixel electrode 390, a light-emitting layer 392, and a common electrode 394 (light-emitting element DO) above an insulating layer 39. The pixel electrode 390 is provided on the insulating layer 39 and inside a contact hole formed in the interlayer insulating layers 34, 38 and the insulating layer 39. An insulating layer 362 is provided on the pixel electrode 390. An opening 363 is provided in the insulating layer 362. The opening 363 corresponds to a light-emitting region. In other words, the insulating layer 362 defines a pixel. The light-emitting layer 392 and the common electrode 394 are provided on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are provided individually for each pixel. On the other hand, the common electrode 394 is provided in common to multiple pixels. Different materials are used for the light-emitting layer 392 depending on the display color of the pixel.

[0092] In the second and third embodiments, the semiconductor device described in the first embodiment is applied to a liquid crystal display device and an organic EL display device. However, the semiconductor device may also be applied to display devices other than these display devices (for example, a self-luminous display device other than an organic EL display device or an electronic paper display device). The semiconductor device 10 can be applied to a wide range of display devices, from small and medium-sized display devices to large display devices, without any particular limitations. Even when manufactured using a large-area substrate, the shape of the oxide semiconductor layer 26 in the semiconductor device 10 varies little. Therefore, when the semiconductor device 10 is applied to the display device 20, display unevenness can be reduced. Furthermore, the yield when manufacturing the display device 20 can be reduced. [Example]

[0093] Example 1 Example 1 In this example, the results of verifying the etching resistance of an oxide semiconductor layer having a polycrystalline structure will be described.

[0094] The samples used in this example will be described. A 30-nm-thick oxide semiconductor layer (Poly-OS) having a polycrystalline structure was formed on a silicon wafer. Next, a conductive film was formed on the oxide semiconductor layer. Four types of conductive films were used: a MoW structure, a MoW / Al / MoW structure, a Ti structure, and a Ti / Al / Ti structure.

[0095] For the MoW structure conductive film and oxide semiconductor layer, we prepared a sample that was wet etched with a mixed acid etching solution, a sample that was wet etched with a H2O2 / NH3 solution, and a sample that was dry etched with a fluorine-based gas.

[0096] For the conductive film with a MoW / Al / MoW structure and the oxide semiconductor layer, a sample was prepared by wet etching using a mixed acid etching solution.

[0097] For the Ti-structure conductive film and oxide semiconductor layer, we prepared a sample that was wet-etched with an H2O2 / NH3 solution, a sample that was dry-etched with a fluorine-based gas, and a sample that was dry-etched with a chlorine-based gas.

[0098] For the conductive film and oxide semiconductor layer with a Ti / Al / Ti structure, we prepared samples in which Ti was wet-etched with a H2O2 / NH3 solution, Al was wet-etched with a mixed acid etching solution, and Ti was wet-etched with a H2O2 / NH3 solution, as well as samples in which dry etching was performed with a chlorine-based gas.

[0099] Next, the sample used in the comparative example will be described. A 40 nm IGZO oxide semiconductor layer was formed on a silicon wafer. Next, a conductive film was formed on the oxide semiconductor layer. A Ti structure was used as the conductive film. A sample was prepared by dry etching the Ti structure conductive film and the oxide semiconductor layer using a chlorine-based gas.

[0100] As this example, Table 1 shows the etching rate [nm / sec] of the polycrystalline oxide semiconductor layer relative to the estimated overetching time after processing various conductive films.

[0101] [Table 1]

[0102] As a comparative example, the etching rate of the oxide semiconductor layer (IGZO) relative to the estimated overetching time after processing the conductive film with a Ti structure was 1.00 nm / sec.

[0103] As shown in Table 1, it was shown that an oxide semiconductor layer having a polycrystalline structure has higher etching resistance than an amorphous oxide semiconductor layer (IGZO). In addition, it was shown that the etching rates were 0.00 nm / sec to 0.06 nm / sec when etching with a mixed acid etching solution, when etching with an H2O2 / NH3 solution, and when etching with a fluorine-based gas. It was also shown that even when etching with a chlorine-based gas, it had sufficiently high etching resistance compared to an oxide semiconductor layer (IGZO).

[0104] Example 2 Next, the results of verifying the electrical characteristics of the semiconductor device 10 manufactured according to the flowchart shown in FIG. 3 of the first embodiment will be described.

[0105] A description will be given of Samples A to H fabricated as the semiconductor device 10 in Example 2. For Samples A to H, steps S1007 and S1008 were omitted from the flow chart shown in FIG.

[0106] (Sample A) A gate electrode 12GE was formed on a substrate, and gate insulating layers 14 and 16 were formed on the gate electrode 12GE. A 3-nm aluminum oxide layer was formed as a metal oxide film 18 on the gate insulating layers 14 and 16, and a 30-nm oxide semiconductor film 22 was formed on the metal oxide film 18. The oxide semiconductor film 22 was processed to form an oxide semiconductor layer 24, and OS annealing was performed at 350°C to 450°C to form an oxide semiconductor layer 26 with a polycrystalline structure (Poly-OS). Furthermore, the metal oxide film 18 was removed using the oxide semiconductor layer 26 as a mask to form a metal oxide layer 28.

[0107] A MoW / Al / MoW structure was formed as a conductive film on the oxide semiconductor layer 26, and the conductive film was wet-etched using a mixed acid etching solution to form source and drain electrodes. Next, an interlayer insulating layer 34 was formed, and then a 10 nm aluminum oxide layer was formed as a metal oxide film 36. After oxidation annealing, the metal oxide film 36 was removed. Finally, an interlayer insulating layer 38 was formed on the interlayer insulating layer 34. When the film thickness of the oxide semiconductor layer was measured after the formation of Sample A, it was found that 1 nm had been removed.

[0108] Samples B to H were formed by changing the structure of the conductive film for forming the source electrode and the drain electrode and the etching conditions from Sample A.

[0109] (Sample B) Sample B was formed under the same conditions as Sample A, except that a MoW structure was used as the conductive film.

[0110] (Sample C) Sample C was formed under the same conditions as Sample A, except that a MoW structure was formed as the conductive film and the source and drain electrodes were formed by dry etching the conductive film using SF6 gas and O2 gas. When the film thickness of the oxide semiconductor layer was measured after the formation of Sample C, it was found that 2 nm had been removed.

[0111] (Sample D) Sample D was formed under the same conditions as Sample A, except that a Ti structure was formed as the conductive film and the conductive film was dry-etched using CF4 gas and O2 gas to form source and drain electrodes. When the film thickness of the oxide semiconductor layer was measured after the formation of Sample D, it was found that 2 nm had been removed.

[0112] (Sample E) Sample E was formed under the same conditions as Sample A, except that a Ti / Al / Ti structure was formed as the conductive film, and the conductive film was dry-etched using Cl2 gas to form the source electrode and the drain electrode.

[0113] (Sample F) Sample F was formed under the same conditions as Sample A, except that a Ti structure was formed as the conductive film, and the conductive film was wet-etched using an H2O2 / NH3 solution to form source and drain electrodes.

[0114] (Sample G) Sample G was formed under the same conditions as Sample A, except that a Ti / Al / Ti structure was formed as the conductive film, and the source and drain electrodes were formed by wet etching the conductive film using a H2O2 / NH3 solution for Ti, a mixed acid etching solution for Al, and a H2O2 / NH3 solution for Ti.

[0115] (Sample H) Sample H is a comparative example, and was formed using a different method from Samples A to G. A gate electrode was formed on a substrate, and a gate insulating layer was formed on the gate electrode. A 95 nm oxide semiconductor layer (IGZO(111)) was formed on the gate insulating layer. The oxide semiconductor layer was processed to form an oxide semiconductor layer, and OS annealing was performed at 350°C to 450°C.

[0116] A Ti / AlSi / Ti laminated structure was formed on the oxide semiconductor layer as a conductive film, and the conductive film was dry-etched using Cl gas to form source and drain electrodes. Next, an interlayer insulating layer was formed, and then a 50-nm aluminum oxide layer was formed as a metal oxide layer, followed by oxidation annealing. The target thickness of the oxide semiconductor layer for dry etching was 60 nm.

[0117] Next, the electrical characteristics of Samples A to H were measured. The conditions for measuring the electrical characteristics of Samples A to H were as follows. Channel area size: W / L=6μm / 6μm Source-drain voltage: 0.1V, 10V Gate voltage: -40V to +40V (0.2V step) Measurement environment: room temperature, dark room Measurement location: 1 location on the board

[0118] Fig. 18 is a diagram showing the electrical characteristics (Id-Vg characteristics) of Sample A, Sample B, and Sample C. Fig. 19 is a diagram showing the electrical characteristics (Id-Vg characteristics) of Sample D and Sample F. Fig. 20 is a diagram showing the electrical characteristics (Id-Vg characteristics) of Sample G, Sample E, and Sample H. The horizontal axis represents gate voltage Vg, and the vertical axis represents drain current (Id).

[0119] 18 to 20, Samples A to G, which have a polycrystalline oxide semiconductor layer (Poly-OS), exhibit high mobility and good electrical properties. In contrast, Sample H, which has an oxide semiconductor layer (IGZO), exhibits lower mobility than the sample with an oxide semiconductor layer (Poly-OS).

[0120] Example 3 Next, a description will be given of the results of examining the electrical characteristics of the semiconductor device 10 manufactured according to the flowchart of the first embodiment shown in Fig. 3. Here, the change in electrical characteristics due to differences in the film thickness of the metal oxide layer 28 was examined.

[0121] A description will be given of Sample I and Sample J fabricated as the semiconductor device 10 in Example 3. In Sample I and Sample J, steps S1007 and S1008 in the flowchart of FIG.

[0122] (Sample I) A gate electrode 12GE was formed on a substrate, and gate insulating layers 14 and 16 were formed on the gate electrode 12GE. A 3-nm aluminum oxide layer was formed as a metal oxide film 18 on the gate insulating layers 14 and 16, and a 30-nm oxide semiconductor film 22 was formed on the metal oxide film 18. The oxide semiconductor film 22 was processed to form an oxide semiconductor layer 24, and OS annealing was performed at 350°C to 450°C to form an oxide semiconductor layer 26 with a polycrystalline structure. Furthermore, the metal oxide film 18 was removed using the oxide semiconductor layer 26 as a mask to form the metal oxide layer 28.

[0123] A MoW / Al / MoW structure was formed as a conductive film on the oxide semiconductor layer 26, and the conductive film was wet-etched using a mixed acid etching solution to form source and drain electrodes. Next, an interlayer insulating layer 34 was formed, and then a 10 nm aluminum oxide layer was formed as a metal oxide film 36. After oxidation annealing at 350°C, the metal oxide film 36 was removed. Finally, an interlayer insulating layer 38 was formed on the interlayer insulating layer 34.

[0124] (Sample J) Sample J was formed under the same conditions as Sample I, except that the thickness of the metal oxide layer 28 was 10 nm.

[0125] Next, the electrical characteristics of Sample I and Sample J were measured under the following conditions. Channel area size: W / L=6μm / 6μm Source-drain voltage: 0.1V, 10V Gate voltage: -40V to +40V (0.4V step) Measurement environment: room temperature, dark room Measurement location: 1 location on the board

[0126] 21 is a diagram showing the electrical characteristics (Id-Vg characteristics) of Sample I. FIG. 22 is a diagram showing the electrical characteristics (Id-Vg characteristics) of Sample J.

[0127] 21 and 22, it was shown that a shift in the threshold voltage of the semiconductor device was suppressed in both Sample I and Sample J. This is thought to be because the oxide semiconductor layer 26 was prevented from being removed by etching, thereby reducing the formation of defects on the surface of the oxide semiconductor layer 26. As a result, even after the subsequent oxidation annealing at 350° C. or higher, the defects formed in the oxide semiconductor layer 26 were sufficiently repaired, which is thought to have contributed to the shift in the threshold voltage of the semiconductor device.

[0128] The above-described embodiments and modifications of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions, based on the semiconductor device and display device of each embodiment or modification, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0129] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0130] 10: semiconductor device, 11: substrate, 12C: wiring, 12GE: gate electrode, 12W: wiring, 14: gate insulating layer, 15: contact hole, 16: gate insulating layer, 18: metal oxide film, 20: display device, 22: oxide semiconductor film, 24: oxide semiconductor layer, 26: oxide semiconductor layer, 28: metal oxide layer, 32: source electrode and drain electrode, 32C: wiring, 32D: drain electrode, 32S: source electrode, 32W: wiring, 34: interlayer insulating layer, 36: metal oxide film, 38: interlayer insulating layer, 39: insulating layer, 42C: common electrode, 44: insulating layer, 46C: electrode, 46P: pixel electrode, 110: driving transistor, 120: selection Transistor, 210: storage capacitor, 211: signal line, 212: gate line, 213: anode power line, 214: cathode power line, 220: liquid crystal region, 240: sealing region, 260: terminal region, 300: array substrate, 301: pixel circuit, 302: source driver circuit, 303: gate driver circuit, 304: source wiring, 305: gate wiring, 306: terminal section, 307: connection wiring, 310: sealing section, 311: liquid crystal element, 320: opposing substrate, 330: flexible printed circuit board, 340: chip, 350: storage capacitor, 362: insulating layer, 363: opening, 390: pixel electrode, 392: light-emitting layer, 394: common electrode

Claims

1. Terminal gate and, The gate insulating layer on the gate electrode, The metal oxide layer on the gate insulating layer, A polycrystalline oxide semiconductor layer on the aforementioned metal oxide layer, Source electrode and drain electrode on the oxide semiconductor layer, It includes an interlayer insulating layer that covers the source electrode and drain electrode and is in contact with the oxide semiconductor layer, The oxide semiconductor layer includes a first region superimposed on the source electrode or the drain electrode, and a second region in contact with the interlayer insulating layer. A semiconductor device in which the difference between the film thickness of the first region and the film thickness of the second region is 5 nm or less.

2. The semiconductor device according to claim 1, wherein the etching rate of the oxide semiconductor layer with respect to the etching solution used to form the source electrode and drain electrode is 0.1 nm / sec or less.

3. The semiconductor device according to claim 1, wherein the etching rate of the oxide semiconductor layer with respect to the etching gas used to form the source electrode and drain electrode is 0.5 nm / sec or less.

4. The semiconductor device according to claim 3, wherein the etching rate is 0.1 nm / sec or less.

5. The semiconductor device according to claim 1, wherein the film thickness of the first region is 10 nm or more and 30 nm or less.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a region containing only one crystal grain along the film thickness direction.

7. The semiconductor device according to claim 1, wherein the thickness of the metal oxide layer is 1 nm or more and 10 nm or less.

8. Forming a terminal station, A gate insulating layer is formed on the gate electrode, A metal oxide film is formed on the gate insulating layer. A polycrystalline oxide semiconductor layer is formed on the aforementioned metal oxide film. Using the aforementioned oxide semiconductor layer as a mask, the metal oxide film is etched to form a metal oxide layer. A conductive film is formed on the oxide semiconductor layer. The conductive film is patterned by etching to form the source electrode and the drain electrode. This includes covering the source electrode and drain electrode and forming an interlayer insulating layer that is in contact with the oxide semiconductor layer, The oxide semiconductor layer includes a first region superimposed on the source electrode or drain electrode and a second region in contact with the interlayer insulating layer. A method for manufacturing a semiconductor device, wherein the difference between the film thickness of the first region and the film thickness of the second region is 5 nm or less.

9. In the etching process described above, an etching solution was used. The method for manufacturing a semiconductor device according to claim 8, wherein the etching rate of the oxide semiconductor layer with respect to the etching solution is 0.1 nm / sec or less.

10. In the etching process described above, etching gas was used. The method for manufacturing a semiconductor device according to claim 8, wherein the etching rate of the oxide semiconductor layer with respect to the etching gas is 0.5 nm / sec or less.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the etching rate is 0.1 nm / sec or less.

12. The method for manufacturing a semiconductor device according to claim 8, wherein the film thickness of the first region is 10 nm or more and 30 nm or less.

13. The method for manufacturing a semiconductor device according to claim 8, wherein the oxide semiconductor layer includes a region containing only one crystal grain along the film thickness direction.

14. The method for manufacturing a semiconductor device according to claim 8, wherein the oxide semiconductor layer is formed by heat treatment of an oxide semiconductor layer having an amorphous structure.

15. The method for manufacturing a semiconductor device according to claim 8, wherein the thickness of the metal oxide layer is 1 nm or more and 10 nm or less.

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