Switched capacitor amplifier and battery monitoring device

Abstract

To provide a switched capacitor amplifier and a battery monitoring device that uses a telescopic type fully differential amplifier to significantly reduce output errors caused by common mode noise and achieve a high CMRR.SOLUTION: A telescopic type fully differential amplifier 14b includes an input portion 20 including input a transistor M1-M2. A bias generating portion 21 generates a bias Vbn1. A cascode portion 22 is cascode-connected to the input portion 20 of the fully differential amplifier 14b and applies the bias Vbn1 to the cascode portion 22. The bias generating section 21 generates the bias Vbn1 so as to depend on the source potentials of the input transistor M1-M2.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a switched capacitor amplifier and a battery monitoring device. [Background technology]

[0002] The applicant has previously proposed a battery monitoring device as shown in Patent Document 1. According to the technology described in Patent Document 1, a voltage detection device is composed of an RC filter, a multiplexer, a differential switched capacitor amplifier including a sampling capacitor and a feedback capacitor, and an AD converter. The battery monitoring device inputs a plurality of battery voltages by switching them using a multiplexer, and detects them using a pair of a differential switched capacitor amplifier and an AD converter. This makes it possible to reduce the size and power consumption. Since battery voltages are noisy, an RC filter with a cutoff frequency set to a low frequency is arranged at the input section of the battery monitoring device.

[0003] Some switched-capacitor fully differential amplifier circuits are provided with a leak cancellation circuit. The leak cancellation circuit is provided to cancel errors caused by the voltage drop determined by the leakage current flowing through the sampling capacitance and the resistance value of the RC filter when the switched-capacitor amplifier is in operation, thereby improving the accuracy of voltage detection. Conventionally, a leak cancellation circuit has a buffer amplifier only on one side of the fully differential amplifier circuit for the purpose of miniaturization. In this way, when the leak cancellation circuit is configured to be differentially asymmetric, the CMRR deteriorates and the accuracy deteriorates. CMRR is an abbreviation for Common Mode Rejection Ratio. Common mode noise is superimposed on the input voltage of the fully differential amplifier circuit, deteriorating the detection accuracy. For example, when used for battery monitoring, the common mode noise is large and this problem becomes prominent. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent No. 10429447 Summary of the Invention [Problem to be solved by the invention]

[0005] When a typical folded cascode amplifier or two-stage amplifier is used, the input common mode tolerance range can be widened, but the power consumption is high. In addition, when a telescopic amplifier with relatively low power consumption is used, there is a concern that the bias state may deviate from the saturation region of the input transistor due to impedance mismatch of the input transistor or fluctuation of the input common mode voltage, resulting in deterioration of linearity.

[0006] If the input common-mode noise exceeds the allowable range of the amplifier's input common-mode voltage, the amplifier's gain decreases and the error increases. In particular, when applied to battery monitoring applications, the problem becomes more pronounced as the common-mode noise increases.

[0007] An object of the present invention is to provide a switched capacitor amplifier and a battery monitoring device that use a telescopic type fully differential amplifier to significantly reduce output errors due to common mode noise and achieve a high CMRR. [Means for solving the problem]

[0008] According to the invention of claim 1, the subject is a switched capacitor amplifier having a fully differential amplifier circuit. The telescopic fully differential amplifier has an input section including an input transistor. The bias generating section generates a bias. The cascode section is cascode-connected to the input section of the fully differential amplifier and bias is applied to it. The bias generating section generates a bias to be applied to the cascode section so that it depends on the source potential of the input transistor. By configuring in this way, it is possible to configure the bias state without departing from the saturation region of the input transistor, and good linearity can be maintained. As a result, it is possible to obtain good characteristics by using the telescopic fully differential amplifier, which greatly reduces output errors due to common mode noise and enables high CMRR. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is an electrical configuration diagram showing a battery monitoring device according to an embodiment of the present invention; [Diagram 2] Example of a circuit configuration of a fully differential amplifier circuit according to an embodiment [Diagram 3] 1. Example of a circuit configuration of a fully differential amplifier circuit as a comparative example [Figure 4] Electrical configuration diagram of a leak cancel circuit according to one embodiment, part 1 [Diagram 5] Electrical configuration diagram of a leak cancel circuit according to one embodiment, part 2 [Figure 6] FIG. 2 is a diagram showing a schematic diagram of a sample / hold signal and an operating state of a leak cancel circuit according to an embodiment; [Figure 7] FIG. 1 is a diagram showing a schematic diagram of a charge flow when a leakage current is cancelled during a hold period according to an embodiment; [Figure 8] FIG. 1 is a diagram illustrating a flow of charge when canceling leakage during a sample period according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] An embodiment of the present invention will be described below with reference to the drawings. The battery monitoring device 1 shown in Fig. 1 monitors an assembled battery 4 mounted on a vehicle, and is configured, for example, by an ASIC. The assembled battery 4 has a plurality of battery cells 4a, 4b..., which are secondary batteries such as lithium ion batteries, connected in series in multiple stages. Therefore, a common mode voltage is superimposed on the plurality of battery cells 4a, 4b....

[0011] The common mode voltage is higher for battery cells 4a connected to the upper stage of the battery pack 4, i.e., the higher potential side. Note that Fig. 1 and other figures only show a portion of the battery cells, two battery cells 4a and 4b, and their corresponding configurations. The negative terminal P9 of the battery cell (not shown) located at the bottom stage of the battery pack 4, i.e., on the lowest potential side, is connected to the ground line Lg. The battery monitoring device 1 has functions such as detecting and amplifying the voltage between the terminals of the battery pack 4, i.e., the battery cells 4a and 4b. Note that the battery monitoring device 1 also has a function of detecting the current flowing through the battery cells 4a and 4b.

[0012] The battery monitoring device 1 includes terminals P1, P2 corresponding to the respective terminals of the battery cell 4a, terminals P3, P4 corresponding to the respective terminals of the battery cell 4b, and a terminal P9 for supplying a ground potential (0V).

[0013] Each terminal of the battery cell 4a is connected to terminals P1, P2 via a filter 3a. The filter 3a is an RC filter and includes resistors R1, R2 and a capacitor C1. Each terminal of the battery cell 4b is connected to terminals P3, P4 via a filter 3b. The filter 3b is an RC filter configured similarly to the filter 3a, and includes resistors R3, R and a capacitor C2. The terminal P9 is configured as the negative terminal of the battery cell (not shown) with the lowest potential, and is connected to the ground line Lg.

[0014] The battery monitoring device 1 includes a leak cancellation circuit 5, a control circuit 13, an integrator 14a configured using a switched-capacitor type fully differential amplifier circuit 14, a subtractor 15, a DA converter 16, and an AD converter 17. The control circuit 13 is configured using a predetermined logic circuit. Fig. 1 mainly illustrates components of a switched-capacitor amplifier 18 related to the present application. For this reason, the digital circuit downstream of the AD converter 17 is not illustrated in Fig. 1.

[0015] The multiplexer MUX selects one of the voltages at terminals P1 and P2, the voltages at terminals P3 and P4, etc., by switching on and off the switches S1, S2, S3, S4, etc., and outputs it to the subsequent stage. The differential analog signal selected by the multiplexer MUX is input to the integrator 14a via the subtractor 15.

[0016] The integrator 14a receives and integrates the differential analog signal, and outputs an integrated voltage according to the accumulated charges in the capacitors C11 to C16 to the higher-level AD converter 17. When the AD converter 17 receives the integrated voltage, it quantizes it into a plurality of levels and outputs it digitally. The digital output is output digitally after a predetermined digital processing, and is also input to the DA converter 16.

[0017] DA converter 16 converts the digital output of AD converter 17 into analog and feeds back the converted output VR to subtractor 15. Subtractor 15 subtracts the converted output VR from the input differential analog signal and inputs the result to integrator 14a. Integrator 14a integrates the difference signal input from subtractor 15 and outputs it to AD converter 17, which quantizes the integrated output and outputs it digitally.

[0018] The fully differential amplifier circuit 14 includes a fully differential amplifier 14b of a differential output type, and includes capacitors C11 to C18 and switches S11 to S30 as a switched capacitor block to configure an integrator 14a. Two voltages output from the multiplexer MUX are input to the fully differential amplifier circuit 14.

[0019] The two output voltages of the multiplexer MUX can be switched between normal and inverted inputs to nodes Np and Nm by controlling chop switches S7a, S7b, S7c, and S7d by the control circuit 13. The voltages at nodes Np and Nm are referred to as input voltages Vip and Vim.

[0020] The input voltages Vip and Vim can be switched between normal and inverted input to the capacitors C11 and C12 serving as sampling capacitances by controlling the chop switches S12a, S12b, S12c, and S12d by the control circuit 13.

[0021] The fully differential amplifier circuit 14 samples the input voltages Vip and Vim using the capacitors C11 and C12, and transfers the sampled charge via the capacitors C13 to C16 that correspond to the feedback capacitance. The fully differential amplifier circuit 14 is a differential sample-and-hold circuit that outputs a detection voltage corresponding to the input voltages Vip and Vim. The fully differential amplifier circuit 14 also performs level shifting to step down a high common mode voltage to a low reference voltage Vcm. In addition, the fully differential amplifier circuit 14 is configured to be able to switch its amplification factor (gain).

[0022] The common voltage of the fully differential amplifier 14b is set equal to a reference voltage Vcm that is the reference for voltage detection. The reference voltage Vcm is an intermediate voltage (e.g., +2.5V) between the power supply voltages (e.g., +5V) of the circuits. The fully differential amplifier 14b outputs output voltages Vop and Vom from its inverting output terminal and non-inverting output terminal, respectively.

[0023] The output voltages Vop, Vom correspond to detection voltages corresponding to the input voltages Vip, Vim, and are converted to digital data by a differential input type AD converter 17. This digital data represents the detection values ​​of the input voltages Vip, Vim, and is acquired by a higher-level control device (not shown). The fully differential amplifier circuit 14 is configured to be able to add an offset so that the output voltages Vop, Vom fall within the input voltage range of the AD converter 17 (for example, +2.5V to -2.5V).

[0024] <Example of circuit configuration of fully differential amplifier 14b> The fully differential amplifier circuit 14 includes a low-power fully differential amplifier 14b. As shown in Fig. 2, the fully differential amplifier 14b is configured as shown in the figure by connecting a cascode section 22, an input section 20 including differential input transistors M1-M2, and a MOS transistor M9 between a power supply and ground. The fully differential amplifier 14b is also configured as a telescopic type in which two pairs of MOS transistors M5-M6 and M7-M8 are connected as an active load 23 between a power supply and an output terminal. The gates of the two pairs of MOS transistors M5-M6 and M7-M8 are connected in common, and appropriate predetermined bias voltages Vbp2 and Vbp1 are applied to the commonly connected gates, respectively.

[0025] The sources of the input transistors M1 and M2 are connected in common to a bias generating unit 21 that generates a predetermined bias. As shown in Fig. 2, the bias generating unit 21 is configured by connecting in series between the drain and source of a current source CI1, a diode-connected n-channel MOS transistor M11, and an n-channel MOS transistor M10. The same bias voltage Vbn2 is applied to the gates of the MOS transistors M9 and M10.

[0026] A current source CI1 applies a predetermined current to the drain of the MOS transistor M11, thereby generating a bias voltage Vbn1 at the common connection point of the MOS transistor M11 and the MOS transistors M9 and M10. This bias voltage Vbn1 is provided to the sources of the differential input transistors M1-M2.

[0027] The fully differential amplifier 14b includes a cascode section 22 connected to input transistors M1 and M2. The cascode section 22 is configured between the input section 20 and an active load 23, and provides an output with high output impedance.

[0028] The cascode section 22 is composed of MOS transistors M3 and M4 cascode-connected to the differential input transistors M1 and M2. The gates of the MOS transistors M3 and M4 are commonly connected, and the aforementioned bias voltage Vbn1 is also applied to this commonly connected gate.

[0029] Here, the bias voltage Vbn1 of the gates of the MOS transistors M3-M4 of the cascode section 22 is set to the same potential as the bias voltage Vbn1 applied to the source potential of the input transistors M1-M2, but is not limited to this. It is preferable that the bias voltage Vbn1 depends on the source potential of the input transistors M1-M2. In other words, it is sufficient that the bias voltage Vbn1 changes in the same way as the source potential of the input transistors M1-M2.

[0030] According to this configuration, the bias generating unit 21 is provided with a diode-connected MOS transistor M11 to generate the bias voltage Vbn1. t、M1 and common mode voltage V in,cm It is possible to generate a bias voltage Vbn1 that depends on the

[0031] Below, we will explain the circuit along with the relationship of the voltages of each node. The input common mode voltage when no differential signal is input is V in,cm (equivalent to VCMIN). The fully differential amplifier circuit 14 detects the change ΔV t,M1 Even if there is an input common-mode voltage V in,cm The change due to the mismatch of the input impedance ΔV must be within the range of the upper and lower limits. t,M1 is present, and the input common-mode voltage V in,cm If fluctuates, the bias state will deviate from the saturation region of the input transistors M1-M2, and the linearity will deteriorate.

[0032] <Comparative Example> For example, a circuit not including the bias generation unit 21 composed of the current source CI1 and the MOS transistors M11 and M10 is shown in FIG. 3 as a comparative example. In the configuration of FIG. 3, a bias generation unit 121 is provided instead of the bias generation unit 21. The bias generation unit 121 includes a current source CI1 and a diode-connected MOS transistor M111, and generates a voltage at a common connection point of the current source CI1 and the MOS transistor M111 as a predetermined bias voltage Vbn1. According to the configuration shown in FIG. 3, the bias voltage Vbn1 is not applied to the gates of the MOS transistors M3 and M4 in a manner that depends on the source potential of the MOS transistor M111. As in the configuration of FIG. 3, when a predetermined bias voltage Vbn1 is applied to the gates of the MOS transistors M3 and M4, the input common-mode voltage V in,cm The lower and upper limits of the condition are the change due to the mismatch of the input impedance ΔV t,M1 The threshold voltage of the MOS transistor M111 varies depending on V t,M111 and the overdrive voltage is V od,M111 Then, the bias voltage Vbn1 is the threshold voltage V t,M111 + Overdrive voltage V od,M111 If the input impedance is mismatched, the input common mode voltage V in,cm The tolerance range becomes narrower.

[0033] <In the case of the configuration of this embodiment> In contrast, consider the case where the bias generating unit 21 is provided as in this embodiment. By providing the bias generating unit 21, a bias voltage Vbn1 that depends on the source potential of the MOS transistor M11 can be applied to the gates of the MOS transistors M3 and M4. In this case, the drain potential of the input transistors M1-M2 is calculated by dividing the bias voltage Vbn1 by the (overdrive voltage V od、M3 + Threshold voltage V t、M3 ) of the MOS transistor M11 from the bias voltage Vbn1. od、M11 + Threshold voltage V t、M11) is subtracted from the drain potential Vbn1. As a result, both the drain potential and the source potential of the input transistors M1-M2 change depending on the bias voltage Vbn1.

[0034] If the input voltages Vinp and Vinm are adjusted so that the input transistors M1 and M2 operate in the saturation region, the change ΔV due to the mismatch in input impedance t,M1 The change is stable and almost independent of

[0035] According to this embodiment, the bias voltage Vbn1 depending on the source potential of the input transistors M1-M2 is applied to the gates of the MOS transistors M3-M4 of the cascode section 22. As a result, the common mode voltage V in,cm It is possible to obtain a robust output that can respond to the fluctuations without being dependent on the fluctuations of the input signal.

[0036] This fully differential amplifier 14b is used as a fully differential amplifier circuit 14 that serves as a switched capacitor amplifier. in,cm Even if the input transistors M1 and M2 fluctuate, the bias state of the input section 20 of the fully differential amplifier 14b can be maintained in the saturation region. As a result, the bias state can be configured not to deviate from the saturation region of the input transistors M1 and M2. Good linearity can be maintained, and high-precision and high-speed operation can be achieved.

[0037] <Explanation of the peripheral configuration of the fully differential amplifier 14b> 1, a pair of capacitors C11 and C12 are provided at the differential input of the fully differential amplifier 14b. The capacitors C11 and C12 have the same capacitance value Cs. In this specification, the term "same capacitance value" does not only mean that the capacitance values ​​are completely the same, but also includes capacitance values ​​that are slightly different from each other and do not strictly match, as long as the desired effect is achieved.

[0038] One terminal of each of the capacitors C11 and C12 is connected to the multiplexer MUX. The other terminal of each of the capacitors C11 and C12 is connected to the non-inverting input terminal and the inverting input terminal of the fully differential amplifier 14b. Between the non-inverting input terminal and the inverting input terminal of the fully differential amplifier 14b, the switches S12e and S12f are connected in series, and the common connection point of the switches S12e and S12f is connected to the input common mode potential line LIN (for example, the input common mode potential VCMIN=2.1V).

[0039] The pair of feedback capacitors C13 and C14 have the same capacitance Cf. The pair of capacitors C15 and C16 in the differential configuration have the same capacitance Cf2. The capacitor C13 is connected in series between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier 14b. The capacitor C14 is connected in series between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier 14b.

[0040] One terminal of the capacitor C15 is connected to the non-inverting input terminal of the fully differential amplifier 14b via a switch S17, and is connected to an input common mode potential line LIN (e.g., an input common mode potential VCMIN=2.1V) via a switch S18. The other terminal of the capacitor C15 is connected to an inverting output terminal of the fully differential amplifier 14b via a switch S19, and is connected to an output common mode potential line LO (e.g., an output common mode potential VCMO=2.5V) via a switch S20.

[0041] One terminal of the capacitor C16 is connected to the inverting input terminal of the fully differential amplifier 14b via a switch S21, and is connected to the input common mode potential line LIN (for example, input common mode potential VCMIN=2.1V) via a switch S22. The other terminal of the capacitor C16 is connected to the non-inverting output terminal of the fully differential amplifier 14b via a switch S23, and is connected to the output common mode potential line LO (for example, output common mode potential VCMO=2.5V) via a switch S24. The input common mode potential line LIN and the output common mode potential line LO are at different potentials.

[0042] According to this configuration, when the switches S17, S19, S21, and S23 are off, the capacitor C13 is connected between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier 14b. Also, the capacitor C14 is connected between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier 14b. In this case, the capacitance value of the feedback capacitance is the capacitance value Cf of the capacitors C13 and C14.

[0043] In contrast, when the switches S17, S19, S21, and S23 are on, the capacitors C13 and C15 are connected in parallel between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier 14b. The capacitors C14 and C16 are connected in parallel between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier 14b. In this case, the capacitance value of the feedback capacitance is the capacitance value Cf of the capacitors C13 and C14 plus the capacitance value Cf2 of the capacitors C15 and C16 (=Cf+Cf2).

[0044] In this embodiment, the switches S17, S19, S21, and S23 form a feedback capacitance switching unit that switches the capacitance value of the feedback capacitance. In this case, the feedback capacitance switching unit increases the capacitance value of the feedback capacitance when the switches S17, S19, S21, and S23 are switched from off to on. The amplification factor of the fully differential amplifier circuit 14 changes depending on the capacitance value of the feedback capacitance. Therefore, in this embodiment, the fully differential amplifier circuit 14 is configured to be able to switch its amplification factor by switching the capacitance value by the feedback capacitance switching unit.

[0045] On the other hand, DA converter 16 receives the digital output value of AD converter 17. In DA converter 16, switches S25 to S30 are switched on and off under the control of control circuit 13. DA converter 16 inputs a conversion output VR corresponding to digital processing of the digital output of AD converter 17 as a reference voltage (any of Vrp, Vcm, and Vrm) to capacitors C17 and C18, which become DAC capacitances. The conversion output VR corresponds to an analog voltage obtained by D / A converting the output value of AD converter 17, and has a relationship of, for example, Vrp>Vcm>Vrm.

[0046] One terminal of the capacitor C17 is connected to one terminal of the capacitor C15. A reference voltage Vrp (e.g., +5 V) can be applied to the other terminal of the capacitor C17 via a switch S25, a reference voltage Vcm can be applied via a switch S26, and a reference voltage Vrm (e.g., 0 V) ​​can be applied via a switch S27.

[0047] One terminal of the capacitor C18 is connected to one terminal of the capacitor C16. A reference voltage Vrp can be applied to the other terminal of the capacitor C18 via a switch S28, a reference voltage Vcm can be applied via a switch S29, and a reference voltage Vrm can be applied via a switch S30.

[0048] In the above configuration, a high common mode voltage superimposed on the battery cells 4a-4c is applied to the capacitors C11, C12 and the circuit elements disposed on the side of the assembled battery 4 between the capacitors C11, C12. For this reason, high-voltage elements that can withstand this voltage are used for the capacitors C11, C12 and the circuit elements on the side of the assembled battery 4. Low-voltage elements are used for the other circuit elements. In this embodiment, at least the capacitors C11, C12 are configured by inter-wire capacitance, thereby realizing a high voltage resistance.

[0049] When detecting the terminal voltage of the battery cell 4a or 4b, the control circuit 13 controls the operation of the multiplexer MUX to output the terminal voltage of the battery cell 4a or 4b, and controls the amplification operation of the fully differential amplifier circuit 14 to switch the amplification factor to a predetermined amplification factor. Furthermore, at this time, the control circuit 13 controls the amplification operation of the fully differential amplifier circuit 14 to apply an offset.

[0050] Furthermore, the control circuit 13 controls the amplifying operation of the fully differential amplifier circuit 14 so that sampling is performed twice for each voltage detection. That is, in one of the two samplings, the control circuit 13 samples the input voltage Vip using the capacitor C11 and samples the input voltage Vim using the capacitor C12. In this way, the control circuit 13 controls the amplifying operation of the multiplexer MUX and the fully differential amplifier circuit 14.

[0051] Furthermore, in the other of the two samplings, the control circuit 13 samples the input voltage Vip using the capacitor C12 and samples the input voltage Vim using the capacitor C11. In this way, the control circuit 13 controls the amplification operation of the multiplexer MUX and the fully differential amplifier circuit 14. With this configuration and the control circuit 13 switching the switches on and off according to a predetermined rule, it is possible to cancel the offset that occurs in the fully differential amplifier circuit 14 when detecting the terminal voltages of the battery cells 4a, 4b, etc.

[0052] <Configuration of the leak cancellation circuit 5> Next, a configuration example of the leak cancel circuit 5 shown in Fig. 1 will be described with reference to Fig. 4 and Fig. 5. In this embodiment, chop switches S12a to S12d are provided on the input side of the fully differential amplifier 14b. These chop switches S12a to S12d, together with the capacitors C11 and C12, form an RC filter, increasing the input impedance of the fully differential amplifier 14b. This makes the amplifier more susceptible to the effects of leak current flowing in from the multiplexer MUX side, so the leak cancel circuit 5 is provided.

[0053] The leak cancellation circuit 5 is connected to the input nodes of the input voltages Vip and Vim of the fully differential amplifier circuit 14. The leak cancellation circuit 5 is configured by connecting in parallel the switched capacitor blocks 8 and 9 shown in FIGS. 4 and 5 together with the DA converter 6 and the amplifier 7.

[0054] 4, the leak cancellation circuit 5 includes a DA converter 6 as a voltage generating circuit, an amplifier 7, and switched capacitor blocks 8 and 9. The DA converter 6 is configured to receive a digital command value for creating a compensation current, convert it into analog, and output two command voltages to be input to the amplifier 7.

[0055] The DA converter 6 is configured with a fully differential DAC. The fully differential DAC outputs two command voltages: a first voltage that is directly proportional to the digital command value with a positive gradient, and a second voltage that is directly proportional to the digital command value with a negative gradient. The DA converter 6 may be configured with a pseudo-differential DAC. The pseudo-differential DAC outputs two command voltages: a first voltage that is constant regardless of the digital command value, and a second voltage that is directly proportional to the digital command value.

[0056] The amplifier 7 is composed of two single-ended buffers 7a and 7b each configured as a voltage follower. The amplifier 7 receives the two command voltages output by the DA converter 6, performs impedance conversion by the voltage follower, and outputs voltages Vdp and Vdm.

[0057] 4 and 5, the switched capacitor blocks 8 and 9 are configured to switch the output of two buffers 7a and 7b to charge and discharge the capacitors C8a, C8b, C9a, and C9b, and output the same configuration. Therefore, the configuration of the switched capacitor block 8 will be mainly described. The components of the switched capacitor blocks 8 and 9 are given the same reference numerals as the switches S8 and S9 and the capacitors C8 and C9, and corresponding components are illustrated with suffixes a, b, c, d, aa, ba, ca, da, etc.

[0058] 5, the switched capacitor block 8 includes switches S8a to S8d, capacitors C8a and C8b, and switches S8aa, S8ba, S8ca, and S8da. The switched capacitor block 9 includes switches S9a to S9d, capacitors C9a and C9b, and switches S9aa, S9ba, S9ca, and S9da.

[0059] The switches S8a to S8d receive the voltages Vdp and Vdm, and are capable of switching between straight and cross connection and passing current through the capacitors C8a and C8b under the control of the control circuit 13. The switches S9a to S9d also receive the voltages Vdp and Vdm, and are capable of switching between straight and cross connection and passing current through the capacitors C9a and C9b under the control of the control circuit 13.

[0060] The control circuit 13 also switches on the switches S8ca and S8da and turns off the switches S8aa and S8ba to switch the current paths of the capacitors C8a and C8b to closed paths. The control circuit 13 switches off the switches S8ca and S8da and turns on the switches S8aa and S8ba to switch the current paths of the outputs of the capacitors C8a and C8b to the node side of the input voltages Vip and Vim.

[0061] The control circuit 13 also switches on the switches S9ca and S9da and turns off the switches S9aa and S9ba to switch the current path of the capacitors C9a and C9b to a closed path. The control circuit 13 switches off the switches S9ca and S9da and turns on the switches S9aa and S9ba to switch the current path of the outputs of the capacitors C9a and C9b to the node side of the input voltages Vip and Vim.

[0062] <Function of leak cancellation circuit 5> Next, leakage cancellation by the leakage cancellation circuit 5 will be explained. Fig. 6 shows the operating states of the switched capacitor blocks 8 and 9 during the hold period / sample period. The leakage cancellation circuit 5 of this embodiment is capable of canceling the effect of offset caused by leakage current flowing in from the multiplexer MUX side during the hold period in Fig. 7 and the sample period in Fig. 8 shown below.

[0063] The control circuit 13 switches the switches S8a to S8d, S9a to S9d, S8aa, S8ba, S8ca, S8da, S9aa, S9ba, S9ca, S9da, and S12a to S12f on or off. This allows connections to be made during the hold period shown in Fig. 7 and the sample period shown in Fig. 8. During the sample period, the chop switches 12a to 12d are switched to sample the capacitors C11 and C12. During the hold period, the voltages held by the capacitors C11 and C12 are input to the differential input terminals of the fully differential amplifier 14b.

[0064] The switched capacitor blocks 8 and 9 repeat these operations during the hold period and the sample period. The integrator 14a outputs an integrated voltage, which is converted by the AD converter 17. The control circuit 13 alternately operates the two switched capacitor blocks 8 and 9 during correlated double sampling. As a result, the leakage cancellation circuit 5 cancels the leakage current by passing a compensation current during both the hold period and the sample period.

[0065] In the steady state of the hold period shown in FIG. 7, the capacitors C8a and C8b hold charges based on the voltages Vdp and Vdm of the switched capacitor block 8 and the intermediate potential (Vip+Vim) / 2 of the differential input terminals of the fully differential amplifier 14b into which leakage current flows.

[0066] At this time, the non-inverting input terminal and the inverting input terminal of the fully differential amplifier 14b are connected so as to be short-circuited by turning on the switches 12e and 12f. The differential input terminals of the fully differential amplifier 14b are each held at the input common-mode potential VCMIN. In the hold period shown in Fig. 7, the switched capacitor block 9 conversely passes a current based on the charge Qlc through the capacitors C9a and C9b to the input side of the fully differential amplifier 14b. This cancels the charge Qsh due to the leakage current flowing in the hold period.

[0067] 8, the capacitors C9a and C9b hold charges based on the voltages Vdp and Vdm, and the intermediate potential (Vip+Vim) / 2 of the differential input terminals into which the leakage current flows. The non-inverting input terminal and the inverting input terminal of the fully differential amplifier 14b are open and in an imaginary short state. Conversely, in the sample period shown in FIG. 8, the switched capacitor block 8 passes a current based on the charge Qlc through the capacitors C8a and C8b to the input side of the fully differential amplifier 14b, canceling the charge Qsh due to the leakage current flowing during the sample period.

[0068] When the sampling capacitance is constant, the leakage cancellation voltage ΔVd for the input voltage ΔVi can be increased by using a MOS transistor with a low threshold voltage Vt, and a leakage cancellation capacitance with a small capacitance value can be used. If the leakage cancellation capacitance can be reduced, the circuit area can be reduced.

[0069] According to this embodiment, the leakage cancellation circuit 5 performs correlated double sampling based on the command voltage from the DA converter 6 to generate a compensation current, so that the leakage current can be canceled during the hold period and sample period when the correlated double sampling is performed.

[0070] <Summary of this embodiment> The purpose, problems, and technical significance of this embodiment will be described below. <Objectives and Problems of the Present Embodiment> In a telescopic amplifier, impedance mismatches and input common mode fluctuations of the input transistors M1 and M2 cause the bias state of the input transistors M1 and M2 to fall out of the saturation region, deteriorating linearity. If a folded cascode or two-stage amplifier is used, the allowable range of the input common mode voltage becomes wider, but power consumption tends to increase.

[0071] When the fully differential amplifier 14b is used in the switched capacitor type fully differential amplifier circuit 14, if common mode noise is introduced into the input, the input common mode of the fully differential amplifier 14b fluctuates and may exceed the allowable range of the input common mode voltage. If the allowable range is exceeded, the gain of the fully differential amplifier 14b decreases and the error increases. This problem is particularly noticeable when used as a battery monitoring device 1, where the common mode noise is large.

[0072] <Technical significance of this embodiment> According to this embodiment, the bias voltage Vbn1 is applied to the gates of the MOS transistors M3-M4 of the cascode section 22, and this bias voltage Vbn1 varies depending on the source potentials of the input transistors M1-M2. This makes it possible to obtain a robust output in response to fluctuations in the reference voltage Vcm input to the fully differential amplifier 14b.

[0073] When this fully differential amplifier 14b is used in the switched-capacitor fully differential amplifier circuit 14, the operating state of the input transistors M1-M2 based on the state of the bias voltage Vbn1 can be maintained in the saturation region even if the reference voltage Vcm on the input side of the fully differential amplifier 14b changes transiently due to the sample / hold operation described above. As a result, it is possible to operate with high precision and high speed.

[0074] The battery monitoring device 1 of this embodiment is provided with chop switches S12a to S12d on the input side of the fully differential amplifier 14b. The chop switches S12a to S12d and the capacitors C11 and C12 act as an RC filter when inputting the voltage of the assembled battery 4. For this reason, the input impedance of the fully differential amplifier 14b becomes high in a region below a cutoff frequency of 1 kHz, for example. When the input impedance becomes high, it is easily affected by leakage current leaking from the multiplexer MUX side.

[0075] For this reason, it is desirable to provide a separate leak cancellation circuit 5 as in this embodiment. The leak cancellation circuit 5 is also configured as a fully differential type, and is configured by combining a DA converter 6 and an amplifier 7 consisting of two single-ended buffers 7a and 7b. For this reason, even if the input impedance becomes high, the effects of the leak current can be suppressed.

[0076] When the leakage cancellation circuit 5 operates, common mode noise is applied to the input of the fully differential amplifier 14b. Even in this case, the application of the configuration of the fully differential amplifier 14b of this embodiment prevents deterioration of accuracy, and a low-power, highly accurate switched-capacitor type fully differential amplifier circuit 14 can be configured. This allows a switched-capacitor amplifier to be configured with a high CMRR.

[0077] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0078] In the drawings, 4 indicates a battery pack, 4a and 4b indicate battery cells, 5 indicates a leakage cancellation circuit, 6 indicates a DA converter, 7a and 7b indicate buffers, C8aa, C8ba, C9aa, and C9ba indicate capacitors, S8a to S8d, S8aa to S8da, S9a to S9d, and S9aa to S9da indicate switches, 12a to 12d indicate chop switches, 14 indicates a fully differential amplifier circuit, M1 and M2 are input transistors, 20 indicates an input section, 21 indicates a bias generation section, and 22 indicates a cascode section.

Claims

1. A switched capacitor amplifier comprising a fully differential amplifier circuit (14), a telescopic type fully differential amplifier (14b) having an input section (20) including input transistors (M1, M2), a bias generation section (21) for generating a bias (Vbn1), a cascode section (22) which is cascode-connected to the input section of the fully differential amplifier and to which the bias is applied, wherein the bias generation section generates the bias applied to the cascode section so as to depend on the source potential of the input transistors, a chopper switch (12a to 12d) is further provided on the input side of the input section of the fully differential amplifier, a leak canceling circuit (5) for canceling leak current is connected to the input side of the input section of the fully differential amplifier, the leak canceling circuit comprising: a DA converter (6) which inputs a digital command value and differentially outputs a command voltage, two single-ended configured buffers (7a, 7b) which input the differential output of the DA converter, switches (S8a to S8d, S8aa to S8da, S9a to S9d, S9aa to S9da) which switch the outputs of the two buffers to charge and discharge capacitors (C8a, C8b, C9a, C9b) and output the result, and is configured to switch a sample period for sampling capacitors (C11, C12) by switching the chopper switch, and a hold period for inputting the holding voltage of the capacitors to the differential input terminals of the fully differential amplifier to apply charge, the leak canceling circuit being a switched capacitor amplifier which applies charge so as to cancel leak current during any of the sample period and the hold period.

2. A battery monitoring device (1) used for monitoring the state of a battery pack (4) formed by combining battery cells (4a, 4b), the battery monitoring device using the switched capacitor amplifier according to Claim 1 for voltage amplification of the voltage between the terminals of the battery cells of the battery pack.

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