High-speed, energy-efficient cmos2p1r1w register file array using recovered data

JP2024152561A5Pending Publication Date: 2026-06-03Metis Microsystems, LLC
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Metis Microsystems, LLC
Filing Date
2023-10-02
Publication Date
2026-06-03

AI Technical Summary

Technical Problem

Conventional 2-port register file arrays face challenges with high energy consumption, leakage, and reliability issues due to simultaneous read and write accesses, which affect performance and scalability in CMOS chips, particularly in GPUs used for AI workloads.

Method used

A new CMOS recovery circuit for 2-port register file arrays that utilizes recovered data to self-limit energy dissipation by eliminating the need for keeper circuits and reducing vertical and lateral electric fields, thereby improving reliability and reducing energy consumption.

Benefits of technology

The proposed circuit significantly reduces energy consumption by more than 70% and improves signal generation speed by up to 50%, while maintaining reliability and minimizing area overhead, without requiring changes to the CMOS platform or array architecture.

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Abstract

To provide a register file array that improves a circuit speed of a two-port / multi-port register file array to self-limit energy dissipation when using recovered data and to significantly reduce the energy cost of moving data along a local bit path and a global bit path.SOLUTION: When a potential of recovered data matches a BL voltage from signal generation, uncertainty in BL signal generation due to statistical variations in cell read current is eliminated by self-invalidating an action of the selected cell, while reducing the number of peripheral circuit transistors required per column compared to conventional sensing methods at the same time.SELECTED DRAWING: Figure 1
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