Exposure device and image formation device

Abstract

To provide a technology capable of suppressing a capacitance of a memory provided in an exposure device.SOLUTION: An exposure device mounted in an image formation device includes one or more of light-emitting chips. The light-emitting chip includes: a plurality of light-emitting elements; output means that receives a synchronous signal periodically transmitted from the image formation device and image data corresponding to each of the plurality of light-emitting elements transmitted from the image formation device in a period of the synchronous signal, and outputs a drive signal corresponding to each of the plurality of light-emitting elements for driving the plurality of light-emitting elements; and drive means that drives the plurality of light-emitting elements on the basis of the drive signal corresponding to each of the plurality of light-emitting elements. The output means includes a plurality of latch circuits corresponding to each of the plurality of light-emitting elements for latching the image data corresponding to each of the plurality of light-emitting elements and outputting the drive signal corresponding to each of the plurality of light-emitting elements.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to an exposure device having a plurality of light-emitting elements, and an image forming apparatus that forms an image using the exposure device. [Background technology]

[0002] An electrophotographic image forming apparatus forms an image by exposing a rotating photoreceptor to light to form an electrostatic latent image on the photoreceptor, and developing the electrostatic latent image with toner. The direction parallel to the rotation axis of the photoreceptor is referred to as the main scanning direction. Patent Document 1 discloses an image forming apparatus that performs exposure using an exposure device in which a row of light emitting units, each of which is arranged in the main scanning direction, is arranged in a sub-scanning direction corresponding to the rotation direction of the photoreceptor. In Patent Document 1, a plurality of light emitting chips are mounted on a substrate, each of which has electrodes, an organic EL (Electro-Luminescence) film, and a circuit unit for emitting light from the organic EL film formed on a silicon wafer. The circuit unit is provided with flip-flop circuits for transferring input image data in the main scanning direction and flip-flop circuits for holding the image data, each of which is equal to the number of light emitting units. When image data is held in all of the flip-flop circuits for holding the image data, the light emitting units are controlled simultaneously. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-35765 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, flip-flop circuits for transferring input image data in the main scanning direction are provided in the same number as the light-emitting units, which results in an increase in the size and cost of the light-emitting chip.

[0005] In view of the above problems, an object of the present invention is to suppress the increase in size and cost of a light-emitting chip. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, an exposure device implemented in an image forming apparatus has one or more light-emitting chips including a plurality of light-emitting elements, an output means for receiving a synchronization signal periodically transmitted from the image forming apparatus and image data corresponding to each of the plurality of light-emitting elements transmitted from the image forming apparatus within the period of the synchronization signal, and outputting a drive signal corresponding to each of the plurality of light-emitting elements to drive the plurality of light-emitting elements, and a drive means for driving the plurality of light-emitting elements based on the drive signal corresponding to each of the plurality of light-emitting elements, and the output means has a plurality of latch circuits corresponding to each of the plurality of light-emitting elements for latching the image data corresponding to each of the plurality of light-emitting elements and outputting a drive signal corresponding to each of the plurality of light-emitting elements. Effect of the Invention

[0007] According to the present disclosure, it is possible to prevent the light-emitting chip from becoming large. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic configuration diagram of an image forming apparatus according to an embodiment. [Diagram 2] FIG. 2 illustrates an exposure head and photoreceptor according to one embodiment. [Diagram 3] FIG. 2 illustrates a printed circuit board for an exposure head according to one embodiment. [Figure 4] FIG. 2 is an illustration of an arrangement of light emitting elements in a light emitting chip according to one embodiment. [Diagram 5] FIG. 2 is a plan view of a light emitting chip according to one embodiment. [Figure 6] 1 is a cross-sectional view of a light emitting chip according to one embodiment. [Figure 7] FIG. 2 is a control configuration diagram of a light emitting chip according to an embodiment. [Figure 8] 11A and 11B are diagrams showing examples of signals on each signal line when accessing a register of a light-emitting chip according to one embodiment. [Figure 9] 11A and 11B are diagrams showing examples of signals on each signal line when transmitting image data to the light-emitting chip according to one embodiment. [Figure 10] FIG. 2 is a functional block diagram of a light-emitting chip according to one embodiment. [Figure 11] FIG. 2 is a block diagram of a forwarding unit according to one embodiment. [Figure 12] FIG. 4 is a configuration diagram of a latch unit according to one embodiment. [Figure 13] FIG. 13 is a configuration diagram of another latch unit according to an embodiment. [Figure 14] 4 is a timing chart of each signal in a circuit section according to one embodiment. [Figure 15] FIG. 4 is a block diagram of a current driver according to one embodiment. [Figure 16] 4 is a flow chart of a process performed by an image controller according to one embodiment. [Figure 17] 11 is another timing chart of each signal in the circuit section according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0010] First Embodiment 1 is a schematic diagram of an image forming apparatus according to the present embodiment. A reading unit 100 optically reads an original placed on a platen and generates image data representing the reading result. An image creating unit 103 forms an image on a sheet based on the image data generated by the reading unit 100 or based on image data received from an external device via a network, for example.

[0011] The image forming unit 103 includes image forming units 101a, 101b, 101c, and 101d. The image forming units 101a, 101b, 101c, and 101d form black, yellow, magenta, and cyan toner images, respectively. The image forming units 101a, 101b, 101c, and 101d have the same configuration, and will be collectively referred to as the image forming unit 101 below. The photoconductor 102 of the image forming unit 101 is rotated clockwise in the figure during image formation. The charger 107 charges the photoconductor 102. The exposure head 106, which is an exposure device, exposes the photoconductor 102 according to image data and forms an electrostatic latent image on the photoconductor 102. The developer 108 develops the electrostatic latent image on the photoconductor 102 with toner. The toner image on the photoconductor 102 is transferred onto a sheet transported on a transfer belt 111. Note that by transferring the toner images of the photoconductors 102 onto a sheet in an overlapping manner, it is possible to reproduce colors other than black, yellow, magenta, and cyan.

[0012] The conveying unit 105 controls the feeding and conveying of the sheet. Specifically, the conveying unit 105 feeds the sheet from a designated unit among the internal storage units 109a and 109b, the external storage unit 109c, and the manual feed unit 109d to a conveying path of the image forming apparatus. The fed sheet is conveyed to the registration rollers 110. The registration rollers 110 convey the sheet onto the transfer belt 111 at a predetermined timing so that the toner images of the photoconductors 102 are transferred onto the sheet. As described above, the toner image is transferred onto the sheet while being conveyed on the transfer belt 111. The fixing unit 104 fixes the toner image onto the sheet by applying heat and pressure to the sheet onto which the toner image has been transferred. After the toner image is fixed, the sheet is discharged to the outside of the image forming apparatus by the discharge rollers 112.

[0013] 2(A) and 2(B) show the photoconductor 102 and the exposure head 106. The exposure head 106 has a light emitting point group 201, a printed circuit board 202 on which the light emitting point group 201 is mounted, a rod lens array 203, and a housing 204 that holds the rod lens array 203 and the printed circuit board 202. The rod lens array 203 focuses the light emitted from the light emitting point group 201 on the photoconductor 102 to form an imaging spot of a predetermined size on the photoconductor 102.

[0014] 3(A) and 3(B) show the printed circuit board 202. FIG. 3(A) shows the surface on which the connector 305 is mounted, and FIG. 3(B) shows the surface on which the light-emitting point group 201 is mounted (the surface opposite to the surface on which the connector 305 is mounted). In this embodiment, the light-emitting point group 201 includes 20 light-emitting chips 400-1 to 400-20. The light-emitting chips 400-1 to 400-20 are arranged in two rows in a staggered manner along the main scanning direction. In the following description, the light-emitting chips 400-1 to 400-20 are also collectively referred to as light-emitting chips 400. Each light-emitting chip 400 has a plurality of light-emitting points (light-emitting elements). Each light-emitting chip 400 of the printed circuit board 202 is connected to an image controller 700 (FIG. 7) which is a control unit via a connector 305.

[0015] FIG. 4 is an explanatory diagram of the arrangement of the light-emitting chip 400 and the light-emitting points 602 provided on the light-emitting chip 400. One light-emitting chip 400 has a plurality of sets of 748 light-emitting points 602 arranged along the main scanning direction. The plurality of sets are arranged along the sub-scanning direction perpendicular to the main scanning direction. In this manner, the light-emitting chip 400 is arranged two-dimensionally along both the main scanning direction and the sub-scanning direction. In the following description, the number of sets is set to 4 as an example. That is, in the following exemplary embodiment, the light-emitting chip 400 has four sets of 748 light-emitting points 602 arranged along the main scanning direction, that is, a total of 2992 light-emitting points 602. The pitch of adjacent light-emitting points 602 in the main scanning direction is about 21.16 μm, which corresponds to a resolution of 1200 dpi. Therefore, the length of one set of 748 light-emitting points 602 in the main scanning direction is about 15.8 mm. The pitch between adjacent light-emitting points 602 in the sub-scanning direction (length P in FIG. 4) is also about 21.16 μm, which corresponds to a resolution of 1200 dpi. Furthermore, the pitch between the light-emitting points 602 of two adjacent light-emitting chips 400 in the main scanning direction (length L in FIG. 4) is also about 21.16 μm, which corresponds to a resolution of 1200 dpi.

[0016] 5 is a plan view of the light-emitting chip 400. The light-emitting chip 400 has a plurality of light-emitting points 602 formed on a light-emitting substrate 402, which is, for example, a silicon substrate. A circuit unit 406 for controlling the plurality of light-emitting points 602 is formed on the light-emitting substrate 402. Signal lines for communicating with the image controller 700, power lines for connecting to a power source, and ground lines for connecting to ground are connected to the pads 408-1 to 408-9. The signal lines, power lines, and ground lines are, for example, wires made of gold.

[0017] FIG. 6 shows a part of the cross section taken along line AA in FIG. 5. A plurality of lower electrodes 504 are formed on the light-emitting substrate 402. A gap of length d is provided between two adjacent lower electrodes 504. A light-emitting layer 506 is provided on the lower electrode 504, and an upper electrode 508 is provided on the light-emitting layer 506. The upper electrode 508 is a common electrode for the plurality of lower electrodes 504. When a predetermined voltage is applied between the lower electrode 504 and the upper electrode 508, a current flows from the lower electrode 504 to the upper electrode 508, causing the light-emitting layer 506 to emit light. Therefore, a region of the light-emitting layer 506 corresponding to a region of one lower electrode 504 corresponds to one light-emitting point 602. That is, in this embodiment, the light-emitting substrate 402 includes a plurality of light-emitting points. The light-emitting point may be called a light-emitting portion.

[0018] For example, an organic EL film can be used for the light-emitting layer 506. Alternatively, an inorganic EL film can be used for the light-emitting layer 506. The upper electrode 508 is composed of a transparent electrode such as indium tin oxide (ITO) so as to transmit the emission wavelength of the light-emitting layer 506. Note that in this embodiment, the entire upper electrode 508 transmits the emission wavelength of the light-emitting layer 506, but it is not necessary for the entire upper electrode 508 to transmit the emission wavelength. Specifically, it is sufficient that the area from which light from each light-emitting point 602 is emitted transmits the emission wavelength.

[0019] In FIG. 6, one continuous light-emitting layer 506 is formed, but a plurality of light-emitting layers 506 each having a width equivalent to the width W of the lower electrode 504 may be formed on the lower electrode 504. In FIG. 6, the upper electrode 508 is one common electrode for the plurality of lower electrodes 504, but a plurality of upper electrodes 508 each having a width equivalent to the width W of the lower electrode may be formed corresponding to each of the lower electrodes 504. In addition, the first plurality of lower electrodes 504 of the lower electrodes 504 of each light-emitting chip 400 may be covered by the first light-emitting layer 506, and the second plurality of lower electrodes 504 may be covered by the second light-emitting layer 506. In addition, the first upper electrode 508 may be commonly formed corresponding to the first plurality of lower electrodes 504 of the lower electrodes 504 of each light-emitting chip 400, and the second upper electrode 508 may be commonly formed corresponding to the second plurality of lower electrodes 504. In such a configuration, one lower electrode 504 and the region of the light emitting layer 506 and upper electrode 508 corresponding to the lower electrode 504 form one light emitting point (light emitting element) 602 .

[0020] 7 shows a control configuration of the light-emitting chip 400. The data switching unit 705 and each light-emitting chip 400 are connected by a plurality of signal lines (wires). Specifically, the data switching unit 705 and the light-emitting chip 400-n (n is an integer from 1 to 20) are connected by a signal line DATAn and a signal line WRITEn. The signal line DATAn is used by the data switching unit 705 to transmit image data to the light-emitting chip 400-n. The signal line WRITEn is used by the data switching unit 705 to write control data to a register of the light-emitting chip 400-n.

[0021] The data switching unit 705 and all the light-emitting chips 400 are connected by one signal line CLK, one signal line SYNC, and one signal line EN. The signal line CLK is used to transmit a clock signal for transmitting data on the signal lines DATAn and WRITEn. The data switching unit 705 outputs a clock signal generated based on a reference clock signal from the clock generating unit 702 to the signal line CLK. The signals transmitted to the signal lines SYNC and EN will be described later.

[0022] The CPU 701 controls the entire image forming apparatus. The image data generating unit 703 performs various image processing such as halftone processing on image data received from the reading unit 100 or an external device to generate image data for controlling the on / off of light emission of the light-emitting points 602 of each light-emitting chip 400. The image data generating unit 703 transmits the generated image data to a data switching unit 705. The register access unit 704 receives control data to be written to a register in each light-emitting chip 400 from the CPU 701 and transmits it to the data switching unit 705.

[0023] 8 shows signals on each signal line when control data is written to the register of the light-emitting chip 400. An enable signal that is at a high level during communication and indicates that communication is in progress is output to the signal line EN. The data switching unit 705 transmits a start bit to the signal line WRITEn in synchronization with the rising edge of the enable signal. Next, the data switching unit 705 transmits a write identification bit indicating a write operation, and then transmits the address of the register to which the control data is to be written (4 bits in this example) and the control data (8 bits in this example). When writing to the register, the data switching unit 705 sets the frequency of the clock signal transmitted to the signal line CLK to, for example, 3 MHz.

[0024] FIG. 9 shows signals on each signal line when image data is transmitted to each light-emitting chip 400. A periodic line synchronization signal indicating the exposure timing of one line on the photoconductor 102 is output to the signal line SYNC. If the peripheral speed of the photoconductor 102 is 200 mm / s and the resolution in the sub-scanning direction is 1200 dpi (approximately 21.16 μm), the line synchronization signal is output at a period of approximately 105.8 μs. The data switching unit 705 transmits image data to the signal lines DATA1 to DATA20 in synchronization with the rising edge of the line synchronization signal. In this embodiment, since each light-emitting chip 400 has 2992 light-emitting points 602, it is necessary to transmit image data indicating whether each of the total 2992 light-emitting points 602 is emitting or not emitting light to each light-emitting chip 400 within a period of approximately 105.8 μs. In order to transmit image data for a total of 2992 light-emitting points 602 within a period of approximately 105.8 μs, in this example, as shown in FIG. 9, when transmitting image data, the data switching unit 705 sets the frequency of the clock signal to be transmitted to the signal line CLK to 30 MHz.

[0025] FIG. 10 is a functional block diagram of one light-emitting chip 400-n. As also shown in FIG. 5, the light-emitting chip 400 has nine pads 408-1 to 408-9. The pads 408-1 and 408-2 are connected to a power supply voltage VCC by a power supply line. Power is supplied from this power supply voltage VCC to each circuit of the circuit unit 406 of the light-emitting chip 400. The pads 408-3 and 408-4 are connected to the ground by a ground line. Each circuit of the circuit unit 406 and the upper electrode 508 are connected to the ground via the pads 408-3 and 408-4. The signal line CLK is connected to the transfer unit 1003, the register 1102, and the latch units 1004-001 to 748 via the pad 408-5. The signal lines SYNC and DATAn are connected to the transfer unit 1003 via the pads 408-6 and 408-7. The signal lines EN and WRITEn are connected to the register 1102 via the pads 408-8 and 408-9. As described above, control data indicating control information is stored in the register 1102. The control information will be described in detail later.

[0026] The operation of the transfer unit 1003 and latch units 1004-001 to 1004-748 (collectively referred to as the latch unit 1004) will be described below with reference to Fig. 11 to Fig. 14. The transfer unit 1003 receives image data D1, D2, D3, ... D2992, each of which indicates the emission or non-emission of one light-emitting point 602, in this order, in synchronization with the clock signal, starting from a line synchronization signal from the signal line SYNC. Fig. 14(A) shows the state in which the transfer unit 1003 has received image data D1 to D12.

[0027] FIG. 11 is a configuration diagram of the transfer unit 1003. The transfer unit 1003 receives a clock signal from a signal line CLK, a line synchronization signal from a signal line SYNC, and image data from a signal line DATAn. The D flip-flops 1101-1 to 1101-8 operate according to the clock signal. The D flip-flop 1101-1 outputs the image data received from DATAn to a signal line PDATA4 in order. The D flip-flop 1101-2 delays the image data received from DATAn by one clock from the image data output by the D flip-flop 1101-1, and outputs it to a signal line PDATA3. Similarly, the D flip-flops 1101-3 and 1101-4 delay the image data received from DATAn by two clocks and three clocks from the image data output by the D flip-flop 1101-1, and output it to signal lines PDATA2 and PDATA1.

[0028] Fig. 14B shows image data that the transfer unit 1003 outputs to signal lines PDATA1 to PDATA4. As shown in Fig. 14B, at the timing when the transfer unit 1003 outputs image data D4 to the signal line PDATA4, the transfer unit 1003 outputs image data D3, D2, and D1 to the signal lines PDATA3, PDATA2, and PDATA1. More generally, at the timing when the transfer unit 1003 outputs image data D(4m) (m is an integer from 1 to 748) to the signal line PDATA4, the transfer unit 1003 outputs image data D(4m-1), D(4m-2), and D(4m-3) to the signal lines PDATA3, PDATA2, and PDATA1.

[0029] The transfer unit 1003 delays the line synchronization signal by the D flip-flops 1101-5 to 1101-8, and outputs a first latched signal to the signal line LAT1 at the timing when the transfer unit 1003 outputs D4 to the signal line PDATA4.

[0030] FIG. 12 is a configuration diagram of the latch unit 1004-001. The D flip-flops 1202-1 to 1202-4 and the latch circuits 1201-1 to 1201-4 operate according to a clock signal from a signal line CLK. The image data from the signal lines PDATA4 to PDATA1 and the first latch signal from the signal line LAT1 are input to the latch circuits 1201-1 to 1201-4. When the latch circuits 1201-1 to 1201-4 receive the first latch signal from the signal line LAT1, they latch the value output to the signal lines PDATA4 to PDATA1 at that time, and output a drive signal based on the latched value to the signal lines PON1-4 to PON1-1 as shown in FIG. 14(C). According to FIG. 14(C), the signal lines PON1-1 to PON1-4 output drive signals based on the image data D1 to D4. In this embodiment, as described with reference to FIG. 4, one light-emitting chip 400 has a structure in which four sets of 748 light-emitting points 602 arranged in the main scanning direction are arranged in the sub-scanning direction. For example, numbers 1 to 748 are assigned to the light-emitting points 602 of each set along the X direction (corresponding to the main scanning direction) in FIG. 5. In this case, the driving signals output to the signal lines PON1-4 to PON1-1 are driving signals for the first light-emitting point 602 of each of the four sets. The driving signals are input to the current driving unit 1104. The latch unit 1004-001 continues to output driving signals based on the image data D1 to D4 until it receives a first latch signal based on the next line synchronization signal. That is, the driving signals based on the image data D1 to D4 are output only for the period of two consecutive line synchronization signals (about 105.8 μs in this example). Furthermore, the latch unit 1004-001 delays the first latched signal by the D flip-flops 1202-1 to 1202-4, and outputs the second latched signal to the signal line LAT2 at the timing when the transfer unit 1003 outputs D8 to the signal line PDATA4.

[0031] FIG. 13 is a configuration diagram of the latch unit 1004-002. The D flip-flops 1302-1 to 1302-4 and the latch circuits 1301-1 to 1301-4 operate according to a clock signal from a signal line CLK. The latch circuits 1301-1 to 1301-4 receive image data from the signal lines PDATA4 to PDATA1 and a second latch signal from the signal line LAT2. When the latch circuits 1301-1 to 1301-4 receive the second latch signal from the signal line LAT2, they latch the value output to the signal lines PDATA4 to PDATA1 at that time, and output a drive signal based on the latched value to the signal lines PON2-4 to PON2-1 as shown in FIG. 14(D). The driving signals output to the signal lines PON2-4 to PON2-1 are driving signals for the light-emitting points 602 adjacent in the main scanning direction (on the right side in FIG. 5) to the light-emitting points 602 driven by the driving signals output to the signal lines PON1-4 to PON1-1. That is, the driving signals output to the signal lines PON2-4 to PON2-1 are driving signals for the second light-emitting points 602 of each of the four sets. According to FIG. 14(D), the signal lines PON2-1 to PON2-4 output driving signals based on the image data D5 to D8. The driving signals are input to the current driving unit 1104. The latch unit 1004-002 continues to output driving signals based on the image data D5 to D8 until it receives a second latch signal based on the next line synchronization signal. That is, the driving signals based on the image data D5 to D8 are output only for the period of two consecutive line synchronization signals (about 105.8 μs in this example). Furthermore, the latch unit 1004-002 delays the second latched signal by the D flip-flops 1302-1 to 1302-4, and outputs a third latched signal to the signal line LAT3 at the timing when the transfer unit 1003 outputs image data D12 to the signal line PDATA4.

[0032] The operations of the latch units 1004-003 to 1004-748 are similar. In summary, each of the latch units 1004-m (m is an integer from 1 to 748) has four latch circuits. The four latch circuits of the latch unit 1004-m latch image data D(4m), D(4m-1), D(4m-2) and D4(m-3) based on the m-th latch signal, and output a drive signal based on the latched image data to the current drive unit 1104 only during the period of two consecutive line synchronization signals. The four latch circuits of the latch unit 1004-m correspond to the m-th light-emitting point 602 among the 748 light-emitting points 602 arranged along the main scanning direction in each of the first to fourth sets. That is, the four latch circuits of the latch unit 1004-m output a drive signal for the m-th light-emitting point 602 in each of the first to fourth sets. Further, the latch units 1004-m other than m=748 generate the (m+1)th latch signal based on the mth latch signal and output it to the latch unit 1004-(m+1). In this manner, the latch units 1004-001 to 1004-748 each output a drive signal for controlling whether each light-emitting point 602 emits light or not to the current drive unit 1104 only for the period of two consecutive line synchronization signals.

[0033] FIG. 17 shows the relationship between the line synchronization signal of the signal line SYNC, the first and second latch signals of the signals LAT1 and LAT2, and the drive signals output to the signal lines PON1-1 to PON1-4 and PON2-1 to PON2-4. The period of the line synchronization signal is about 105.8 μs as described above. The period of the first and second latch signals is about 105.8 μs, the same as that of the line synchronization signal. The timing of the second latch signal is four clocks later than the first latch signal. More generally, the timing of the q+1th latch signal (q is an integer from 1 to 747) is four clocks later than the qth latch signal.

[0034] The transfer unit 1003 sequentially receives image data D1[1] to D2992[1] in synchronization with the first line synchronization signal in FIG. 17. The transfer unit 1003 sequentially receives image data D1[2] to D2992[2] in synchronization with the second line synchronization signal in FIG. 17. The four latch circuits of the latch unit 1004-001 output drive signals based on image data D1[1] to D4[1] to the signal lines PON1-1 to PON1-4 from the timing of the first latch signal based on the first line synchronization signal in FIG. 17. The output of drive signals based on image data D1[1] to D4[1] continues until the first latch signal based on the second line synchronization signal is received. When the four latch circuits of the latch unit 1004-001 receive the first latch signal based on the second line synchronization signal, they output drive signals based on image data D1[2] to D4[2] to the signal lines PON1-1 to PON1-4. Similarly, the four latch circuits of the latch unit 1004-002 output drive signals based on image data D5[1] to D8[1] to the signal lines PON2-1 to PON2-4 from the timing of the second latch signal based on the first line synchronization signal. The output of drive signals based on image data D5[1] to D8[1] continues until the second latch signal based on the second line synchronization signal is received. When the four latch circuits of the latch unit 1004-002 receive the second latch signal based on the second line synchronization signal, they output drive signals based on image data D5[2] to D8[2] to the signal lines PON2-1 to PON2-4. The same applies to the latch units 1004-003 to 1004-748.

[0035] In this embodiment, the transfer unit 1003 and the latch unit 1004 constitute an output unit that receives image data corresponding to each of the multiple light-emitting points 602 and outputs a drive signal for the corresponding light-emitting point 602 based on the received image data. More specifically, each of the 748 latch units 1004-001 to 1004-748 in this embodiment has four latch circuits, and therefore the output unit has a total of 2992 latch circuits. Each latch circuit corresponds to one of the 2992 light-emitting points 602 included in one light-emitting chip 400. Each latch circuit latches image data of the corresponding light-emitting point 602 and outputs a drive signal for the corresponding light-emitting point 602 based on the latched image data.

[0036] FIG. 15 shows the configuration of the current driving unit 1104. Note that FIG. 15 shows only a circuit portion corresponding to one light-emitting point 602. The light-emitting chip 400 according to this embodiment has a total of 2992 light-emitting points 602, and therefore the light-emitting chip 400 has 2992 circuit portions shown in FIG. 15. The DAC 1501 outputs an analog voltage according to a digital value indicated by the control data stored in the register 1102. The FET 1502 is a Pch MOSFET, and the source terminal is connected to a power supply voltage VCC, and the drain terminal is connected to a source terminal of the FET 1503. The analog voltage output by the DAC 1501 is applied to the gate terminal of the FET 1502. The FET 1503 is also a Pch MOSFET, and the drain terminal is connected to the lower electrode 504. A driving signal output from the image data holding unit 1103 is input to the gate terminal of the FET 1503 via the switching circuit 1504. The drive signal is a binary signal of high level or low level. When the drive signal is at the high level, the FET 1503 is on, and when the drive signal is at the low level, the FET 1503 is off.

[0037] While the FET 1503 is on, a current flows from the power supply voltage VCC through the FET 1502 and FET 1503 to the light emitting layer 506, causing the light emitting points 602 to emit light. The light emission intensity of the light emitting points 602 changes according to the current flowing through the light emitting layer 506, and the value of the current is controlled by the analog voltage output by the DAC 1501. In other words, the light emission intensity of each light emitting point 602 is controlled by the control data stored in the register 1102. Note that the control data may indicate the digital values ​​of the DACs 1501 corresponding to each light emitting point 602 individually, or may indicate one digital value for each group of a plurality of light emitting points 602.

[0038] The switching circuit 1504 is provided to switch between a normal state in which a drive signal is applied to the gate terminal of the FET 1503 and a test state. In the test state, the switching circuit 1504 applies a high-level signal to the gate terminal of the FET 1503 to forcibly turn on the FET 1503. The switching between the normal state and the test state is also performed based on the control data stored in the register 1102. The test state can be used to cause any light-emitting point 602 to emit light during the manufacture of the exposure head 106.

[0039] FIG. 16 is a flowchart of a process executed by the image controller 700 when a print request is received from a user. In S10, the image controller 700 writes control data for setting each switching circuit 1504 to a normal state in the register 1102 of each light-emitting chip 400. In S11, the image controller 700 sets a digital value to be set in the DAC 1501 corresponding to each light-emitting point 602 in the register 1102 of each light-emitting chip 400. Next, when it is time to start image formation, the image controller 700 transmits image data in S12 and starts exposing the photoconductor 102. In S13, the image controller 700 determines whether image formation is complete, and if image formation is not complete, repeats the process from S12. On the other hand, if image formation is complete, the image controller 700 ends the process of FIG. 13.

[0040] When each light-emitting point 602 is made to emit light during manufacturing of the exposure head 106, the image controller 700 first sets in the register 1102 a digital value to be set in the DAC 1501 corresponding to the target light-emitting point 602. After that, the image controller 700 writes in the register 1102 control data for changing the state of the switching circuit 1504 to a test state. After the test is completed, the image controller 700 writes control data for changing the state of the switching circuit 1504 to a normal state. Regarding the light-emitting points 602 to be in the test state, each light-emitting point 602 may be designated independently, or each light-emitting point group including two or more light-emitting points 602 may be designated, for example, all the light-emitting points 602 may be designated collectively.

[0041] As described above, in this embodiment, the latch unit 1004-m latches the image data D(4m), D(4m-1), D(4m-2) and D4(m-3) when the m-th latch signal is input, and outputs a drive signal based on the latched image data to the current drive unit 1104. With this configuration, it is possible to light up a plurality of light-emitting points 602 based on image data transmitted by serial communication without providing a flip-flop circuit for transferring the input image data in the main scanning direction corresponding to the number of light-emitting units. That is, it is possible to prevent the light-emitting chip from becoming larger and the cost of the light-emitting chip from increasing due to the flip-flop circuit for transferring the input image data in the main scanning direction being provided corresponding to the number of light-emitting units. That is, it is possible to prevent the light-emitting chip from becoming larger and the cost from increasing compared to the conventional art.

[0042] In general, the amount of light emitted by an organic EL film is smaller than that of an LED formed of, for example, gallium arsenide. In this embodiment, a drive signal that controls whether each light emitting point 602 emits light is output to the current drive unit 1104 only during the period of two consecutive line synchronization signals. That is, in this embodiment, the light emitting point 602 can be made to emit light during the period of two consecutive line synchronization signals. As a result, the time for exposing the photoconductor 102 can be made longer than in a configuration in which the light emitting point 602 emits light only during a part of the period of two consecutive line synchronization signals. As a result, the photoconductor 102 can be exposed to light for an amount necessary for the toner image to be formed, and the toner image is appropriately formed on the photoconductor 102. That is, it is possible to suppress the photoconductor 102 from not being exposed to light for an amount necessary for the toner image to be formed due to the light emitting point 602 emitting light only during a part of the period of two consecutive line synchronization signals.

[0043] When the FET 1503 is turned on, the voltage of the power supply line fluctuates due to the current output from the power supply VCC being supplied to the light-emitting point 602, and radiation noise may occur from the power supply line. In this embodiment, all of the light-emitting points 602 provided in the light-emitting chip 400 are not turned on at the same time, but the light-emitting points 602 are turned on sequentially in groups of four. As a result, the fluctuation in the voltage of the power supply line is suppressed compared to the case where the FETs 1503 corresponding to the respective light-emitting points 602 are turned on simultaneously to simultaneously light all of the light-emitting points 602 provided in the light-emitting chip 400. As a result, radiation noise generated from the power supply line can be reduced.

[0044] In this embodiment, one light-emitting chip 400 has four sets of 748 light-emitting points 602 arranged along the main scanning direction. Therefore, a total of 2992 latch circuits corresponding to each light-emitting point 602 are grouped into four groups corresponding to the number of sets, resulting in a total of 748 groups, and one latch unit 1004 is provided corresponding to one group. In addition, since one group includes four latch circuits, the transfer unit 1003 transfers image data to four signal lines PDATA1 to PDATA4 in sequence. However, for example, the number of latch circuits included in one group may be an integer multiple of the number of sets. For example, for a light-emitting chip 400 having four sets of 748 light-emitting points 602 arranged along the main scanning direction, if the number of latch circuits included in one group is doubled to the number of sets, the number of groups will be 374, and the number of latch units 1004 will also be 374. In this case, the transfer unit 1003 transfers image data to eight signal lines in sequence. In the present invention, the number of latch circuits included in one group is not limited to an integer multiple of the number of sets, and may be, for example, an integer division of the number of sets. The number of latch circuits included in one group may also be set independent of the number of sets. Furthermore, the number of light-emitting points 602 (or the number of latch circuits) included in each group does not have to be the same. In other words, the number of light-emitting points 602 (or the number of latch circuits) included in each group may be any number equal to or greater than one.

[0045] In the above embodiment, specific numerical values ​​are used for explanation, but these specific numerical values ​​are merely examples, and the present invention is not limited to the specific numerical values ​​used in the embodiment. Specifically, the number of light-emitting chips 400 provided on one printed circuit board 202 is not limited to 20, and can be any number equal to or greater than one. The number of light-emitting points 602 included in each light-emitting chip 400 is not limited to 2992, and can be any other number. In the present embodiment, one light-emitting chip 400 has four sets of 748 light-emitting points arranged along the main scanning direction, but the number of sets can be any number equal to or greater than one. In addition, the light-emitting points 602 are arranged at a pitch of about 21.16 μm corresponding to a resolution of 1200 dpi in the main scanning direction, but the arrangement interval of the light-emitting points 602 may also be another value.

[0046] In the above embodiment, the image forming apparatus transfers the toner images formed on the photoconductors 102 to a sheet transported on the transfer belt 111. However, the image forming apparatus may transfer the toner images on the photoconductors 102 to a sheet via an intermediate transfer body. The image forming apparatus may be a color image forming apparatus that forms an image using toners of multiple colors, or a monochrome image forming apparatus that forms an image using toner of one color.

[0047] [Other embodiments] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0048] The disclosure of this embodiment includes the following configuration. (Configuration 1) An exposure device mounted in an image forming apparatus, A plurality of light emitting elements; an output unit that receives a synchronization signal periodically transmitted from the image forming apparatus and image data corresponding to each of the plurality of light-emitting elements transmitted from the image forming apparatus within the period of the synchronization signal, and outputs a drive signal corresponding to each of the plurality of light-emitting elements for driving the plurality of light-emitting elements; a driving means for driving the plurality of light-emitting elements based on the driving signals corresponding to the plurality of light-emitting elements; One or more light emitting chips having The output means has a plurality of latch circuits corresponding to the plurality of light-emitting elements, for latching the image data corresponding to each of the plurality of light-emitting elements and outputting a drive signal corresponding to each of the plurality of light-emitting elements. (Configuration 2) 2. The exposure device according to configuration 1, wherein the synchronization signal is a signal indicating exposure timing for one line of a photoconductor mounted on the image forming device. (Configuration 3) 3. The exposure apparatus according to configuration 1 or 2, wherein the output unit outputs the drive signal corresponding to each of the plurality of light-emitting elements for a period equal to a cycle of the synchronization signal. (Configuration 4) The image data corresponding to each of the plurality of light-emitting elements is input to the plurality of latch circuits in sequence, The exposure apparatus according to any one of configurations 1 to 3, wherein the output means generates a latch signal corresponding to each of the plurality of latch circuits, the latch signal indicating to each of the plurality of latch circuits the timing for latching the image data, based on the synchronization signal. (Configuration 5) 5. The exposure apparatus according to configuration 4, wherein a period of the latch signal corresponding to each of the plurality of latch circuits is equal to a period of the synchronization signal. (Configuration 6) the plurality of latch circuits are grouped into a plurality of groups, each group including two or more latch circuits; 6. The exposure apparatus according to configuration 4 or 5, wherein the output means generates the latch signals corresponding to the two or more latch circuits included in the same group at the same timing based on the synchronization signal. (Configuration 7) the number of the two or more latch circuits included in each of the plurality of groups is the same; the output means includes a transfer means for receiving the image data corresponding to each of the plurality of light emitting elements, and outputting the image data to each of a plurality of signal lines, the number of which is the same as the number of the two or more latch circuits included in each of the plurality of groups, in sequence; 7. The exposure apparatus according to configuration 6, wherein each of the two or more latch circuits included in each of the plurality of groups receives the image data from one signal line of the plurality of signal lines. (Configuration 8) 8. The exposure apparatus according to configuration 7, wherein the light emitting elements corresponding to the image data output by the transfer means to each of the plurality of signal lines at the same timing are different. (Configuration 9) the plurality of light-emitting elements are two-dimensionally arranged along both a main scanning direction parallel to a rotation axis of a photoconductor mounted in the image forming apparatus and a sub-scanning direction perpendicular to the main scanning direction, 9. The exposure apparatus according to configuration 7 or 8, wherein the number of the two or more latch circuits included in each of the plurality of groups is an integer multiple of the number of light-emitting elements arranged along the sub-scanning direction. (Configuration 10) The light emitting chip further includes a storage means for storing control information; An exposure apparatus described in any one of configurations 1 to 9, wherein the driving means is provided with a switching means for switching, based on the control information, whether to drive a light-emitting element corresponding to the drive signal using the drive signal, or to drive a light-emitting element corresponding to the drive signal regardless of the drive signal. (Configuration 11) 11. The exposure apparatus according to configuration 10, wherein when the control information drives the light-emitting element corresponding to the drive signal regardless of the drive signal, the light-emitting element is caused to emit light. (Configuration 12) 12. The exposure apparatus according to configuration 10 or 11, wherein the control information collectively indicates one or more of the plurality of light-emitting elements that are to be driven without using the drive signal. (Configuration 13) 13. The exposure apparatus according to any one of configurations 1 to 12, wherein the plurality of light-emitting elements include an organic EL film. (Configuration 14) A photoconductor; An exposure device according to any one of configurations 1 to 13 for exposing the photoconductor; An image forming apparatus comprising:

[0049] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0050] 602: light emitting point, 1003: transfer section, 1004-001 to 1004-748: latch section

Claims

1. An exposure device for exposing a photoconductor, comprising: A long substrate; a light-emitting chip including a plurality of light-emitting elements mounted on the substrate and arranged along a longitudinal direction of the substrate, a driving unit that drives the plurality of light-emitting elements, and a receiving unit that receives image data that controls lighting of the plurality of light-emitting elements; Equipped with The receiving unit receives the image data as serial data, converts the image data received as serial data into parallel data, and outputs the parallel data. An exposure apparatus comprising:

2. The light-emitting chip further includes an output unit that outputs a drive signal for driving the plurality of light-emitting elements based on the image data, The driving section drives the plurality of light-emitting elements based on the driving signal, the output unit includes a latch circuit for latching the image data and outputting the drive signal; 2. The exposure apparatus according to claim 1.

3. The output unit outputs the drive signal based on the image data, which is parallel data output by the receiving unit.

3. The exposure apparatus according to claim 2.

4. The exposure apparatus periodically receives a synchronization signal; the receiving unit receives the image data, which is serial data, within a period of the synchronization signal.

3. The exposure apparatus according to claim 2.

5. The synchronization signal is a signal indicating the exposure timing of one line in the direction of the rotation axis of the photosensitive body.

5. The exposure apparatus according to claim 4.

6. The output unit outputs the drive signal for a period equal to a cycle of the synchronization signal.

5. The exposure apparatus according to claim 4.

7. The plurality of light-emitting elements include an organic electroluminescent (EL) light-emitting film.

2. The exposure apparatus according to claim 1.

8. A photoconductor; An exposure device according to claim 1 that exposes the photoconductor; An image forming apparatus comprising:

Images