A / d conversion control circuit

Abstract

To execute high-speed A / D conversion processing.SOLUTION: An A / D conversion control circuit comprises: a scan group control unit for controlling a plurality of A / D conversion channels in a plurality of groups where the priorities are different; and a FIFO unit including FIFOs which are provided corresponding to the plurality of groups and in each of which output from the control unit is stored on a corresponding group basis. The control unit includes: an input receiving section ISG by which an A / D conversion channel of a corresponding group in the plurality of A / D conversion channels is received in accordance with an instruction and outputted to a corresponding FIFO; and an arbitration section for determining the timing of conversion start, interruption and resumption in each of the plurality of groups. The FIFO unit includes a plurality of pointer control sections provided corresponding to the plurality of FIFOs. Each pointer control section clears or changes a position of a write / read pointer of the corresponding FIFO in the timing of any one of start, interruption and resumption of the corresponding group in accordance with the priority of the group.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to A / D conversion processing for converting an analog signal into a digital signal. [Background technology]

[0002] One example of a semiconductor integrated circuit device is a microcontroller unit for controlling an automobile engine. As each generation of microcontroller units for controlling an automobile engine advances, they are required to convert analog information from many sensors at high speed.

[0003] In this regard, a method has been disclosed in which analog information from a sensor is divided into scan groups and efficiently converted (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2013-179568 A Summary of the Invention [Problem to be solved by the invention]

[0005] On the other hand, when analog / digital conversion is performed for each scan group, if a certain analog / digital conversion process is interrupted according to priority, the conversion results of the interrupted channel remain. Since it takes time to delete the remaining data, this poses an issue in terms of high-speed A / D conversion processing.

[0006] The present disclosure has been made to solve the above problems, and provides an A / D conversion control circuit capable of high-speed A / D conversion processing.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] The A / D conversion control circuit of the present disclosure includes a scan group control unit that controls a plurality of AD conversion channels in a plurality of scan groups with different priorities, and a FIFO unit that is provided corresponding to each of the plurality of scan groups and has a plurality of FIFO memories that sequentially store the output from the scan group control unit for each of the corresponding scan groups. The scan group control unit includes an input receiving unit that receives an AD conversion channel of a corresponding scan group among the plurality of AD conversion channels according to an instruction and outputs the input to the corresponding FIFO memory, and an arbitration unit that determines the timing of conversion start, interruption, and restart in each of the plurality of scan groups. The FIFO unit further includes a plurality of pointer control units that are provided corresponding to each of the plurality of FIFO memories. Each pointer control unit clears or changes the position of the write pointer / read pointer of the corresponding FIFO memory at least at the timing of start, interruption, and restart of the corresponding scan group according to the priority of the scan group. Effect of the Invention

[0009] The A / D conversion control circuit of the present disclosure includes a pointer control unit, which is capable of clearing or changing the position of the write pointer / read pointer of the corresponding FIFO memory at least at the timing of starting, interrupting, and resuming the corresponding scan group in accordance with the priority of the corresponding scan group, thereby enabling high-speed A / D conversion processing. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a data processing system 10 according to a first embodiment. [Diagram 2] 1 is a diagram illustrating a configuration of an A / D conversion control circuit 125 according to the first embodiment. FIG. [Diagram 3] 10 is a diagram illustrating a determination signal from an arbitration unit 110 according to the first embodiment. FIG. [Figure 4] 2 is a diagram illustrating a configuration of a pointer control unit PCTn according to the first embodiment. FIG. [Diagram 5] FIG. 2 is a diagram illustrating a scan group according to the first embodiment. [Figure 6] 11A and 11B are diagrams illustrating interrupt processing of a high-priority scan group according to a comparative example. [Figure 7] 13 is a diagram illustrating a FIFO memory M1 in processing an interrupt of a high-priority scan group according to a comparative example. FIG. [Figure 8] 11A and 11B are diagrams illustrating reading from a FIFO memory according to a comparative example. [Figure 9] FIG. 11 is a flowchart illustrating a process flow of AD conversion according to a comparative example. [Figure 10] FIG. 11 is a diagram illustrating interrupt processing of a high-priority scan group according to the first embodiment. [Figure 11] 11 is a diagram illustrating a FIFO memory M1 in processing an interrupt of a high-priority scan group according to the first embodiment. FIG. [Figure 12] 10 is a diagram illustrating reading from a FIFO memory according to the first embodiment. FIG. [Figure 13] FIG. 4 is a flowchart illustrating a process flow of AD conversion according to the first embodiment. [Figure 14] FIG. 11 is a diagram illustrating a configuration of an A / D conversion control circuit 125# according to a second embodiment. [Figure 15] FIG. 11 is a diagram illustrating a configuration of a pointer control unit PCT#n according to the second embodiment. [Figure 16] FIG. 11 is a diagram illustrating interrupt processing for a high-priority scan group according to the second embodiment. [Figure 17] 13 is a diagram illustrating a FIFO memory M1 in processing an interrupt of a high-priority scan group according to the second embodiment. FIG. [Figure 18] FIG. 11 is a flowchart illustrating a process flow of AD conversion according to the second embodiment. [Figure 19]FIG. 11 is a diagram for explaining a first application example. [Figure 20] FIG. 11 is a diagram for explaining a second application example. [Figure 21] FIG. 11 is a diagram for explaining a third application example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The embodiments will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference characters, and the description thereof will not be repeated.

[0012] (Embodiment 1) FIG. 1 is a diagram illustrating a data processing system 10 according to the first embodiment.

[0013] 1, a data processing system 10 includes a semiconductor integrated circuit device 11 capable of processing analog signals. A microcontrol unit (MCU) 11, which is an example of the semiconductor integrated circuit device, will be described.

[0014] The MCU 11 includes a plurality of analog ports 111 (AN0 to ANn) and an A / D conversion circuit 118 that executes A / D conversion processing for converting analog signals received via the analog ports into digital signals. The MCU 11 also includes an A / D conversion control circuit 125 that controls the operation of the A / D conversion circuit, and a selector 117 that selects analog signals from the plurality of analog ports 111 in accordance with instructions from the A / D conversion control circuit 125.

[0015] The MCU 11 also includes a CPU (Central Processing Unit) 120, an internal RAM (Random Access Memory) 121, and a DMAC (Direct Memory Access Controller) 122. The CPU 120, the internal RAM 121, and the DMAC 122 are coupled to each other via an internal bus 124 so as to be able to exchange signals with each other. A peripheral bus 123 is coupled to the internal bus 124. An A / D conversion control circuit 125 is coupled to this peripheral bus 123.

[0016] The CPU 120 performs overall operational control of the MCU 11 in accordance with a preset program. The internal RAM 121 is used as a work area for the arithmetic processing in the CPU 120. The DMAC 122 controls data transfer that is performed directly without going through the CPU 120. The selector 117 selects and outputs the analog signals captured via the analog ports 111 (AN0 to ANn), respectively.

[0017] The A / D conversion circuit 118 converts the analog signal selected by the selector 117 into a digital signal.

[0018] The A / D conversion control circuit 125 controls the selection operation of the selector 117 and the A / D conversion operation of the A / D conversion circuit 118 .

[0019] FIG. 2 is a diagram illustrating a configuration of the A / D conversion control circuit 125 according to the first embodiment.

[0020] With reference to FIG. 2, A / D conversion control circuit 125 includes a scan group control unit 127 and a FIFO unit 129.

[0021] The scan group control unit 127 controls a plurality of AD conversion channels into a plurality of scan groups having different priorities.

[0022] The FIFO units 129 are provided corresponding to the multiple scan groups SG0 to SG2 (collectively referred to as scan groups SG), respectively, and each has a multiple number of FIFO memories M0 to M2 (collectively referred to as FIFO memories M) that store the output from the scan group control unit 127 in order for each corresponding scan group SG.

[0023] The scan group control unit 127 includes input receiving units ISG0 to ISG2 (also referred to as input receiving unit ISG) that receive an AD conversion channel of a corresponding scan group SG among the multiple AD conversion channels in accordance with an instruction and output it to a corresponding FIFO memory M, and an arbitration unit 110 that determines the timing of starting, interrupting, and resuming conversion in each of the multiple scan groups.

[0024] The input reception unit ISG receives an AD conversion channel of the corresponding scan group SG and outputs the conversion result to the corresponding FIFO memory M of the FIFO unit 129, and also receives input of various control signals.

[0025] Specifically, the input reception unit ISG0 receives a conversion start trigger signal for the scan group SG0 from the CPU 120 in response to the scan group SG0. The input reception unit ISG0 outputs a control signal SGACT0 to the arbitration unit 110 in response to the input of the conversion start trigger signal for the scan group SG0. The input reception unit ISG0 also outputs information on the rising and falling edges of the control signal SGACT0 to the arbitration unit 110. The control signal SGACT0 is set to "1" from the first to the final AD conversion channel for the scan group SG0. In all other cases, the control signal SGACT0 is 0.

[0026] In this example, a case will be described in which a conversion start trigger signal is output from CPU 120 as an example, but this is not limited to this, and the signal may be input from outside together with the analog signal input to analog port 111 (AN0 to ANn).

[0027] Similarly, the input reception unit ISG1 receives a conversion start trigger signal for the scan group SG1 from the CPU 120 in response to the scan group SG1. The input reception unit ISG1 outputs a control signal SGACT1 to the arbitration unit 110 in response to the input of the conversion start trigger signal for the scan group SG1. The input reception unit ISG1 also outputs information on the rising and falling edges of the control signal SGACT1 to the arbitration unit 110. The control signal SGACT1 is set to "1" from the first to the final AD conversion channel for the scan group SG1. In all other cases, the control signal SGACT1 is 0.

[0028] Similarly, the input reception unit ISG2 receives a conversion start trigger signal for the scan group SG2 from the CPU 120 in response to the scan group SG2. The input reception unit ISG2 outputs a control signal SGACT2 to the arbitration unit 110 in response to the input of the conversion start trigger signal for the scan group SG2. The input reception unit ISG2 also outputs information on the rising and falling edges of the control signal SGACT2 to the arbitration unit 110. The control signal SGACT2 is set to "1" from the first to the final AD conversion channel for the scan group SG2. In all other cases, the control signal SGACT2 is 0.

[0029] The arbitration unit 110 determines the timings for starting, suspending, and restarting conversion for the scan groups SG0-SG2 based on the control signals SGACT0-SGACT2 and information on the rising and falling edges of the control signals SGACT0-SGACT2, and outputs determination signals SGA0-SGA2, SGB0-SGB2, and SGC0-SGC2, respectively.

[0030] The FIFO unit 129 includes write pointer control units WP0-WP2 (also collectively referred to as write pointer control units WP) that are provided corresponding to the FIFO memories M0-M2 and control writing to the FIFO memories M0-M2, respectively. The FIFO unit 129 includes read pointer control units RP0-RP2 (also collectively referred to as read pointer control units RP) that are provided corresponding to the FIFO memories M0-M2 and control reading from the FIFO memories M0-M2, respectively. The FIFO unit 129 includes pointer control units PCT0-PCT2 (also referred to as pointer control units PCT) that are provided corresponding to the FIFO memories M0-M2, respectively, and control the write pointer control units WP0-WP2 and the read pointer control units RP0-RP2.

[0031] Based on the inputs of the determination signals SGA0, SGB0, SGC0 and the clear timing selection signal from the arbitration unit 110, the pointer control unit PCT0 outputs a clear pointer position command signal and a pointer change timing signal to the write pointer control unit WP0 and the read pointer control unit RP0.

[0032] Based on the inputs of the determination signals SGA1, SGB1, SGC1 and the clear timing selection signal from the arbitration unit 110, the pointer control unit PCT1 outputs a clear pointer position command signal and a pointer change timing signal to the write pointer control unit WP1 and the read pointer control unit RP1.

[0033] Based on the inputs of the determination signals SGA2, SGB2, SGC2 and the clear timing selection signal from the arbitration unit 110, the pointer control unit PCT2 outputs a clear pointer position command signal and a pointer change timing signal to the write pointer control unit WP2 and the read pointer control unit RP2.

[0034] FIG. 3 is a diagram illustrating a determination signal from the arbitration unit 110 according to the first embodiment.

[0035] With reference to FIG. 3, in this example, a case will be described in which scan group SG0 has the highest priority, scan group SG1 has the next highest priority, and scan group SG2 has the lowest priority.

[0036] The arbitration unit 110 outputs a determination signal SGA0 indicating the timing of starting conversion of the scan group SG0 to the pointer control unit PCT0 of the FIFO unit 129 in response to the rising edge of the control signal SGACT0. In this example, the scan group SG0 has a high priority and is therefore not suspended or resumed. Therefore, the determination signals SGB0 and SGC0 are not output.

[0037] Next, the arbitration unit 110 outputs a determination signal SGA1 indicating the timing of starting conversion of the scan group SG1 to the pointer control unit PCT1 of the FIFO unit 129 in response to the rise of the control signal SGACT1 while the control signal SGACT0 is 0.

[0038] Furthermore, the arbitration unit 110 outputs a determination signal SGB1 indicating the timing of interrupting the scan group SG1 to the pointer control unit PCT1 of the FIFO unit 129 in response to the rise of the control signal SGACT0 when the control signal SGACT1 is 1.

[0039] Furthermore, the arbitration unit 110 outputs a determination signal SGC1 indicating the timing for restarting the scan group SG1 to the pointer control unit PCT1 of the FIFO unit 129 in response to the falling edge of the control signal SGACT0 when the control signal SGACT1 is 1.

[0040] Next, when the control signals SGACT0 and SGACT1 are 0, the arbitration unit 110 outputs a determination signal SGA2 indicating the timing to start conversion of the scan group SG2 to the pointer control unit PCT1 of the FIFO unit 129 in response to the rise of the control signal SGACT2.

[0041] Furthermore, the arbitration unit 110 outputs a determination signal SGB2 indicating the timing of interrupting the scan group SG2 to the pointer control unit PCT2 of the FIFO unit 129 when the control signal SGACT2 is 1, the control signal SGACT1 is 0, and the rise of the control signal SGACT0.

[0042] Furthermore, the arbitration unit 110 outputs a determination signal SGB2 indicating the timing of interrupting the scan group SG2 to the pointer control unit PCT2 of the FIFO unit 129 when the control signal SGACT2 is 1, the control signal SGACT0 is 0, and the rise of the control signal SGACT1.

[0043] Furthermore, the arbitration unit 110 outputs a determination signal SGC2 indicating the timing to restart scan group SG2 to the pointer control unit PCT2 of the FIFO unit 129 when the control signal SGACT2 is 1, the control signal SGACT0 is 0, and the control signal SGACT1 falls.

[0044] Furthermore, the arbitration unit 110 outputs a determination signal SGC2 indicating the timing to restart scan group SG2 to the pointer control unit PCT2 of the FIFO unit 129 when the control signal SGACT2 is 1, the control signal SGACT1 is 0, and the control signal SGACT0 falls.

[0045] FIG. 4 is a diagram illustrating the configuration of the pointer control unit PCTn according to the first embodiment.

[0046] 4, the pointer control unit PCTn includes a selector SL that receives the input of the determination signals SGAn, SGBn, and SGCn and selects according to the clear timing selection signal. n can take any value. In this example, n is in the range of 0 to 2.

[0047] The clear timing selection signal is output based on information stored in the clear timing selection register 128. As an example, the clear timing selection register 128 is configured with three bits corresponding to start, interruption, and restart of the clear timing. Note that, although the example has been described with a three-bit configuration, the present invention is not limited to this, and any number of bits may be used as long as they are multiple bits capable of indicating each of the relevant states.

[0048] When any bit of the clear timing selection register 128 is set, a clear timing selection signal ("1") is output to the selector SL.

[0049] For example, when "1" is set in the bit corresponding to the start of the clear timing selection register 128, the selector SL outputs the determination signal SGAn to the write pointer control unit WPn and the read pointer control unit RPn as a pointer change timing signal.

[0050] In this case, at the timing when conversion of the scan group SGn starts, the write pointer control unit WPn and the read pointer control unit RPn set the pointer to the clear pointer position ("0").

[0051] Similarly, for example, when the bit corresponding to the interruption of the clear timing selection register 128 is set to "1", the selector SL outputs the determination signal SGBn to the write pointer control unit WPn and the read pointer control unit RPn as a pointer change timing signal.

[0052] In this case, at the timing when the scan group SGn is suspended, the write pointer control unit WPn and the read pointer control unit RPn set the pointer to the clear pointer position ("0").

[0053] Similarly, for example, when the bit corresponding to restart in the clear timing selection register 128 is set to "1", the selector SL outputs the determination signal SGCn to the write pointer control unit WPn and the read pointer control unit RPn as a pointer change timing signal.

[0054] In this case, at the timing when the scan group SGn is restarted, the write pointer control unit WPn and the read pointer control unit RPn set the pointer to the clear pointer position ("0").

[0055] FIG. 5 is a diagram illustrating a scan group according to the first embodiment.

[0056] 5, in this example, scan groups SG0 to SG2 are provided. AD conversion channels CH0 to CH2 are assigned to scan group SG0. AD conversion channels CH4 to CH7 are assigned to scan group SG1. AD conversion channels CH10 to CH12 are assigned to scan group SG2.

[0057] AD conversion is performed for each scan group SG. Scan group SG0 has the highest priority, followed by scan group SG1, and then scan group SG2.

[0058] Therefore, AD conversion of scan group SG0 may interrupt AD conversion of scan group SG1.

[0059] (Comparative Example) In the comparative example, a configuration in which the pointer control unit PCT is not provided will be described. That is, in the comparative example, the timing for clearing the FIFO memory will be described when the memory is full and when reading is performed.

[0060] FIG. 6 is a diagram illustrating interrupt processing of a high-priority scan group according to a comparative example.

[0061] With reference to FIG. 6, in this example, scan groups SG0 and SG1 will be described.

[0062] At time T1, a conversion start trigger for the scan group SG1 is input, and the AD conversion channels of the scan group SG1 are sequentially input to the input reception unit ISG1. The input reception unit ISG1 sets a control signal SGACT1 to 1.

[0063] In this example, the AD conversion channels CH4 to CH6 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0064] Then, at time T2, which is midway through the timing at which the input reception unit ISG1 receives the AD conversion channel CH7, a conversion start trigger for the scan group SG0 is input. This causes the input reception unit ISG0 to set the control signal SGACT0 to 1. Then, the AD conversion of the scan group SG1 is interrupted. The input reception unit ISG0 then receives the AD conversion channels CH0 to CH2 of the scan group SG0 and stores them sequentially in the FIFO memory M0.

[0065] Next, at time T3, the input reception unit ISG0 receives a notification that conversion has ended for the final AD conversion channel CH2 of the scan group SG0. This sets the control signal SGACT0 to 0. Then, AD conversion for the scan group SG1 is resumed.

[0066] In this example, the AD conversion channels CH4 to CH5 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0067] Then, at time T4, which is midway through the timing at which the input reception unit ISG1 receives the AD conversion channel CH6, a conversion start trigger for the scan group SG0 is input. This causes the input reception unit ISG0 to set the control signal SGACT0 to 1. Then, the AD conversion of the scan group SG1 is interrupted. The input reception unit ISG0 then receives the AD conversion channels CH0 to CH2 of the scan group SG0 and stores them sequentially in the FIFO memory M0.

[0068] Next, at time T5, the input reception unit ISG0 receives a notification that conversion has ended for the final AD conversion channel CH2 of the scan group SG0. This sets the control signal SGACT0 to 0. Then, AD conversion for the scan group SG1 is resumed.

[0069] In this example, the AD conversion channels CH4 to CH7 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0070] At time T6, the FIFO memory M1 is in a full state. In this case, it is necessary to temporarily save the data in the FIFO memory M1 to secure a storage area. At time T7, the last AD conversion channel CH7 is stored in the FIFO memory M1, and the AD conversion of the scan group SG1 is completed. As a result, the control signal SGACT1 is set to 0.

[0071] Next, at time T8, a conversion start trigger for the scan group SG1 is input, and the AD conversion channels of the scan group SG1 are sequentially input to the input reception unit ISG1. The input reception unit ISG1 sets the control signal SGACT1 to 1.

[0072] In this example, the AD conversion channels CH4 to CH5 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0073] Then, at time T9, which is midway between when the input reception unit ISG1 receives the AD conversion channel CH6, a conversion start trigger for the scan group SG0 is input. This causes the input reception unit ISG0 to set the control signal SGACT0 to 1. Then, the AD conversion of the scan group SG1 is interrupted. The input reception unit ISG0 then receives the AD conversion channels CH0 to CH2 of the scan group SG0 and stores them sequentially in the FIFO memory M0.

[0074] Next, at time T10, the input reception unit ISG0 receives a notification that conversion has ended for the final AD conversion channel CH2 of the scan group SG0. This sets the control signal SGACT0 to 0. Then, AD conversion for the scan group SG1 is resumed.

[0075] In this example, the AD conversion channels CH4 to CH7 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0076] Then, at time T11, the final AD conversion channel CH7 is stored in the FIFO memory M1, and AD conversion of the scan group SG1 is completed. As a result, the control signal SGACT1 is set to 0.

[0077] FIG. 7 is a diagram illustrating the FIFO memory M1 in processing an interrupt for a high-priority scan group according to a comparative example.

[0078] With reference to FIG. 7(A), in this example, it is assumed that the FIFO memory M1 is provided with eight stages of storage areas.

[0079] At time T6, the FIFO memory M1 is full due to the data remaining after the interruption. In this case, from the top, the first stored AD conversion channels CH4 to CH6 and the next stored AD conversion channels CH4 and CH5 are unnecessary data. The last stored AD conversion channels CH4 to CH6 need to be temporarily saved.

[0080] 7B, a case is shown in which after all the data in the FIFO memory M1 is read out, the AD conversion channel CH7 is stored, whereby it is possible to obtain a data set of the AD conversion channels CH4 to CH7 of the scan group SG1.

[0081] Referring to FIG. 7(C), a case is shown in which a data set of AD conversion channels CH4 to CH7 of scan group SG1 is acquired at time T11.

[0082] In this case as well, the data from the first AD conversion channels CH4 and CH5 is unnecessary due to the interruption process.

[0083] FIG. 8 is a diagram illustrating reading from a FIFO memory according to a comparative example.

[0084] Referring to FIG. 8, a read process is executed for the FIFO memory Mn (step S100).

[0085] Next, the read channel number is obtained (step S102).

[0086] Next, it is determined based on the obtained channel number whether or not the last channel is to be read (step S104).

[0087] If it is determined in step S104 that the final channel is to be read (YES in step S104), data from the first channel to the final channel, including the temporarily saved data, is obtained (step S108).

[0088] Then, unnecessary data is deleted (step S112).

[0089] Then, the process ends (END).

[0090] On the other hand, if it is determined in step S104 that the last channel is not being read (NO in step S104), it is determined whether the FIFO memory Mn is empty (step S106).

[0091] If it is determined in step S106 that the FIFO memory Mn is not empty (NO in step S106), the process returns to step S100 and the above processing is repeated.

[0092] If it is determined in step S106 that the FIFO memory Mn is empty, only the latest data of each channel is temporarily saved (step S110).

[0093] Next, unnecessary data is deleted (step S112).

[0094] Then, the process ends (END).

[0095] FIG. 9 is a flow diagram illustrating a process flow of AD conversion according to the comparative example.

[0096] Referring to FIG. 9, AD conversion of scan group SG1 is started (step ST1). Next, AD conversion of AD conversion channels CH4 to CH6 is completed (step ST2). The number of data in FIFO memory M1 is 3. Next, AD conversion of scan group SG0 is started (step ST3). This causes AD conversion of scan group SG1 to be interrupted. Next, AD conversion of scan group SG0 is completed (step ST4). Next, AD conversion of scan group SG1 is resumed (step ST5). Next, AD conversion of AD conversion channels CH4 and CH5 is completed (step ST6). The number of data in FIFO memory M1 is 5.

[0097] Next, AD conversion of scan group SG0 is started (step ST7). This causes AD conversion of scan group SG1 to be interrupted. Next, AD conversion of scan group SG0 is completed (step ST8). Next, AD conversion of scan group SG1 is resumed (step ST9). Next, AD conversion of AD conversion channels CH4 to CH6 is completed (step ST10). The number of data in FIFO memory M1 is 8. This causes FIFO memory M1 to become full.

[0098] Next, the full state of the FIFO memory M1 is detected and the data in the FIFO memory M1 is read (step ST11), whereby the number of data in the FIFO memory M1 becomes 0.

[0099] Next, the unnecessary data that has been read out is deleted (step ST12). Next, AD conversion of AD conversion channel CH7 is completed (step ST13). Next, AD conversion of scan group SG1 is completed (step ST14). Next, the completion of AD conversion of scan group SG1 is detected, and data in FIFO memory M1 is read (step ST15). As a result, the number of data in FIFO memory M1 becomes 0.

[0100] Next, AD conversion of scan group SG1 is started (step ST16). Next, AD conversion of AD conversion channels CH4 and CH5 is completed (step ST17). The number of data in FIFO memory M1 is 2. Next, AD conversion of scan group SG0 is started (step ST18). This causes the AD conversion of scan group SG1 to be interrupted. Next, AD conversion of scan group SG0 is completed (step ST19).

[0101] Next, AD conversion of scan group SG1 is resumed (step ST20). Next, AD conversion of AD conversion channels CH4 to CH7 is completed (step ST21). The number of data in FIFO memory M1 is 6. Next, AD conversion of scan group SG1 is completed (step ST22). Next, the completion of AD conversion of scan group SG1 is detected, and the data in FIFO memory M1 is read (step ST23). As a result, the number of data in FIFO memory M1 becomes 0. Next, the unnecessary data that was read is deleted (step ST24).

[0102] When scan group SG1 is interrupted by scan group SG0 and AD conversion channels are stored in 8-stage FIFO memory M1, the conversion results before scan group SG1 was interrupted remain in FIFO memory M1. When scan group SG0 finishes conversion, scan group SG1 resumes conversion from the first channel, so if scan group SG0 is interrupted continuously, the FIFO memory will become full. This requires software to read the data and delete unnecessary data.

[0103] This process posed a challenge in terms of high-speed A / D conversion.

[0104] (Example) In the embodiment, a method is described in which the pointer control unit PCT clears the FIFO memory at least at the timing of the start, interruption, and restart of a scan group. As an example, a case is described in which the bit corresponding to restart in the clear timing selection register 128 is set to "1". In this case, at the timing of restart of the scan group SG1, the write pointer control unit WP1 and the read pointer control unit RP1 set the pointer to the clear pointer position ("0").

[0105] FIG. 10 is a diagram illustrating interrupt processing for a high-priority scan group according to the first embodiment.

[0106] With reference to FIG. 10, in this example, scan groups SG0 and SG1 will be described.

[0107] At time T21, a conversion start trigger for the scan group SG1 is input, and the AD conversion channels of the scan group SG1 are sequentially input to the input reception unit ISG1. The input reception unit ISG1 sets a control signal SGACT1 to 1.

[0108] In this example, the AD conversion channels CH4 to CH6 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0109] Then, at time T22, which is midway through the timing at which the input reception unit ISG1 receives the AD conversion channel CH7, a conversion start trigger for the scan group SG0 is input. This causes the input reception unit ISG0 to set the control signal SGACT0 to 1. Then, the AD conversion of the scan group SG1 is interrupted. The input reception unit ISG0 then receives the AD conversion channels CH0 to CH2 of the scan group SG0 and stores them sequentially in the FIFO memory M0.

[0110] Next, at time T23, the input reception unit ISG0 receives the end of conversion of the final AD conversion channel CH2 of the scan group SG0. As a result, the control signal SGACT0 is set to 0. Then, as AD conversion of the scan group SG1 is resumed, the determination signal SGC1 is set to "1." As a result, the write pointer control unit WP1 and the read pointer control unit RP1 set the pointers to the clear pointer position ("0").

[0111] In this example, the AD conversion channels CH4 to CH5 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0112] Then, at time T24, which is halfway through the timing at which the input reception unit ISG1 receives the AD conversion channel CH6, a conversion start trigger for the scan group SG0 is input. This causes the input reception unit ISG0 to set the control signal SGACT0 to 1. Then, the AD conversion of the scan group SG1 is interrupted. The input reception unit ISG0 then receives the AD conversion channels CH0 to CH2 of the scan group SG0 and stores them sequentially in the FIFO memory M0.

[0113] Next, at time T25, the input reception unit ISG0 receives the end of conversion of the final AD conversion channel CH2 of the scan group SG0. As a result, the control signal SGACT0 is set to 0. Then, as AD conversion of the scan group SG1 is resumed, the determination signal SGC1 is set to "1." As a result, the write pointer control unit WP1 and the read pointer control unit RP1 set the pointers to the clear pointer position ("0").

[0114] In this example, the AD conversion channels CH4 to CH7 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0115] Then, at time T26, the final AD conversion channel CH7 is stored in the FIFO memory M1, and AD conversion of the scan group SG1 is completed. As a result, the control signal SGACT1 is set to 0.

[0116] Next, at time T28, a conversion start trigger for the scan group SG1 is input, and the AD conversion channels of the scan group SG1 are sequentially input to the input reception unit ISG1. The input reception unit ISG1 sets the control signal SGACT1 to 1.

[0117] In this example, the AD conversion channels CH4 to CH5 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0118] Then, at time T29, which is midway between when the input reception unit ISG1 receives the AD conversion channel CH6, a conversion start trigger for the scan group SG0 is input. This causes the input reception unit ISG0 to set the control signal SGACT0 to 1. Then, the AD conversion of the scan group SG1 is interrupted. The input reception unit ISG0 then receives the AD conversion channels CH0 to CH2 of the scan group SG0 and stores them sequentially in the FIFO memory M0.

[0119] Next, at time T30, the input reception unit ISG0 receives the end of conversion of the final AD conversion channel CH2 of the scan group SG0. As a result, the control signal SGACT0 is set to 0. Then, as AD conversion of the scan group SG1 is resumed, the determination signal SGC1 is set to "1." As a result, the write pointer control unit WP1 and the read pointer control unit RP1 set the pointers to the clear pointer position ("0").

[0120] In this example, the AD conversion channels CH4 to CH7 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0121] Then, at time T31, the final AD conversion channel CH7 is stored in the FIFO memory M1, and AD conversion of the scan group SG1 is completed. As a result, the control signal SGACT1 is set to 0.

[0122] FIG. 11 is a diagram illustrating the FIFO memory M1 in processing an interrupt for a high-priority scan group according to the first embodiment.

[0123] With reference to FIG. 11(A), in this example, it is assumed that the FIFO memory M1 is provided with eight stages of storage areas.

[0124] At time T26, the FIFO memory M1 stores data from the AD conversion channels CH4 to CH7. The FIFO memory M1 has been cleared twice during restart before this state was reached.

[0125] 11B, a case is shown in which the AD conversion channels CH4 to CH7 are stored at time T31. Before this state was reached, the FIFO memory M1 was cleared at the time of restart.

[0126] In this example, the FIFO memory M1 is cleared when restarting, so no unnecessary data remains, and the FIFO memory M1 will not become full due to unnecessary data remaining therein.

[0127] FIG. 12 is a diagram illustrating reading from the FIFO memory according to the first embodiment.

[0128] 12, a read process of the FIFO memory Mn is executed (step S100). The read process of the FIFO memory Mn is executed after the last AD conversion of the scan group SGn is completed and the last AD conversion channel CH is stored.

[0129] Next, the read channel number is obtained (step S102).

[0130] Next, it is determined based on the obtained channel number whether or not the last channel is to be read (step S104).

[0131] If it is determined in step S104 that the final channel is to be read (YES in step S104), data from the first channel to the final channel is obtained (step S105).

[0132] Then, the process ends (END).

[0133] On the other hand, if it is determined in step S104 that the last channel is not being read (NO in step S104), it is determined whether the FIFO memory Mn is empty (step S106).

[0134] If it is determined in step S106 that the FIFO memory Mn is not empty (NO in step S106), the process returns to step S100 and the above processing is repeated.

[0135] If it is determined in step S106 that the FIFO memory Mn is empty, the process ends (END).

[0136] FIG. 13 is a flowchart illustrating a process flow of AD conversion according to the first embodiment.

[0137] Referring to FIG. 13, AD conversion of scan group SG1 is started (step ST31). Next, AD conversion of AD conversion channels CH4 to CH6 is completed (step ST32). The number of data in FIFO memory M1 is 3. Next, AD conversion of scan group SG0 is started (step ST33). This causes AD conversion of scan group SG1 to be interrupted. Next, AD conversion of scan group SG0 is completed (step ST34). Next, AD conversion of scan group SG1 is resumed (step ST35). At this time, the pointer is set to the clear pointer position ("0"), so that the number of data in FIFO memory M1 becomes 0. Next, AD conversion of AD conversion channels CH4 and CH5 is completed (step ST36). The number of data in FIFO memory M1 is 2.

[0138] Next, AD conversion of scan group SG0 is started (step ST37). This causes AD conversion of scan group SG1 to be interrupted. Next, AD conversion of scan group SG0 is completed (step ST38). Next, AD conversion of scan group SG1 is resumed (step ST39). At this time, the pointer is set to the clear pointer position ("0"), so the number of data in FIFO memory M1 becomes 0.

[0139] Next, AD conversion of AD conversion channels CH4 to CH7 is completed (step ST40). Next, AD conversion of scan group SG1 is completed (step ST41). Next, the completion of AD conversion of scan group SG1 is detected, and data in FIFO memory M1 is read (step ST42). As a result, the number of data in FIFO memory M1 becomes 0.

[0140] Next, AD conversion of scan group SG1 is started (step ST43). Next, AD conversion of AD conversion channels CH4 and CH5 is completed (step ST44). The number of data in FIFO memory M1 is 2. Next, AD conversion of scan group SG0 is started (step ST45). This causes the AD conversion of scan group SG1 to be interrupted. Next, AD conversion of scan group SG0 is completed (step ST46).

[0141] Next, AD conversion of the scan group SG1 is resumed (step ST47). At this time, the pointer is set to the clear pointer position ("0"), so that the number of data in the FIFO memory M1 becomes 0.

[0142] Next, AD conversion of AD conversion channels CH4 to CH7 is completed (step ST48). The number of data in FIFO memory M1 is 4. Next, AD conversion of scan group SG1 is completed (step ST49). Next, the completion of AD conversion of scan group SG1 is detected, and the data in FIFO memory M1 is read (step ST50). As a result, the number of data in FIFO memory M1 becomes 0.

[0143] In the case where AD conversion channels are stored in the 8-stage FIFO memory M1 under the condition that scan group SG1 is suspended by scan group SG0, the FIFO memory M1 is cleared when scan group SG1 is resumed, so the conversion results before the suspension of scan group SG1 do not remain in the FIFO memory M1. Therefore, the FIFO memory does not become full, and there is no need for software to read data and delete unnecessary data.

[0144] This makes it possible to execute high-speed A / D conversion processing.

[0145] In this embodiment, the FIFO memory M1 is cleared when conversion is resumed. However, the FIFO memory may be cleared when conversion is started or interrupted.

[0146] (Embodiment 2) FIG. 14 is a diagram illustrating a configuration of an A / D conversion control circuit 125# according to the second embodiment.

[0147] 14, A / D conversion control circuit 125# differs from A / D conversion control circuit 125 in that FIFO unit 129 is replaced with FIFO unit 129#.

[0148] FIFO unit 129# differs in that pointer control unit PCTn is replaced with pointer control unit PCT#n. As the rest of the configuration is similar, detailed description thereof will not be repeated.

[0149] The pointer control unit PCT#n has a function of storing the write pointer position.

[0150] FIG. 15 is a diagram illustrating the configuration of a pointer control unit PCT#n according to the second embodiment.

[0151] 15, the pointer control unit PCT#n includes a recovery buffer BF that stores the pointer position held by the write pointer control unit WPn according to the determination signal SGAn, and a selector SL that receives the input of the determination signals SGBn and SGCn and selects according to the clear timing selection signal. n can take any value. In this example, n is in the range of 0 to 2.

[0152] The restore buffer BF instructs the write pointer control unit WPn in response to the input of the judgment signal SGAn to obtain and store the pointer position of the write pointer control unit WPn. The value stored in the restore buffer BF is held as the clear pointer position.

[0153] The clear timing selection signal is output based on information stored in the clear timing selection register 128. The clear timing selection register 128 is configured with two bits each corresponding to interruption and restart of the clear timing.

[0154] When any bit of the clear timing selection register 128 is set, a clear timing selection signal ("1") is output to the selector SL.

[0155] For example, when "1" is set in the bit corresponding to the interruption of the clear timing selection register 128, the selector SL outputs the determination signal SGBn to the write pointer control unit WPn as a pointer change timing signal.

[0156] In this case, at the timing when the scan group SGn is suspended, the write pointer control unit WPn sets the pointer position to a position corresponding to the value stored in the restoration buffer BF.

[0157] Similarly, for example, when "1" is set in the bit corresponding to restart in the clear timing selection register 128, the selector SL outputs the determination signal SGCn to the write pointer control unit WPn as a pointer change timing signal.

[0158] In this case, at the timing when scan group SGn is to be restarted, the write pointer control unit WPn sets the pointer position to a position corresponding to the value stored in the restoration buffer BF.

[0159] FIG. 16 is a diagram illustrating interrupt processing for a high-priority scan group according to the second embodiment.

[0160] With reference to FIG. 16, in this example, scan groups SG0 and SG1 will be described.

[0161] At time T41, a conversion start trigger for the scan group SG1 is input, and the AD conversion channels of the scan group SG1 are sequentially input to the input reception unit ISG1. The input reception unit ISG1 sets a control signal SGACT1 to 1.

[0162] In addition, as the control signal SGACT is set to "1", the determination signal SGA1 is set to "1". Accordingly, the restoration buffer BF of the pointer control unit PCT#1 stores the pointer position of the write pointer control unit WP1. In this example, the restoration buffer BF stores and holds "0".

[0163] In this example, the AD conversion channels CH4 to CH6 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1.

[0164] Then, at time T42, halfway through the timing at which the input reception unit ISG1 receives the AD conversion channel CH7, a conversion start trigger for the scan group SG0 is input. This causes the input reception unit ISG0 to set the control signal SGACT0 to 1. Then, the AD conversion of the scan group SG1 is interrupted. The input reception unit ISG0 then receives the AD conversion channels CH0 to CH2 of the scan group SG0 and stores them sequentially in the FIFO memory M0.

[0165] Next, at time T43, the input reception unit ISG0 receives the end of conversion of the final AD conversion channel CH2 of the scan group SG0. As a result, the control signal SGACT0 is set to 0. Then, as AD conversion of the scan group SG1 is resumed, the determination signal SGC1 is set to "1." As a result, the write pointer control unit WP1 sets the pointer position ("0") based on the value stored in the restoration buffer BF.

[0166] In this example, the AD conversion channels CH4 to CH5 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0167] Then, at time T44, which is midway through the timing at which the input reception unit ISG1 receives the AD conversion channel CH6, a conversion start trigger for the scan group SG0 is input. This causes the input reception unit ISG0 to set the control signal SGACT0 to 1. Then, the AD conversion of the scan group SG1 is interrupted. The input reception unit ISG0 then receives the AD conversion channels CH0 to CH2 of the scan group SG0 and stores them sequentially in the FIFO memory M0.

[0168] Next, at time T45, the input reception unit ISG0 receives the end of conversion of the final AD conversion channel CH2 of the scan group SG0. As a result, the control signal SGACT0 is set to 0. Then, as AD conversion of the scan group SG1 is resumed, the determination signal SGC1 is set to "1." Accordingly, the write pointer control unit WP1 sets the pointer position ("0") based on the value stored in the restoration buffer BF.

[0169] In this example, the AD conversion channels CH4 to CH7 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0170] Then, at time T46, the final AD conversion channel CH7 is stored in the FIFO memory M1, and AD conversion of the scan group SG1 is completed. As a result, the control signal SGACT1 is set to 0.

[0171] Next, at time T48, a conversion start trigger for the scan group SG1 is input, and the AD conversion channels of the scan group SG1 are sequentially input to the input reception unit ISG1. The input reception unit ISG1 sets the control signal SGACT1 to 1.

[0172] In addition, as a result of the control signal SGACT being set to "1", the determination signal SGA1 is set to "1". Accordingly, the restoration buffer BF of the pointer control unit PCT#1 stores the pointer position of the write pointer control unit WP1. In this example, the restoration buffer BF stores and holds "4".

[0173] In this example, the AD conversion channels CH4 to CH5 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0174] Then, at time T49, which is midway through the timing at which the input reception unit ISG1 receives the AD conversion channel CH6, a conversion start trigger for the scan group SG0 is input. This causes the input reception unit ISG0 to set the control signal SGACT0 to 1. Then, the AD conversion of the scan group SG1 is interrupted. The input reception unit ISG0 then receives the AD conversion channels CH0 to CH2 of the scan group SG0 and stores them sequentially in the FIFO memory M0.

[0175] Next, at time T50, the input reception unit ISG0 receives the end of conversion of the final AD conversion channel CH2 of the scan group SG0. As a result, the control signal SGACT0 is set to 0. Then, as AD conversion of the scan group SG1 is resumed, the determination signal SGC1 is set to "1." As a result, the write pointer control unit WP1 sets the pointer position ("4") based on the value stored in the restoration buffer BF.

[0176] In this example, the AD conversion channels CH4 to CH7 are input to the input receiving unit ISG1 in order and stored in the FIFO memory M1 in sequence.

[0177] Then, at time T51, the final AD conversion channel CH7 is stored in the FIFO memory M1, and AD conversion of the scan group SG1 is completed. As a result, the control signal SGACT1 is set to 0.

[0178] Also, at time T51, the FIFO memory M1 is shown to be in a full state, where the data in the FIFO memory M1 is read out.

[0179] FIG. 17 is a diagram illustrating the FIFO memory M1 in processing an interrupt for a high-priority scan group according to the second embodiment.

[0180] With reference to FIG. 17(A), in this example, it is assumed that FIFO memory M1 is provided with eight stages of storage areas.

[0181] At time T46, the case where the AD conversion channels CH4 to CH7 are stored is shown. Before this state was reached, the pointer of the FIFO memory M1 was set to a position corresponding to the value ("0") stored in the restoration buffer BF at the two restart times.

[0182] 17B, ​​a case where the AD conversion channels CH4 to CH7 are stored at time T51 is shown. Before this state was reached, the pointer of the FIFO memory M1 was set to a position corresponding to the value ("4") stored in the restoration buffer BF at the one restart.

[0183] In this example, at the start, the value of the pointer in FIFO memory M1 is stored in restoration buffer BF, and at the restart, the pointer in FIFO memory M1 is set to a position corresponding to the value stored in restoration buffer BF. Therefore, when AD conversion is interrupted and then restarted, the pointer in FIFO memory M1 is reset to the value at the start, so that the data remaining in FIFO memory M1 at the time of interruption is reset, and no unnecessary data remains in FIFO memory M1.

[0184] Moreover, reading is performed when the FIFO memory M1 is full, so that the eight-stage storage area of ​​the FIFO memory M1 can be used effectively.

[0185] For example, it is desirable to set the number of stages of the FIFO memory M to an integer multiple of the total number of AD conversion channels in the scan group SG. This makes it possible to fully utilize the storage area of ​​the FIFO memory M.

[0186] Regarding reading from the FIFO memory according to the second embodiment, the read process is executed when the FIFO memory is full, not after the last AD conversion of the scan group SGn is completed and the last AD conversion channel CH is stored. The specific process is the same as that described in the flow of FIG. 12, and therefore the detailed description thereof will not be repeated.

[0187] FIG. 18 is a flowchart illustrating a process flow of AD conversion according to the second embodiment.

[0188] Referring to FIG. 18, AD conversion of scan group SG1 is started (step ST61). At this start, the restoration buffer BF of the pointer control unit PCT#1 stores and holds the pointer position ("0") of the write pointer control unit WP1. Next, AD conversion of AD conversion channels CH4 to CH6 is completed (step ST62). The number of data in FIFO memory M1 is 3. Next, AD conversion of scan group SG0 is started (step ST63). This causes AD conversion of scan group SG1 to be interrupted. Next, AD conversion of scan group SG0 is completed (step ST64). Next, AD conversion of scan group SG1 is resumed (step ST65). At this time, the pointer is set to the pointer position ("0") stored in the restoration buffer BF, so that the number of data in FIFO memory M1 becomes 0. Next, AD conversion of AD conversion channels CH4 and CH5 is completed (step ST66). The number of data in FIFO memory M1 is 2.

[0189] Next, AD conversion of scan group SG0 is started (step ST67). This causes AD conversion of scan group SG1 to be interrupted. Next, AD conversion of scan group SG0 is completed (step ST68). Next, AD conversion of scan group SG1 is resumed (step ST69). At this time, the pointer is set to the pointer position ("0") stored in the restoration buffer BF, so that the number of data in FIFO memory M1 becomes 0.

[0190] Next, AD conversion of AD conversion channels CH4 to CH7 is completed (step ST70). Next, AD conversion of scan group SG1 is completed (step ST71). Next, AD conversion of scan group SG1 is started (step ST72). At this start, the restoration buffer BF of the pointer control unit PCT#1 stores and holds the pointer position ("4") of the write pointer control unit WP1.

[0191] Next, AD conversion of AD conversion channels CH4 and CH5 is completed (step ST73). The number of data in FIFO memory M1 is 2. Next, AD conversion of scan group SG0 is started (step ST74). This causes AD conversion of scan group SG1 to be interrupted. Next, AD conversion of scan group SG0 is completed (step ST75).

[0192] Next, AD conversion of the scan group SG1 is resumed (step ST76). At this time, the number of data in the FIFO memory M1 becomes 0 because the pointer is set to the pointer position ("4") stored in the restoration buffer BF.

[0193] Next, AD conversion of the AD conversion channels CH4 to CH7 is completed (step ST77). The number of data in the FIFO memory M1 is 8. Next, AD conversion of the scan group SG1 is completed (step ST78). Next, data in the FIFO memory M1 is read (step ST79). As a result, the number of data in the FIFO memory M1 becomes 0.

[0194] In the case where AD conversion channels are stored in the 8-stage FIFO memory M1 under the condition that scan group SG1 is interrupted by scan group SG0, the FIFO memory M1 is set to the pointer position stored in the restoration buffer BF when the scan group SG1 is resumed, so the conversion results before the interruption of scan group SG1 do not remain in the FIFO memory M1. Therefore, no unnecessary data remains in the FIFO memory M1, and the process of reading data and deleting unnecessary data by software is not required.

[0195] This makes it possible to execute high-speed A / D conversion processing.

[0196] In this example, a method has been described in which the pointer of the FIFO memory M1 is set to the pointer position stored in the restoration buffer BF when resuming, but it is also possible to set the pointer of the FIFO memory M1 to the pointer position stored in the restoration buffer BF at the timing of interruption.

[0197] (Examples) FIG. 19 is a diagram for explaining the first application example.

[0198] 19, this example shows a case where a motor 504 that drives a load 506, a three-phase inverter 502 that drives the motor 504, and an MCU 11A that controls the three-phase inverter 502 are provided. The motor 504 is provided with a tacho generator 509 for detecting the motor speed. In addition, the three-phase inverter 502 is provided with a current sensor 508 that detects a current in order to detect the rotor position of the motor 504.

[0199] A detection value detected by a current sensor 508 is fed back to the MCU 11A. Also, a detection value detected by a tacho generator 509 is fed back to the MCU 11A.

[0200] The MCU 11A includes a CPU 120A that performs calculations in response to instructions, a pulse generating circuit 500 that outputs a PWM pulse for a three-phase inverter 502 based on the calculation results of the CPU 120A, and an A / D conversion circuit 118A and an A / D conversion control circuit 125A that convert analog signals, which are the detection values ​​of a current sensor 508 and a tacho generator 509, into digital values.

[0201] For example, when data stored in the FIFO memory is to be used instantly, the A / D conversion circuit 118A and the A / D conversion control circuit 125A described in the first embodiment above can be applied.

[0202] FIG. 20 is a diagram illustrating the second application example.

[0203] 20, there is shown a case in which an amplifier 510 for amplifying an analog signal 512 is provided, and an MCU 11B for receiving an input of a signal from the amplifier 510 is also provided.

[0204] The MCU 11B includes an A / D conversion circuit 118B and an A / D conversion control circuit 125B that convert the analog signal amplified by the amplifier 510 into a digital value, and a CPU 120B that executes arithmetic processing based on the converted digital signal.

[0205] For example, if the data stored in the FIFO memory does not need to be used instantly, the A / D conversion circuit 118B and the A / D conversion control circuit 125B described in the second embodiment above can be applied.

[0206] FIG. 21 is a diagram illustrating the third application example.

[0207] Referring to FIG. 21, there is shown a case where a voltage monitor 520 that monitors a power supply 522 and an MCU 11C are provided.

[0208] The MCU 11C includes an A / D conversion circuit 118C and an A / D conversion control circuit 125C that convert an analog signal monitored by the voltage monitor 520 into a digital value, and a CPU 120C that executes arithmetic processing based on the converted digital signal. As an example, the CPU 120C can execute anomaly detection based on the voltage value detected by the voltage monitor 520.

[0209] For example, in the case of abnormality detection as in this example, the A / D conversion circuit 118C and the A / D conversion control circuit 125C described in the first or second embodiment can be applied.

[0210] While the present disclosure has been specifically described above based on the embodiments, it goes without saying that the present disclosure is not limited to the embodiments and can be modified in various ways without departing from the spirit of the present disclosure. [Explanation of symbols]

[0211] 10 data processing system, 11 semiconductor integrated circuit device, 110 arbitration unit, 111 analog port, 117, SL selector, 118, 118A, 118B, 118C A / D conversion circuit, 121 RAM, 123 peripheral bus, 124 internal bus, 125, 125A, 125B, 125C A / D conversion control circuit, 127 scan group control unit, 128 clear timing selection register, 129 FIFO unit.

Claims

1. a scan group control unit that controls a plurality of AD conversion channels by a plurality of scan groups having different priorities; a FIFO unit provided corresponding to each of the plurality of scan groups, each of the FIFO units having a plurality of FIFO memories for sequentially storing outputs from the scan group control unit for each of the corresponding scan groups; The scan group control unit an input receiving unit that receives an AD conversion channel of a corresponding scan group among the plurality of AD conversion channels in accordance with an instruction and outputs the received AD conversion channel to a corresponding FIFO memory; an arbitration unit that determines timings for starting, suspending, and resuming conversion in each of the plurality of scan groups; The FIFO unit includes: The memory device further includes a plurality of pointer control units provided corresponding to the plurality of FIFO memories, an A / D conversion control circuit, wherein each of the pointer control units clears or changes the position of the write pointer / read pointer of the corresponding FIFO memory at least one of the timings of starting, interrupting, and resuming the corresponding scan group in accordance with the priority of the scan group;

2. 2. The A / D conversion control circuit according to claim 1, wherein said corresponding FIFO memory executes a read process using a read pointer in response to reception of the last A / D conversion channel of the corresponding scan group.

3. 2. The A / D conversion control circuit according to claim 1, wherein each of said pointer control sections includes a buffer for storing the position of a writer pointer at the start timing of a corresponding scan group.

4. 4. The A / D conversion control circuit according to claim 3, wherein each of said pointer control circuits instructs storing data based on the position of a writer pointer stored in said buffer at the timing when the corresponding scan group is restarted.

5. 4. The A / D conversion control circuit according to claim 3, wherein the number of stages of said FIFO memory is set to an integer multiple of the total number of AD conversion channels included in the corresponding scan group.

6. 2. The A / D conversion control circuit as claimed in claim 1, wherein each of the pointer control units outputs a clear signal for clearing or changing the position of a write pointer / read pointer of a corresponding FIFO memory at at least one of the start, interruption, and restart of conversion of the corresponding scan group based on a combination of a timing signal at the start, interruption, and restart of conversion by the corresponding scan group from the arbitration unit and a clear timing selection signal.

7. 2. The A / D conversion control circuit according to claim 1, wherein the arbitration section determines timings for starting, suspending, and restarting conversion in each of the plurality of scan groups based on rising and falling edges of a conversion start trigger in each of the plurality of scan groups.

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