Communication device and communication method

Abstract

To switch a communication device from one communication mode to another communication mode in a shorter time compared to a conventional technique.SOLUTION: A host device 1 and an SD card 2 are connected to each other via a first signal line and a second signal line. The first signal line includes a third signal line which is common to at least a portion of the second signal line, and a fourth signal line that is separate from the second signal line. The host device 1 and the SD card 2 can operate in an SD I / F mode where they transmit the data via the first signal line, and a PCIe I / F mode where they transmit the data via the second signal line. When the host device 1 and the SD card 2 are operating in the PCIe I / F mode, a first command signal that commands communication mode switching is transmitted from the host device 1 to the SD card 2 via the fourth signal line. After transmitting the first command signal, when the data that should be transmitted in the PCIe I / F mode does not exist, the host device 1 and the SD card 2 are switched to the SD I / F mode.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The present disclosure relates to a communication device and a communication method. [Background technology]

[0002] Data may be transmitted between two communication devices connected to each other via a specific communication interface, such as a digital camera and a memory card. For various purposes, such as speeding up data transmission between the communication devices, each communication device may have multiple communication interfaces that transmit data using different communication protocols. In this case, each communication device can operate in multiple communication modes that transmit data through one of the multiple communication interfaces.

[0003] For example, Patent Document 1 discloses an SD card (SD Express card) equipped with an SD interface and a PCI Express interface. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 7213435 Summary of the Invention [Problem to be solved by the invention]

[0005] A communication device with multiple communication interfaces generally has characteristics such as data transmission speed and power consumption that differ for each communication mode. A communication device may be required to switch communication modes during operation due to constraints on some characteristics. For example, in the case of a conventional SD Express card, in order to switch communication modes, it is necessary to stop reading and writing data once and initialize the SD interface and the PCI Express interface. In this case, data cannot be read or written for several seconds, which may impair user convenience. Therefore, in a communication device that supports multiple communication modes, it is required to switch from one communication mode to another communication mode in a short time.

[0006] The present disclosure provides a communication device and a communication method that support a plurality of communication modes and that can switch from one communication mode to another in a shorter time than conventional communication modes. [Means for solving the problem]

[0007] According to one aspect of the present disclosure, 1. A communication method for transmitting data between a first communication device and a second communication device, comprising: the first and second communication devices are connected to each other via a plurality of first signal lines and a plurality of second signal lines, the first signal lines including a third signal line common to at least a portion of the second signal lines, and a fourth signal line separate from the second signal lines; the first and second communication devices are operable in a first communication mode in which they transmit data to each other using a first communication protocol via the first signal line, and in a second communication mode in which they transmit data to each other using a second communication protocol via the second signal line; The communication method includes: transmitting a first command signal, which instructs switching of a communication mode, from the first communication device to the second communication device via the fourth signal line using the first communication protocol when the first and second communication devices are operating in the second communication mode; and switching the first and second communication devices from the second communication mode to the first communication mode when there is no data to be transmitted in the second communication mode after transmitting the first command signal. Effect of the Invention

[0008] According to one aspect of the present disclosure, in a communication device supporting multiple communication modes, it is possible to switch from one communication mode to another in a shorter time than in the past. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a configuration of a host device 1 according to an embodiment. [Diagram 2] 2 is a block diagram showing the configuration of an SD card 2 according to the embodiment. FIG. [Diagram 3] FIG. 3 is a diagram showing a terminal layout of the SD card 2 in FIG. [Figure 4] 4 is a table showing signals transmitted via signal lines including terminals #1 to #18 of SD card 2 in FIG. [Diagram 5] 1 is a diagram showing a connection between a host device 1 and an SD card 2 according to an embodiment. [Figure 6] 4 is a timing chart showing an example of the initialization operation of the host device 1 and the SD card 2 according to the embodiment. [Figure 7] FIG. 1 is a diagram illustrating an outline of the architecture of a host device 1 and an SD card 2 according to an embodiment, in which the host device 1 and the SD card 2 operate in SD I / F mode. [Figure 8] FIG. 1 is a diagram illustrating an outline of the architecture of a host device 1 and an SD card 2 according to an embodiment, in which the host device 1 and the SD card 2 operate in PCIe I / F mode. [Figure 9]1 is a diagram showing the format of a signal CMD transmitted and received between a host device 1 and an SD card 2 according to an embodiment, in which the signal CMD includes a CMD52 command signal transmitted from the host device 1 to the SD card 2. FIG. [Figure 10] 13 is a diagram showing the format of a signal CMD transmitted and received between a host device 1 and an SD card 2 according to an embodiment, in which the signal CMD includes a CMD52 response signal transmitted from the SD card 2 to the host device 1. FIG. [Figure 11] 2 is a diagram illustrating signal transmission when the host device 1 and the SD card 2 according to the embodiment operate in PCIe I / F mode. FIG. [Figure 12] 1 is a diagram illustrating signal transmission when the host device 1 and the SD card 2 according to an embodiment are switched from a PCIe I / F mode to an SD I / F mode. [Figure 13] 2 is a diagram illustrating signal transmission when the host device 1 and the SD card 2 according to the embodiment operate in SD I / F mode. FIG. [Figure 14] 1 is a timing chart showing a first operation example when the host device 1 and the SD card 2 according to the embodiment are switched from a PCIe I / F mode to an SD I / F mode. [Figure 15] 10 is a timing chart showing a second operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. [Figure 16] 13 is a timing chart showing a third operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. [Figure 17] 13 is a timing chart showing a fourth operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. [Figure 18] 13 is a timing chart showing a fifth operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. [Figure 19] 13 is a timing chart showing a sixth operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. [Figure 20] 13 is a timing chart showing a seventh operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed explanations than necessary may be omitted. For example, detailed explanations of already well-known matters or duplicate explanations of substantially the same configurations may be omitted. This is to avoid the following explanation becoming unnecessarily redundant and to facilitate understanding by those skilled in the art. Note that components with the same reference numerals have the same functions in each embodiment.

[0011] In addition, the present disclosure provides the accompanying drawings and the following description for the understanding of those skilled in the art, and is not intended to limit the subject matter described in the claims.

[0012] [Configuration of the embodiment] Fig. 1 is a block diagram showing the configuration of a host device 1 according to an embodiment of the present invention, and Fig. 2 is a block diagram showing the configuration of an SD card 2 according to an embodiment of the present invention.

[0013] The host device 1 is, for example, a digital camera (still images, video), a personal computer, a mobile phone, an audio player, a drive recorder, a car navigation system, etc. The SD card 2 is an SD Express card equipped with both a legacy SD interface and a PCI Express (PCIe) interface. The host device 1 also has both a legacy SD interface and a PCIe interface, and is configured to be connected to the SD card 2 so as to be able to read and write data.

[0014] The host device 1 is an example of a first communication device, and the SD card 2 is an example of a second communication device or an external device.

[0015] The host device 1 and the SD card 2 can operate in an SD I / F mode in which data is transmitted between them using a legacy SD protocol via a legacy SD interface, and in a PCIe I / F mode in which data is transmitted between them using a PCIe protocol via a PCIe interface. In this specification, the legacy SD interface and the legacy SD protocol refer to an interface and its communication protocol defined by the SD specification version 3.01 or earlier, and include, for example, a UHS-I (Ultra High Speed-I) bus interface and its communication protocol. The host device 1 and the SD card 2 are provided with a PCIe interface, and thus can read and write data at a higher speed than when using a legacy SD interface. In addition, the host device 1 and the SD card 2 are provided with a legacy SD interface, and thus have compatibility with conventional devices that do not have a PCIe interface.

[0016] The SD I / F mode is an example of a first communication mode, and the PCIe I / F mode is an example of a second communication mode.

[0017] 1, the host device 1 includes a host control circuit 11, a main memory 12, and a socket 13. The host control circuit 11 controls the overall operation of the host device 1, and also controls reading and writing of data from and to the SD card 2. The host control circuit 11 may be configured as a single integrated circuit such as a System on a Chip (SoC) device. The main memory 12 temporarily stores programs and data processed by the host control circuit 11. The socket 13 is configured to accommodate the SD card 2, and has a number of terminals each connected to a terminal of the SD card 2 (described later with reference to FIG. 3).

[0018] 2, the SD card 2 includes a card control circuit 21, a NAND flash memory 22, and a terminal group 23. The card control circuit 21 is connected to the host device 1 via the terminal group 23, and controls reading and writing of data from and to the NAND flash memory 22. The NAND flash memory 22 is a non-volatile storage medium that stores data. The terminal group 23 includes a number of terminals, which will be described later with reference to FIG. 3.

[0019] By connecting the terminals of the socket 13 and the terminals of the SD card 2 to each other, a signal line is formed for transmitting data between the host device 1 and the SD card 2 and for supplying power from the host device 1 to the SD card 2.

[0020] Referring again to FIG. 1, the host control circuit 11 includes a bus 110, a CPU 111, a ROM 112, a power supply circuit 113, an SD host interface circuit (I / F) 114, a PCIe host interface circuit (I / F) 115, and a selector .

[0021] The CPU 111 is a processor that controls the overall operation of the host device 1 and also controls reading and writing of data from and to the SD card 2.

[0022] The ROM 112 stores programs and data for controlling the host device 1.

[0023] The power supply circuit 113 supplies, via the socket 13, to the SD card 2, a voltage of 3.3 V for operating the SD card 2 in the SD I / F mode, and a voltage of 1.8 V for operating the SD card 2 in the PCIe I / F mode.

[0024] The SD host interface circuit 114 is a communication circuit that transmits and receives data to and from the SD card 2 using the legacy SD protocol via a predetermined signal line when the host device 1 and SD card 2 operate in the SD I / F mode. Some of the terminals of the SD host interface circuit 114 are connected to the socket 13 via a selector 116, and the remaining terminals of the SD host interface circuit 114 are connected directly to the socket 13.

[0025] The PCIe host interface circuit 115 is a communication circuit that transmits or receives data to or from the SD card 2 using a PCIe protocol via a predetermined signal line when the host device 1 and the SD card 2 operate in the PCIe I / F mode. The PCIe host interface circuit 115 includes physical layer circuits for a phase-locked loop, a clock data recovery, a serializer and a deserializer, 8b / 10b encoding and decoding, and 128b / 130b encoding and decoding. The PCIe host interface circuit 115 operates as a PCI Express root complex. Some of the terminals of the PCIe host interface circuit 115 are connected to the socket 13 via a selector 116, and the remaining terminals of the PCIe host interface circuit 115 are directly connected to the socket 13.

[0026] The selector 116 connects one of the terminals of the SD host interface circuit 114 and the PCIe host interface circuit 115 to the socket 13. By connecting the terminals of the socket 13 and the terminals of the SD card 2 to each other, the host device 1 and the SD card 2 are connected to each other via a plurality of first signal lines for transmitting data in the SD I / F mode and a plurality of second signal lines for transmitting data in the PCIe I / F mode. The first signal lines include a third signal line common to at least a part of the second signal line and a fourth signal line separate from the second signal line. Hereinafter, in this specification, the third signal line is referred to as a "common signal line" and the fourth signal line is referred to as a "dedicated signal line". The second signal line may include a dedicated signal line separate from the first signal line. In other words, the selector 116 connects the shared signal line to one of the SD host interface circuit 114 and the PCIe host interface circuit 115.

[0027] Under the control of the CPU 111, the SD host interface circuit 114 starts and stops the supply of a voltage of 3.3 V to the SD card 2, and also controls the power supply circuit 113 to start and stop the supply of a voltage of 1.8 V to the SD card 2. In addition, under the control of the CPU 111, the SD host interface circuit 114 controls the selector 116 to connect one of a terminal of the SD host interface circuit 114 or a terminal of the PCIe host interface circuit 115 to the socket 13.

[0028] The CPU 111 , the ROM 112 , the SD host interface circuit 114 , and the PCIe host interface circuit 115 are connected to one another via a bus 110 , and are also connected to a main memory 12 external to the host control circuit 11 via the bus 110 .

[0029] The host device 1 may further include a storage device, other interfaces (wireless LAN, wired LAN, USB, etc.), an input device, a display device, and the like, but these are omitted for simplicity of illustration.

[0030] Referring again to FIG. 2, the card control circuit 21 includes a bus 210, a CPU 211, an SD card interface circuit (I / F) 212, a PCIe card interface circuit (I / F) 213, an NVMe (NVM Express) controller 214, a buffer memory 215, a buffer controller 216, an encryption engine 217, a sequencer 218, and a NAND controller 219.

[0031] The CPU 211 is a processor that controls the overall operation of the SD card 2 and also controls reading and writing of data from and to the NAND flash memory 22 .

[0032] The SD card interface circuit 212 is a communication circuit that transmits and receives data to and from the host device 1 using the legacy SD protocol via a first signal line when the host device 1 and the SD card 2 operate in the SD I / F mode.

[0033] The PCIe card interface circuit 213 is a communication circuit that transmits or receives data to the host device 1 using the PCIe protocol via the second signal line when the host device 1 and the SD card 2 operate in the PCIe I / F mode. The PCIe card interface circuit 213 includes physical layer circuits for a phase-locked loop, a clock data recovery, a serializer and a deserializer, 8b / 10b encoding and decoding, and 128b / 130b encoding and decoding. The PCIe card interface circuit 213 operates as an endpoint of PCI Express.

[0034] The NVMe controller 214 controls reading and writing of data to the NAND flash memory 22 via the PCIe interface in accordance with the NVMe standard.

[0035] The buffer memory 215 temporarily stores data to be read from and written to the NAND flash memory 22 .

[0036] The buffer controller 216 controls the reading and writing of data from and to the buffer memory 215 .

[0037] The encryption engine 217 encrypts and decrypts data to be read from and written to the NAND flash memory 22 .

[0038] The sequencer 218 controls programming and erasing of the NAND flash memory 22 .

[0039] The NAND controller 219 controls reading and writing of data from and to the NAND flash memory 22 .

[0040] The CPU 211, the SD card interface circuit 212, the PCIe card interface circuit 213, the NVMe controller 214, the buffer memory 215, the buffer controller 216, the encryption engine 217, the sequencer 218, and the NAND controller 219 are connected to each other via a bus 210.

[0041] In the card control circuit 21, components other than the PCIe card interface circuit 213 operate on a voltage of 3.3 V supplied from the host device 1. The PCIe card interface circuit 213 operates on a voltage of 1.8 V supplied from the host device 1. In addition, the NAND flash memory 22 operates on a voltage of 3.3 V supplied from the host device 1.

[0042] FIG. 3 is a diagram showing the terminal layout of the SD card 2 in FIG. 2. Referring to FIG. 3, the terminal group 23 includes a terminal group R1 consisting of terminals #1 to #9, and a terminal group R2 consisting of terminals #10 to #18. The terminals #1 to #9 are part of the legacy SD interface. The terminals #10 to #18 are terminals added to support the PCIe interface. By connecting the terminals #1 to #18 of the SD card 2 to the corresponding terminals of the socket 13, a signal line is formed between the host device 1 and the SD card 2, as described above.

[0043] Fig. 4 is a table showing signals transmitted via signal lines including terminals #1 to #18 of SD card 2 in Fig. 3. Hereinafter in this specification, the signal lines including terminals #1 to #18 will be referred to as L1 to L18.

[0044] When the host device 1 and the SD card 2 operate in the SD I / F mode, the following signals or voltages are transmitted via signal lines L1 to L9.

[0045] (L1) DAT3: A data signal transmitted from the host device 1 to the SD card 2, or from the SD card 2 to the host device 1. (L2) CMD: A command signal transmitted from the host device 1 to the SD card 2, or a response signal transmitted from the SD card 2 to the host device 1. (L3) VSS1: Ground voltage of 0V. (L4) VDD1: 3.3V power supply voltage supplied from host device 1 to SD card 2. (L5) SDCLK: Clock signal sent from the host device 1 to the SD card 2. (L6) VSS2: Ground voltage of 0V. (L7) DAT3: A data signal transmitted from the host device 1 to the SD card 2, or from the SD card 2 to the host device 1. (L8) DAT3: A data signal transmitted from the host device 1 to the SD card 2, or from the SD card 2 to the host device 1. (L9) DAT3: A data signal transmitted from the host device 1 to the SD card 2, or from the SD card 2 to the host device 1. (L10~L18) Not used.

[0046] When the host device 1 and SD card 2 operate in SD I / F mode, 4-bit data signals DAT0-DAT3 are transmitted in a single-ended manner from the host device 1 to the SD card 2, or from the SD card 2 to the host device 1. A 1-bit signal CMD is also transmitted in a single-ended manner from the host device 1 to the SD card 2, or from the SD card 2 to the host device 1. A clock signal SDCLK ​​is also transmitted in a single-ended manner from the host device 1 to the SD card 2.

[0047] When the host device 1 and the SD card 2 operate in the PCIe I / F mode, the following signals or voltages are transmitted via the signal lines L1 to L18.

[0048] (L1) PERST#: A signal from the host device 1 to the SD card 2 to instruct the SD card 2 to reset. (L2) Not used. (L3) VSS1: Ground voltage of 0V. (L4) VDD1: 3.3V power supply voltage supplied from host device 1 to SD card 2. (L5) Not used. (L6) VSS2: Ground voltage of 0V. (L7) REFCLK+: One side of a differential signal including a reference clock signal transmitted from the host device 1 to the SD card 2. (L8) REFCLK-: the other of the differential signals including the reference clock signal transmitted from the host device 1 to the SD card 2 (i.e., the inverted signal of the signal REFCLK+). (L9) CLKREQ#: a signal requesting the host device 1 to supply a reference clock signal from the SD card 2, or a signal from the host device 1 to the SD card 2 to instruct initialization of the SD card 2. (L10) VSS3: Ground voltage of 0V. (L11) PCIe Tx+: One side of a differential signal including a data signal transmitted from the host device 1 to the SD card 2. (L12) PCIe Tx-: the other of the differential signals including the data signal transmitted from the host device 1 to the SD card 2 (i.e., the inverted signal of the signal PCIe Tx+). (L13) VSS4: Ground voltage of 0V. (L14) VDD2: 1.8V power supply voltage supplied from host device 1 to SD card 2. (L15) PCIe Rx+: One side of a differential signal including a data signal transmitted from the SD card 2 to the host device 1. (L16) PCIe Rx-: the other of the differential signals including the data signal transmitted from the SD card 2 to the host device 1 (i.e., the inverted signal of the signal PCIe Rx+). (L17) VSS5: Ground voltage of 0V. (L18) Reserved.

[0049] When the host device 1 and the SD card 2 operate in the PCIe I / F mode, a data signal is transmitted from the host device 1 to the SD card 2 by differential transmission (i.e., as a pair of differential signals PCIe Tx+ and PCIe Tx-), and a data signal is transmitted from the SD card 2 to the host device 1 by differential transmission (i.e., as a pair of differential signals PCIe Rx+ and PCIe Rx-). In this case, a reference clock signal is transmitted from the host device 1 to the SD card 2 by differential transmission (i.e., as a pair of differential signals REFCLK+ and REFCLK-). The differential transmission method has higher noise resistance than the single-ended method, so that the signal amplitude can be reduced more than in the single-ended method, and therefore data can be transmitted at a higher speed than in the single-ended method.

[0050] In Figure 4, "input" indicates that a signal is input to the SD card 2, "output" indicates that a signal is output from the SD card 2, and "I / O" indicates that a signal is input to and output from the SD card 2.

[0051] Fig. 5 is a diagram showing the connection between the host device 1 and the SD card 2 according to the embodiment. Signal lines L1 to L18 are formed between the host device 1 and the SD card 2 by connecting terminals #1 to #18 of the SD card 2 to corresponding terminals of the socket 13. In Fig. 5, terminals #3, #6, #10, #13, #17, #18 and signal lines L3, L6, L10, L13, L17, L18 are omitted for simplicity of illustration.

[0052] The signal line L1 is a shared signal line used for transmitting the data signal DAT3 in the SD I / F mode and the signal PERST# in the PCIe I / F mode. The signal line L7 is a shared signal line used for transmitting the data signal DAT0 in the SD I / F mode and the signal REFCLK+ in the PCIe I / F mode. The signal line L8 is a shared signal line used for transmitting the data signal DAT1 in the SD I / F mode and the signal REFCLK- in the PCIe I / F mode. The signal line L9 is a shared signal line used for transmitting the data signal DAT2 in the SD I / F mode and the signal CLKREQ# in the PCIe I / F mode.

[0053] The signal line L2 is a dedicated signal line that is not used for signal transmission in the PCIe I / F mode, and is used only for transmitting the signal CMD in the SD I / F mode. The signal line L5 is a dedicated signal line that is not used for signal transmission in the PCIe I / F mode, and is used only for transmitting the clock signal SDCLK ​​in the SD I / F mode. In this specification, a dedicated signal line means a signal line that is separate from a shared signal line and is not used in the PCIe I / F mode. For example, when an additional mode different from both the SD I / F mode and the PCIe I / F mode exists, the dedicated signal line may be used in the additional mode in addition to the SD I / F mode.

[0054] The signal line L4 (as well as the signal lines L3 and L6) are used to supply a power supply voltage of 3.3 V from the host device 1 to the SD card 2 in both the SD I / F mode and the PCIe I / F mode.

[0055] The signal lines L10 to L18 are not used for signal transmission in the SD I / F mode, but are dedicated signal lines used only for transmitting signals and voltages in the PCIe I / F mode.

[0056] The selector 116 connects the signal lines L1, L7 to L9 to one of the SD host interface circuit 114 and the PCIe host interface circuit 115 so that one of the data signals DAT3, DAT0, DAT1, and DAT2 in the SD I / F mode and the signals PERST#, REFCLK+, REFCLK-, and CLKREQ# in the PCIe I / F mode is transmitted via the signal lines L1, L7 to L9.

[0057] In the example of FIG. 5, the signal lines L1, L7 to L9 are connected to both the SD card interface circuit 212 and the PCIe card interface circuit 213. When the SD card 2 operates in the SD I / F mode, the terminals of the SD card interface circuit 212 connected to the signal lines L1, L7 to L9 are set to low impedance, while the terminals of the PCIe card interface circuit 213 connected to the signal lines L1, L7 to L9 are set to high impedance. This allows the data signals DAT0 to DAT3 to be transmitted between the SD host interface circuit 114 and the SD card interface circuit 212. Also, when the SD card 2 operates in the PCIe I / F mode, the terminals of the PCIe card interface circuit 213 connected to the signal lines L1, L7 to L9 are set to low impedance, while the terminals of the SD card interface circuit 212 connected to the signal lines L1, L7 to L9 are set to high impedance. As a result, the signals PERST#, REFCLK+, REFCLK−, and CLKREQ# are transmitted between the PCIe host interface circuit 115 and the PCIe card interface circuit 213.

[0058] The SD host interface circuit 114 and the SD card interface circuit 212 are DC-coupled to each other in order to transmit signals in a single-ended manner. The PCIe host interface circuit 115 and the PCIe card interface circuit 213 may be AC-coupled to each other via a capacitor Cac in order to transmit signals in a differential transmission manner. By using AC coupling, it is possible to reduce the influence of ground bounce and achieve high signal quality compared to DC coupling.

[0059] When the host device 1 operates in the SD I / F mode, the SD host interface circuit 114 controls the power supply circuit 113 to supply a power supply voltage of 3.3V to the SD card 2, and controls the selector 116 to connect the signal lines L1, L7 to L9 to the SD host interface circuit 114. As a result, the CPU 111 reads and writes data from and to the SD card 2 using the SD host interface circuit 114. Also, when the host device 1 operates in the PCIe I / F mode, the SD host interface circuit 114 controls the power supply circuit 113 to supply a power supply voltage of 3.3V and 1.8V to the SD card 2, and controls the selector 116 to connect the signal lines L1, L7 to L9 to the PCIe host interface circuit 115. As a result, the CPU 111 reads and writes data from and to the SD card 2 using the PCIe host interface circuit 115.

[0060] When the SD card 2 operates in the SD I / F mode, the CPU 211 transmits or receives data to be read from or written to the NAND flash memory 22 to or from the host device 1 using the SD card interface circuit 212. When the SD card 2 operates in the PCIe I / F mode, the CPU 211 transmits or receives data to be read from or written to the NAND flash memory 22 to or from the host device 1 using the PCIe card interface circuit 213.

[0061] [Operation of the embodiment] Hereinafter, the host device 1 and the SD card 2 according to the embodiment operate as follows.

[0062] [Initializing host device 1 and SD card 2] 6 is a timing chart showing an example of the initialization operation of the host device 1 and the SD card 2 according to the embodiment. When the SD card 2 is connected to the host device 1, or when the host device 1 to which the SD card 2 is connected is powered on, the host device 1 initializes the SD card 2. The initialization of the SD card 2 includes an initialization stage of the legacy SD interface, an initialization stage of the PCIe interface, and an initialization stage of the NAND flash memory 22.

[0063] The initialization stage of the legacy SD interface begins when the host device 1 supplies a power supply voltage VDD1 of 3.3 V to the SD card 2. When the power supply voltage VDD1 of 3.3 V is supplied, the SD card interface circuit 212 enters an operating state. The CPU 111 of the host device 1 communicates with the SD card interface circuit 212 using the SD host interface circuit 114 to execute the initialization stage of the legacy SD interface.

[0064] In the initialization stage of the legacy SD interface, the SD host interface circuit 114 transmits a clock signal SDCLK ​​to the SD card interface circuit 212 via the signal line L5. The SD host interface circuit 114 also controls the selector 116 to connect the signal lines L1, L7 to L9 to the terminals of the SD host interface circuit 114. Next, the SD host interface circuit 114 transmits a command signal Ci(a) inquiring about the specifications of the SD card 2 to the SD card interface circuit 212 via the signal line L2. The specifications of the SD card 2 include the capacity and data transmission speed of the SD card 2, whether the SD card 2 supports a PCIe interface, and the like. In response to the command signal Ci(a), the SD card interface circuit 212 transmits a response signal Ri(a) indicating the specifications of the SD card 2 to the SD host interface circuit 114 via the signal line L2.

[0065] If the response signal Ri(a) indicates that the SD card 2 supports the PCIe interface, the CPU 111 of the host device 1 ends the initialization stage of the legacy SD interface and starts the initialization stage of the PCIe interface. To end the initialization stage of the legacy SD interface, the SD host interface circuit 114 stops transmitting the clock signal SDCLK. In addition, the SD host interface circuit 114 controls the selector 116 to connect the signal lines L1, L7 to L9 to terminals of the PCIe host interface circuit 115.

[0066] The initialization stage of the PCIe interface is started by the host device 1 supplying a power supply voltage VDD2 of 1.8 V to the SD card 2. When the power supply voltage VDD2 of 1.8 V is supplied, the PCIe card interface circuit 213 enters an operating state. The CPU 111 of the host device 1 communicates with the PCIe card interface circuit 213 using the PCIe host interface circuit 115 to execute the initialization stage of the PCIe interface.

[0067] In the initialization stage of the PCIe interface, the PCIe host interface circuit 115 transmits a reference clock signal to the PCIe card interface circuit 213 via signal lines L7 and L8. Then, the PCIe host interface circuit 115 transmits a command signal Ci(1) instructing the initialization of the PCIe interface to the PCIe card interface circuit 213 via signal lines L11 and L12. The initialization of the PCIe interface includes generating a clock signal (e.g., 2 GHz) for the PCIe interface based on a reference clock signal (e.g., 100 MHz). The generation of the clock signal for the PCIe interface includes, for example, the PCIe host interface circuit 115 and the PCIe card interface circuit 213 performing a phase-locked loop and clock data recovery based on the reference clock signal to generate clock signals synchronized with each other. The PCIe card interface circuit 213 transmits a response signal Ri(1) indicating that the initialization of the PCIe interface has been completed to the PCIe host interface circuit 115 via signal lines L15 and L16.

[0068] After the initialization of the PCIe interface is completed, the CPU 111 of the host device 1 ends the initialization stage of the PCIe interface and starts the initialization stage of the NAND flash memory 22.

[0069] In the initialization stage of the NAND flash memory 22, the PCIe host interface circuit 115 transmits a command signal Ci(2) instructing the initialization of the NAND flash memory 22 to the SD card 2 via the signal lines L11 and L12. The initialization of the NAND flash memory 22 includes, for example, starting up the NAND flash memory 22, reading firmware for controlling the NAND flash memory 22, and updating a table for maintaining consistency between file data recorded in the NAND flash memory 22 and a management table. In response to the command signal Ci(2), the CPU 211 of the SD card 2 initializes the NAND flash memory 22. The PCIe card interface circuit 213 transmits a response signal Ri(2) indicating that the initialization of the NAND flash memory 22 has been completed to the PCIe host interface circuit 115 via the signal lines L15 and L16.

[0070] When the initialization of the NAND flash memory 22 is completed, the initialization of the SD card 2 is completed, and the host device 1 can access the NAND flash memory 22 through the PCIe interface. The PCIe host interface circuit 115 transmits a command signal C(1) instructing reading or writing from the NAND flash memory 22 to the PCIe card interface circuit 213 through the signal lines L11 and L12. The CPU 211 of the SD card 2 executes an operation associated with the command signal C(1) (i.e., reading or writing from the NAND flash memory 22). The PCIe card interface circuit 213 transmits a response signal R(1) in response to the command signal C(1) to the PCIe host interface circuit 115 through the signal lines L15 and L16. The response signal R(1) indicates that the operation associated with the command signal C(1) has been executed and completed, and includes data read from the NAND flash memory 22 or indicates the write result. Thereafter, reading and writing of data through the PCIe interface is performed in the same manner.

[0071] It should be noted that the above-mentioned procedure for initializing the SD card 2 is just an example, and other procedures can also be used.

[0072] [SD I / F mode and PCIe I / F mode] FIG. 7 is a diagram showing an architecture of the host device 1 and the SD card 2 according to the embodiment, and shows a case where the host device 1 and the SD card 2 operate in the SD I / F mode. FIG. 8 is a diagram showing an architecture of the host device 1 and the SD card 2 according to the embodiment, and shows a case where the host device 1 and the SD card 2 operate in the PCIe I / F mode. FIGS. 7 and 8 show a software hierarchy 300 of a program such as an operating system executed by the CPU 111 of the host device 1. In addition, FIGS. 7 and 8 show components of the card control circuit 21 other than the SD card interface circuit 212 and the PCIe card interface circuit 213 as a card control circuit 21A.

[0073] The software hierarchy 300 includes an SD driver 301, a PCIe / NVMe driver 302, a file system 303, and an application program 304. The SD driver 301 controls the SD host interface circuit 114, the SD card interface circuit 212, etc., and provides an interface to these devices. The PCIe / NVMe driver 302 controls the PCIe host interface circuit 115, the PCIe card interface circuit 213, etc., and provides an interface to these devices. The file system 303 indicates files and directories stored in the SD card 2 that are accessed via the SD driver 301 or the PCIe / NVMe driver 302. The application program 304 processes files included in the file system 303.

[0074] When the host device 1 and the SD card 2 operate in the SD I / F mode, the file system 303 accesses the NAND flash memory 22 via the SD driver 301, the SD host interface circuit 114, the SD card interface circuit 212, etc. When the host device 1 and the SD card 2 operate in the PCIe I / F mode, the file system 303 accesses the NAND flash memory 22 via the PCIe / NVMe driver 302, the PCIe host interface circuit 115, the PCIe card interface circuit 213, etc.

[0075] In the PCIe I / F mode using the differential transmission method, data can be transmitted at a higher speed than in the SD I / F mode using the single-ended method. However, in the PCIe I / F mode, the PCIe host interface circuit 115 and the PCIe card interface circuit 213 always generate clock signals synchronized with each other by performing a phase-locked loop and clock data recovery based on a reference clock signal. Therefore, in the PCIe I / F mode, power consumption is greater than that in the SD I / F mode to generate clock signals.

[0076] According to a conventional SD Express card, only one of the legacy SD interface and the PCIe interface is used exclusively. For example, when a battery-powered host device operates in the PCIe I / F mode and the remaining battery power is low, it may be required to switch from the PCIe I / F mode to the SD I / F mode in order to reduce power consumption. For example, in the case of a conventional SD Express card, in order to switch the communication mode, it is necessary to stop reading and writing data in the PCIe I / F mode once and initialize the SD interface to be used after the switch. In this case, data cannot be read or written for several seconds, which may impair user convenience. As a result, for example, if the host device is a digital camera, it will not be possible to take pictures for several seconds. Therefore, in a host device and an SD card that support both the SD I / F mode and the PCIe I / F mode, it is required to switch from the PCIe I / F mode to the SD I / F mode in a short time.

[0077] The host device 1 and SD card 2 according to the embodiment operate as described below, and are therefore capable of switching from the PCIe I / F mode to the SD I / F mode in a shorter time than in the past.

[0078] [Switching communication modes] 5, the signal lines L2 and L5 are dedicated signal lines that are not used for signal transmission in the PCIe I / F mode, but are used only for transmitting the signals CMD and SDCLK ​​in the SD I / F mode. Therefore, when the host device 1 and the SD card 2 are operating in the PCIe I / F mode, the host device 1 transmits a command signal to the SD card 2 via the signal line L2, instructing the SD card 2 to switch from the PCIe I / F mode to the SD I / F mode.

[0079] In order to instruct switching from the PCIe I / F mode to the SD I / F mode, for example, the IO_RW_DIRECT (or CMD52) command signal and its response signal defined in the SDIO specification can be used. The CMD52 command signal and its response signal are used to access one register in the register space of the SD card 2 in any I / O function. The register space accessible (Read / Write) using the IO_RW_DIRECT (or CMD52) command signal of the SD card 2 consists of, for example, up to 131072 1-byte registers provided inside or outside the CPU 211. This command reads or writes 1-byte data to a single register using only a pair of command signal and response signal. Typical uses include register initialization and monitoring of state values ​​of I / O functions. The CMD52 command signal and its response signal have formats shown in FIG. 9 and FIG. 10, respectively.

[0080] FIG. 9 is a diagram showing the format of a signal CMD transmitted between the host device 1 and the SD card 2 according to the embodiment, in which the signal CMD includes a CMD52 command signal transmitted from the host device 1 to the SD card 2. The CMD52 command signal includes a start bit (S), a direction bit (D), a command number, a read / write (R / W) flag, a function number, a RAW flag, stuff, a register address, stuff, write data or stuff, CRC7, and an end bit (E). The numbers under each field indicate the number of bits in the field. The command number field includes the bit string "110100", indicating that this signal is a CMD52 command signal. The register address field specifies one register in the register space. The write data or stuff field includes one byte of data to be written to the specified address if this signal instructs writing to a register, and includes a stuff bit if this signal instructs reading from a register.

[0081] 10 is a diagram showing the format of a signal CMD transmitted and received between the host device 1 and the SD card 2 according to the embodiment, in which the signal CMD includes a CMD52 response signal transmitted from the SD card 2 to the host device 1. The CMD52 response signal includes a start bit (S), a direction bit (D), a command number, a stuff bit, a response flag, read or write data, a CRC7, and an end bit (E). The command number field includes a bit string "110100", indicating that this signal is a CMD52 response signal. The read or write data includes data indicating the write result if the CMD52 command signal instructs writing to a register, and includes data read from a specified address if the CMD52 command signal instructs reading from a register.

[0082] A switching flag indicating switching from the PCIe I / F mode to the SD I / F mode is defined in a register at a predetermined address provided in the SD card 2. When switching from the PCIe I / F mode to the SD I / F mode, the SD host interface circuit 114 transmits a CMD52 command signal specifying a register including the switching flag to the SD card interface circuit 212. When the SD card interface circuit 212 receives this CMD52 command signal, the CPU 211 of the SD card 2 turns on the switching flag of the specified register. Next, the SD card interface circuit 212 transmits a CMD52 response signal indicating that the change of the switching flag has been completed to the SD host interface circuit 114. In this way, the host device 1 can instruct the SD card 2 to switch from the PCIe I / F mode to the SD I / F mode.

[0083] Thereafter, when the conditions described with reference to FIGS. 14 to 20 are satisfied, the CPU 111 switches the host device 1 from the PCIe I / F mode to the SD I / F mode, and the CPU 211 switches the SD card 2 from the PCIe I / F mode to the SD I / F mode.

[0084] Next, signal transmission when the host device 1 and the SD card 2 are switched from the PCIe I / F mode to the SD I / F mode will be described with reference to Figures 11 to 13. In Figures 11 to 13, solid signal lines indicate that a signal or voltage is being supplied, and dashed signal lines indicate that the supply of a signal or voltage is stopped.

[0085] 11 is a diagram for explaining signal transmission when the host device 1 and the SD card 2 according to the embodiment operate in the PCIe I / F mode. The power supply circuit 113 supplies power supply voltages of 3.3V and 1.8V to the SD card 2, and thus both the SD card interface circuit 212 and the PCIe card interface circuit 213 are in an operating state. The selector 116 connects the signal lines L1, L7 to L9 to the PCIe host interface circuit 115. The PCIe host interface circuit 115 transmits or receives signals PERST#, REFCLK+, REFCLK-, and CLKREQ# to or from the PCIe card interface circuit 213 via the signal lines L1, L7 to L9. In addition, the PCIe host interface circuit 115 transmits or receives signals PCIe Tx+, PCIe Tx-, PCIe Rx+, and PCIe Rx- to or from the PCIe card interface circuit 213 via the signal lines L11, L12, L15, and L16.

[0086] When the host device 1 and the SD card 2 operate in the PCIe I / F mode, the SD host interface circuit 114 stops sending and receiving the signals DAT0 to DAT3. In this case, the SD host interface circuit 114 may also stop sending and receiving the signal CMD and sending SDCLK.

[0087] 12 is a diagram for explaining signal transmission when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. When the transmission of the signal SDCLK ​​is stopped, the SD host interface circuit 114 resumes the transmission of the signal SDCLK ​​via the signal line L5. The SD host interface circuit 114 transmits a CMD52 command signal including an address including a switching flag to the SD card interface circuit 212 via the signal line L2. After that, when the conditions described with reference to FIGS. 14 to 20 are satisfied, the CPU 111 switches the host device 1 from the PCIe I / F mode to the SD I / F mode, and the CPU 211 switches the SD card 2 from the PCIe I / F mode to the SD I / F mode.

[0088] 13 is a diagram for explaining signal transmission when the host device 1 and the SD card 2 according to the embodiment operate in the SD I / F mode. The power supply circuit 113 stops the supply of the power supply voltage of 1.8V from the host device 1 to the SD card 2, and the PCIe card interface circuit 213 enters a pause state. The selector 116 connects the signal lines L1, L7 to L9 to the SD host interface circuit 114. The SD host interface circuit 114 transmits or receives data signals DAT3, DAT0, DAT1, and DAT2 to or from the SD card interface circuit 212 via the signal lines L1, L7 to L9. In addition, the SD host interface circuit 114 transmits or receives a signal CMD to or from the SD card interface circuit 212 via the signal line L2, and transmits a signal SDCLK ​​to the SD card interface circuit 212 via the signal line L5.

[0089] Next, with reference to FIGS. 14 to 20, the operation when the host device 1 and the SD card 2 are switched from the PCIe I / F mode to the SD I / F mode will be described.

[0090] FIG. 14 is a timing chart showing a first operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode.

[0091] In the initial state of FIG. 14, the host device 1 and the SD card 2 are in the PCIe I / F mode. The selector 116 connects the signal lines L1, L7 to L9 to the terminals of the PCIe host interface circuit 115. The PCIe host interface circuit 115 transmits a reference clock signal to the PCIe card interface circuit 213 via the signal lines L7 and L8. The PCIe host interface circuit 115 and the PCIe card interface circuit 213 generate a clock signal for the PCIe interface based on the reference clock signal. The PCIe host interface circuit 115 transmits command signals C(1) to C(N) to the PCIe card interface circuit 213 via the signal lines L11 and L12. The command signals C(1) to C(N) instruct reading or writing from the NAND flash memory 22. The CPU 211 of the SD card 2 executes the operation associated with the command signals C(1) to C(N) (i.e., reading or writing from the NAND flash memory 22). The PCIe card interface circuit 213 transmits response signals R(1) to R(N) in response to the command signals C(1) to C(N) to the PCIe host interface circuit 115 via signal lines L15 and L16. The response signals R(1) to R(N) indicate that the operations associated with the command signals C(1) to C(N) have been executed and completed, and include data read from the NAND flash memory 22 or indicate the write result.

[0092] When the host device 1 and the SD card 2 operate in the PCIe I / F mode, the SD host interface circuit 114 may stop transmitting the signals CMD and SDCLK.

[0093] For example, when the battery-driven host device 1 operates in the PCIe I / F mode and the remaining capacity of the battery falls below a threshold, the CPU 111 decides to switch the host device 1 and the SD card 2 from the PCIe I / F mode to the SD I / F mode. In this case, the CPU 111 instructs the SD host interface circuit 114 to instruct the SD card 2 to switch from the PCIe I / F mode to the SD I / F mode. The SD host interface circuit 114 first resumes transmission of the clock signal SDCLK ​​via the signal line L5. Next, the SD host interface circuit 114 transmits a command signal C(a) instructing the switching from the PCIe I / F mode to the SD I / F mode to the SD card interface circuit 212 via the signal line L2. The command signal C(a) may be, for example, a CMD52 command signal that designates a register including a switching flag, as described above. The CPU 211 of the SD card 2 turns on the switching flag of the designated register. Next, the SD card interface circuit 212 transmits a response signal R(a) to the command signal C(a) via signal line L2 to the SD host interface circuit 114. The response signal R(a) may be, for example, a CMD52 response signal indicating that the change of the switching flag has been completed, as described above.

[0094] After transmitting a command signal C(a) and receiving a response signal R(a), the CPU 111 of the host device 1 switches the host device 1 from the PCIe I / F mode to the SD I / F mode when there is no data to be transmitted in the PCIe I / F mode. When the host device 1 receives the response signals R(1)-R(N) to one or a series of command signals C(1)-C(N) that were being transmitted when the command signal C(a) was transmitted, the CPU 111 determines that there is no data to be transmitted in the PCIe I / F mode. In this case, the CPU 111 instructs the SD host interface circuit 114 to switch the host device 1 from the PCIe I / F mode to the SD I / F mode. The SD host interface circuit 114 controls the selector 116 to connect the signal lines L1, L7-L9 to the SD host interface circuit 114. After that, the SD host interface circuit 114 controls the power supply circuit 113 to stop the supply of the 1.8V power supply voltage from the host device 1 to the SD card 2. As a result, the CPU 111 reads and writes data from and to the SD card 2 using the SD host interface circuit 114 .

[0095] After switching the host device 1 from the PCIe I / F mode to the SD I / F mode, the SD host interface circuit 114 transmits command signals C(b), C(c), ..., which instruct the transmission of data via signal lines L1, L7 to L9, to the SD card interface circuit 212 via signal line L2. In the example of Fig. 14, the command signal C(b) instructs the host device 1 to read data from the SD card 2, and the command signal C(c) instructs the host device 1 to write data to the SD card 2.

[0096] When there is no data to be transmitted in the PCIe I / F mode after receiving the command signal C(a), the CPU 211 of the SD card 2 switches the SD card 2 from the PCIe I / F mode to the SD I / F mode. When the SD card 2 receives the first command signal C(b) from the host device 1 via the signal line L2 after receiving the command signal C(a), which instructs the transmission of data via the signal lines L1, L7 to L9, the CPU 211 determines that there is no data to be transmitted in the PCIe I / F mode. In this case, the CPU 211 transmits or receives data to be read from or written to the NAND flash memory 22 to or from the host device 1 using the SD card interface circuit 212.

[0097] The SD card interface circuit 212 transmits response signals R(b), R(c), ... in response to command signals C(b), C(c), ... to the SD host interface circuit 114 via signal line L2. After transmitting the response signal R(b), the SD card interface circuit 212 transmits a data signal D_read including data read from the NAND flash memory 22 to the SD host interface circuit 114 via signal lines L1, L7 to L9. After receiving the response signal R(c), the SD host interface circuit 114 transmits a data signal D_write to the SD card interface circuit 212 via signal lines L1, L7 to L9. The SD card interface circuit 212 writes the data included in the data signal D_write to the NAND flash memory 22.

[0098] The CPU 111 of the host device 1 may put the PCIe host interface circuit 115 into a suspend state when the host device 1 is switched from the PCIe I / F mode to the SD I / F mode. Also, the CPU 211 of the SD card 2 may put the PCIe card interface circuit 213 into a suspend state when the SD card 2 is switched from the PCIe I / F mode to the SD I / F mode.

[0099] Fig. 15 is a timing chart showing a second operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. Fig. 14 shows a case where operations associated with the command signals C(1) to C(N) are executed and completed in the order in which the command signals C(1) to C(N) are transmitted, and the corresponding response signals R(1) to R(N) are transmitted. However, in the PCIe I / F mode, the operations associated with the command signals C(1) to C(N) are not necessarily executed and completed in the order in which the command signals C(1) to C(N) are transmitted. Therefore, as shown in Fig. 15, the response signals R(1) to R(N) may be transmitted in an order different from the order in which the command signals C(1) to C(N) are transmitted. In this case as well, when the host device 1 receives response signals R(1)-R(N) to one or all of the series of command signals C(1)-C(N) that were being transmitted at the time of transmitting the command signal C(a), the CPU 111 of the host device 1 determines that there is no data to be transmitted in the PCIe I / F mode. Thereafter, the CPU 111 switches the host device 1 from the PCIe I / F mode to the SD I / F mode, in the same manner as described with reference to FIG.

[0100] FIG. 16 is a timing chart showing a third operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. After transmitting the command signal C(a), the PCIe host interface circuit 115 may retransmit the command signal C(n) when it does not receive a response signal R(n) within a predetermined time period T1 after transmitting the command signal C(n) (n=2 in the example of FIG. 16). In this case as well, when the host device 1 receives the response signals R(1)-R(N) to one or a series of command signals C(1)-C(N) that were being transmitted when the command signal C(a) was transmitted, the CPU 111 of the host device 1 determines that there is no data to be transmitted in the PCIe I / F mode. Thereafter, the CPU 111 switches the host device 1 from the PCIe I / F mode to the SD I / F mode in the same manner as described with reference to FIG. 14.

[0101] FIG. 17 is a timing chart showing a fourth operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. When the PCIe host interface circuit 115 receives an error signal C(ne) indicating that an operation associated with the command signal C(n) (n=2 in the example of FIG. 17) has been executed by the SD card 2 and failed, via the signal lines L15 and L16 from the PCIe card interface circuit 213, the PCIe host interface circuit 115 may retransmit the command signal C(n). In this case as well, when the host device 1 receives response signals R(1)-R(N) to all of the one or a series of command signals C(1)-C(N) that were being transmitted when the command signal C(a) was transmitted, the CPU 111 of the host device 1 determines that there is no data to be transmitted in the PCIe I / F mode. After that, the CPU 111 switches the host device 1 from the PCIe I / F mode to the SD I / F mode.

[0102] 18 is a timing chart showing a fifth operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. When the PCIe host interface circuit 115 receives a response signal R(n) to the retransmitted command signal C(n) as described with reference to FIG. 16, the SD host interface circuit 114 may retransmit the command signal C(a). After that, when there is no data to be transmitted in the PCIe I / F mode after receiving the response signal R(a) to the retransmitted command signal C(a), the CPU 111 of the host device 1 switches the host device 1 from the PCIe I / F mode to the SD I / F mode in the same manner as described with reference to FIG. 14.

[0103] 19 is a timing chart showing a sixth operation example when the host device 1 and the SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. When the PCIe host interface circuit 115 receives a response signal R(n) to the retransmitted command signal C(n) as described with reference to FIG. 17, the SD host interface circuit 114 may retransmit the command signal C(a). After that, when there is no data to be transmitted in the PCIe I / F mode after receiving the response signal R(a) to the retransmitted command signal C(a), the CPU 111 of the host device 1 switches the host device 1 from the PCIe I / F mode to the SD I / F mode in the same manner as described with reference to FIG. 14.

[0104] 20 is a timing chart showing a seventh operation example when the host device 1 and SD card 2 according to the embodiment are switched from the PCIe I / F mode to the SD I / F mode. The CPU 111 of the SD card 2 may switch the SD card 2 from the PCIe I / F mode to the SD I / F mode when the supply of the 1.8V power supply voltage from the host device 1 to the SD card 2 is stopped, instead of when the first command signal C(b) instructing the transmission of data via the signal lines L1, L7 to L9 is received (see FIG. 14).

[0105] 14 to 20, when there is no data to be transmitted in PCIe I / F mode, first the host device 1 is switched from the PCIe I / F mode to the SD I / F mode, and after the switching of the host device 1 is completed, the SD card 2 is switched from the PCIe I / F mode to the SD I / F mode. This makes it possible to prevent collision between the data signals DAT3, DAT0, DAT1, and DAT2 in the SD I / F mode transmitted via the signal lines L1, L7 to L9 and the signals PERST#, REFCLK+, REFCLK-, and CLKREQ# in the PCIe I / F mode.

[0106] According to the host device 1 and SD card 2 of the embodiment, the host device 1 transmits a command signal instructing a change in communication mode to the SD card 2 via the signal line L2 used only for signal transmission in the SD I / F mode. This allows the host device 1 and the SD card 2 to be switched from the PCIe I / F mode to the SD I / F mode without initializing the SD interface and the PCIe interface. Therefore, the host device 1 and the SD card 2 can be switched from the PCIe I / F mode to the SD I / F mode in a shorter time than before. For example, if the host device 1 is a digital camera, the length of time during which image capture is not possible can be shortened.

[0107] A typical SD Express card and host device consumes 0.72 to 1.8 W of power when operating in SD I / F mode, and 2 to 4 W of power when operating in PCIe I / F mode. When a battery-powered host device 1 operates in PCIe I / F mode and the remaining battery power falls below a threshold, the host device 1 and SD card 2 can be switched from the PCIe I / F mode to the SD I / F mode to reduce the power consumption of the host device 1 and SD card 2 and extend the operating time.

[0108] When the host device 1 and the SD card 2 operate in the PCIe I / F mode, the supply of the clock signal SDCLK ​​can be stopped, thereby further reducing power consumption.

[0109] [Effects of the embodiment] The communication method according to the embodiment transmits data between a host device 1 and an SD card 2. The host device 1 and the SD card 2 are connected to each other via a plurality of first signal lines and a plurality of second signal lines. The first signal lines include shared signal lines L1, L7 to L9 that are common to at least a portion of the second signal lines, and dedicated signal lines L2, L5 that are separate from the second signal lines. The host device 1 and the SD card 2 can operate in an SD I / F mode in which they transmit data to each other using a legacy SD protocol via the first signal lines, and in a PCIe I / F mode in which they transmit data to each other using a PCIe protocol via the second signal lines. This communication method includes a step of transmitting a first command signal, which instructs switching of the communication mode, from the host device 1 to the SD card 2 using the legacy SD protocol via the dedicated signal line L2 when the host device 1 and the SD card 2 are operating in the PCIe I / F mode. This communication method includes switching the host device 1 and the SD card 2 from the PCIe I / F mode to the SD I / F mode when there is no data to be transmitted in the PCIe I / F mode after transmitting the first command signal.

[0110] This allows the host device 1 and SD card 2, which support both the SD I / F mode and the PCIe I / F mode, to switch from the PCIe I / F mode to the SD I / F mode in a shorter time than before.

[0111] The communication method according to the embodiment includes transmitting a second command signal from the host device 1 to the SD card 2 using the PCIe protocol via a second signal line when the host device 1 and the SD card 2 are operating in the PCIe I / F mode, and transmitting a response signal to the second command signal from the SD card 2 to the host device 1 using the PCIe protocol via the second signal line. The switching step includes switching the host device 1 from the PCIe I / F mode to the SD I / F mode when the host device 1 receives a response signal to one or all of a series of second command signals that were being transmitted at the time of transmitting the first command signal.

[0112] This allows the host device 1 to switch from the PCIe I / F mode to the SD I / F mode when there is no data to be transmitted in the PCIe I / F mode.

[0113] The communication method according to the embodiment includes, after transmitting a first command signal, retransmitting the second command signal when the host device 1 does not receive a response signal to the second command signal within a predetermined time period after transmitting the second command signal, and retransmitting the first command signal when the host device 1 receives a response signal to the retransmitted second command signal.

[0114] This enables the host device to reliably transmit the first command signal, which instructs the SD card to switch the communication mode.

[0115] A communication method according to an embodiment includes: after transmitting a first command signal, when the host device 1 receives an error signal from the SD card 2 via a second signal line using the PCIe protocol indicating that an operation associated with the second command signal has been executed by the SD card 2 and failed, retransmitting the second command signal; and when the host device 1 receives a response signal to the retransmitted second command signal indicating that the operation associated with the second command signal has been executed by the SD card 2 and completed, retransmitting the first command signal.

[0116] This enables the host device to reliably transmit the first command signal, which instructs the SD card to switch the communication mode.

[0117] According to the communication method of the embodiment, the host device 1 includes an SD host interface circuit 114 that transmits or receives data to or from the SD card 2 using the legacy SD protocol via a first signal line, a PCIe host interface circuit 115 that transmits or receives data to or from the SD card 2 using the PCIe protocol via a second signal line, and a selector 116 that connects the shared signal lines L1, L7 to L9 to one of the SD host interface circuit 114 and the PCIe host interface circuit 115. The switching step includes controlling the selector 116 to connect the shared signal lines L1, L7 to L9 to the SD host interface circuit 114 instead of the PCIe host interface circuit 115.

[0118] This allows the host device 1 to switch from the PCIe I / F mode to the SD I / F mode.

[0119] According to the communication method of the embodiment, the switching step includes switching the SD card 2 from the PCIe I / F mode to the SD I / F mode when the SD card 2 receives, after receiving the first command signal, a third command signal instructing the transmission of data via the shared signal lines L1, L7 to L9 from the host device 1 via the dedicated signal line L2 using the legacy SD protocol.

[0120] This allows the SD card 2 to be switched from the PCIe I / F mode to the SD I / F mode.

[0121] According to the communication method of the embodiment, the host device 1 includes a power supply circuit 113 that supplies a first voltage that causes the SD card 2 to operate in the SD I / F mode and a second voltage that causes the SD card 2 to operate in the PCIe I / F mode to the SD card 2. The switching step includes controlling the power supply circuit 113 to stop supplying the second voltage from the host device 1 to the SD card 2.

[0122] This allows the host device 1 to switch from the PCIe I / F mode to the SD I / F mode.

[0123] According to the communication method of the embodiment, the switching step includes switching the SD card 2 from the PCIe I / F mode to the SD I / F mode when the supply of the second voltage from the host device 1 to the SD card 2 is stopped.

[0124] This allows the SD card 2 to be switched from the PCIe I / F mode to the SD I / F mode.

[0125] A host device 1 according to the embodiment is connected to an SD card 2 via a plurality of first signal lines and a plurality of second signal lines. The first signal lines include shared signal lines L1, L7 to L9 that are common to at least a portion of the second signal lines, and dedicated signal lines L2, L5 that are separate from the second signal lines. The host device 1 includes an SD host interface circuit 114 that transmits or receives data to the SD card 2 using a legacy SD protocol via the first signal lines, a PCIe host interface circuit 115 that transmits or receives data to the SD card 2 using a PCIe protocol via the second signal lines, and a CPU 111 that controls the SD host interface circuit 114 and the PCIe host interface circuit 115. The host device 1 can operate in an SD I / F mode in which data is transmitted to or received from the SD card 2 by the SD host interface circuit 114, and a PCIe I / F mode in which data is transmitted to or received from the SD card 2 by the PCIe host interface circuit 115. When the host device 1 is operating in the PCIe I / F mode, the CPU 111 controls the SD host interface circuit 114 to transmit a first command signal instructing switching of the communication mode to the SD card 2 via the dedicated signal line L2 using the legacy SD protocol. After transmitting the first command signal, when there is no data to be transmitted or received in the PCIe I / F mode, the CPU 111 controls the SD host interface circuit 114 and the PCIe host interface circuit 115 to switch the host device 1 from the PCIe I / F mode to the SD I / F mode.

[0126] This allows the host device 1, which supports both the SD I / F mode and the PCIe I / F mode, to switch from the PCIe I / F mode to the SD I / F mode in a shorter time than before.

[0127] The SD card 2 according to the embodiment is connected to the host device 1 via a plurality of first signal lines and a plurality of second signal lines. The first signal lines include shared signal lines L1, L7 to L9 that are common to at least a portion of the second signal lines, and dedicated signal lines L2, L5 that are separate from the second signal lines. The SD card 2 includes an SD card interface circuit 212 that transmits or receives data to the host device 1 using a legacy SD protocol via the first signal lines, a PCIe card interface circuit 213 that transmits or receives data to the host device 1 using a PCIe protocol via the second signal lines, and a CPU 211 that controls the SD card interface circuit 212 and the PCIe card interface circuit 213. The SD card 2 can operate in an SD I / F mode in which data is transmitted to or received from the host device 1 by the SD card interface circuit 212, and a PCIe I / F mode in which data is transmitted to or received from the host device 1 by the PCIe card interface circuit 213. When the SD card 2 is operating in the PCIe I / F mode, the CPU 211 receives a first command signal instructing switching of the communication mode from the host device 1 using the legacy SD protocol via the dedicated signal line L2 through the SD card interface circuit 212. After receiving the first command signal, when there is no data to be transmitted or received in the PCIe I / F mode, the CPU 211 controls the SD card interface circuit 212 and the PCIe card interface circuit 213 to switch the SD card 2 from the PCIe I / F mode to the SD I / F mode.

[0128] This makes it possible for an SD card 2 that supports both the SD I / F mode and the PCIe I / F mode to switch from the PCIe I / F mode to the SD I / F mode in a shorter time than before.

[0129] [Other embodiments] In order to instruct the SD card 2 to switch from the PCIe I / F mode to the SD I / F mode from the host device 1, other command signals and response signals transmitted via the signal line L2 may be used, in addition to the CMD52 command signal and response signal.

[0130] The SD card 2 may further include a selector that connects the signal lines L1, L7 to L9 to one of the SD card interface circuit 212 and the PCIe card interface circuit 213, similar to the selector 116 of the host device 1.

[0131] When switching the host device 1 and the SD card 2 from the SD I / F mode to the PCIe I / F mode, reading and writing of data may be stopped once, and the SD interface and the PCIe interface may be reinitialized as described with reference to FIG.

[0132] 3 shows a full-size SD card, the host device 1 and SD card 2 according to the embodiment may be configured as a miniSD card or a microSD card and its host device. Also, while Fig. 3 and Fig. 4 show a case where the SD card 2 has a one-lane PCIe interface, the host device 1 and SD card 2 according to the embodiment may have a two-lane (or more) PCIe interface.

[0133] The communication device and communication method according to the embodiment are not limited to an SD Express card having an SD interface and a PCIe interface, but can also be applied to any communication device and communication method that supports a plurality of communication modes.

[0134] [Summary of the embodiment] According to a first aspect of the present disclosure, 1. A communication method for transmitting data between a first communication device and a second communication device, comprising: the first and second communication devices are connected to each other via a plurality of first signal lines and a plurality of second signal lines, the first signal lines including a third signal line common to at least a portion of the second signal lines, and a fourth signal line separate from the second signal lines; the first and second communication devices are operable in a first communication mode in which they transmit data to each other using a first communication protocol via the first signal line, and in a second communication mode in which they transmit data to each other using a second communication protocol via the second signal line; The communication method includes: transmitting a first command signal, which instructs switching of a communication mode, from the first communication device to the second communication device via the fourth signal line using the first communication protocol when the first and second communication devices are operating in the second communication mode; and switching the first and second communication devices from the second communication mode to the first communication mode when there is no data to be transmitted in the second communication mode after transmitting the first command signal.

[0135] According to a second aspect of the present disclosure, in the first aspect, The communication method includes, when the first and second communication devices are operating in the second communication mode, transmitting a second command signal from the first communication device to the second communication device using the second communication protocol via the second signal line; transmitting a response signal to the second command signal from the second communication device to the first communication device using the second communication protocol via the second signal line; The step of switching includes switching the first communication device from the second communication mode to the first communication mode when the first communication device receives a response signal to one or all of a series of second command signals that were in transmission at the time of transmitting the first command signal.

[0136] According to a third aspect of the present disclosure, in the second aspect, The communication method includes, after transmitting the first command signal, retransmitting the second command signal when the first communication device does not receive a response signal to the second command signal within a predetermined time period after transmitting the second command signal; retransmitting the first command signal when the first communication device receives a response signal to the retransmitted second command signal.

[0137] According to a fourth aspect of the present disclosure, in the second or third aspect, The communication method includes, after transmitting the first command signal, retransmitting the second command signal when the first communication device receives an error signal from the second communication device via the second signal line using the second communication protocol, indicating that an operation associated with the second command signal was executed by the second communication device and failed; retransmitting the first command signal when the first communication device receives a response signal to the retransmitted second command signal indicating that an operation associated with the second command signal has been performed and completed by the second communication device.

[0138] According to a fifth aspect of the present disclosure, in one of the first to fourth aspects, The first communication device is a first communication circuit that transmits or receives data to or from the second communication device using the first communication protocol via the first signal line; a second communication circuit that transmits or receives data to or from the second communication device using the second communication protocol via the second signal line; a selector that connects the third signal line to one of the first and second communication circuits; The step of switching includes controlling the selector to connect the third signal line to the first communication circuit instead of the second communication circuit.

[0139] According to a sixth aspect of the present disclosure, in the fifth aspect, The switching step includes switching the second communication device from the second communication mode to the first communication mode when, after receiving the first command signal, the second communication device receives a third command signal from the first communication device via the fourth signal line using the first communication protocol, the third command signal instructing transmission of data via the third signal line.

[0140] According to a seventh aspect of the present disclosure, in one of the first to sixth aspects, the first communication device includes a power supply circuit that supplies to the second communication device a first voltage that causes the second communication device to operate in the first communication mode and a second voltage that causes the second communication device to operate in the second communication mode; The switching step includes controlling the power supply circuit to stop supplying the second voltage from the first communication device to the second communication device.

[0141] According to an eighth aspect of the present disclosure, in the seventh aspect, The step of switching includes switching the second communication device from the second communication mode to the first communication mode when supply of the second voltage from the first communication device to the second communication device is stopped.

[0142] According to a ninth aspect of the present disclosure, in one of the first to eighth aspects, When operating in the second communication mode, the first and second communication devices transmit data to each other at a higher data transmission rate than in the first communication mode and have greater power consumption than in the first communication mode.

[0143] According to a tenth aspect of the present disclosure, in one of the first to eighth aspects, the first communication protocol is a legacy SD protocol; The second communication protocol is a PCI Express protocol.

[0144] According to an eleventh aspect of the present disclosure, A communication device connected to an external device via a plurality of first signal lines and a plurality of second signal lines, the first signal line includes a third signal line shared with at least a portion of the second signal line, and a fourth signal line separate from the second signal line; The communication device includes: a first communication circuit that transmits or receives data to or from the external device using a first communication protocol via the first signal line; a second communication circuit that transmits or receives data to or from the external device using a second communication protocol via the second signal line; a processor that controls the first and second communication circuits; the communication device is operable in a first communication mode in which data is transmitted to or received from the external device by the first communication circuit, and in a second communication mode in which data is transmitted to or received from the external device by the second communication circuit; The processor, controlling the first communication circuit to transmit a first command signal, which instructs switching of a communication mode, to the external device via the fourth signal line using the first communication protocol when the communication device is operating in the second communication mode; and controlling the first and second communication circuits to switch the communication device from the second communication mode to the first communication mode when there is no data to be transmitted or received in the second communication mode after transmitting the first command signal.

[0145] According to a twelfth aspect of the present disclosure, A communication device connected to a host device via a plurality of first signal lines and a plurality of second signal lines, the first signal line includes a third signal line shared with at least a portion of the second signal line, and a fourth signal line separate from the second signal line; The communication device includes: a first communication circuit that transmits or receives data to or from the host device using a first communication protocol via the first signal line; a second communication circuit that transmits or receives data to or from the host device using a second communication protocol via the second signal line; a processor that controls the first and second communication circuits; the communication device is operable in a first communication mode in which data is transmitted to or received from the host device by the first communication circuit, and in a second communication mode in which data is transmitted to or received from the host device by the second communication circuit; The processor, receiving a first command signal, which instructs switching of a communication mode, from the host device by the first communication circuit via the fourth signal line using the first communication protocol when the communication device is operating in the second communication mode; After receiving the first command signal, when there is no data to be transmitted or received in the second communication mode, the first and second communication circuits are controlled to switch the communication device from the second communication mode to the first communication mode. [Industrial Applicability]

[0146] The present disclosure is applicable to communication devices and communication methods that support multiple communication modes, such as SD Express cards and their host devices. [Explanation of symbols]

[0147] 1. Host device 2 SD card 11 Host control circuit 12. Main memory 13 Socket 21, 21A Card control circuit 22 NAND Flash Memory 23 terminal group 110 Bus 111 CPU 112 ROM 113 Power supply circuit 114 SD host interface circuit 115 PCIe host interface circuit 116 Selector 210 Bus 211 CPU 212 SD card interface circuit 213 PCIe card interface circuit 214 NVMe controller 215 Buffer Memory 216 Buffer Controller 217 Encryption Engine 218 Sequencer 219 NAND Controller 300 Software Layers 301 SD driver 302 PCIe / NVMe Driver 303 File System 304 Application Program

Claims

1. 1. A method of transmitting data between a first and a second communication device, comprising: the first and second communication devices are connected to each other via a plurality of first signal lines and a plurality of second signal lines, the first signal lines including a third signal line common to at least a portion of the second signal lines, and a fourth signal line separate from the second signal lines; the first and second communication devices are operable in a first communication mode in which they transmit data to each other using a first communication protocol via the first signal line, and in a second communication mode in which they transmit data to each other using a second communication protocol via the second signal line; The communication method includes: transmitting a first command signal, which instructs switching of a communication mode, from the first communication device to the second communication device via the fourth signal line using the first communication protocol when the first and second communication devices are operating in the second communication mode; switching the first and second communication devices from the second communication mode to the first communication mode when there is no data to be transmitted in the second communication mode after transmitting the first command signal. Communication methods.

2. The communication method includes, when the first and second communication devices are operating in the second communication mode, transmitting a second command signal from the first communication device to the second communication device using the second communication protocol via the second signal line; transmitting a response signal to the second command signal from the second communication device to the first communication device using the second communication protocol via the second signal line; the step of switching includes switching the first communication device from the second communication mode to the first communication mode when the first communication device receives a response signal to one or all of a series of second command signals that were in transmission at the time of transmission of the first command signal. The communication method according to claim 1.

3. The communication method includes, after transmitting the first command signal, retransmitting the second command signal when the first communication device does not receive a response signal to the second command signal within a predetermined time period after transmitting the second command signal; and retransmitting the first command signal when the first communication device receives a response signal to the retransmitted second command signal. The communication method according to claim 2.

4. The communication method includes, after transmitting the first command signal, retransmitting the second command signal when the first communication device receives an error signal from the second communication device via the second signal line using the second communication protocol, indicating that an operation associated with the second command signal was executed by the second communication device and failed; retransmitting the first command signal when the first communication device receives a response signal to the retransmitted second command signal, the response signal indicating that an operation associated with the second command signal has been performed and completed by the second communication device. The communication method according to claim 2.

5. The first communication device is a first communication circuit that transmits or receives data to or from the second communication device using the first communication protocol via the first signal line; a second communication circuit that transmits or receives data to or from the second communication device using the second communication protocol via the second signal line; a selector that connects the third signal line to one of the first and second communication circuits; the step of switching includes controlling the selector to connect the third signal line to the first communication circuit instead of the second communication circuit. The communication method according to claim 1.

6. the step of switching includes switching the second communication device from the second communication mode to the first communication mode when the second communication device receives, after receiving the first command signal, a third command signal from the first communication device via the fourth signal line using the first communication protocol, the third command signal instructing transmission of data via the third signal line. The communication method according to claim 5.

7. the first communication device includes a power supply circuit that supplies to the second communication device a first voltage that causes the second communication device to operate in the first communication mode and a second voltage that causes the second communication device to operate in the second communication mode; the switching step includes controlling the power supply circuit to stop supplying the second voltage from the first communication device to the second communication device. The communication method according to claim 1.

8. the step of switching includes switching the second communication device from the second communication mode to the first communication mode when a supply of the second voltage from the first communication device to the second communication device is stopped. The communication method according to claim 7.

9. When operating in the second communication mode, the first and second communication devices transmit data to each other at a higher data transmission rate than in the first communication mode, and have a higher power consumption than in the first communication mode. A communication method according to one of claims 1 to 8.

10. the first communication protocol is a legacy SD protocol; The second communication protocol is a PCI Express protocol. A communication method according to one of claims 1 to 8.

11. A communication device connected to an external device via a plurality of first signal lines and a plurality of second signal lines, the first signal line includes a third signal line shared with at least a portion of the second signal line, and a fourth signal line separate from the second signal line; The communication device includes: a first communication circuit that transmits or receives data to or from the external device using a first communication protocol via the first signal line; a second communication circuit that transmits or receives data to or from the external device using a second communication protocol via the second signal line; a processor that controls the first and second communication circuits; the communication device is operable in a first communication mode in which data is transmitted to or received from the external device by the first communication circuit, and in a second communication mode in which data is transmitted to or received from the external device by the second communication circuit; The processor, controlling the first communication circuit to transmit a first command signal, which instructs switching of a communication mode, to the external device via the fourth signal line using the first communication protocol when the communication device is operating in the second communication mode; controlling the first and second communication circuits to switch the communication device from the second communication mode to the first communication mode when there is no data to be transmitted or received in the second communication mode after transmitting the first command signal. Communications equipment.

12. A communication device connected to a host device via a plurality of first signal lines and a plurality of second signal lines, the first signal line includes a third signal line shared with at least a portion of the second signal line, and a fourth signal line separate from the second signal line; The communication device includes: a first communication circuit that transmits or receives data to or from the host device using a first communication protocol via the first signal line; a second communication circuit that transmits or receives data to or from the host device using a second communication protocol via the second signal line; a processor that controls the first and second communication circuits; the communication device is operable in a first communication mode in which data is transmitted to or received from the host device by the first communication circuit, and in a second communication mode in which data is transmitted to or received from the host device by the second communication circuit; The processor, receiving a first command signal, which instructs switching of a communication mode, from the host device by the first communication circuit via the fourth signal line using the first communication protocol when the communication device is operating in the second communication mode; controlling the first and second communication circuits to switch the communication device from the second communication mode to the first communication mode when there is no data to be transmitted or received in the second communication mode after receiving the first command signal. Communications equipment.

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