Data processing apparatus

Abstract

To provide a data processing apparatus which can be restored early from a malfunction due to an abnormal serial clock waveform which is caused by noise or power supply fluctuation.SOLUTION: A data processing apparatus includes a master unit and a plurality of slave units, and communicates data between the master unit and the slave units based on I2C standard. The master unit includes: detection means which detects that a serial data line has been in an L level for a predetermined time; and output means which outputs, when the detection means detects that the serial data line has been in the L level for the predetermined time, dummy clocks to the serial clock line until the serial data line becomes an H level, or outputs dummy clocks to the serial clock line until the dummy clocks are output a predetermined number of times.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a data processing device. [Background technology]

[0002] 2. Description of the Related Art I2C (Inter-Integrated Circuit) is known as a serial data communication method between a master unit such as a microcomputer and a slave unit such as a sensor or an EEPROM (Electrically Erasable Programmable Read-Only Memory) (see, for example, Patent Documents 1 to 5). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-84792 A [Patent Document 2] JP 2017-38825 A [Patent Document 3] Japanese Patent Application Publication No. 9-265436 [Patent Document 4] JP 2016-95629 A [Patent Document 5] Special Publication No. 2002-534734 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-mentioned I2C, if the serial clock waveform becomes abnormal due to noise or power supply fluctuations when the master unit reads data from the slave unit, the serial data line is fixed at L level, and subsequent data communication may become impossible.

[0005] The present invention has been made in consideration of the above, and aims to provide a data processing device that can quickly recover even if an abnormality occurs when the serial clock waveform becomes abnormal due to noise or power supply fluctuations. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object, a data processing device according to one aspect of the present invention is a data processing device comprising a master unit and a plurality of slave units, and performing data communication between the master unit and the slave units according to the I2C standard. The master unit comprises a detection means for detecting that a serial data line is at L level for a predetermined time, and an output means for outputting a dummy clock to a serial clock line until the serial data line becomes H level or outputting the dummy clock to the serial clock line until a predetermined number of times is reached when the detection means detects that the serial data line is at L level for the predetermined time.

[0007] A data processing device according to an aspect of the present invention can quickly recover from an abnormality that occurs when the serial clock has an abnormal waveform due to noise or power supply fluctuation. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a data processing device according to a comparative example. [Diagram 2] FIG. 2 is an example of a time chart showing a process in which the master unit normally reads data from the slave unit. [Diagram 3] FIG. 3 is an example (1) of a time chart showing a case where an abnormality occurs when the master unit reads data from the slave unit. [Figure 4] FIG. 4 is an example (2) of a time chart showing a case where an abnormality occurs when the master unit reads data from the slave unit. [Diagram 5]FIG. 5 is a diagram (1) showing an example of the configuration of a data processing device that has measures in place to deal with abnormalities. [Figure 6] FIG. 6 is a diagram (2) showing an example of the configuration of a data processing device in which measures against abnormalities are implemented. [Figure 7] FIG. 7 is a flowchart (1) showing an example of processing of a data processing device in which measures against abnormalities are implemented. [Figure 8] FIG. 8 is a diagram illustrating an example of abnormality detection using an interval timer. [Figure 9] FIG. 9 is an example of a time chart including measures to be taken when an abnormality occurs when the master unit reads data from the slave unit. [Figure 10] FIG. 10 is a flowchart (2) showing a processing example of a data processing device in which measures against abnormalities are implemented. [Figure 11] FIG. 11 is a diagram illustrating an example of abnormality detection by input capture. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a data processing device according to an embodiment will be described with reference to the drawings. Note that the present invention is not limited to this embodiment. In addition, the dimensional relationship of each element in the drawings, the ratio of each element, etc. may differ from reality. Even between drawings, there may be parts with different dimensional relationships and ratios. In addition, the contents described in one embodiment or modified example are, in principle, similarly applicable to other embodiments or modified examples.

[0010] (Comparative Example) 1 is a diagram showing a configuration example of a data processing device 1 of a comparative example. In FIG. 1, the data processing device 1 includes a master unit 2 such as a microcomputer, and a plurality of slave units 31, 32, etc., each of which is made up of an IC (Integrated Circuit) such as a sensor or an EEPROM. The master unit 2 and the slave units 31, 32, etc. are connected to a ground line GND and a power supply line VDD, and are also connected to each other through serial clock lines SCL and serial data lines SDA. Pull-up resistors R1 and R2 are connected between the serial clock line SCL and the power supply line VDD, and between the serial data line SDA and the power supply line VDD, respectively. The output terminals of the master unit 2 and the slave units 31, 32, etc. are open drain, and when any output terminal connected to the line is short-circuited, the output terminals are at L level, and when all output terminals connected to the line are open, the output terminals are at H level due to the pull-up resistors R1 and R2.

[0011] 2 is an example of a time chart of the process in which the master unit 2 normally reads data from the slave unit side. For example, assume that data is read from the slave unit 31 with slave address "45H", and the slave unit 31 outputs the data "47H".

[0012] 2, for example, at time t1, the master unit 2 outputs a start condition to the serial clock line SCL and the serial data line SDA using a predetermined signal pattern. From the following times t2 to t8, the master unit 2 outputs "1000101" (1=H level, 0=L level) corresponding to the slave address "45H" to the serial data line SDA in sync with the clock of the serial clock line SCL. Then, at time t9, the master unit 2 outputs "1" corresponding to READ to the serial data line SDA in sync with the clock of the serial clock line SCL.

[0013] Next, at time t10, the slave unit 31 corresponding to the slave address "45H" outputs "0" corresponding to an acknowledgement (ACK) to the serial data line SDA in synchronization with the clock of the serial clock line SCL, and then, from time t11 to t18, the slave unit 31 outputs "01000111" corresponding to the data "47H" in synchronization with the clock of the serial clock line SCL. Next, at time t19, in the case of a read (READ), "1" (NAK) is output based on the I2C communication specifications. Then, at time t20, the master unit 2 outputs a stop condition to the serial clock line SCL and the serial data line SDA using a predetermined signal pattern, completing a series of communications.

[0014] 3 is an example of a time chart in which an error occurs when the master unit 2 reads data from the slave unit. As in FIG. 2, data is read from the slave unit 31 with slave address "45H", and the slave unit 31 attempts to output data "47H".

[0015] In Fig. 3, the process up until just before time t13 is the same as in Fig. 2, but from time t13 to t19, when the clock on the serial clock line SCL becomes abnormal due to noise or power supply fluctuation, the slave unit 31 continues to maintain the bit "0" of the data it was trying to output. That is, the master unit 2 detects the abnormality at time t19 because the NAK does not become the normal "1", and generally performs a retry, although this differs depending on the specifications. However, since the slave unit 31 is outputting data (READ DATA) of "0" (LOW) to the serial data line SDA, the bus becomes busy (BUS BUSY) state (SDA=LOW) and the retry process cannot be performed. As a result, subsequent data communication is not possible.

[0016] 4 is another example of a time chart showing a case where an error occurs when the master unit 2 reads data from the slave unit side. As in FIG. 2, data is read from the slave unit 31 with slave address "45H", and the slave unit 31 attempts to output data "47H".

[0017] In Fig. 4, the process up until just before time t10 is the same as in Fig. 2, but when the clock on the serial clock line SCL becomes abnormal at time t10 due to noise or power supply fluctuation, the acknowledgement (ACK) "0" that the slave unit 31 was about to output is read not at time t10 but at time t11, the next rising edge of the serial clock line SCL. Also, the data on the serial data line SDA is shifted to the next one at the falling edge of the serial clock line SCL, but since the clock on the serial clock line SCL does not arrive, the serial data line SDA remains at "0". After that, even if the master unit 2 tries to send data to the slave unit, it cannot send it because the bus is busy (SDA=LOW). As a result, no data communication can be performed after that.

[0018] (Examples of countermeasures) FIG. 5 is a diagram showing a configuration example of a data processing device 1 in which measures against abnormalities are taken. The difference from the configuration of the comparative example in FIG. 1 is that the general-purpose input / output terminal (GPIO: General Purpose Input / Output) of the master unit 2 is connected to the serial data line SDA as an "SDA LOW (GPIO) terminal", and the serial data line SDA being fixed to "0" (L level) by an interval timer or input capture is detected as an abnormality. In addition, the serial clock line SCL of the master unit 2 is switched to a general-purpose input / output terminal (GPIO) by software, and when an abnormality is detected, a dummy clock is output to the serial clock line SCL, and then a start condition and a stop condition are output by the serial clock line SCL and the serial data line SDA. Note that for products that can be restored from an abnormal state to a normal state by only the dummy clock, the output of the start condition and the stop condition can be omitted.

[0019] Fig. 6 is a diagram showing another example of the configuration of the data processing device 1 in which measures against abnormalities are implemented. The difference from the configuration in Fig. 5 is that the general-purpose input / output terminal of the master unit 2 is connected to the serial clock line SCL as an "SCL (GPIO) terminal", and when an abnormality is detected, a dummy clock is output to the serial clock line SCL, and a start condition and a stop condition are output by the serial clock line SCL and the serial data line SDA. Note that for products that can return from an abnormal state to a normal state using only the dummy clock, the output of the start condition and the stop condition can be omitted.

[0020] Fig. 7 is a flow chart showing an example of processing by the data processing device 1 with measures taken against abnormalities, and is an example of detecting an abnormality in which the serial data line SDA is fixed at "0" (L level) using an interval timer. Note that although the terminals of the master unit 2 used are different, this is a processing example common to Figs. 5 and 6.

[0021] 7, the illustrated process is started, for example, every 100 μsec. When the master unit 2 starts the process, it determines whether the serial data line SDA is at L (LOW) level (step S11).

[0022] When the master unit 2 determines that the serial data line SDA is not at L (LOW) level (No in step S11), it sets the variable TIMER to a count value "0" corresponding to 0 msec (step S12) and ends the process.

[0023] Furthermore, if the master unit 2 determines that the serial data line SDA is at L (LOW) level (Yes in step S11), it adds a count value "1" equivalent to 100 μsec to the variable TIMER (step S13).

[0024] Next, the master unit 2 judges whether the variable TIMER has reached (elapsed) a count value of "50", which corresponds to, for example, 5 msec as the time for judging an abnormality (step S14). Note that the time for judging an abnormality is determined within a range that exceeds the time during which the serial data line SDA becomes L level, which does not occur in normal operation, and does not exceed a time that affects other processes.

[0025] When the master unit 2 determines that the variable TIMER has not reached (elapsed) the count value "50", which corresponds to, for example, 5 msec as the time for determining that the variable TIMER is abnormal (No in step S14), the process ends.

[0026] Furthermore, if the master unit 2 determines that the variable TIMER has reached (elapsed) a count value of "50", which corresponds to, for example, 5 msec, as an abnormal time (Yes in step S14), it outputs a dummy clock to the serial clock line SCL (step S15).

[0027] Next, the master unit 2 determines whether the dummy clock has reached the maximum number of times (step S16).

[0028] When the master unit 2 determines that the dummy clock has not reached the maximum number of times (No in step S16), it determines whether the serial data line SDA has become H (HIGH) level (step S17).

[0029] When the master unit 2 determines that the serial data line SDA is not at H (HIGH) level (No in step S17), it continues outputting the dummy clock to the serial clock line SCL (step S15).

[0030] Furthermore, if the master unit 2 determines that the dummy clock has reached the maximum number of times (Yes in step S16) or that the serial data line SDA has become H (HIGH) level (Yes in step S17), it outputs a start condition (step S18), then outputs a stop condition (step S19), and ends the process.

[0031] This eliminates the problem of the serial data line SDA being fixed at the L level, and eliminates the inconvenience of subsequent data communication being unable to be performed.

[0032] Fig. 8 is a diagram showing an example of anomaly detection by an interval timer. In Fig. 8, for example, when the serial data line SDA goes to L level at time t01, the variable TIMER is incremented by 100 μsec at the time the process in Fig. 7 is started until the serial data line SDA goes to H level. Also, when the serial data line SDA goes to L level at time t03, the variable TIMER reaches 5 msec at time t04, and an anomaly is detected.

[0033] 9 is an example of a time chart including measures to be taken when an abnormality occurs when the master unit 2 reads data from the slave unit side. Reading is performed from the slave unit 31 with the slave address "45H", and the slave unit 31 attempts to output the data "47H", just like in FIGS. 2 to 4.

[0034] In Figure 9, when the serial data line SDA becomes "0" (L level) between time t1 and times t2 and t3, between times t6 and t7, between times t9 and t10, or between times t12 and t13, the variable TIMER in Figure 7 starts counting up from the "0" state.

[0035] Then, when the "0" (L level) state of the serial data line SDA reaches 5 msec between times t12 and t13 (time t101), it is determined that an abnormality has occurred. As a result, a dummy clock is output to the serial clock line SCL from time t101. Also, a start condition is output at time t103, and a stop condition is output at time t104. This causes a recovery from the abnormal state to a normal state, and subsequent data communication is carried out normally.

[0036] Fig. 10 is a flow chart showing another processing example of the data processing device 1 with measures taken against abnormalities, which is an example of detecting an abnormality in which the serial data line SDA is fixed at "0" (L level) using an input capture. Note that although the terminals of the master unit 2 used are different, this is a processing example common to Figs. 5 and 6.

[0037] In Fig. 10, the illustrated process may be started periodically or when an interrupt occurs. When started periodically, it is started at short, predetermined intervals, for example, by an interval timer. In this case, since no interrupts are used, there is an advantage that it does not affect the interrupt load.

[0038] When the master unit 2 starts processing, it determines whether or not an overflow interrupt request flag is present (set) (step S21). The overflow interrupt request flag is set when a predetermined time (e.g., 5 msec) has elapsed since the serial data line SDA became "0" (L level).

[0039] When the master unit 2 determines that there is no overflow interrupt request flag (No in step S21), the process ends.

[0040] When the master unit 2 determines that the overflow interrupt request flag exists (Yes in step S21), it clears the interrupt request flag (step S22).

[0041] Next, the master unit 2 outputs a dummy clock to the serial clock line SCL (step S23).

[0042] Next, the master unit 2 determines whether the dummy clock has reached the maximum number of times (step S24).

[0043] When the master unit 2 determines that the dummy clock has not reached the maximum number of times (No in step S24), it determines whether the serial data line SDA has become H (HIGH) level (step S25).

[0044] When the master unit 2 determines that the serial data line SDA is not at H (HIGH) level (No in step S25), it continues outputting the dummy clock to the serial clock line SCL (step S23).

[0045] Furthermore, if the master unit 2 determines that the dummy clock has reached the maximum number of times (Yes in step S24) or that the serial data line SDA has reached the H (HIGH) level (Yes in step S25), it outputs a start condition (step S26), then outputs a stop condition (step S27), and ends the process.

[0046] This eliminates the problem of the serial data line SDA being fixed at the L level, and eliminates the inconvenience of subsequent data communication being unable to be performed.

[0047] Fig. 11 is a diagram showing an example of abnormality detection by input capture. The master unit 2 starts counting when the serial data line SDA goes to L level (times t01 and t03), and sets an input capture overflow flag (overflow interrupt request flag) when a predetermined count value is reached (time t04). For example, if one count is 50 nsec, then 100,000 counts equals 5 msec. The time for one count can be changed using the peripheral functions of the microcontroller.

[0048] Moreover, the process in FIG. 10 is as follows when an interrupt occurs and is started. The interrupt in this case is an interrupt based on the input capture overflow flag in FIG. 11. In this case, there are cases where it is necessary to determine the cause of the interrupt and cases where it is not necessary to determine the cause of the interrupt. For example, when there is one interrupt vector address and one interrupt cause, it is not necessary to determine the cause of the interrupt. Also, there are cases where it is necessary to clear the interrupt flag and cases where it is not necessary to clear the interrupt flag (the interrupt flag is automatically cleared). For example, when there is one interrupt vector address and one interrupt cause, if an interrupt is permitted and an interrupt occurs, the interrupt request flag is generally automatically cleared. Also, when there is one interrupt vector address and two interrupt causes, if an interrupt is permitted and an interrupt occurs, it is necessary to determine which interrupt cause caused the interrupt after the interrupt occurs.

[0049] When it is necessary to determine the cause of the interrupt and it is necessary to clear the interrupt flag, the process is the same as that in Fig. 10. Also, when it is necessary to determine the cause of the interrupt and it is not necessary to clear the interrupt flag, the process of step S22 is unnecessary. Also, when it is not necessary to determine the cause of the interrupt and it is necessary to clear the interrupt flag, the process of step S21 is unnecessary. Also, when it is not necessary to determine the cause of the interrupt and it is not necessary to clear the interrupt flag, the processes of steps S21 and S22 are unnecessary.

[0050] Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention.

[0051] As described above, the data processing device according to the embodiment is a data processing device that includes a master unit and a plurality of slave units and performs data communication between the master unit and the slave units according to the I2C standard, and the master unit includes a detection means for detecting that the serial data line is at L level for a predetermined time, and an output means for outputting a dummy clock to the serial clock line until the serial data line becomes H level or outputting the dummy clock to the serial clock line until a predetermined number of times is reached when the detection means detects that the serial data line is at L level for the predetermined time. This allows for early recovery even if the serial clock becomes abnormal due to noise or power supply fluctuations, causing an abnormality.

[0052] The master unit further includes a second output means for outputting a start condition and a stop condition following the dummy clock, thereby making it possible to deal with products that cannot be restored from an abnormal state to a normal state by using only the dummy clock.

[0053] Furthermore, the master unit uses an interval timer to detect whether the serial data line is at L level for a predetermined period of time, which makes it easy to measure time for detecting an abnormality.

[0054] Furthermore, the master unit detects that the serial data line is at L level for a predetermined period of time using an input capture, which makes it easy to measure the time required for detecting an abnormality.

[0055] The predetermined time detected by the detection means is determined within a range exceeding the time during which the serial data line is at L level, which does not occur under normal operation, but not exceeding a time that does not affect other processes, thereby making it possible to appropriately respond to an abnormality.

[0056] Furthermore, the present invention is not limited to the above-mentioned embodiment. The present invention also includes a configuration in which the above-mentioned components are appropriately combined. Further effects and modifications can be easily derived by those skilled in the art. Therefore, the broader aspects of the present invention are not limited to the above-mentioned embodiment, and various modifications are possible. [Explanation of symbols]

[0057] 1 data processing device, 2 master unit, 31, 32 slave units, SCL serial clock line, SDA serial data line, GND ground line, VDD power supply line, R1 pull-up resistor, R2 pull-up resistor

Claims

1. A data processing device comprising a master unit and a plurality of slave units, and performing data communication between the master unit and the slave units according to an I2C standard, The master unit includes: A detection means for detecting that the serial data line is at an L level for a predetermined period of time; an output means for outputting a dummy clock to the serial clock line until the serial data line goes to an H level or until a predetermined number of times is reached when the detection means detects that the serial data line has been at an L level for a predetermined period of time; A data processing device comprising:

2. the master unit further comprises a second output means for outputting a start condition and a stop condition following the dummy clock; 2. A data processing apparatus according to claim 1.

3. the master unit detects that the serial data line is at L level for a predetermined period of time using an interval timer; 2. A data processing apparatus according to claim 1.

4. The master unit detects that the serial data line is at L level for a predetermined period of time using an input capture.

2. A data processing apparatus according to claim 1.

5. The predetermined time detected by the detection means is determined within a range exceeding a time during which the serial data line is at an L level, which does not occur in normal operation, and not exceeding a time that does not affect other processes.

2. A data processing apparatus according to claim 1.

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