Data processing apparatus

Abstract

To provide a data processing apparatus capable of reducing an influence on data communication with other slave units even when one of slave units fails.SOLUTION: A data processing apparatus includes a master unit and a plurality of slave units, and communicates data between the master unit and the slave units based on I2C standard. The master unit includes means which excludes a slave unit that failed to perform data communication normally, from a management table which manages presence / absence of the slave units, when data cannot be normally communicated with one of the slave units a predetermined number of times.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a data processing device. [Background technology]

[0002] 2. Description of the Related Art I2C (Inter-Integrated Circuit) is known as a serial data communication method between a master unit such as a microcomputer and a slave unit such as a sensor or an EEPROM (Electrically Erasable Programmable Read-Only Memory) (see, for example, Patent Documents 1 to 5). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-84792 A [Patent Document 2] JP 2017-38825 A [Patent Document 3] Japanese Patent Application Publication No. 9-265436 [Patent Document 4] JP 2016-95629 A [Patent Document 5] Special Publication No. 2002-534734 Summary of the Invention [Problem to be solved by the invention]

[0004] However, if a failure or the like occurs in any of the slave units and data communication becomes impossible, retry processing or the like must be repeated for that slave unit, which may affect data communication with other slave units.

[0005] The present invention has been made in consideration of the above, and aims to provide a data processing device that can reduce the impact on data communication between other slave units even if a failure or the like occurs in one of the slave units. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object, a data processing device according to one aspect of the present invention is a data processing device that includes a master unit and a plurality of slave units and performs data communication between the master unit and the slave units according to the I2C standard. The master unit includes a means for excluding a slave unit with which normal data communication has not been performed from a management table that manages the presence or absence of the slave units when normal data communication has not been performed with any of the slave units a predetermined number of times.

[0007] A data processing device according to an aspect of the present invention can reduce the effect on data communication with other slave units even if a failure or the like occurs in any of the slave units. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of a data processing device according to an embodiment. [Diagram 2] FIG. 2 is a flowchart (1) showing an example of processing by the data processing device. [Diagram 3] FIG. 3 is a flowchart (2) showing an example of processing by the data processing device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a data processing device according to an embodiment will be described with reference to the drawings. Note that the present invention is not limited to this embodiment. In addition, the dimensional relationship of each element in the drawings, the ratio of each element, etc. may differ from reality. Even between drawings, there may be parts with different dimensional relationships and ratios. In addition, the contents described in one embodiment or modified example are, in principle, similarly applicable to other embodiments or modified examples.

[0010] FIG. 1 is a diagram showing a configuration example of a data processing device 1 according to an embodiment. In FIG. 1, the data processing device 1 includes a master unit 2 such as a microcomputer, and a plurality of slave units 31 to 35 such as ICs (Integrated Circuits) such as sensors and EEPROMs. The master unit 2 and the slave units 31 to 35 are connected to a ground line GND and a power supply line VDD, respectively, and are connected to each other via serial clock lines SCL and serial data lines SDA. Pull-up resistors R1 and R2 are connected between the serial clock line SCL and the power supply line VDD, and between the serial data line SDA and the power supply line VDD, respectively. The output terminals of the master unit 2 and the slave units 31 to 35 are open drain, and when any output terminal connected to the line is short-circuited, the output terminals are at L level, and when all output terminals connected to the line are open, the output terminals are at H level due to the pull-up resistors R1 and R2. In the illustrated example, the number of slave units is five, but the number is not limited to five.

[0011] 2 is a flow chart showing an example of processing by the data processing device 1, which is processing when the master unit 2 writes or reads data to any of the slave units. Note that, although processing for a slave unit with a slave address of "42H" is shown as an example, the slave address differs depending on the slave unit being processed.

[0012] In FIG. 2, when the master unit 2 starts processing, it determines whether or not a slave unit with a slave address "42H" is in the management table T (is marked as "present" (valid)) (step S11).

[0013] If the master unit 2 determines that there is no slave unit with the slave address "42H" ("None" (invalid)) (No in step S11), the process ends.

[0014] Furthermore, if the master unit 2 determines that there is a slave unit with slave address "42H" (Yes in step S11), it initializes (sets to 0) the error count (step S12).

[0015] Next, the master unit 2 performs a process of writing or reading data to or from the slave unit at the slave address "42H" (step S13).

[0016] Next, the master unit 2 judges whether the process of writing or reading data to or from the slave unit at the slave address "42H" has ended normally (step S14).

[0017] When the master unit 2 determines that the process of writing or reading data to or from the slave unit at the slave address "42H" has ended normally (Yes in step S14), it ends the process.

[0018] Furthermore, if the master unit 2 determines that the data write or read process to the slave unit with the slave address "42H" did not end normally (No in step S14), it adds "1" to the error count (step S15).

[0019] Next, the master unit 2 judges whether the error count reaches "3" (step S16). Note that "3" is a threshold value for judging an abnormality, and can be changed depending on the environment.

[0020] If the master unit 2 determines that the error count has not reached "3" (No in step S16), it repeats the process from writing or reading data to or from the slave unit at slave address "42H" (step S13).

[0021] Furthermore, if the master unit 2 determines that the error count has reached "3" (Yes in step S16), it removes the slave unit with the slave address "42H" from the management table T (step S17). That is, it sets data meaning "none" (invalid) to the corresponding slave address. Then, the process ends.

[0022] As a result, data communication, including retry processing, will no longer be performed for the slave unit in which the abnormality occurred, and data communication for other slave units will not be affected.

[0023] 3 is a flowchart showing an example of processing by the data processing device 1, which is a process of writing data to a slave unit mainly composed of an EEPROM. Note that, although the processing for a slave unit with a slave address of "41H" is shown as an example, the slave address differs depending on the slave unit to be processed.

[0024] In FIG. 3, when the master unit 2 starts processing, it initializes (sets) the error count (step S21).

[0025] Next, the master unit 2 determines whether or not the slave unit with the slave address "41H" is in the management table T (is marked as "present" (valid)) (step S22).

[0026] If the master unit 2 determines that there is no slave unit with the slave address "41H" ("None" (invalid)) (No in step S22), the process ends.

[0027] Furthermore, if the master unit 2 determines that there is a slave unit with slave address "41H" (Yes in step S22), it performs an EEPROM write process on the slave unit with slave address "41H" (step S23).

[0028] Next, the master unit 2 performs an EEPROM read process on the slave unit with the same slave address "41H" (step S24).

[0029] Next, the master unit 2 compares the write data with the read data to determine whether or not they match (step S25).

[0030] When the master unit 2 determines that the written data and the read data match (Yes in step S25), it ends the process.

[0031] Moreover, if the master unit 2 determines that the write data and the read data do not match (No in step S25), it adds "1" to the error count (step S26).

[0032] Next, the master unit 2 judges whether the error count reaches "3" (step S27). Note that "3" is a threshold value for judging an abnormality, and can be changed depending on the environment.

[0033] If the master unit 2 determines that the error count has not reached "3" (No in step S27), it repeats the process from the EEPROM write process (step S23) for the slave unit with slave address "41H".

[0034] Furthermore, if the master unit 2 determines that the error count has reached "3" (Yes in step S27), it removes the slave unit with the slave address "41H" from the management table T (step S28). That is, it sets data meaning "none" (invalid) to the corresponding slave address. Then, the process ends.

[0035] As a result, data communication, including retry processing, will no longer be performed for the slave unit in which the abnormality occurred, and data communication for other slave units will not be affected.

[0036] Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention.

[0037] As described above, the data processing device according to the embodiment is a data processing device that includes a master unit and a plurality of slave units and performs data communication between the master unit and the slave units according to the I2C standard, and the master unit includes a means for excluding a slave unit with which normal data communication has not been performed from a management table that manages the presence or absence of the slave units when normal data communication with any of the slave units has not been performed a predetermined number of times. This makes it possible to reduce the impact on data communication with other slave units even if a failure or the like occurs in any of the slave units.

[0038] In addition, the master unit writes data to the slave unit, which mainly uses EEPROM, and then reads the written data, and if the written data and the read data do not match a specified number of times, it determines that normal data communication was not performed. This allows for checking for abnormalities during normal EEPROM writing and excluding the slave unit from communication targets.

[0039] Furthermore, the master unit refers to the management table when communicating data with the slave unit, and if the slave unit is determined to be non-existent, does not communicate data with the slave unit. This avoids data communication with a slave unit in which an abnormality has occurred, thereby saving time.

[0040] The management table also associates the slave addresses of all the slave units with the presence or absence of the slave units, thereby making it possible to specifically configure the management table.

[0041] Furthermore, the present invention is not limited to the above-mentioned embodiment. The present invention also includes a configuration in which the above-mentioned components are appropriately combined. Further effects and modifications can be easily derived by those skilled in the art. Therefore, the broader aspects of the present invention are not limited to the above-mentioned embodiment, and various modifications are possible. [Explanation of symbols]

[0042] 1 Data processing device, 2 Master unit, 31-35 Slave units

Claims

1. A data processing device comprising a master unit and a plurality of slave units, and performing data communication between the master unit and the slave units according to an I2C standard, the master unit is provided with a means for excluding a slave unit with which normal data communication has not been performed a predetermined number of times from a management table for managing the presence or absence of the slave units, when the master unit has not been able to perform normal data communication with any of the slave units a predetermined number of times; Data processing device.

2. the master unit writes data to the slave unit mainly made up of an EEPROM, and then reads the written data, and if the written data and the read data do not match a predetermined number of times, determines that normal data communication has not been performed; 2. A data processing apparatus according to claim 1.

3. the master unit refers to the management table when performing data communication with the slave unit, and if the slave unit is determined to be non-existent, does not perform data communication with the slave unit; 2. A data processing apparatus according to claim 1.

4. The management table associates the slave addresses of all the slave units with the presence or absence of the slave units.

2. A data processing apparatus according to claim 1.

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