Multilayer wiring board, semiconductor device, and method for designing the same

Abstract

To provide a semiconductor device capable of suppressing warpage.SOLUTION: According to one aspect of the present invention, there is provided a semiconductor device including: a multilayer wiring board which includes a core substrate and in which a plurality of conductor layers and a plurality of insulating resin layers are formed on both sides of the core substrate; and a semiconductor element which is mounted on at least one side of the multilayer wiring board via connection terminals. When Y ppm / °C denotes a linear expansion coefficient of a core resin constituting the core substrate, and X ppm / °C denotes a linear expansion coefficient of the insulating resin layers, 10≤X≤25, 0.5≤Y, and Y≤-0.23X+11 are satisfied. Thus, warpage can be suppressed in a temperature cycle test. By selecting linear expansion coefficients of a core resin and insulating resin layers, there is provided a multilayer wiring board on which a highly reliable semiconductor element suppressed in warpage can be mounted.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a multilayer wiring board on which electronic components such as semiconductor elements (chips) can be mounted, a semiconductor device on which the semiconductor elements are mounted, and a method for designing the same. [Background technology]

[0002] In recent years, as semiconductor devices have become more sophisticated, the size of semiconductor elements has increased, and the size of multilayer wiring boards for mounting semiconductor elements, such as FC-BGA (Flip Chip-Ball Grid Array) has also increased. As the size of semiconductor devices made of multilayer wiring boards increases, warping that occurs when heated and cooled tends to increase.

[0003] As a result, when the semiconductor device is warped, the joint between the semiconductor element and the multilayer wiring board is easily broken, which is a problem, especially when a thermal load is applied, such as in a temperature cycle test.

[0004] Patent Document 1 discloses a technique for adjusting the wiring density of electrodes formed on a multilayer substrate by forming a plurality of holes in at least a part of a planar ground electrode provided on the multilayer substrate, thereby reducing warpage of the multilayer substrate. Specifically, the multilayer substrate 1 is formed using a laminate in which a plurality of insulating layers L1-L6 and electrodes 2, 3 are laminated, and the electrodes 2, 3 at least include a planar ground electrode 2 provided on any one of the insulating layers L1-L6, and a plurality of holes 4 are formed in at least a part of the ground electrode 2 to adjust the wiring density of the electrodes 2, 3 formed on the multilayer substrate 1, thereby reducing warpage of the multilayer substrate 1, and a module including the multilayer substrate is disclosed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2013 / 054808 Summary of the Invention [Problem to be solved by the invention]

[0006] In Patent Document 1, multiple holes are formed in the ground electrode to adjust the wiring density of the multilayer board. Therefore, in order to reduce warping of the multilayer board, the number and size of holes to be placed in the ground electrode must be determined for each individual wiring board, making the design process complicated.

[0007] The present invention was created in consideration of the problems in the conventional technology, and aims to provide a multilayer wiring board, a semiconductor device, and a design method thereof that can suppress warping by selecting the linear expansion coefficient of the core resin and insulating resin layer of the core substrate that constitutes the multilayer wiring board. [Means for solving the problem]

[0008] In order to solve the above problems, one representative multilayer wiring board of the present invention is A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which a core board, insulating resin layers using an organic insulating material on both sides of the core board, and wiring layers using a conductive material are alternately laminated, When the linear expansion coefficient of the core resin constituting the core substrate of the multilayer wiring board is Y ppm / °C and the linear expansion coefficient of the insulating resin layer is X ppm / °C, 10≦X≦25 and Y≦−0.23X+11 are satisfied. Effect of the Invention

[0009] According to the present invention, it is possible to provide a multilayer wiring board, a semiconductor device, and a design method thereof that can suppress warping by selecting the linear expansion coefficient of the core resin and the insulating resin layer of the core substrate that constitutes the multilayer wiring board. [Brief description of the drawings]

[0010] [Figure 1]FIG. 1 is a cross-sectional view of a multilayer wiring board according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the semiconductor device according to the second embodiment. [Diagram 3] FIG. 3 is a plan view of the semiconductor device according to the second embodiment. [Figure 4] Figure 4 is a cross-sectional view showing the thermal expansion of a rod with one end fixed. [Diagram 5] FIG. 5 is a cross-sectional view of a rod with both ends fixed. [Figure 6] FIG. 6 is a diagram explaining two types of warping states. [Figure 7] FIG. 7 is an explanatory diagram showing an example of a method for manufacturing a core substrate. [Figure 8] FIG. 8 is an explanatory diagram showing a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 9] FIG. 9 is an explanatory diagram showing a method for manufacturing a multilayer wiring board according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the drawings. The dimensional ratios in the drawings may differ from the actual ratios for the convenience of explanation, and the number of layers or part of the configuration may be omitted from the drawings. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc. disclosed in the drawings.

[0012] In this disclosure, "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Additionally, "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing when a plate-shaped member or a layer contained in the plate-shaped member is illustrated. Additionally, the "upper surface" and "lower surface" may also be referred to as the "first surface" and the "second surface". Moreover, the surface farther from the core substrate may be referred to as the outer surface.

[0013] In addition, "upward" refers to the vertically upward direction when a plate-like member or layer is placed horizontally. Furthermore, "upward" and its opposite, "downward," are sometimes referred to as the "Z-axis positive direction" and the "Z-axis negative direction," and the horizontal direction is sometimes referred to as the "X-axis direction" and the "Y-axis direction."

[0014] Furthermore, the term "layer" does not necessarily refer to a state in which an object is uniformly formed. It may refer to an object having a pattern with gaps, or a collection of individual objects. For example, the term "conductor layer" may refer to multiple conductors formed on the same surface among surfaces parallel to the main surface of a core substrate.

[0015] <First embodiment> A first embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view showing a multilayer wiring board according to a first embodiment of the present invention. It should be noted that a semiconductor element can be mounted on the multilayer wiring board of the present disclosure by applying flip chip connection via solder bumps.

[0016] In FIG. 1, the multilayer wiring board 100 includes a core substrate 1, a plurality of insulating resin layers 11, and a plurality of conductor layers 13. (Core Board) In the first embodiment, the core substrate 1 includes a core resin 1', through holes 3 for electrically connecting the front and back surfaces, a hole-filling resin 4 filled in the through holes, a conductor layer 23, a conductor layer (pad portion) 43, and the like. The core resin 1' is formed of, for example, a fiber-reinforced composite material. A fiber-reinforced composite material is a material in which a woven or non-woven fabric such as glass fiber, carbon fiber, or aramid fiber is impregnated with a thermosetting insulating resin such as an epoxy resin. By using the core resin 1' as a fiber-reinforced composite material, it is possible to improve the strength, dimensional stability, and the like compared to the case where a thermosetting insulating resin such as an epoxy resin is used alone. The thermosetting insulating resin such as epoxy resin to be impregnated may contain a filler made of an organic or inorganic material. In the first embodiment, a glass epoxy material is used in which glass cloth is impregnated with epoxy resin. In addition, the glass cloth, filler, etc. are omitted from each figure.

[0017] In the first embodiment, the thickness of the core resin 1' is preferably 0.4 mm to 2.0 mm. If the thickness of the core resin 1' is less than 0.4 mm, the rigidity is low and warping is likely to occur. On the other hand, if the thickness of the core resin 1' is more than 2 mm, it may be difficult to form the through hole 3, or the through hole 3 may become too long, which may deteriorate the electrical characteristics.

[0018] (insulating resin layer) The insulating resin layer 11 can be made of a thermosetting resin, a thermoplastic resin, a photosensitive resin, or a resin mixture thereof. For example, it can be made of an epoxy resin, an acrylic resin, a phenolic resin, a melamine resin, a silicone resin, a polyimide resin, a polyphenylene ether resin, a maleimide resin, a liquid crystal polymer, a fluororesin, or a combination of two or more of these, and may contain an inorganic filler or an organic filler. For the inorganic filler, a material to which silica, titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added can be used. By containing a filler, it becomes possible to reduce the linear expansion coefficient of the insulating resin layer 11. Inorganic fillers are more preferable than organic fillers because they have a greater effect of reducing the linear expansion coefficient.

[0019] In the first embodiment, when the linear expansion coefficient of the core resin 1' is Y ppm / °C and the linear expansion coefficient of the insulating resin layer 11 is X ppm / °C, X and Y are selected so as to satisfy the conditions shown in the following formulas (1) and (2). 10≦X≦25 (1) Y≦―0.23X+11 (2) By selecting and using materials in which the linear expansion coefficient Y of the core resin 1' and the linear expansion coefficient X of the insulating resin layer 11 satisfy the condition shown in formula (1), it is possible to reduce the amount of warping in a temperature cycle test. Specifically, it is possible to make the absolute value of the amount of warping at the lowest temperature in the temperature cycle test less than 0.5% of the size of the semiconductor element mounted on the multilayer wiring board 100. The method of deriving equation (1) will be described later.

[0020] If the absolute value of the amount of warping at the lowest temperature in the temperature cycle test is 0.5% or more of the semiconductor element size, the load on the solder bumps 20 of the multilayer wiring board 100 will increase, and there is a risk of breakage such as cracks occurring. Due to temperature changes after mounting the semiconductor element on the multilayer wiring board 100, peeling at the interface between the semiconductor element 34 and the underfill resin 35, and between the underfill resin 35 and the multilayer wiring board 100, cracks in the underfill resin 35, and the like may occur.

[0021] The coefficient of linear expansion (CTE) is a value that indicates the rate of change in length in response to an increase in temperature within a predetermined temperature range. The coefficient of linear expansion is obtained by measurement using a thermomechanical analyzer. In the first embodiment, the coefficient of linear expansion of the insulating resin layer 11 is obtained by measurement using a thermomechanical analyzer. In this embodiment, the coefficient was obtained from a temperature range of 30°C to 120°C. Moreover, the coefficient of linear expansion of the core resin 1' was obtained from a temperature range of 30°C to 240°C.

[0022] If the linear expansion coefficient of the insulating resin layer 11 is less than 10 ppm / °C and more than 25 ppm / °C, there is a risk of peeling or cracks occurring due to stress caused by the difference with the linear expansion coefficient of 17 ppm / °C of copper used in the conductor layer 13. For this reason, in the first embodiment, a material with a linear expansion coefficient of 10 to 25 ppm / °C is selected for the insulating resin layer 11, and the linear expansion coefficient of the core resin 1' is accordingly selected to satisfy the condition of the above formula (1) to design the multilayer wiring board.

[0023] The tensile modulus (Young's modulus) of the insulating resin layer 11 is not particularly limited. The tensile modulus reflects the elastic properties of a material and is a value that indicates how difficult the material is to deform. The tensile modulus is obtained by measurement using a tensile tester. By measuring while heating, the storage modulus at a desired temperature can be measured.

[0024] Other elements constituting the multilayer wiring board 100 will be described later in the explanation of the second embodiment and examples.

[0025] <Second embodiment> Next, a semiconductor device according to a second embodiment will be described with reference to FIGS. Fig. 2 is a cross-sectional view of the semiconductor device 200 according to the second embodiment, and Fig. 3 is a plan view of the semiconductor device 200 according to the second embodiment. The second embodiment differs from the first embodiment in that a semiconductor element 34 is mounted on one surface of the multilayer wiring board described in the first embodiment.

[0026] In FIG. 2, a semiconductor element 34 is joined to a multilayer wiring board 100 by solder bumps 20, and an underfill resin 35 is filled between the semiconductor element 34 and the multilayer wiring board 100. In addition, in FIG. 3, the area indicated by the dotted line A indicates the area where the semiconductor element 34 is mounted. In the following description, the same or equivalent components as those in the first embodiment described above are denoted by the same reference numerals, and the description thereof will be simplified or omitted.

[0027] (Semiconductor element) The semiconductor element 34 (silicon chip) may be an IC, an LSI, etc. The solder bumps 20 may be made of solder such as Sn, Sn--Pb, Sn--Ag, Sn--Cu, Sn--Ag--Cu, or Sn--Bi.

[0028] (Underfill resin) The underfill resin 35 may be, for example, a material in which one or more of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin are mixed together to which a filler such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide is added.

[0029] (Warpage simulation) A simulation of warpage was carried out for a semiconductor device having a structure similar to that of the semiconductor device 200 shown in FIG.

[0030] <Derivation of Equations (1) and (2)> (finite element method) In this disclosure, a warpage simulation was performed using structural analysis by the finite element method. The finite element method (FEM) is a method of virtually dividing a structure into a finite number of elements and performing numerical analysis, and numerical analysis is the approximation of a differential equation. In addition, structural analysis is a method of inputting the shape, material, boundary conditions (load, constraint), etc., and obtaining the displacement, stress, and strain using numerical analysis. In static structural problems, equations for load and displacement, displacement and strain, and stress and strain are constructed and solved, and the basic equation is expressed as F=kx (F: load, k: stiffness, x: displacement). Structural analysis using the finite element method is generally performed using a computer and dedicated software. In this invention, the structural analysis software ANSYS Mechanical was used.

[0031] In a structure in which one end of a rod is fixed as shown in Figure 4, when a temperature change causes the shape to change from the solid line to the dotted line, the change in length Δl is expressed as the product of the linear expansion coefficient α and the temperature difference ΔT over length l (Δl = αlΔT). Also, when a temperature change occurs in a structure in which both ends of a rod are fixed as shown in Figure 5, the shape does not change because both ends of the rod are fixed, but thermal stress occurs. Thermal stress σt is expressed as the product of the linear expansion coefficient α, the tensile modulus of elasticity E, and the temperature difference ΔT (σt = αΔTE). In other words, the linear expansion coefficient α is involved in deformation and stress due to temperature changes. This time, the inventors of the present invention have hypothesized that the warpage can be controlled by controlling the linear expansion coefficient, while ignoring the tensile elastic modulus as the main factor that causes warpage in a multilayer wiring board. Specifically, for example, in a multilayer wiring board 100 having a thickness of 2 mm, the inventors have focused on the linear expansion coefficients of the core resin 1' and the insulating resin layer 11, which are thicker materials, on the premise that the thickness of the core resin 1' is 1.2 mm and the total thickness of the insulating resin layer 11 is 0.46 mm.

[0032] (Simulation model) As shown in FIG. 3, a model was created for a semiconductor device in which a semiconductor element is mounted in region A (hereinafter, referred to as "semiconductor device model M"). The semiconductor device model M has a rectangular planar shape of 20 mm x 20 mm, a semiconductor element thickness of 0.55 mm, a core resin 1' thickness of 1.2 mm, a total thickness of the conductor layer 13 of 15 μm, a total thickness of the insulating resin layer 11 of 30 μm, and a total thickness of the front and rear of the solder resist layer 17 of 15 μm. In the semiconductor device model M, the volume ratio of the wiring part and the via part in the conductor layer and the insulating resin layer on the semiconductor element side is 31%, and the volume ratio of the wiring part and the via part in the conductor layer and the insulating resin layer on the other side of the multilayer wiring board 100 is 29%. The warpage at -55°C when a temperature cycle test (-55°C to 125°C) was performed on the semiconductor device model M was simulated using structural analysis software ANSYS Mechanical. In the warpage simulation, the positive direction in which warpage occurs means that the center of the semiconductor device model M goes down and the ends go up, as shown in FIG. 6(a), and the negative direction means that the center of the semiconductor device model M goes up and the ends go down, as shown in FIG. 6(b).

[0033] Table 1 shows the results of the warpage simulation. [Table 1] Table 1 shows the warpage when the linear expansion coefficient of the insulating resin layer 11 and the linear expansion coefficient of the core resin 1' are changed. The warpage values ​​shown in Table 1 are all negative values, and warpage occurs in the negative direction. Here, when the linear expansion coefficient of the insulating resin layer 11 is X ppm / °C and the linear expansion coefficient of the core resin 1' is Y ppm / °C, the conditions under which the absolute value of the amount of warping is less than 0.5% of the semiconductor element size were analyzed, and the conditions of the following equations (1) and (2) were obtained. 10≦X≦25 (1) Y≦―0.23X+11 (2)

[0034] (verification) In order to verify the validity of the condition settings determined by the above formulas (1) and (2), simulations were performed by setting various values ​​for the linear expansion coefficient X of the insulating resin layer 11 and the linear expansion coefficient Y of the core layer, and the results of the following Examples 1 to 9 and Comparative Examples 1 and 2 were obtained.

[0035] In Example 1, the linear expansion coefficient of the core resin 1' was 6.5 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 10 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 10 GPa. At this time, the semiconductor device model M was warped by 89 μm in the negative direction.

[0036] In Example 2, the linear expansion coefficient of the core resin 1' was 5 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 10 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 10 GPa. At this time, the semiconductor device model M was warped by 82 μm in the negative direction.

[0037] In Example 3, the linear expansion coefficient of the core resin 1' was 5 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 20 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 10 GPa. At this time, the semiconductor device model M was warped by 93 μm in the negative direction.

[0038] In Example 4, the linear expansion coefficient of the core resin 1' was 0.5 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 10 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 10 GPa. At this time, the semiconductor device model M was warped by 61 μm in the negative direction.

[0039] In Example 5, the linear expansion coefficient of the core resin 1' was 0.5 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 25 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 10 GPa. At this time, the semiconductor device model M was warped by 77 μm in the negative direction.

[0040] In Example 6, the linear expansion coefficient of the core resin 1' was 5 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 10 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 4 GPa. At this time, the semiconductor device model M was warped by 79 μm in the negative direction.

[0041] In Example 7, the linear expansion coefficient of the core resin 1' was 5 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 10 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 16 GPa. At this time, the semiconductor device model M was warped by 85 μm in the negative direction.

[0042] In Example 8, the linear expansion coefficient of the core resin 1' was 0.5 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 25 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 4 GPa. At this time, the semiconductor device model M was warped by 69 μm in the negative direction.

[0043] In Example 9, the linear expansion coefficient of the core resin 1' was 0.5 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 25 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 16 GPa. At this time, the semiconductor device model M was warped by 83 μm in the negative direction.

[0044] In Comparative Example 1, the linear expansion coefficient of the core resin 1' was 8 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 30 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 10 GPa. In this case, the semiconductor device model M was warped by 117 μm in the negative direction.

[0045] In Comparative Example 2, the linear expansion coefficient of the core resin 1' was 11 ppm / ° C., the linear expansion coefficient of the insulating resin layer 11 was 15 ppm / ° C., and the Young's modulus of the insulating resin layer 11 was 10 GPa. In this case, the semiconductor device model M was warped by 116 μm in the negative direction.

[0046] The simulation results are shown in Table 2. [Table 2] In Examples 1 to 9 in which the linear expansion coefficient Y of the core resin 1' was smaller than the calculated value Y' (=-0.23X+11), the warpage was less than 0.5% of the semiconductor element size. On the other hand, in Comparative Examples 1 and 2 in which the linear expansion coefficient Y of the core resin 1' was larger than the calculated value Y', the warpage was greater than 0.5% of the semiconductor element size. Furthermore, in Examples 1 to 9, the tensile modulus of elasticity (Young's modulus) of the insulating resin layer 11 was changed, but it was verified that when 10≦X≦25, Y≦-0.23X+11 were satisfied, the warpage was less than 0.5% of the semiconductor element size regardless of the tensile modulus of elasticity (Young's modulus).

[0047] In this manner, by using the simulation of the present disclosure, it has been found that by controlling the linear expansion coefficient of the insulating resin layer and the linear expansion coefficient of the core resin, regardless of the tensile modulus of elasticity (Young's modulus), it is possible to suppress warping during a temperature cycle test, thereby providing a highly reliable semiconductor device.

[0048] <Design and manufacturing methods for multilayer wiring boards> A method for designing and manufacturing the multilayer wiring board 100 according to the first embodiment will be described with reference to Fig. 7. Fig. 7 is an explanatory diagram showing an example of a method for manufacturing a core board of the present invention.

[0049] (Core board manufacturing process) First, materials are selected so that the linear expansion coefficient X ppm / °C of the insulating resin layer 11 and the linear expansion coefficient Y ppm / °C of the core resin 1' used in manufacturing the multilayer wiring board meet the conditions of the following formulas (1) and (2). 10≦X≦25 (1) Y≦―0.23X+11 (2) Next, through holes 3 for electrically connecting the front and back surfaces are formed by a drill or the like in the core resin 1' having copper foils 2 attached to both sides (FIG. 7(a)).

[0050] Next, a conductor layer 23 is formed on the surface of the copper foil 2 and the wall surface of the through hole 3 by electroless plating and electrolytic plating (Figure 7(b)). In the electroless plating of the conductor layer 23, a material similar to that of the seed layer 13a can be used. In addition, in the electrolytic plating of the conductor layer 23, a material similar to that of the plating layer 13b can be used.

[0051] Next, the through-holes 3 are filled with filling resin 4. Any excess filling resin 4 that protrudes from the through-holes 3 is removed by buffing or the like (FIG. 7(c)). Note that if the through-holes 3 are completely filled with plating in the step shown in FIG. 7(b), this step is omitted.

[0052] Next, a conductor layer 33 is formed on the entire surface by electroless plating and electrolytic plating (FIG. 7(d)). Note that this step may be omitted if the through-holes 3 are completely filled with plating in the step shown in FIG. 7(b) or if the conductor layer 33 is not required on the hole filling resin.

[0053] Next, a resist is applied or laminated, and a resist pattern 6 is formed by photolithography on the portions of the conductor layers 23 and 33 that are to remain as conductors (FIG. 7(e)).

[0054] Next, the portions of the conductor layers 23 and 33 on which the resist pattern 6 is not formed are removed by etching to form a plurality of conductors (FIG. 7(f)).

[0055] Next, the resist pattern 6 is removed to form the core substrate 1 having the pad portion 43 (FIG. 7(g)). The pad portion 43 is electrically connected to the wiring board laminated on the core substrate 1. Although the method for producing the core substrate 1 has been described above, this is only one example and the core substrate 1 may be produced by other methods.

[0056] (Manufacturing process for multi-layer wiring boards) Next, a description will be given of a process for laminating insulating resin and conductors on the fabricated core substrate 1 to fabricate the multilayer wiring substrate 100. The insulating resin and conductors are laminated on both sides of the core substrate 1.

[0057] 8 and 9 are explanatory diagrams showing a multilayer wiring board and a manufacturing method thereof according to the first embodiment of the present invention. Note that in the subsequent explanatory diagrams of the manufacturing method, the core resin 1' of the core substrate 1 is omitted.

[0058] First, an insulating resin layer 11 is formed on the core substrate 1. The insulating resin layer 11 used here may be a thermosetting resin or a photosensitive resin, but a material that satisfies the linear expansion coefficient condition of the above-mentioned formula (2) is selected. In the case of a thermosetting resin, the insulating resin layer 11 is protected from UV or CO irradiation so that the pad parts 43 for electrical connection in the lower layer are exposed. 2 In the case of using a photosensitive resin, the via opening 8 is formed by a laser such as SiO 2 or by photolithography (FIG. 8(a)).

[0059] Next, a seed layer 13a is formed by electroless plating or sputtering on the outer surface of the insulating resin layer 11, the wall surface of the via opening 8, and the pad portion 43 that corresponds to the bottom surface of the via opening 8 (FIG. 8(b)).

[0060] (Seed layer) The seed layer 13a is laminated on the insulating resin layer 11. There are no particular limitations on the material constituting the seed layer 13a. When the seed layer 13a is formed by electroless plating, for example, metal materials such as Cu, Pd, Al, Sn, Ni, and Cr can be used. When the seed layer 13a is formed by sputtering, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide), ZnO, PZT (lead zirconate titanate), TiN, Cu 3 N 4 , Cu alloys, or combinations of two or more of these materials can be used.

[0061] Next, a resist is applied or laminated onto the seed layer 13a, and then exposed and developed to form a resist pattern 16 corresponding to the pattern of the plating layer 13b (FIG. 8(c)).

[0062] Next, a plating layer 13b is formed by electrolytic plating on the seed layer 13a on which the resist pattern 16 has been formed (FIG. 8(d)). The plating layer 13b is laminated on the surface of the seed layer 13a opposite to the insulating resin layer 11. The material constituting the plating layer 13b is mainly a metal, and the type is not particularly limited, but for example, Cu and Cu alloys, Ag and Ag alloys, Sn, Pd, Au, Ni, Cr, Pt, Fe, or a combination of two or more of these materials can be used. Next, the resist pattern 16 is removed (FIG. 5(e)).

[0063] Next, the seed layer 13a (the seed layer 13a not covered with the plating layer 13b) exposed by removing the resist pattern 16 is removed by etching (FIG. 5(f)). This forms the conductor layer 13. That is, the conductor layer 13 has, in this order from the lower insulating resin layer 11 side, the seed layer 13a and the plating layer 13b. The conductor layer 13 may include various patterns such as wiring, vias, pads, shields, grounds, and dummies, but wiring, vias, and pads are shown in Figures 8 and 9. Adjacent conductors 13' are formed spaced apart in the surface direction of the insulating resin layer 11.

[0064] Next, an insulating resin layer 11 is laminated so as to cover the conductor layer 13 and the underlying insulating resin layer 11. When a desired number of circuit layers have been formed, this step is omitted.

[0065] The above steps are repeated until a circuit with the desired number of layers is formed (FIG. 9(g)).

[0066] After forming the desired number of layers of circuits, a solder resist layer 17 is formed on the outermost layer by coating or lamination (FIG. 9(h)).

[0067] The solder resist openings 18 are formed on the pad portions 53 by photolithography or the like (FIG. 9(i)). The solder resist layer 17 is, for example, a photosensitive epoxy resin, which may contain an inorganic filler. When a non-photosensitive thermosetting resin is used, the solder resist openings 18 are formed on the pad portions 53 by photolithography or the like (FIG. 9(i)). 2 Solder resist openings 18 are formed by laser, photolithography or the like.

[0068] Next, a surface treatment layer 19 is formed on the pads 53 in the solder resist openings 18 (FIG. 9(j)).

[0069] Next, the multilayer wiring board 100 can be formed by forming the solder bumps 20 in the solder resist openings 18 on the mounting side of the semiconductor element 34 (FIG. 6(k)). The solder bumps 20 can be formed by screen printing when solder paste is used, and when solder balls are used, they can be formed by screen printing flux, then mounting the solder balls by ball transfer, and melting each by reflow.

[0070] (Semiconductor device mounting) Next, a semiconductor element 34 (silicon chip) is mounted on the multilayer wiring board 100 to obtain the semiconductor device 200 shown in Fig. 2. In the semiconductor device 200, electrode terminals of the semiconductor element 34 are electrically connected to corresponding pad portions 53 on the multilayer wiring board 100 via conductive materials such as solder bumps 20 (flip-chip mounting). Furthermore, the gap between the mounted semiconductor element 34 and the multilayer wiring board 100 is filled with underfill resin 35 such as a thermosetting epoxy resin, and mechanical bonding between the semiconductor element 34 and the multilayer wiring board 100 is ensured by heat curing.

[0071] On the other hand, solder bumps 20 used as external connection terminals are formed on pad portions 53 exposed from the solder resist layer 17 on the side opposite to the mounting surface side of the semiconductor element 34 after mounting the semiconductor element 34. Through the solder bumps 20, the multilayer wiring board 100 is mounted on a motherboard or the like.

[0072] The above-described embodiment is merely an example, and it goes without saying that other specific details such as structure can be modified as appropriate. The present disclosure also includes the following aspects.

[0073] (Aspect 1) A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which a core board, insulating resin layers using an organic insulating material on both sides of the core board, and wiring layers using a conductive material are alternately laminated, A multilayer wiring board that satisfies the conditions of the following formulas (1) and (2), where the linear expansion coefficient of a core resin of a core substrate constituting the multilayer wiring board is Y ppm / °C and the linear expansion coefficient of the insulating resin layer is X ppm / °C. 10≦X≦25 (1) Y≦―0.23X+11 (2)

[0074] (Aspect 2) In the multilayer wiring board according to aspect 1, A multilayer wiring board, characterized in that the thickness of the core resin is 0.4 mm to 2.0 mm.

[0075] (Aspect 3) In the multilayer wiring board according to the first or second aspect, The multilayer wiring board has a rectangular planar shape of 20 mm x 20 mm, a core resin thickness of 1.2 mm, a total thickness of the conductor layers of 15 μm, a total thickness of the insulating resin layers of 30 μm, a total thickness of the front and back of the solder resist layer 17 of 15 μm, a volume ratio of the wiring portion and via portion in the conductor layer and insulating resin layer on the side on which the semiconductor element is mounted is 31%, and a volume ratio of the wiring portion and via portion in the conductor layer and insulating resin layer on the side on which the semiconductor element is not mounted is 29%.

[0076] (Aspect 4) In the multilayer wiring board according to any one of aspects 1 to 3, the insulating resin contains a filler made of an inorganic material; 2. A multilayer wiring board, comprising: a core resin made of a fiber-reinforced composite material reinforced with glass fibers;

[0077] (Aspect 5) A semiconductor device comprising the multilayer wiring board according to any one of the first to fourth aspects and a semiconductor element mounted thereon.

[0078] (Aspect 6) A method for designing a multilayer wiring board having a core board and insulating resin layers formed on both sides of the core board, comprising: A method for designing a multilayer wiring board, comprising the steps of: selecting the core resin and the insulating resin layer so as to satisfy the following formulas (1) and (2), where the linear expansion coefficient of the core resin of the core substrate constituting the multilayer wiring board is Y ppm / °C and the linear expansion coefficient of the insulating resin layer is X ppm / °C. 10≦X≦25 (1) Y≦―0.23X+11 (2) [Explanation of symbols]

[0079] 1 Core Board 1' Core resin 2 Copper foil 3 Through Hole 4. Hole filling resin 6, 16 Resist pattern 8 Via opening 11 Insulating resin layer 13, 23, 33 Conductor layers 13a Seed layer 13b Plating layer 16 Resist Pattern 17 Solder resist layer 18 Solder resist opening 19 Surface treatment layer 20 Solder Bumps 34 Semiconductor elements 35 Underfill resin 43, 53 Pad section 100 Multilayer wiring board 200 Semiconductor device A Warpage simulation model area

Claims

1. A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which a core board, insulating resin layers using an organic insulating material on both sides of the core board, and wiring layers using a conductive material are alternately laminated, A multilayer wiring board that satisfies the conditions of the following formulas (1) and (2), where the linear expansion coefficient of the core resin of the core substrate that constitutes the multilayer wiring board is Y ppm / °C and the linear expansion coefficient of the insulating resin layer is X ppm / °C. 10≦X≦25 (1) Y≦-0.23X+11...(2)

2. 2. The multilayer wiring board according to claim 1, A multilayer wiring board, wherein the thickness of the core resin is 0.4 mm to 2.0 mm.

3. 3. The multilayer wiring board according to claim 2, The multilayer wiring board has a rectangular planar shape of 20 mm x 20 mm, a core resin thickness of 1.2 mm, a total thickness of the conductor layers of 15 μm, a total thickness of the insulating resin layers of 30 μm, a total thickness of the front and back of the solder resist layer 17 of 15 μm, a volume ratio of the wiring portion and via portion in the conductor layer and insulating resin layer on the side on which the semiconductor element is mounted is 31%, and a volume ratio of the wiring portion and via portion in the conductor layer and insulating resin layer on the side on which the semiconductor element is not mounted is 29%.

4. 4. The multilayer wiring board according to claim 3, the insulating resin layer contains a filler made of an inorganic material, 2. A multilayer wiring board, comprising: a core resin made of a fiber-reinforced composite material reinforced with glass fibers;

5. A semiconductor device comprising the multilayer wiring board according to claim 1 and a semiconductor element mounted on the multilayer wiring board.

6. A method for designing a multilayer wiring board having a core board and insulating resin layers formed on both sides of the core board, comprising: A method for designing a multilayer wiring board, comprising the steps of: selecting the core resin and the insulating resin layer so as to satisfy the following formulas (1) and (2), where the linear expansion coefficient of the core resin of the core substrate constituting the multilayer wiring board is Y ppm / °C and the linear expansion coefficient of the insulating resin layer is X ppm / °C. 10≦X≦25 (1) Y≦-0.23X+11...(2)

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