Manufacturing method and manufacturing equipment of display device

Abstract

To provide a configuration in which lines provided in a display area can be satisfactorily connected to an upper electrode of each display element.SOLUTION: A manufacturing method of a display device includes: preparing a substrate including a lower electrode, a rib having a pixel aperture which overlaps the lower electrode, and a partition having a lower portion and an upper portion which protrudes from a side surface of the lower portion; forming an organic layer, which is in contact with the lower electrode through the pixel aperture, by vapor deposition for the substrate; and forming an upper electrode, which covers the organic layer and is in contact with the lower portion of the partition, by vapor deposition for the substrate. A first evaporation source used to form a first thin film of the organic layer includes a first nozzle which emits a material toward the substrate that relatively moves with respect to the first evaporation source. A second evaporation source used to form the upper electrode includes a second nozzle which emits a material toward the substrate that relatively moves with respect to the second evaporation source. An axis of at least one of the first nozzle and the second nozzle inclines to a direction orthogonal to a moving direction of the substrate in plan view with respect to a normal direction of the substrate.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] An embodiment of the present invention relates to a manufacturing method and a manufacturing apparatus for a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a lower electrode, an organic layer that covers the lower electrode, and an upper electrode that covers the organic layer. A common voltage is applied to the upper electrodes of each display element through wiring arranged in the display area.

[0003] The organic layer and the upper electrode are formed by deposition on the substrate on which the wiring is provided, and in this case, there is a possibility that the previously formed organic layer may impede the connection between the upper electrode and the wiring. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a manufacturing method and manufacturing apparatus for a display device that can satisfactorily connect wiring provided in a display region to upper electrodes of display elements. [Means for solving the problem]

[0006] Generally, according to an embodiment, a method for manufacturing a display device includes: preparing a substrate including a lower electrode, a rib having a pixel opening overlapping the lower electrode, and a partition wall having a conductive lower portion disposed on the rib and an upper portion protruding from a side surface of the lower portion; forming an organic layer on the substrate by deposition, the organic layer contacting the lower electrode through the pixel opening and emitting light in response to application of a voltage; and forming an upper electrode on the substrate by deposition, the organic layer covering the organic layer and contacting the lower portion of the partition wall. The organic layer includes a first thin film. A first deposition source used for forming the first thin film includes a first nozzle that emits a vaporized material toward the substrate moving relative to the first deposition source. A second deposition source used for forming the upper electrode includes a second nozzle that emits a vaporized material toward the substrate moving relative to the second deposition source. Furthermore, at least one axis of the first nozzle and the second nozzle is inclined with respect to a normal direction of the substrate in a direction perpendicular to a moving direction of the substrate in a plan view.

[0007] According to an embodiment, a manufacturing apparatus for a display device includes a first deposition apparatus for forming an organic layer that contacts the lower electrode through the pixel opening and emits light in response to application of a voltage on a substrate including a lower electrode, a rib having a pixel opening overlapping the lower electrode, and a partition wall having a conductive lower portion disposed on the rib and an upper portion protruding from a side surface of the lower portion, and a second deposition apparatus for forming an upper electrode on the substrate, the organic layer being in contact with the lower portion of the partition wall and covering the organic layer. The organic layer includes a first thin film. The first deposition apparatus includes a first deposition source provided with a first nozzle, and the first nozzle ejects a vaporized material of the first thin film toward the substrate moving relative to the first deposition source. The second deposition apparatus includes a second deposition source provided with a second nozzle, and the second nozzle ejects a vaporized material of the upper electrode toward the substrate moving relative to the second deposition source. Furthermore, an axis of at least one of the first nozzle and the second nozzle is inclined with respect to a normal direction of the substrate in a direction perpendicular to a moving direction of the substrate in a plan view. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a diagram showing an example of a layer structure that can be applied to the organic layer. [Diagram 5] FIG. 5 is a schematic cross-sectional view of the display device taken along line VV in FIG. [Figure 6] FIG. 6 is a schematic plan view of a partition wall surrounding a sub-pixel. [Figure 7] FIG. 7 is a flowchart showing an example of a method for manufacturing a display device. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 8B] FIG. 8B is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 8A. [Figure 8C] FIG. 8C is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 8D. [Figure 8F] FIG. 8F is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 8E. [Figure 8G] FIG. 8G is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 8F. [Figure 9] FIG. 9 is a diagram showing a schematic configuration of a part of a manufacturing apparatus for a display device. [Figure 10] FIG. 10 is a schematic plan view showing an example of the relationship between the transported substrate and the deposition source. [Figure 11] FIG. 11 is a schematic perspective view showing an example of a configuration applicable to a vapor deposition source for a hole injection layer. [Figure 12] FIG. 12 is a schematic perspective view showing still another example of a configuration applicable to the vapor deposition source of the hole injection layer. [Figure 13] FIG. 13 is a schematic perspective view showing an example of a configuration applicable to the deposition sources of the hole transport layer, the electron blocking layer, the light emitting layer, the hole blocking layer, the electron transport layer, and the electron injection layer. [Figure 14] FIG. 14 is a schematic perspective view showing an example of a configuration applicable to a vapor deposition source of the upper electrode. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a step of forming a hole injection layer. [Figure 16] FIG. 16 is a schematic cross-sectional view showing the steps of forming a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a step of forming an upper electrode. [Figure 18] FIG. 18 is a diagram showing another example of the step of forming the upper electrode. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a first modified example of a configuration that can be applied to the partition wall. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a second modified example of a configuration that can be applied to the partition wall. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0010] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of a plane that includes the X-direction and the Y-direction. Moreover, viewing various elements parallel to the Z-direction is called planar view.

[0011] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0012] 1 is a diagram showing an example of the configuration of a display device DSP according to an embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. The pixels PX include a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0016] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power lines PL. In the example of Fig. 1, the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0018] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and a column in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG.

[0021] A rib 5 is disposed in the display area DA. The rib 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio, and the subpixel SP3 has the smallest aperture ratio.

[0022] The subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel aperture AP3.

[0023] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] A conductive partition wall 6 is disposed on the rib 5. The partition wall 6 overlaps the rib 5 as a whole and has the same planar shape as the rib 5. That is, the partition wall 6 has openings in each of the subpixels SP1, SP2, and SP3. From another perspective, the rib 5 and the partition wall 6 are lattice-shaped in a planar view and surround each of the subpixels SP1, SP2, and SP3. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0025] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes unevenness caused by the circuit layer 11.

[0026] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. Although not shown in the cross section of FIG. 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0027] The partition 6 includes a conductive lower portion 61 disposed on the rib 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition 6 is called an overhang shape.

[0028] In the example of FIG. 3, the lower part 61 has a bottom layer 63 arranged on the rib 5 and a shaft layer 64 arranged on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In addition, in the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0029] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0030] The display element DE1 includes a cap layer CP1 disposed on an upper electrode UE1. The display element DE2 includes a cap layer CP2 disposed on an upper electrode UE2. The display element DE3 includes a cap layer CP3 disposed on an upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0031] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.

[0032] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located below the partition wall 6 (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located below the partition wall 6 (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located below the partition wall 6 (a part that constitutes the display element DE3).

[0033] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE1 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE2 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE3 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0034] 3, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are separated from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are separated from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0035] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15. The resin layers 13, 15, and the sealing layer 14 are provided continuously at least throughout the display area DA, and a portion of them extends into the peripheral area SA.

[0036] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer 15. Such a cover member may be adhered to the resin layer 15 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0037] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib 5 and the sealing layers 14, SE1, SE2, and SE3 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the rib 5 is formed of silicon oxynitride, and the sealing layers 14, SE1, SE2, and SE3 are formed of silicon nitride. The resin layers 13 and 15 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0038] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0039] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0040] 4 is a diagram showing an example of a layer structure applicable to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including an emitting layer EML. In this embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are laminated in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of emitting layers EML.

[0041] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, a plurality of transparent layers are stacked. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE1, SE2, and SE3. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0042] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0043] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. The metal material forming the lower layer may be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide forming the upper layer may be, for example, ITO or IZO. The upper portion 62 may have a single layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0044] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal of the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0045] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in the red wavelength region.

[0046] As another example, the emitting layers EML of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the emitting layers EML into light of a color corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the emitting layers EML to generate light of a color corresponding to the subpixels SP1, SP2, and SP3.

[0047] 5 is a schematic cross-sectional view of the display device DSP taken along line VV in FIG. 2. The cross-section shown in this figure corresponds to a YZ cross-section defined by the Y and Z directions, and shows three sub-pixels SP1 aligned in the Y direction. Note that the substrate 10, the circuit layer 11, the resin layer 13, the sealing layer 14, and the resin layer 15 are omitted. In the following description, the partition 6 on the left side in FIG. 5 is referred to as a first partition 6A, and the partition 6 on the right side is referred to as a second partition 6B. These partitions 6A and 6B are arranged to sandwich the pixel opening AP1 in the center of FIG. 5 in the Y direction.

[0048] 5, the stacked film FL1 and the sealing layer SE1 are not interrupted on the partition walls 6A and 6B. That is, the sealing layer SE1 continuously covers the partition walls 6A and 6B and the cap layer CP1 of each subpixel SP1.

[0049] As shown in enlarged views in (a) and (b) of FIG. 5, the organic layer OR1 has a first layer L1 and a second layer L2 on the first layer L1. In this embodiment, it is assumed that the first layer L1 is composed of a hole injection layer HIL, and the second layer L2 is composed of a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. However, the first layer L1 may further include other layers such as a hole transport layer HTL in addition to the hole injection layer HIL. Note that the cap layer CP1 and the sealing layer SE1 are omitted in FIG. 5(a) and (b).

[0050] The thicknesses of the first layer L1 and the second layer L2 decrease as they approach the partition walls 6A and 6B. Similarly, the thickness of the upper electrode UE1 decreases as they approach the partition walls 6A and 6B.

[0051] The first layer L1 has an end E1a on the first partition 6A side and an end E1b on the second partition 6B side. From the viewpoint of suppressing the occurrence of leakage current between the organic layer OR1 and the partitions 6A and 6B, it is preferable that the hole injection layer HIL constituting the first layer L1 is not electrically connected to the partition 6. That is, it is preferable that the ends E1a and E1b are separated from the bottom layers 63 of the partitions 6A and 6B, respectively, as shown in FIG. 5. However, the first layer L1 may be in slight contact with at least one of these bottom layers 63.

[0052] The second layer L2 has an end E2a on the first partition wall 6A side and an end E2b on the second partition wall 6B side. In the example of FIGS. 5(a) and 5(b), the ends E2a and E2b are located on the bottom layers 63 of the partition walls 6A and 6B, respectively. That is, the second layer L2 is in contact with the bottom layers 63 of the partition walls 6A and 6B. As another example, the second layer L2 may not be in contact with the bottom layer 63 of the first partition wall 6A. Furthermore, the second layer L2 may not be in contact with both the bottom layers 63 of the partition walls 6A and 6B.

[0053] As shown in FIG. 5(a), the end E2a is spaced apart from the axial layer 64 of the first partition wall 6A. As a result, an area that is not covered with the second layer L2 is formed on the upper surface of the bottom layer 63 of the first partition wall 6A. On the other hand, in the example of FIG. 5(b), the end E2b is in contact with the axial layer 64 of the second partition wall 6B. As a result, the upper surface of the bottom layer 63 of the second partition wall 6B is entirely covered with the second layer L2. As another example, the end E2b may be spaced apart from the axial layer 64 of the second partition wall 6B.

[0054] The upper electrode UE1 has an end E3a on the first partition 6A side and an end E3b on the second partition 6B side. In the example of FIG. 5(a), the end E3a is located on the bottom layer 63 of the first partition 6A and is in contact with the axis layer 64. However, the end E3a may be separated from the axis layer 64. On the other hand, in the example of FIG. 5(b), the end E3b is located on the second layer L2 and is not in contact with the bottom layer 63 and axis layer 64 of the second partition 6B. As another example, the end E3b may be in contact with the axis layer 64 of the second partition 6B.

[0055] The line segment Va indicated by the dashed line in Fig. 5(a) is a straight line passing through the first end portion 62a of the upper portion 62 of the first partition wall 6A and parallel to the Z direction. Further, the line segment Vb indicated by the dashed line in Fig. 5(b) is a straight line passing through the second end portion 62b of the upper portion 62 of the second partition wall 6B and parallel to the Z direction.

[0056] At the position where it intersects the line segment Va, that is, directly below the first end portion 62a, the organic layer OR1 has a thickness T1a. Further, at the position where it intersects the line segment Vb, that is, directly below the second end portion 62b, the organic layer OR1 has a thickness T1b. The thicknesses T1a and T1b correspond to the total thickness of the first layer L1 and the second layer L2.

[0057] At the position where it intersects the line segment Va, that is, directly below the first end portion 62a, the upper electrode UE1 has a thickness T2a. Further, at the position where it intersects the line segment Vb, that is, directly below the second end portion 62b, the upper electrode UE1 has a thickness T2b. For example, the thickness T2a is smaller than the thickness T1a (T2a < T1a). Also, the thickness T2b is smaller than the thickness T1b (T2b < T1b).

[0058] In the present embodiment, the thickness T1a is smaller than the thickness T1b (T1a < T1b). Further, the thickness T2a is larger than the thickness T2b (T2a > T2b). That is, the organic layer OR1 is formed thinner in the vicinity of the first partition wall 6A and thicker in the vicinity of the second partition wall 6B. Also, the upper electrode UE1 is formed thicker in the vicinity of the first partition wall 6A and thinner in the vicinity of the second partition wall 6B.

[0059] Also, in the present embodiment, the contact area between the lower portion 61 (bottom layer 63 and shaft layer 64) of the first partition wall 6A and the organic layer OR1 is smaller than the contact area between the lower portion 61 of the second partition wall 6B and the organic layer OR1.

[0060] Furthermore, the contact area between the lower portion 61 of the first partition wall 6A and the upper electrode UE1 is larger than the contact area between the lower portion 61 of the second partition wall 6B and the upper electrode UE1. In the example of FIG. 5(b), the upper electrode UE1 is not in contact with the lower portion 61 of the second partition wall 6B. In this case, the contact area between the lower portion 61 of the second partition wall 6B and the upper electrode UE1 is zero. This example is not limited, and the upper electrode UE1 may be in contact with the bottom layer 63 or the axis layer 64 of the second partition wall 6B, so that the contact area does not have to be zero.

[0061] 5, the organic layer OR1 is thinned near the first partition 6A and the upper electrode UE1 is thickened, thereby ensuring a wide contact area between the bottom layer 63 of the first partition 6A and the upper electrode UE1. This allows the upper electrode UE1 and the partition 6 to be satisfactorily conductive.

[0062] Each of the subpixels SP1 arranged in the display region DA has a shape similar to that of the subpixel SP1 shown in the center of Fig. 5. That is, focusing on each of the partitions 6A and 6B, the vicinity of one side surface of the lower portion 61 has the structure shown in Fig. 5(a), and the vicinity of the other side surface has the structure shown in Fig. 5(b).

[0063] 6 is a schematic plan view of the partition wall 6 surrounding the subpixels SP1, SP2, and SP3. As shown in the figure, the four sides of the partition wall 6 surrounding the subpixel SP1 are defined as sides S1a, S1b, S1c, and S1d, the four sides of the partition wall 6 surrounding the subpixel SP2 are defined as sides S2a, S2b, S2c, and S2d, and the four sides of the partition wall 6 surrounding the subpixel SP3 are defined as sides S3a, S3b, S3c, and S3d. The sides S1a, S1b, S2a, S2b, S3a, and S3b are parallel to the X direction. The sides S1c, S1d, S2c, S2d, S3c, and S3d are parallel to the Y direction.

[0064] Sides S1a, S2b, and S3a enclosed by dashed lines correspond to contact sides where the upper electrodes UE1, UE2, and UE3 are in contact with the partition wall 6. A common voltage is supplied to the upper electrodes UE1, UE2, and UE3 through at least these contact sides.

[0065] The structure of side S1a is as shown in Fig. 5(a). The structures of the organic layer OR2, the upper electrode UE2, and the partition wall 6 on side S2b are similar to the structures of the organic layer OR1, the upper electrode UE1, and the first partition wall 6A shown in Fig. 5(a). The structures of the organic layer OR3, the upper electrode UE3, and the partition wall 6 on side S3a are similar to the structures of the organic layer OR1, the upper electrode UE1, and the first partition wall 6A shown in Fig. 5(a). This ensures good electrical continuity between the upper electrodes UE2 and UE3 and the partition wall 6, just like the upper electrode UE1.

[0066] The structure of side S1b is as shown in Fig. 5(b). The structures of the organic layer OR2, the upper electrode UE2, and the partition wall 6 on side S2a are the same as the structures of the organic layer OR1, the upper electrode UE1, and the second partition wall 6B shown in Fig. 5(b). The structures of the organic layer OR3, the upper electrode UE3, and the partition wall 6 on side S3b are the same as the structures of the organic layer OR1, the upper electrode UE1, and the second partition wall 6B shown in Fig. 5(b).

[0067] In addition to the contact sides shown in the figure, the upper electrodes UE1, UE2, UE3 may be in contact with the lower portion 61 at other sides. The positions of the contact sides of the subpixels SP1, SP2, SP3 are not limited to the example in FIG. 6 and can be changed as appropriate.

[0068] Fig. 7 is a flowchart showing an example of a manufacturing method of the display device DSP. Fig. 8A to Fig. 8G are schematic cross-sectional views showing the manufacturing process of the display device DSP. In Fig. 8A to Fig. 8G, the substrate 10 and the circuit layer 11 are omitted.

[0069] In manufacturing the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10, and then, as shown in FIG. 8A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR1).

[0070] 8B, the ribs 5 and the partition walls 6 are formed (step PR2). The pixel openings AP1, AP2, AP3 of the ribs 5 may be provided after or before the partition walls 6 are formed.

[0071] After the substrate on which the lower electrodes LE1, LE2, LE3, the ribs 5, and the partition walls 6 are formed is prepared by steps PR1 and PR2, steps for forming the display elements DE1, DE2, and DE3 are carried out. In this embodiment, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0072] In forming the display element DE1, first, as shown in FIG. 8C, a laminated film FL1 and a sealing layer SE1 are formed (step PR3). As shown in FIG. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by deposition. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The laminated film FL1 is divided into a plurality of parts by overhanging partition walls 6. The sealing layer SE1 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0073] After step PR3, the laminated film FL1 and the sealing layer SE1 are patterned (step PR4). In this patterning, a resist R is disposed on the sealing layer SE1 as shown in Fig. 8D. The resist R covers the subpixel SP1 and a part of the partition wall 6 around it.

[0074] Thereafter, by etching using the resist R as a mask, the laminated film FL1 and the sealing layer SE1 are removed in portions exposed from the resist R, as shown in FIG. 8E. In other words, the laminated film FL1 and the sealing layer SE1 are left in portions overlapping with the lower electrode LE1, and the other portions are removed. This forms a display element DE1 in the subpixel SP1. For example, the etching includes wet etching and dry etching that are performed in sequence on the sealing layer SE1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R is removed.

[0075] The display element DE2 is formed in the same manner as the display element DE1. That is, in forming the display element DE2, a laminated film FL2 and a sealing layer SE2 are formed over the entire display area DA (step PR5). As shown in FIG. 3, the laminated film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0076] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by deposition. The sealing layer SE2 is formed by CVD. The laminated film FL2 is divided into a plurality of parts by overhanging partition walls 6. The sealing layer SE2 continuously covers each divided part of the laminated film FL2 and the partition walls 6.

[0077] After step PR5, the laminated film FL2 and the sealing layer SE2 are patterned (step PR6), thereby forming a display element DE2 in the subpixel SP2, as shown in FIG.

[0078] The display element DE3 is formed in the same manner as the display elements DE1 and DE2. That is, in forming the display element DE3, a laminated film FL3 and a sealing layer SE3 are formed over the entire display area DA (step PR7). As shown in FIG. 3, the laminated film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0079] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 are formed by deposition. The sealing layer SE3 is formed by CVD. The laminated film FL3 is divided into a plurality of parts by overhanging partition walls 6. The sealing layer SE3 continuously covers each divided part of the laminated film FL3 and the partition walls 6.

[0080] After step PR7, the stacked film FL3 and the sealing layer SE3 are patterned (step PR8), thereby forming a display element DE3 in the subpixel SP3, as shown in FIG.

[0081] After the display elements DE1, DE2, and DE3 are formed, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in Fig. 3 are formed in this order (step PR9). Through these steps, the display device DSP is completed.

[0082] 9 is a diagram showing a schematic configuration of a part of a manufacturing apparatus 100 for manufacturing a display device DSP. The manufacturing apparatus 100 shown in this figure corresponds to a manufacturing line for forming an organic layer OR1 and an upper electrode UE1, and includes deposition apparatuses DD1 to DD7 for forming a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. The deposition apparatuses DD1 to DD7 configure a first deposition apparatus for forming the organic layer OR1. The manufacturing apparatus 100 further includes a deposition apparatus DD8 (second deposition apparatus) for forming the upper electrode UE1.

[0083] The deposition devices DD1 to DD8 include chambers C1 to C8 whose interiors are maintained at a vacuum, and deposition sources DS1 to DS8 arranged inside the chambers C1 to C8, respectively. Furthermore, the manufacturing apparatus 100 includes a transfer device CD that transfers the substrate 10X on which the partition walls 6 have been formed after the process PR2. The substrate 10X may be a mother substrate on which a plurality of panel portions each corresponding to the display device DSP are formed. The transfer device CD transfers the substrate 10X to the chambers C1 to C8 in sequence. In the following description, the direction in which the substrate 10X passes through the chambers C1 to C8 (the direction in which the substrate 10X moves relative to the deposition sources DS1 to DS8) is referred to as the movement direction FD.

[0084] 9 shows an example in which the manufacturing apparatus 100 includes deposition apparatuses DD1 to DD7, assuming that the organic layer OR1 has a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are laminated in this order. However, the configuration of the deposition apparatuses included in the manufacturing apparatus 100 may be changed depending on the configuration of the thin film included in the organic layer OR1.

[0085] 10 is a schematic plan view showing an example of the relationship between a substrate 10X to be transported and deposition sources DS (DS1 to DS8). The deposition source DS includes a crucible CR, a long container CT connected to the crucible CR, and a plurality of nozzles N provided in the container CT.

[0086] The crucible CR heats the material contained therein to vaporize (evaporate or sublimate) the material. The vaporized material is supplied to a container CT and is ejected from each nozzle N toward a substrate 10X that moves in a moving direction FD relative to the deposition source DS. The multiple nozzles N are aligned in a straight line along a nozzle arrangement direction ND on one surface of the container CT facing the substrate 10X.

[0087] For example, the substrate 10X is transported so that the movement direction FD is perpendicular to the nozzle arrangement direction ND. In the example of Fig. 10, the width direction WD of the deposition source DS perpendicular to the nozzle arrangement direction ND, the movement direction FD, and the X direction are parallel to each other.

[0088] In the following description, a first side SD1, a second side SD2, a third side SD3, and a fourth side SD4 with respect to the nozzle N are defined as shown in FIG. 10. The first side SD1 and the second side SD2 are opposite to each other, and in the example of FIG. 10, are parallel to the nozzle arrangement direction ND and the Y direction. That is, the first side SD1 and the second side SD2 are perpendicular to the moving direction FD in a plan view. The third side SD3 and the fourth side SD4 are opposite to each other, and in the example of FIG. 10, are parallel to the moving direction FD, the width direction WD, and the X direction. In addition, the third side SD3 faces the upstream side in the moving direction FD, and the fourth side SD4 faces the downstream side in the moving direction FD.

[0089] 11 is a schematic perspective view showing an example of a configuration applicable to the deposition source DS1 of the hole injection layer HIL. In the following description, the nozzle N of the deposition source DS1 is referred to as the nozzle N0. The nozzle N0 emits vaporized material M of the hole injection layer HIL in the deposition direction MD0.

[0090] The deposition direction MD0 is, for example, parallel to the axis AX0 of the nozzle N0 (extension direction of the nozzle N0). In the example of Fig. 11, the axis AX0 is perpendicular to the nozzle arrangement direction ND and the width direction WD. The material M is emitted from the nozzle N0 with a predetermined spread angle centered on the deposition direction MD0. The deposition direction MD0 can also be said to be a direction parallel to the central axis of the material M emitted from the nozzle N0, or the main emission direction of the material M.

[0091] The deposition source DS1 may further include a shield 20 that surrounds the multiple nozzles N. In the example of Fig. 11, the shield 20 surrounds the container CT and each nozzle N0, and has a shape that is open on the nozzle N0 side.

[0092] The shield 20 has a first side wall 21 and a second side wall 22 in the width direction WD. These side walls 21, 22 protrude in the deposition direction MD0 beyond the tip of each nozzle N0 and suppress the spread of the material M in the width direction WD.

[0093] 12 is a schematic perspective view showing yet another example of a configuration applicable to the deposition source DS1. In the example of this figure, a shield 30 is further disposed for the nozzle N0. The shield 30 is, for example, cylindrical and surrounds the nozzle N0, and is attached to the container CT. For example, the shield 30 is provided for each of the multiple nozzles N0 of the deposition source DS1.

[0094] The shield 30 protrudes in the deposition direction MD0 beyond the tip of the nozzle N0. The height of the shield 30 (the length of protrusion from the tip of the nozzle N0) is uniform over the entire circumference of the nozzle N0. This prevents the material M emitted from the nozzle N0 from spreading in all directions around the nozzle N0.

[0095] 13 is a schematic perspective view showing an example of a configuration applicable to the deposition sources DS2 to DS7 of the hole transport layer HTL, the electron blocking layer EBL, the emitting layer EML, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL. In the following description, the nozzle N of the deposition sources DS2 to DS7 is referred to as the nozzle N1. The nozzle N1 emits vaporized material M in the deposition direction MD1.

[0096] The deposition direction MD1 is, for example, parallel to the axis AX1 of the nozzle N1 (extension direction of the nozzle N1). The material M is released from the nozzle N1 with a predetermined spread angle centered on the deposition direction MD1. The deposition direction MD1 can also be said to be a direction parallel to the central axis of the material M released from the nozzle N1, or the main release direction of the material M. In the example of FIG. 13, the axis AX1 of each nozzle N1 is inclined to the first side direction SD1. As a result, the deposition direction MD1 is also inclined to the first side direction SD1.

[0097] At least one of the deposition sources DS2 to DS7 may further include a shield 20 as shown in Fig. 13. At least one of the deposition sources DS2 to DS7 may further include a shield 30 as shown in Fig. 12.

[0098] 14 is a schematic perspective view showing an example of a configuration applicable to the deposition source DS8 of the upper electrode UE1. In the following description, the nozzle N of the deposition source DS8 is referred to as the nozzle N2. The nozzle N2 emits vaporized material M in a deposition direction MD2.

[0099] The deposition direction MD2 is, for example, parallel to the axis AX2 of the nozzle N2 (extension direction of the nozzle N2). The material M is emitted from the nozzle N2 with a predetermined spread angle centered on the deposition direction MD2. The deposition direction MD2 can also be said to be a direction parallel to the central axis of the material M emitted from the nozzle N2, or the main emission direction of the material M. In the example of FIG. 14, the axis AX2 of each nozzle N2 is inclined toward the second side SD2. As a result, the deposition direction MD2 is also inclined toward the second side SD2.

[0100] The deposition source DS8 may further include a shield 20 as shown in FIG 14. The deposition source DS8 may further include a shield 30 as shown in FIG 12.

[0101] Fig. 15 is a schematic cross-sectional view showing a process of forming a hole injection layer HIL by a deposition source DS1. The cross section shown in this figure corresponds to the YZ cross section similar to Fig. 5. Although one nozzle N0 and a container CT in the vicinity thereof are shown above the substrate 10X, in reality, multiple nozzles N0 are lined up in the left-right direction of Fig. 15.

[0102] 15, the axis AX0 of the nozzle N0 is parallel to the Z direction (the normal direction of the substrate 10X). That is, the deposition direction MD0 is not inclined with respect to the Z direction.

[0103] As described above, it is preferable that the hole injection layer HIL is separated from the bottom layer 63 of the partition wall 6. Therefore, in order to reduce the spread of the material M discharged from the nozzle N0, the deposition source DS1 is preferably provided with the shield 30 shown in FIG. 12. The deposition source DS1 may further include the shield 20 shown in FIG. 11. If the spread of the material M is reduced, the material M is blocked by the upper portion 62 of the partition wall 6, and the material M is less likely to adhere to the lower portion of the upper portion 62. This makes it possible to suppress contact between the hole injection layer HIL (first layer L1) and the lower portion 61 (the bottom layer 63 and the axial layer 64).

[0104] Fig. 16 is a schematic cross-sectional view showing a process of forming a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL using deposition sources DS2 to DS7. The cross section shown in this figure corresponds to the YZ cross section similar to Fig. 15. Although one nozzle N1 and a container CT in its vicinity are shown above the substrate 10X, in reality, multiple nozzles N1 are lined up in the left-right direction of Fig. 16.

[0105] The axis AX1 of the nozzle N1 is inclined toward the first side SD1 with respect to the Z direction. As a result, the axis AX1 and the deposition direction MD1 form an acute angle θ1 with respect to the Z direction. Each of the deposition sources DS2 to DS7 may include at least one of the shields 20 and 30 described above.

[0106] 16, the deposition direction MD1 of the deposition sources DS2 to DS7 is inclined as shown in FIG. 16, the material M is likely to adhere to the vicinity of the side surface on the second side SD2 side of each partition 6, and the material M is unlikely to adhere to the vicinity of the side surface on the first side SD1 side. This makes it possible to form the second layer L2 having different thicknesses in the vicinity of the partitions 6A and 6B as shown in FIG.

[0107] Fig. 17 is a schematic cross-sectional view showing a process of forming the upper electrode UE1 by the deposition source DS8. The cross section shown in this figure corresponds to the YZ cross section similar to Fig. 15 and Fig. 16. Although one nozzle N2 and a container CT in the vicinity thereof are shown above the substrate 10X, in reality, multiple nozzles N2 are lined up in the left-right direction of Fig. 17.

[0108] The axis AX2 of the nozzle N2 is inclined toward the second side SD2 with respect to the Z direction. As a result, the deposition direction MD2 is inclined in the opposite direction to the deposition direction MD1. The axis AX2 and the deposition direction MD2 form an acute angle θ2 with respect to the Z direction. The angle θ2 may be equal to or different from the angle θ1. The deposition source DS8 may include at least one of the shields 20 and 30 described above.

[0109] 17, when the deposition direction MD2 of the deposition source DS8 is inclined, the material M is likely to adhere to the vicinity of the side surface on the first side SD1 side of each partition 6, and the material M is unlikely to adhere to the vicinity of the side surface on the second side SD2 side. This makes it possible to form the upper electrode UE1 having different thicknesses in the vicinity of the partitions 6A and 6B, as shown in FIG.

[0110] 18 is a diagram showing another example of a process for forming the upper electrode UE1. When the upper electrode UE1 is made of an alloy of magnesium and silver as described above, the upper electrode UE1 is formed by co-evaporation of magnesium and silver.

[0111] Specifically, a deposition source DS8a that emits a material Ma of magnesium and a deposition source DS8b that emits a material Mb of silver are disposed in a chamber C8 (see FIG. 9) of the deposition device DD8. These deposition sources DS8a and DS8b are disposed adjacent to each other in the movement direction FD, for example, as shown in the plan view of FIG.

[0112] Fig. 18(b) is a schematic side view of the deposition sources DS8a and DS8b shown in Fig. 18(a) as viewed along the movement direction FD. Fig. 18(c) is a schematic side view of the deposition sources DS8a and DS8b shown in Fig. 18(a) as viewed along the nozzle arrangement direction ND. As shown in Figs. 18(b) and 18(c), the deposition source DS8a includes a nozzle N2a, and the deposition source DS8b includes a nozzle N2b.

[0113] As shown in Fig. 18(b), the axis AX2a of the nozzle N2a and the axis AX2b of the nozzle N2b are both inclined to the second side SD2 with respect to the Z direction. As a result, the deposition direction MD2a of the deposition source DS8a and the deposition direction MD2b of the deposition source DS8b are also inclined to the second side SD2 with respect to the Z direction. For example, in Fig. 18(b), the angles that the axes AX2a and AX2b (or the deposition directions MD2a and MD2b) make with the Z direction are equal.

[0114] It is preferable that the region where the deposition source DS8a emits the material Ma and the region where the deposition source DS8b emits the material Mb overlap on the surface of the substrate 10X. Therefore, in FIG. 18(c), the axes AX2a and AX2b are also inclined in the XZ plane defined by the X direction and the Z direction.

[0115] Specifically, the axis AX2a is inclined to the fourth side direction SD4 with respect to the Z direction. As a result, the deposition direction MD2a is also inclined to the fourth side direction SD4 with respect to the Z direction. Moreover, the axis AX2b is inclined to the third side direction SD3 with respect to the Z direction. As a result, the deposition direction MD2b is also inclined to the third side direction SD3 with respect to the Z direction.

[0116] With this configuration, the materials Ma and Mb are mixed together in the moving direction FD and adhere to the substrate 10X. Therefore, the upper electrode UE1 having uniform properties can be formed over the entire substrate 10X.

[0117] 15 and 16 show how each thin film of the organic layer OR1 is formed by one deposition source. However, among the multiple thin films constituting the organic layer OR1, for example, the hole injection layer HIL, the light emitting layer EML, and the electron transport layer ETL may be formed by co-evaporation of a host material and a dopant. In the deposition apparatus for forming such thin films, multiple deposition sources having different nozzle axes (inclinations of the deposition direction) may be arranged in the chamber, as in the example of FIG. 18.

[0118] 9 to 18 can also be applied to the deposition of the organic layers OR2, OR3 and the upper electrodes UE2, UE3. That is, when forming the organic layers OR2, OR3 and the upper electrodes UE2, UE3, the deposition direction MD0 of the hole injection layer HIL should be parallel to the Z direction, and the deposition direction MD1 of the hole transport layer HTL, the electron blocking layer EBL, the light emitting layer EML, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL should be inclined in the opposite direction to the deposition direction MD2 of the upper electrodes UE2, UE3.

[0119] 6, when the sides S1a, S2b, and S3a are set as the contact sides of the subpixels SP1, SP2, and SP3, respectively, the deposition directions MD1 and MD2 in forming the organic layer OR2 and the upper electrode UE2 are inclined in the opposite directions to the deposition directions MD1 and MD2 in forming the organic layer OR1 and the upper electrode UE1, respectively. This makes it possible to reduce the thickness of the organic layer OR2 and increase the thickness of the upper electrode UE2 in the vicinity of the side S2b.

[0120] By using the manufacturing method according to this embodiment, it is possible to make the organic layers OR1, OR2, and OR3 thin and the upper electrodes UE1, UE2, and UE3 thick in the vicinity of the contact side, as in the structure illustrated in Fig. 5. This allows for good electrical continuity between the upper electrodes UE1, UE2, and UE3 and the partition wall 6 at the contact side, as described with reference to Figs. 5 and 6.

[0121] In this embodiment, the deposition directions MD1 and MD2 of the deposition sources DS2 to DS8 are inclined in a direction perpendicular to the moving direction FD (first side SD1 or second side SD2). Such a configuration is advantageous when performing co-deposition as shown in FIG. 18. That is, in a configuration in which the deposition directions MD1 and MD2 are inclined in a direction parallel to the moving direction FD (third side SD3 or fourth side SD4), it may be difficult to mix materials emitted from multiple deposition sources for co-deposition well in the moving direction FD. If the regions where these materials adhere to the substrate 10X are misaligned in the moving direction FD, the film formed by deposition may have uneven properties in the thickness direction (for example, uneven dopant concentration).

[0122] On the other hand, when the deposition directions MD1 and MD2 are inclined in a direction perpendicular to the moving direction FD (first side direction SD1 or second side direction SD2), the deposition directions of the deposition sources are also inclined in a direction parallel to the moving direction FD as shown in Fig. 18(c), for example, so that the materials emitted from the deposition sources can be mixed well in the moving direction FD. As a result, the film formed by deposition is less likely to have uneven properties in the thickness direction.

[0123] 9 to 18, the hole transport layer HTL, the electron blocking layer EBL, the light emitting layer EML, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL are examples of the first thin film formed by tilting the axis of the nozzle, and the hole injection layer HIL is an example of the second thin film formed without tilting the axis of the nozzle.

[0124] As another example, all of the thin films constituting the organic layer OR1, including the hole injection layer HIL, may be formed using a nozzle having an axis inclined with respect to the Z direction, as in the example of Fig. 16. Also, at least one of the hole transport layer HTL, the electron blocking layer EBL, the emitting layer EML, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL may be formed using a nozzle having an axis parallel to the Z direction, as in the example of Fig. 15.

[0125] That is, at least one of the multiple thin films constituting the organic layer OR1 may be formed using a nozzle having an axis inclined in the opposite direction to the nozzle N2 of the upper electrode UE1. This makes the organic layer OR1 thinner at the contact side where the upper electrode UE1 is formed thick. Therefore, the conduction between the upper electrode UE1 and the partition wall 6 is improved compared to the case where all of the multiple thin films are formed using a nozzle having an axis parallel to the Z direction.

[0126] Furthermore, the deposition direction of at least one of the thin films constituting the organic layer OR1 may be inclined in the same direction as the deposition direction of the upper electrode UE1 at an angle smaller than that of the deposition direction of the upper electrode UE1. Even in this case, the upper electrode UE1 can be formed closer to the lower portion 61 than the organic layer OR1 on the contact side.

[0127] As yet another example, all of the multiple thin films constituting the organic layer OR1 may be formed using a nozzle having an axis parallel to the Z direction. Alternatively, at least one of the multiple thin films constituting the organic layer OR1 may be formed using a nozzle having an axis inclined with respect to the Z direction, and the upper electrode UE1 may be formed using a nozzle having an axis parallel to the Z direction.

[0128] 9 to 18, the substrate 10X is transported in the moving direction FD by the transport device CD, and the substrate 10X moves relative to the stationary deposition sources DS1 to DS8. As another example, during deposition by the deposition sources DS1 to DS8, the substrate 10X may be stationary in each of the chambers C1 to C8, and the deposition sources DS1 to DS8 may move relative to the substrate 10X. In this case, for example, the deposition devices DD1 to DD8 each include a drive mechanism for moving the deposition sources DS1 to DS8 in the chambers C1 to C8.

[0129] The modifications described above regarding the organic layer OR1 and the upper electrode UE1 can be similarly applied to the organic layers OR2 and OR3 and the upper electrodes UE2 and UE3.

[0130] The configuration of the partition wall 6 is not limited to that shown in Fig. 5 etc. Some modified examples that can be applied to the partition wall 6 are described below.

[0131] FIG. 19 is a schematic cross-sectional view showing a first modified example of a configuration applicable to the partition wall 6. In the example of this figure, both ends of the bottom layer 63 are aligned with the side surfaces of the axis layer 64. The right side surface of the partition wall 6 shown in the figure corresponds to the contact side with the upper electrode UE1. That is, the upper electrode UE1 of the right subpixel SP1 in the figure is in contact with the side surfaces of the bottom layer 63 and the axis layer 64. On the other hand, the organic layer OR1 of the right subpixel SP1 is separated from the side surfaces of the bottom layer 63 and the axis layer 64. As another example, the organic layer OR1 may be in contact with the side surfaces of the bottom layer 63 and the axis layer 64.

[0132] 20 is a schematic cross-sectional view showing a second modified example of a configuration applicable to the partition wall 6. In the example of this figure, the lower part 61 does not include a bottom layer 63. That is, the lower part 61 is formed of an axis layer 64. In this figure, too, the right side surface of the partition wall 6 corresponds to the contact edge, and the upper electrode UE1 is in contact with this side surface. As in the example of FIG. 19, the organic layer OR1 of the right subpixel SP1 is separated from the side surface of the axis layer 64. As another example, the organic layer OR1 may be in contact with the side surface of the axis layer 64.

[0133] All display devices, manufacturing methods, and manufacturing apparatuses that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices, manufacturing methods, and manufacturing apparatuses described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0134] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0135] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0136] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE1, SE2, SE3...sealing layer, DD1 to DD8...evaporation device, DS1 to DS8...evaporation source, N0, N1, N2...nozzle, 5...rib, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axial layer, 100...manufacturing equipment.

Claims

1. preparing a substrate including a lower electrode, a rib having a pixel opening overlapping the lower electrode, and a partition wall having a conductive lower portion disposed on the rib and an upper portion protruding from a side surface of the lower portion; forming an organic layer on the substrate by deposition, the organic layer being in contact with the lower electrode through the pixel opening and emitting light in response to application of a voltage; forming an upper electrode by deposition on the substrate, the upper electrode covering the organic layer and contacting the lower portion of the partition wall; Including, the organic layer comprises a first thin film; a first deposition source used to form the first thin film includes a first nozzle configured to eject a vaporized material toward the substrate moving relatively to the first deposition source; a second deposition source used for forming the upper electrode includes a second nozzle configured to eject a vaporized material toward the substrate that moves relative to the second deposition source; an axis of at least one of the first nozzle and the second nozzle is inclined with respect to a normal direction of the substrate in a direction perpendicular to a moving direction of the substrate in a plan view; A method for manufacturing a display device.

2. an axis of the first nozzle is inclined with respect to the normal direction toward a first side direction perpendicular to the movement direction in a plan view; The axis of the second nozzle is inclined with respect to the normal direction toward a second side opposite the first side. The method for manufacturing the display device according to claim 1 .

3. the first deposition source includes a plurality of the first nozzles arranged in a direction perpendicular to the moving direction in a plan view, an axis of each of the plurality of first nozzles is inclined toward the first side; The method for manufacturing the display device according to claim 2 .

4. the second deposition source includes a plurality of the second nozzles arranged in a direction perpendicular to the moving direction in a plan view, an axis of each of the plurality of second nozzles is inclined toward the second side; The method for manufacturing the display device according to claim 2 .

5. the organic layer comprises a second thin film; a third deposition source used for forming the second thin film includes a third nozzle for ejecting a vaporized material; The axis of the third nozzle is parallel to the normal direction. The method for manufacturing the display device according to claim 2 .

6. The third deposition source further includes a shield that surrounds the third nozzle and has a uniform height around the entire circumference of the third nozzle. The method for manufacturing the display device according to claim 5 .

7. The first thin film is any one of a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The method for manufacturing the display device according to claim 5 .

8. The second thin film is a hole injection layer. The method for manufacturing the display device according to claim 7 .

9. the partition wall includes a first partition wall and a second partition wall disposed to sandwich the pixel opening, the upper portion of the first partition has a first end; the upper portion of the second partition has a second end; the organic layer is formed so that a thickness directly below the first end is smaller than a thickness directly below the second end; The method for manufacturing the display device according to claim 2 .

10. the upper electrode is formed so that a thickness directly below the first end is greater than a thickness directly below the second end. The method for manufacturing the display device according to claim 9 .

11. When forming the first thin film and the upper electrode, the substrate is moved relative to the first evaporation source and the second evaporation source which are stationary. The method for manufacturing the display device according to claim 1 .

12. When forming the first thin film and the upper electrode, the first evaporation source and the second evaporation source are moved relative to the stationary substrate. The method for manufacturing the display device according to claim 1 .

13. forming a cap layer covering the upper electrode. A method for manufacturing the display device according to claim 1 .

14. forming a sealing layer continuously covering the cap layer and the partition wall; The method for manufacturing the display device according to claim 13 .

15. a first deposition device for forming an organic layer, the organic layer being in contact with the lower electrode through the pixel opening and emitting light in response to application of a voltage, on a substrate including a lower electrode, a rib having a pixel opening overlapping the lower electrode, and a partition wall having a conductive lower portion disposed on the rib and an upper portion protruding from a side surface of the lower portion; a second deposition apparatus for forming an upper electrode on the substrate, the upper electrode covering the organic layer and contacting the lower portion of the partition wall; Equipped with the organic layer comprises a first thin film; the first deposition device includes a first deposition source provided with a first nozzle, the first nozzle ejecting vaporized material of the first thin film toward the substrate moving relatively to the first deposition source; the second deposition device includes a second deposition source provided with a second nozzle, the second nozzle ejecting vaporized material of the upper electrode toward the substrate moving relatively to the second deposition source; an axis of at least one of the first nozzle and the second nozzle is inclined with respect to a normal direction of the substrate in a direction perpendicular to a moving direction of the substrate in a plan view; Display device manufacturing equipment.

16. an axis of the first nozzle is inclined with respect to the normal direction toward a first side direction perpendicular to the movement direction in a plan view; The axis of the second nozzle is inclined with respect to the normal direction toward a second side opposite the first side. The display device manufacturing apparatus according to claim 15 .

17. the first deposition source includes a plurality of the first nozzles arranged in a direction perpendicular to the moving direction in a plan view, an axis of each of the plurality of first nozzles is inclined toward the first side; An apparatus for manufacturing a display device according to claim 16.

18. the second deposition source includes a plurality of the second nozzles arranged in a direction perpendicular to the moving direction in a plan view, an axis of each of the plurality of second nozzles is inclined toward the second side; An apparatus for manufacturing a display device according to claim 16.

19. the organic layer comprises a second thin film; a third deposition source used for forming the second thin film includes a third nozzle for ejecting a vaporized material; The axis of the third nozzle is parallel to the normal direction. An apparatus for manufacturing a display device according to claim 16.

20. The third deposition source further includes a shield that surrounds the third nozzle and has a uniform height around the entire circumference of the third nozzle.

20. An apparatus for manufacturing a display device according to claim 19.

21. The first thin film is any one of a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

20. An apparatus for manufacturing a display device according to claim 19.

22. The second thin film is a hole injection layer. An apparatus for manufacturing a display device according to claim 21.

23. When forming the first thin film and the upper electrode, the substrate is moved relative to the first evaporation source and the second evaporation source which are stationary. The display device manufacturing apparatus according to claim 15 .

24. When forming the first thin film and the upper electrode, the first evaporation source and the second evaporation source are moved relative to the stationary substrate. The display device manufacturing apparatus according to claim 15 .

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