Semiconductor device

Abstract

To realize a semiconductor device 1 in which the width of a channel region 5 and the width of a JFET region 8 can be designed freely in a trench MOSFET of a vertical channel fin structure.SOLUTION: A semiconductor device 1 is a trench MOSFET of a vertical channel fin structure. End parts in a width direction of the bottom surfaces of a plurality of trenches 2 are arranged in a body region 9. A channel region 5 is connected to the body region 9 and a channel current flows in the channel region 5 in a vertical direction. A JFET region 8 has a first JFET region 8A and a second JFET region 8B arranged closer to the channel region 5 than the first JFET region 8A. The second JFET region 8B is wider than the first JFET region 8A.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] As one type of trench-type MOSFET, a trench MOSFET with a vertical channel fin structure has been proposed.

[0003] Fig. 17 is a perspective view for explaining a typical structure of a conventional trench MOSFET having a vertical channel fin structure, in which the gate electrode, gate insulating film, interlayer insulating film, source electrode, and drain electrode are omitted.

[0004] A conventional semiconductor device 1 shown in Fig. 17 has a longitudinal direction in a first direction and a lateral direction in a second direction when viewed in a plan view, and has a plurality of trenches 2 arranged in the second direction. Note that the trenches 2 shown by dotted lines in the cross section at the front of Fig. 17 show positions that virtually correspond to the trenches 2 in order to explain the positional relationship between other components and the trenches 2.

[0005] The first conductivity type source region 3 includes a region having a fin structure at least partially separated by a plurality of trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the source region 3 in contact with the source region 3. A first conductivity type JFET region 8 is formed below the channel region 5, and a second conductivity type body region 9 is formed on the side of the JFET region 8. The ends of the bottom surfaces of the plurality of trenches 2 in the first direction are disposed in the body region 9. The channel region 5 is connected to the body region 9. A first conductivity type drift region 10 is formed below the JFET region 8, and a first conductivity type drain region 11 is formed below the drift region 10.

[0006] 17 has a gate insulating film disposed inside the trench 2 and a gate electrode including a region at least partially disposed inside the trench 2, and a channel current flows vertically (in the depth direction) through the channel region 5. The gate electrodes embedded inside the trench 2 are connected to each other outside the trench 2.

[0007] Incidentally, an example of a patent document related to such technology is Patent Document 1. Although the names of the components and the detailed structure are different, paragraphs 0048 to 0052, FIG. 3, and FIG. 14 to FIG. 18 of Patent Document 1 describe a configuration similar to FIG. 17 described above. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2004-207289 A Summary of the Invention [Problem to be solved by the invention]

[0009] According to the structure of the conventional semiconductor device 1 shown in FIG. 17, the trench pitch can be reduced to increase the channel density, thereby increasing the number of channels, thereby reducing the on-resistance when viewed as a whole semiconductor chip.

[0010] In addition, due to the presence of the JFET region 8 formed between the body regions 9, a depletion layer extends from the body region 9 to the JFET region 8 in the event of a short circuit, causing pinch-off, thereby providing a high short-circuit resistance.

[0011] Furthermore, since the ends of the bottom surfaces of the multiple trenches 2 in the first direction are disposed within the body region 9, the three-dimensional corners of the trenches 2 are located within the body region 9. As a result, even when a high voltage is applied, the concentration of the electric field is alleviated at the three-dimensional corners of the trenches 2, where the electric field is likely to concentrate and the gate insulating film is likely to be destroyed, and the destruction of the gate insulating film can be suppressed.

[0012] Here, the on-resistance can also be reduced by increasing the width of the channel region 5 (the length of the channel region 5 in the first direction) to reduce the channel resistance.

[0013] However, in the structure of the conventional semiconductor device 1 shown in FIG. 17, the channel region 5 has a fin structure separated by a plurality of trenches 2, the ends of the bottom surfaces of the plurality of trenches 2 in the first direction are disposed in the body region 9, and the channel region 5 is connected to the body region 9. Therefore, the width of the channel region 5 is the width obtained by subtracting the overlapping width between the trench 2 and the body region 9 from the longitudinal width of the trench 2 (the length of the trench 2 in the first direction), and the width of the channel region 5 and the width of the JFET region 8 immediately below it (the length of the JFET region 8 in the first direction) are the same. Therefore, the width of the channel region 5 and the width of the JFET region 8 immediately below it cannot be designed independently, and if an attempt is made to reduce the on-resistance by increasing the width of the channel region 5 to improve performance, the width of the JFET region 8 increases, causing a problem that the short circuit withstand capability and withstand voltage decrease, resulting in a decrease in reliability, and there is a trade-off between performance and reliability.

[0014] The problem to be solved by the present invention is to realize a semiconductor device having a high degree of freedom in designing the width of the channel region and the width of the JFET region in a trench MOSFET with a vertical channel fin structure. [Means for solving the problem]

[0015] In order to achieve the above object, a semiconductor device of the present invention includes a first conductivity type source region including a region having a longitudinal direction in a first direction and a lateral direction in a second direction when viewed in a plan view, the longitudinal direction being in a first direction and a lateral direction being in a second direction and arranged in the second direction, at least a portion of which is a fin structure separated by the trenches, a second conductivity type channel region of a fin structure separated by the trenches and in contact with a lower surface of the source region, a gate insulating film disposed within the trenches, a gate electrode including a region at least a portion of which is disposed within the trenches, and a first conductivity type gate insulating film disposed below the channel region. and a body region of a second conductivity type arranged on a side of the JFET region, wherein ends of bottom surfaces of the plurality of trenches in the first direction are arranged in the body region, the channel region is connected to the body region, and a channel current flows in a vertical direction through the channel region, the JFET region has a first JFET region and a second JFET region arranged on the channel region side of the first JFET region, and the length of the second JFET region in the first direction is longer than the length of the first JFET region in the first direction. Effect of the Invention

[0016] According to the present invention, it is possible to realize a semiconductor device having a high degree of freedom in designing the width of the channel region and the width of the JFET region in a trench MOSFET having a vertical channel fin structure. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a perspective view showing a schematic configuration of a semiconductor device according to a first embodiment. [Diagram 2] Cross-sectional view taken along the line X1-X1' of Figure 1. [Diagram 3] Cross-sectional view taken along the line X2-X2' of Figure 1. [Figure 4] Cross-sectional view taken along the line Y1-Y1' in Figure 1. [Diagram 5] 3 is a cross-sectional view taken along the line X1-X1' of FIG. 2, showing another example of the schematic configuration of the semiconductor device according to the first embodiment. FIG. [Figure 6]FIG. 11 is a cross-sectional view taken along the line X1-X1′ showing a schematic configuration of a semiconductor device according to a second embodiment, and is a diagram showing a schematic view of the expansion of a depletion layer during normal operation. [Figure 7] FIG. 11 is a cross-sectional view taken along the line X1-X1′ showing a schematic configuration of a semiconductor device according to a second embodiment, and is a diagram showing a schematic view of the expansion of a depletion layer during short-circuiting or blocking. [Figure 8] FIG. 11 is a diagram showing the trade-off between performance and reliability in a case where reliability is prioritized in a design of the semiconductor device according to the second embodiment. [Figure 9] FIG. 11 is a diagram showing the trade-off between performance and reliability in the case of a performance-oriented design in the semiconductor device of the second embodiment. [Figure 10] FIG. 11 is a cross-sectional view taken along the line X1-X1′ showing a schematic configuration of a semiconductor device according to a third embodiment, and is a diagram showing a schematic view of the expansion of a depletion layer during short-circuiting or blocking. [Figure 11] FIG. 11 is a cross-sectional view taken along the line X1-X1′ showing a schematic configuration of a semiconductor device according to a fourth embodiment. [Figure 12] 12 is a diagram showing an impurity concentration profile in the depth direction along the line Z1-Z1′ in FIG. 11. [Figure 13] FIG. 11 is a cross-sectional view taken along the line X1-X1′ showing a schematic configuration of a semiconductor device according to a fifth embodiment. [Figure 14] FIG. 13 is a diagram for explaining the relationship between the integral value of the dose in the JFET region and the electric field in the gate insulating film in the semiconductor device of Example 6. [Figure 15] 13 is a cross-sectional view taken along the line X1-X1' for explaining a manufacturing method of the semiconductor device according to the seventh embodiment. FIG. [Figure 16] 16 is a diagram showing an impurity concentration profile in the depth direction along the line Z2-Z2′ in FIG. 15, illustrating the manufacturing method of the semiconductor device of Example 7. [Figure 17] FIG. 1 is a perspective view illustrating a structure of a conventional trench MOSFET having a vertical channel fin structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and duplicated explanations will be omitted. EXAMPLES

[0019] Fig. 1 is a perspective view showing a schematic configuration of a semiconductor device of Example 1. Fig. 2 is a cross-sectional view taken along X1-X1' in Fig. 1. Fig. 3 is a cross-sectional view taken along X2-X2' in Fig. 1. Fig. 4 is a cross-sectional view taken along Y1-Y1' in Fig. 1. Note that in Fig. 1, the gate electrode 7, gate insulating film 6, interlayer insulating film 14, source electrode 12, and drain electrode 13 are omitted from illustration.

[0020] The semiconductor device 1 of this embodiment has a plurality of trenches 2, a source region 3 of a first conductivity type, a channel region 5 of a second conductivity type, a gate insulating film 6, a gate electrode 7, a JFET region 8 of the first conductivity type, and a body region 9 of the second conductivity type.

[0021] In this embodiment, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type.

[0022] The multiple trenches 2 have a longitudinal direction in a first direction (X1-X1' direction in FIG. 1) when viewed in a plane, a lateral direction in a second direction (Y1-Y1' direction in FIG. 1), and are arranged in a plurality of rows in the second direction. Note that the trenches 2 shown by dotted lines in the cross sections of FIG. 1 and FIG. 2 show positions that virtually correspond to the trenches 2 in order to explain the positional relationship between the other components and the trenches 2.

[0023] The first conductivity type source region 3 includes a region having at least a part of a fin structure separated by a plurality of trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the source region 3 in contact with the source region 3. A first conductivity type JFET region 8 is formed below the channel region 5, and a second conductivity type body region 9 is formed on the side of the JFET region 8. The channel region 5 is connected to the body region 9. Therefore, the width of the channel region 5 is the width of the trench 2 in the longitudinal direction minus the overlap width between the trench 2 and the body region 9.

[0024] A gate insulating film 6 is disposed inside the trench 2. At least a portion of a gate electrode 7 is disposed inside the trench 2. The gate electrodes 7 disposed inside the trench 2 are connected to each other outside the trench 2. The gate electrodes 7 can be formed of, for example, polysilicon.

[0025] In the semiconductor device 1 of this embodiment, a channel current flows vertically (in the depth direction) in the channel region 5 of the fin structure by inputting and controlling a gate drive signal to the gate electrode 7 inside the trench 2. That is, the semiconductor device 1 is a trench MOSFET with a vertical channel fin structure. Therefore, the number of channels can be increased by reducing the trench pitch and increasing the channel density, so that the on-resistance when viewed as a whole semiconductor chip can be reduced. In addition, since there is a JFET region 8 formed between the body regions 9, a depletion layer extends from the body region 9 to the JFET region 8 and pinches off during a short circuit, so that the short circuit resistance is high.

[0026] In addition, the semiconductor device 1 of this embodiment also has a first conductivity type drift region 10 arranged below the JFET region 8, a first conductivity type drain region 11 arranged below the drift region 10, a source electrode 12 arranged on the front side, a drain electrode 13 arranged on the back side, and an interlayer insulating film 14.

[0027] The source electrode 12 is an electrode made of a metal such as aluminum, and is electrically connected to the source region 3. In this embodiment, the source electrode 12 is electrically connected to the body region 9 via the contact region 4 of the second conductivity type having a higher impurity concentration than the body region 9, but the present invention is not limited to this, and the source electrode 12 may be directly connected to the body region 9.

[0028] The drain electrode 13 is an electrode made of a metal such as aluminum, and is electrically connected to the drain region 11 .

[0029] The interlayer insulating film 14 is formed between the mutually connected portions of the gate electrodes 7 and the source region 3. The interlayer insulating film 14 is also formed so as to cover the upper and side portions of the mutually connected portions of the gate electrodes 7.

[0030] In the semiconductor device 1 of this embodiment, the ends of the bottom surfaces of the multiple trenches 2 in the first direction are disposed within the body region 9. This results in a structure in which three-dimensional corners of the trenches 2 are present within the body region 9. Therefore, in the three-dimensional corners of the trenches 2 where an electric field is likely to concentrate and breakdown of the gate insulating film 6 is likely to occur, the concentration of the electric field is alleviated even when a high voltage is applied, and breakdown of the gate insulating film 6 can be suppressed.

[0031] Furthermore, in the semiconductor device 1 of this embodiment, the JFET region 8 has a first JFET region 8A and a second JFET region 8B arranged closer to the channel region 5 than the first JFET region 8A, and the width of the second JFET region 8B (the length in the first direction of the second JFET region 8B) is longer than the width of the first JFET region 8A (the length in the first direction of the first JFET region 8A). As a result, even if there is a constraint that the width of the channel region 5 and the width of the second JFET region 8B directly below it are the same, the width of the channel region 5 and the width of the first JFET region 8A are not subject to that constraint, and both can be designed independently. Also, the smaller the width of the JFET region 8, the easier it is for the depletion layer extending from the body region 9 to the JFET region 8 to close and pinch off within the JFET region 8 during a short circuit, so the short circuit resistance is increased. Therefore, by increasing the width of the channel region 5 to reduce the on-resistance in order to improve performance, while making the width of the first JFET region 8A smaller than that, it is possible to ensure short circuit resistance and withstand voltage, and therefore reliability can also be ensured, and the degree of design freedom is high compared to the conventional case where the JFET region 8 has only one width, improving the trade-off relationship between performance and reliability, and making it possible to achieve both performance and reliability. In addition, since the width of the first JFET region 8A can be changed independently of the width of the channel region 5 according to the required withstand voltage, design changes become easier.

[0032] As described above, according to this embodiment, in a trench MOSFET having a vertical channel fin structure, a semiconductor device 1 having a high degree of freedom in designing the width of the channel region 5 and the width of the JFET region 8 can be realized.

[0033] It is preferable that the position in the depth direction of the lower end of the gate electrode 7 disposed inside the trench 2 overlaps with the position in the depth direction of the second JFET region 8B. Here, the position in the depth direction of the lower end of the gate electrode 7 may be the same as the position in the depth direction of the upper end or the lower end of the second JFET region 8B, but in consideration of manufacturing variations, it is preferable that the position in the depth direction of the lower end of the gate electrode 7 is deeper than the position in the depth direction of the upper end of the second JFET region 8B and shallower than the position in the depth direction of the lower end of the second JFET region 8B.

[0034] Furthermore, it is desirable that the width of the first JFET region 8A is 0.1 μm or more, and the width of the second JFET region 8B is 5 μm or less, but this is not limitative.

[0035] The impurity concentration of the first JFET region 8A may be the same as or different from the impurity concentration of the second JFET region 8B.

[0036] As for the impurity concentration, the first JFET region 8A and the second JFET region 8B are illustrated as n, the body region 9 and the channel region 5 as p, the drift region 10 as low concentration n-, the source region 3 and the drain region 11 as high concentration n+, and the contact region 4 as high concentration p+ as an example in this embodiment, but this is not limited as long as the intended operation of this embodiment can be realized. For example, the first JFET region 8A and the second JFET region 8B may be low concentration n-.

[0037] The semiconductor device 1 of this embodiment can be formed using, for example, an n+ type SiC substrate, but is not limited to this and may be formed using a Si substrate, etc. Furthermore, for parts in this specification where there is no special description of the manufacturing method, the semiconductor device can be manufactured by a general semiconductor device manufacturing method, for example, by forming an n+ type drain region 11 on an n+ type SiC substrate and forming an n- type drift region 10 by epitaxial growth, and so a detailed description will be omitted.

[0038] FIG. 5 is a cross-sectional view taken along line X1-X1' corresponding to FIG. 2, showing another example of the schematic configuration of the semiconductor device according to the first embodiment.

[0039] In Fig. 2, the JFET region 8 and the body region 9 are illustrated as simplified shapes such as rectangles, but in reality, since each region is fabricated by ion implantation or epitaxial growth, they may have a shape without corners and the boundary portion may be smoothly connected, as shown in Fig. 5, and there may be no clear boundary between the first JFET region 8A and the second JFET region 8B. Even in this case, it is the same as Fig. 2 in that the width of the second JFET region 8B is formed larger than the width of the first JFET region 8A.

[0040] In the following embodiments, the description will be based on the shape shown in FIG. EXAMPLES

[0041] Example 2 is a modification of Example 1, in which the first conductivity type impurity concentration of the second JFET region 8B is lower than the first conductivity type impurity concentration of the first JFET region 8A. Note that when the first conductivity type impurity concentration of the second JFET region 8B is 1×10 15 cm -3 or more, and the first conductivity type impurity concentration of the first JFET region 8A is 1×10 20 cm -3 The following is preferable, but not limited to this.

[0042] FIG. 6 is an X1-X1′ cross-sectional view showing a schematic configuration of the semiconductor device of Example 2, and is a diagram showing the expansion of the depletion layer during normal operation. FIG. 7 is an X1-X1′ cross-sectional view showing a schematic configuration of the semiconductor device of Example 2, and is a diagram showing the expansion of the depletion layer during short-circuiting or blocking. The depletion layer 17 is more likely to expand when the impurity concentration is low. Note that the expansion of the depletion layer 17 differs depending on the applied drain voltage value and the impurity concentration in each region, so FIGS. 6 and 7 are merely examples.

[0043] 6, during normal operation, the depletion layer 17 tends to expand in the second JFET region 8B, which has a low concentration, but the second JFET region 8B is wide, so the resistance in the second JFET region 8B is sufficiently low. Furthermore, although the first JFET region 8A is narrow, the depletion layer 17 does not easily extend from the body region 9 due to the high concentration, so the resistance is sufficiently low, resulting in high performance.

[0044] 7, during short circuit or blocking, the depletion layer 17 closes and pinches off in the second JFET region 8B because the second JFET region 8B has a low concentration, and the current is saturated. Since the second JFET region 8B is pinched off, the electric field of the gate insulating film 6 at the bottom of the trench 2 can be reduced.

[0045] In addition, as in this embodiment, the structure in which the width of the second JFET region 8B is larger than that of the first JFET region 8A and the first conductivity type impurity concentration of the second JFET region 8B is lower than that of the first conductivity type impurity concentration of the first JFET region 8A has the advantage that the electrical characteristics of the semiconductor device 1 are less affected by manufacturing variations within the wafer surface or between wafers. Specifically, since the width of the second JFET region 8B is wide, even if the width varies during manufacturing, the change in resistance of the JFET region 8 is small. Furthermore, since the first JFET region 8A has a high concentration, the depletion layer 17 does not easily extend, so even if the width varies during manufacturing, the change in resistance of the JFET region 8 is small. Furthermore, the first JFET region 8A requires a width that does not close the depletion layer 17 during normal operation, but even if the width varies during manufacturing, the depletion layer 17 does not easily extend due to the high concentration, so the effect of the width variation is small. Regarding the short circuit withstand capability, since the width of the second JFET region 8B that is pinched off during a short circuit is wider, the effect of width variations is smaller. Also, the need for precise exposure adjustment in the photo process during manufacturing can be reduced.

[0046] Next, the characteristics of the semiconductor device 1 of this embodiment will be described.

[0047] The semiconductor device 1 of this embodiment can widen the design window compared to the conventional one. An example will be described with reference to FIGS.

[0048] Fig. 8 is a diagram showing a trade-off between performance and reliability in a case where reliability is prioritized in a design in the semiconductor device of Example 2. Fig. 9 is a diagram showing a trade-off between performance and reliability in a case where performance is prioritized in a design in the semiconductor device of Example 2. In Figs. 8 and 9, the horizontal axis indicates the width of the first JFET region 8A, the vertical axis on the left indicates the saturation current at short circuit as an example of reliability, and the vertical axis on the right indicates the resistance of the JFET region 8 as an example of performance. Note that other indicators of performance and reliability may be used.

[0049] In FIG. 8, 101 indicates the characteristic of the short-circuit saturation current of the conventional specification, and 102 indicates the characteristic of the resistance of the JFET region 8 of the conventional specification. Here, the conventional specification is a specification in which there is no second JFET region 8B, and the entire JFET region 8 is composed only of the first JFET region 8A. Note that the characteristic changes depending on the depth and impurity concentration of the first JFET region 8A, so the one shown in FIG. 8 is only an example. The characteristic 101 of the short-circuit saturation current of the conventional specification increases as the width of the first JFET region 8A increases, so that the threshold point 103, which is equal to the threshold value of the allowable short-circuit saturation current, is the upper limit of the design width of the first JFET region 8A. The characteristic 102 of the resistance of the JFET region 8 of the conventional specification increases as the width of the first JFET region 8A decreases, and increases rapidly when the width of the first JFET region 8A becomes smaller than the threshold point 104 at which the depletion layer 17 pinches off in the JFET region 8 during normal operation. Therefore, the threshold point 104 is the lower limit of the design of the width of the first JFET region 8A. The area between the upper and lower design limits is the design window. The design window 105 of the width of the first JFET region 8A according to the conventional specifications has a size shown in FIG.

[0050] In contrast to this, 111 indicates the characteristics of the saturation current during short circuit in the reliability-oriented specification in this embodiment, and 112 indicates the resistance characteristics of the JFET region 8 in the reliability-oriented specification in this embodiment.

[0051] In the reliability-oriented specification and performance-oriented specification in this embodiment, a second JFET region 8B is added which is wider than the first JFET region 8A and has a lower impurity concentration of the first conductivity type. As an example, an example will be described in which the impurity concentration of the second JFET region 8B is lower than that of the JFET region 8 of the conventional specification, and the impurity concentration of the first JFET region 8A is higher than that of the JFET region 8 of the conventional specification, but the present invention is not limited to this.

[0052] The reliability-oriented specification in this embodiment is realized, for example, when the impurity concentration of the second JFET region 8B is relatively low, when the width of the second JFET region 8B is relatively narrow, when the impurity concentration of the first JFET region 8A is set to a value close to the impurity concentration of the second JFET region 8B, etc., but is not limited to these. Note that the characteristics change depending on the depth and impurity concentration of the first JFET region 8A and the width, depth, and impurity concentration of the second JFET region 8B, so the one shown in FIG. 8 is just an example.

[0053] Regarding the reliability index, in the characteristic 111 of the short-circuit saturation current of the reliability-oriented specification, the depletion layer 17 closes and pinches off in the second JFET region 8B before the first JFET region 8A at high voltage, preventing a large current (short-circuit current) from flowing, so that the short-circuit saturation current can be made smaller than the characteristic 101 of the short-circuit saturation current of the conventional specification even if the width of the first JFET region 8A is the same. Accordingly, the threshold point 113 corresponding to the threshold point 103 moves to the right of the threshold point 103, and the upper limit of the design width of the first JFET region 8A is expanded.

[0054] Regarding the performance index, in the resistance characteristic 112 of the JFET region 8 of the reliability-oriented specification, there are some regions where the resistance is somewhat higher than the resistance characteristic 102 of the JFET region 8 of the conventional specification, but since the second JFET region 8B is wider than the first JFET region 8A and the first JFET region 8A has a higher concentration than the conventional specification, the threshold point 114 (pinch-off point) at which the depletion layer 17 is pinched off in the first JFET region 8A during normal operation can be made to the left of the threshold point 104 of the conventional specification. In this way, by moving the threshold point 114 to the left of the threshold point 104, the lower limit of the design width of the first JFET region 8A is expanded.

[0055] Therefore, the design window 115 for the width of the first JFET region 8A according to the reliability-oriented specifications in this embodiment can be made wider than the design window 105 for the width of the first JFET region 8A according to the conventional specifications.

[0056] In addition, although Fig. 8 shows an example in which the impurity concentration of the first JFET region 8A with reliability-oriented specifications is made higher than the impurity concentration of the first JFET region 8A with conventional specifications, it may be made the same as the impurity concentration of the first JFET region 8A with conventional specifications. In that case, the threshold point 114 becomes closer to the threshold point 104, so the lower limit of the design of the width of the first JFET region 8A does not change much, but the saturation current during short circuit is further reduced than that in Fig. 8, so the upper limit of the design is expanded. Therefore, even in this case, the design window 115 can be made wider than the design window 105.

[0057] The performance-oriented design of FIG. 9 has specifications in which the resistance of the JFET region 8 is lowered and the current during normal operation is increased compared to the reliability-oriented design of FIG.

[0058] In FIG. 9, a characteristic 101 of the saturation current at short circuit according to the conventional specification and a characteristic 102 of the resistance of the JFET region 8 according to the conventional specification are the same as those in FIG.

[0059] In contrast to this, 121 indicates the characteristics of the saturation current at short circuit in the performance-oriented specifications in this embodiment, and 122 indicates the resistance characteristics of the JFET region 8 in the performance-oriented specifications in this embodiment.

[0060] The performance-oriented specification of this embodiment can be realized, for example, by making the impurity concentration of the second JFET region 8B higher than the impurity concentration of the second JFET region 8B of the reliability-oriented specification while satisfying the condition that the second JFET region 8B has a lower concentration than the first JFET region 8A. Note that this is not limited to this, and at least one of the impurity concentration of the first JFET region 8A and the impurity concentration of the second JFET region 8B may be higher than the reliability-oriented specification while satisfying the condition that the second JFET region 8B has a lower concentration than the first JFET region 8A. Note that the characteristics change depending on the depth and impurity concentration of the first JFET region 8A and the width, depth, and impurity concentration of the second JFET region 8B, so the one shown in FIG. 9 is just an example.

[0061] Regarding the performance index, the resistance characteristic 122 of the JFET region 8 of the performance-oriented specification is smaller than the resistance characteristic 102 of the JFET region 8 of the conventional specification. This allows the current during normal operation to be increased, improving performance. Since the first JFET region 8A is highly doped, even if the width of the first JFET region 8A is narrowed to a narrower width than the conventional specification, it does not pinch off. Therefore, the threshold point 124 at which the depletion layer 17 pinches off in the first JFET region 8A during normal operation has moved to the left of the threshold point 104. Note that the second JFET region 8B is wide and does not pinch off during normal operation.

[0062] Regarding the reliability index, in the characteristic 121 of the short circuit saturation current of the performance-oriented specification, the short circuit saturation current is larger than that of the characteristic 101 of the short circuit saturation current of the conventional specification, and although the threshold point 123 corresponding to the threshold point 103 has moved to the left of the threshold point 103, the threshold point 124 corresponding to the threshold point 104 has also moved to the left, so that the design window 125 of the width of the first JFET region 8A of the performance-oriented specification is wider than the design window 105 of the width of the first JFET region 8A of the conventional specification. Also, at the time of high voltage, the depletion layer 17 closes and pinches off in the second JFET region 8B, preventing a large current (short circuit current) from flowing, so that the performance can be improved while the reliability can be ensured. EXAMPLES

[0063] Example 3 is a modification of Example 1, in which the first conductivity type impurity concentration of the second JFET region 8B is higher than the first conductivity type impurity concentration of the first JFET region 8A. Note that when the first conductivity type impurity concentration of the first JFET region 8A is 1×10 15 cm -3 or more, and the first conductivity type impurity concentration of the second JFET region 8B is 1×10 20 cm -3 The following is preferable, but not limited to this.

[0064] FIG. 10 is a cross-sectional view taken along the line X1-X1' showing a schematic configuration of a semiconductor device according to Example 3, and is a diagram showing a schematic view of the spread of a depletion layer during short-circuiting or blocking.

[0065] Example 3 differs from Example 2 in that the depletion layer 17 closes and pinches off in a part of the first JFET region 8A and the drift region 10. The location where the depletion layer 17 closes and pinches off is different from Example 2, but in this example, the width of the channel region 5 and the width of the first JFET region 8A can be designed independently. In addition, compared to Example 2, the pinched-off path can be made longer, so that the resistance of the path through which the saturation current flows increases, and the saturation current can be suppressed.

[0066] Although not shown, even during normal operation, the second JFET region 8B has a high concentration and therefore has a low resistance. EXAMPLES

[0067] Example 4 is a modification of Example 1, and has a channel push-back region 15 in a part of the second JFET region 8B, the channel push-back region 15 having a higher concentration of the first conductivity type impurity than the other part of the second JFET region 8B.

[0068] Fig. 11 is an X1-X1' cross-sectional view showing a schematic configuration of a semiconductor device of Example 4. Fig. 12 is a diagram showing an impurity concentration profile in the depth direction along Z1-Z1' in Fig. 11. In Fig. 12, the horizontal axis represents depth and the vertical axis represents impurity concentration. Note that Fig. 12 shows an example in which a channel push-back region 15 is provided in Example 2, but is not limited to this and may be applied to Example 1 or 3.

[0069] In addition to the effects of the first to third embodiments, the present embodiment can prevent the base of the second conductivity type impurity concentration in the channel region 5 from spreading by the channel push-back region 15 as shown in FIG. EXAMPLES

[0070] Example 5 is a modification of Example 1, in which the first conductivity type impurity concentration of the first JFET region 8A is different from the first conductivity type impurity concentration of the second JFET region 8B, and the JFET region having the higher first conductivity type impurity concentration of the first JFET region 8A or the second JFET region 8B has, between the body region 9, a low concentration region having a first conductivity type impurity concentration lower than other portions, or an intrinsic region 16 that is not doped with the first conductivity type impurity.

[0071] FIG. 13 is a cross-sectional view taken along the line X1-X1' showing a schematic configuration of a semiconductor device according to a fifth embodiment.

[0072] 13 shows an example in which an intrinsic region 16 is provided in the first JFET region 8A, which has a higher concentration, than the second JFET region 8B, as in Example 2. However, this is not limiting, and a low concentration region, in which the first conductivity type impurity concentration is lower than other portions, may be used instead of the intrinsic region 16. It is desirable for the low concentration region to have a sufficiently low concentration.

[0073] For example, if the second JFET region 8B is made very low concentration, it is necessary to make the first JFET region 8A somewhat high concentration in order to reduce the resistance of the JFET region 8. However, in that case, the junction electric field at the boundary between the first JFET region 8A and the body region 9 becomes high, which may cause undesirable operations such as avalanche multiplication and hot carrier effect. Therefore, by providing an intrinsic region 16 (i layer) as shown in Figure 13, the maximum electric field can be reduced by the following formula.

[0074] Emax(with i layer) / Emax(without i layer)=(1+d 2 / Wd 2 ) 0.5 -d / Wd Here, Wd is the depletion layer width in the pn junction, and d is the width of the i layer.

[0075] When the second JFET region 8B has a higher concentration than the first JFET region 8A as in the third embodiment, a low concentration region or intrinsic region 16 may be provided in the second JFET region 8B having a higher concentration. EXAMPLES

[0076] The sixth embodiment is a modification of the first embodiment.

[0077] In the semiconductor device 1 of this embodiment, at least some of the parameters of the width, depth, and first conductivity type impurity concentration of the first JFET region 8A and the width, depth, and first conductivity type impurity concentration of the second JFET region 8B are set so that (1) the integral value of the dose in the JFET region 8 is minimized, (2) the maximum value of the quasi-Fermi level of the JFET region 8 when a voltage is applied during normal operation is minimized, and (3) the depth of the depletion layer 17 that spreads into the drift region 10 during a short circuit is maximized.

[0078] Fig. 14 is a diagram for explaining the relationship between the integral value of the dose in the JFET region and the electric field of the gate insulating film in the semiconductor device of Example 6. In Fig. 14, the horizontal axis is the integral value of the dose in the JFET region 8, and the vertical axis is the electric field of the gate insulating film 6 during blocking. Note that the integral value of the dose in the JFET region 8 on the horizontal axis is the integral value of the dose in the entire JFET region 8 including the first JFET region 8A and the second JFET region 8B.

[0079] The condition (1) can reduce the electric field of the gate insulating film 6 during blocking. Note that, as shown in FIG. 14, within the design range of this embodiment, an example in which the relationship between the two is approximately linear is shown, but the present invention is not limited to this.

[0080] Condition (2) makes it possible to reduce the on-resistance of the entire JFET region 8 during normal operation.

[0081] Condition (3) makes it possible to minimize the current flowing through the JFET region 8 during a short circuit, thereby reducing the saturation current.

[0082] Furthermore, in combination with the second embodiment, (4) the design windows 115, 125 (see FIGS. 8 and 9) for the width of the first JFET region 8A may be set to be wider than a predetermined value or to be maximized.

[0083] As a design method, for example, at least some of the parameters among the width, depth, and first-conductivity-type impurity concentration of the first JFET region 8A and the width, depth, and first-conductivity-type impurity concentration of the second JFET region 8B are set as variables, and the rest are fixed, and values ​​that satisfy the requirements of conditions (1) to (3) or (1) to (4) are obtained. This design may be made by a person or may be made by using an optimization system using AI (Artificial Intelligence).

[0084] According to this embodiment, a semiconductor device that achieves both high performance and reliability can be realized. EXAMPLES

[0085] The seventh embodiment is a modification of the first embodiment.

[0086] Fig. 15 is an X1-X1' cross-sectional view for explaining the manufacturing method of the semiconductor device of Example 7. Fig. 16 is a diagram showing an impurity concentration profile in the depth direction along Z2-Z2' in Fig. 15 for explaining the manufacturing method of the semiconductor device of Example 7. In Fig. 16, the horizontal axis represents depth and the vertical axis represents impurity concentration.

[0087] In this embodiment, when the body region 9 is formed using the resist 18 as a mask, ions are implanted so that the depth-wise peak position of the second conductivity type impurity concentration is located at the depth-wise position of the first JFET region 8A, thereby giving a part of the body region 9 a protruding shape, and it is possible to form the body region 9 such that the width of the second JFET region 8B is greater than the width of the first JFET region 8A with a single ion implantation.

[0088] As a result, the semiconductor device 1 of this embodiment has a structure in which the peak position of the second conductivity type impurity concentration in the body region 9 in the depth direction overlaps with the position in the depth direction of the first JFET region 8A.

[0089] The manufacturing method and structure are not limited to those described above, and the body region 9 may be formed in two steps so that the width of the second JFET region 8B is larger than the width of the first JFET region 8A. In this case, the impurity concentration of the second conductivity type in the body region 9 does not need to have a peak in the depth direction.

[0090] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied. [Explanation of symbols]

[0091] 1 Semiconductor device 2. Trench 3 Source Area 4 Contact Area 5 Channel Area 6 Gate insulating film 7 Gate electrode 8 JFET area 8A First JFET Region 8B Second JFET Region 9. Body Region 10 Drift Region 11 Drain region 12 Source electrode 13 Drain electrode 14 Interlayer insulating film 15 Channel Rebound Region 16 Intrinsic domain 17 Depletion Layer 18 Resist

Claims

1. A plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction when viewed in a plan view, the trenches being arranged in the second direction; a first conductivity type source region including a region having a fin structure at least a portion of which is separated by the plurality of trenches; a second conductivity type channel region having a fin structure in contact with a lower surface of the source region and separated by the plurality of trenches; a gate insulating film disposed inside the trench; a gate electrode including a region at least partially disposed within the trench; a JFET region of a first conductivity type disposed below the channel region; a body region of a second conductivity type disposed on a side of the JFET region; ends of bottom surfaces of the plurality of trenches in the first direction are disposed within the body region; the channel region is connected to the body region, and a channel current flows vertically through the channel region; the JFET region has a first JFET region and a second JFET region disposed closer to the channel region than the first JFET region; A semiconductor device, wherein the length of the second JFET region in the first direction is longer than the length of the first JFET region in the first direction.

2. In claim 1, a first conductivity type impurity concentration in the second JFET region is lower than a first conductivity type impurity concentration in the first JFET region.

3. In claim 2, The first conductivity type impurity concentration of the second JFET region is 1×10 １５ cm －３ That's all. The first conductive type impurity concentration of the first JFET region is 1×10 ２０ cm －３ A semiconductor device characterized in that:

4. In claim 1, a first conductivity type impurity concentration in the second JFET region is higher than a first conductivity type impurity concentration in the first JFET region.

5. In claim 4, The first conductive type impurity concentration of the first JFET region is 1×10 １５ cm －３ That's all. The first conductivity type impurity concentration of the second JFET region is 1×10 ２０ cm －３ A semiconductor device characterized in that:

6. In claim 1, a peak position of the concentration of the second conductive type impurity in the body region in the depth direction overlaps with a position of the first JFET region in the depth direction.

7. In claim 1, a gate electrode disposed inside the trench and having a lower end positioned in a depth direction thereof overlapping a second JFET region in a depth direction thereof;

8. In claim 1, a channel return region having a higher first conductivity type impurity concentration than other portions of the second JFET region, the channel return region being in a portion of the second JFET region;

9. In claim 1, a contact region provided on a surface side of the body region and having a second conductivity type impurity concentration higher than that of the body region; a source electrode connected to the contact region and the source region;

10. In claim 1, the length of the first JFET region in the first direction is 0.1 μm or more; The semiconductor device according to claim 1, wherein the length of the second JFET region in the first direction is 5 μm or less.

11. In claim 1, a first conductivity type impurity concentration of the first JFET region is different from a first conductivity type impurity concentration of the second JFET region; a first JFET region having a higher concentration of a first conductivity type impurity than other portions, or an intrinsic region not doped with the first conductivity type impurity, between the body region and the first JFET region and the second JFET region, the first JFET region having a higher concentration of a first conductivity type impurity than other portions, the first conductivity type impurity being a low concentration region,

12. In claim 1, a drift region of a first conductivity type disposed below the JFET region; a drain region of a first conductivity type disposed below the drift region.

13. In claim 12, at least some of the parameters of the length in the first direction, the depth, and the first conductivity type impurity concentration of the first JFET region, and the length in the first direction, the depth, and the first conductivity type impurity concentration of the second JFET region are set so that an integral value of a dose in the JFET region is minimized, a maximum value of a quasi-Fermi level in the JFET region when a voltage is applied during normal operation is minimized, and a depth of a depletion layer spreading in the drift region during a short circuit is maximized.

14. In claim 1, A semiconductor device, wherein the length of the trench in the first direction is longer than the length of the second JFET region in the first direction.

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