Groove type MOSFET device for improving switching loss

Abstract

The invention belongs to the technical field of semiconductors, and discloses a trench MOSFET device for improving switching loss, which comprises an epitaxial layer formed above a substrate; the trench gate structures are arranged at intervals and are formed above the epitaxial layer region; the first well region is formed between the trench gate structures which are arranged at intervals; the second well region is formed above the first well region and has a second conduction type; the third well region is formed above the first well region, is positioned on two sides of the second well region, and is respectively in contact with the vertical wall surfaces of the trench gate structure; the trench gate structure comprises a gate and a gate oxide layer wrapping the outer wall surface of the gate, groove sections arranged at intervals are distributed in the longitudinal straight line section, perpendicular to the wall surface, of the gate oxide layer in the longitudinal direction, and the groove sections are concaved outwards in the transverse direction from the gate. According to the invention, the gate-source capacitance and the gate-drain capacitance of the whole assembly can be improved only by optimizing the trench gate structure design, and the production cost is greatly reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a trench MOSFET device for improving switching loss. Background Art

[0002] In the design of power conversion circuits, the metal oxide semiconductor field effect transistor (MOSFET), as a core switching device, its switching performance is mainly restricted by the parasitic capacitance effect inside the device. Specifically, as Figure 3 shown, the input capacitance Ciss of this device, as a key parameter of the gate drive characteristic, is composed of the parallel connection of the gate-source capacitance Cgs and the gate-drain capacitance Cgd. During the actual working process, the switching action of the MOSFET needs to repeatedly charge and discharge this input capacitance, which makes the input capacitance Ciss parameter not only directly affect the design requirements of the drive circuit, but also determine the switching loss level of the system.

[0003] To improve the high-frequency switching performance, the existing technology generally adopts the shielded-gate trench MOSFET structure. Although this structure effectively reduces the parasitic capacitance effect, its complex process leads to a significantly higher production cost than that of the conventional trench MOSFET, which seriously restricts its popularization in cost-sensitive application fields. Therefore, how to reduce the device manufacturing cost while ensuring the high-frequency switching performance has become an urgent technical problem to be solved in the current power semiconductor field. Summary of the Invention

[0004] To solve the deficiencies in the prior art, the present invention provides a trench MOSFET device for improving switching loss, which can improve the overall gate-source capacitance and gate-drain capacitance of the component only by optimizing the trench gate structure design, and greatly reduces the production cost.

[0005] The main technical solution adopted in the present invention is as follows: A trench MOSFET device for improving switching loss, comprising: An epitaxial layer formed above the substrate and having a first conductivity type; Trench gate structures arranged at intervals, formed above the epitaxial layer region; A first well region formed between the trench gate structures arranged at intervals and having a second conductivity type; A second well region formed above the first well region and having a second conductivity type; A third well region (105) formed above the first well region and located on both sides of the second well region, respectively contacting the vertical wall surfaces of the trench gate structures and having a first conductivity type; The trench gate structure includes a gate and a gate oxide layer coated on the outer wall surface of the gate. The longitudinal straight segment of the gate oxide layer perpendicular to the wall surface is longitudinally distributed with groove segments arranged at intervals, and the groove segments are concave outward in the transverse direction from the gate.

[0006] Preferably, each unit cell constituting the trench MOSFET device includes at least one group of groove segments.

[0007] Preferably, the gate is a polysilicon layer with a doping concentration of 5e15 - 1e16 cm -2 .

[0008] Preferably, the groove segments of the gate oxide layer are formed by oxidizing grooves filled with polysilicon. The longitudinal width of the groove filled with polysilicon is denoted as D3, the transverse width of the straight segment of the gate oxide layer is denoted as D, the thickness of the gate oxide layer formed by surface oxidation is denoted as D1, and the thickness of the gate oxide layer formed by consuming the polysilicon surface is denoted as D2. Then D = D1 + D2, and D3 ≤ 2 × D2.

[0009] Preferably, the first well region is formed by boron ion implantation with a doping concentration of 4e12 - 3e13 cm -2 .

[0010] Preferably, the second well region is formed by boron ion or boron difluoride ion implantation with a doping concentration of 8e14 - 5e15 cm -2 .

[0011] Preferably, the third well region is formed by phosphorus ion or arsenic ion implantation with a doping concentration of 5e15 - 1e16 cm -2 .

[0012] Preferably, it further includes a dielectric layer and a metal electrode layer. The dielectric layer is formed on the upper surface of the device, and the metal electrode layer is formed on the upper surface of the dielectric layer and contacts the second well region and the third well region respectively through the dielectric layer.

[0013] Beneficial effects: The present invention provides a trench power metal-oxide-semiconductor field-effect transistor for improving switching loss, having the following advantages: (1) By locally designing the longitudinal straight segment of the gate oxide layer perpendicular to the wall surface as a groove structure, while retaining the main structure, the thickness of the gate oxide layer is locally increased. This design effectively reduces the gate-source capacitance (Cgs) and gate-drain capacitance (Cgd) of the component on the basis of maintaining the original static characteristics of the device, thereby significantly reducing the switching loss of the MOSFET device and improving the high-frequency performance and energy efficiency performance of the device.

[0014] (2) Compared with the existing shielded gate trench MOSFET structure, the present invention reduces the number of photomasks through optimized design, significantly simplifies the manufacturing process flow, not only reduces the process complexity, but also greatly reduces the production cost and enhances the market competitiveness of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a longitudinal cross-sectional schematic diagram of Embodiment 1; Figure 2 is Figure 1 A-A cross-sectional schematic diagram of; Figure 3 is Figure 1 B-B cross-sectional schematic diagram of; Figure 4 It is a top view of a single groove segment; In the figure: epitaxial layer 100, gate oxide layer 101, straight segment 101a, groove segment 101b, gate 102, first well region 103, second well region 104, third well region 105, dielectric layer 106, metal electrode layer 107. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application. Embodiment 1

[0017] Hereinafter, taking the first conduction type as N-type and the second conduction type as P-type as an example, in combination with Figures 1-4 , the specific structure of Embodiment 1 will be described, where, as Figures 1-3 shown, the X-axis direction is the lateral direction of the device, the Y-axis direction is the longitudinal direction of the device, and the Z-axis direction is the vertical direction of the device.

[0018] A trench MOSFET device for improving switching loss, comprising: An epitaxial layer 100, formed above the substrate, having the first conduction type (N-type); Groove gate structures arranged at intervals, formed above the epitaxial layer 100 region; A first well region 103, formed between the groove gate structures arranged at intervals, having the second conduction type (P-type); A second well region 104, formed above the first well region 103, having the second conduction type (P-type); The third well region 105 is formed above the first well region 103 and on both sides of the second well region, and is in contact with the vertical wall surfaces of the trench gate structure respectively, and has the first conductivity type (N-type); The trench gate structure includes a gate 102 and a gate oxide layer 101 covering the outer wall surface of the gate 102. Groove segments 101b are arranged at intervals along the longitudinal straight segment 101a of the vertical wall surface of the gate oxide layer 101 in the longitudinal direction, and the groove segments 101b are concave outward in the transverse direction from the gate 102. In Embodiment 1, the gate 102 is a polysilicon layer, and its doping concentration is 5e15 - 1e16 cm -2 .

[0019] The dielectric layer 106 is formed on the upper surface of the device; The metal electrode layer 107 is formed on the upper surface of the dielectric layer 106 and passes through the dielectric layer 106 to be in contact with the second well region 104 and the third well region 105 respectively, serving as the source electrode.

[0020] In terms of the theoretical architecture, the gate oxide layer 101 is formed by oxidizing the polysilicon surface of the gate 102. Specifically in Embodiment 1, the longitudinal straight segment 101a of the gate oxide layer 101 is formed by oxidizing the longitudinal straight segment of the gate 102, and the groove segment 101b is formed by oxidizing the polysilicon filled in the groove. Since when forming silicon oxide on the polysilicon surface of the gate 102, the silicon oxide of this layer will consume part of the polysilicon surface layer. Therefore, in order to ensure that all the polysilicon filled in the groove can be oxidized to form silicon oxide, that is, the silicon oxide can fill the groove, the following design needs to be met: As Figure 4 shown is the top view of a single groove segment. Among them, the transverse width of the straight segment 101a of the gate oxide layer 101 is denoted as D, the thickness of the gate oxide layer formed by surface oxidation is denoted as D1, the thickness of the gate oxide layer formed by consuming the polysilicon surface is denoted as D2, and the longitudinal width of the polysilicon filling the groove is denoted as D3. Then D = D1 + D2 is satisfied, and D3 ≤ 2×D2.

[0021] In Embodiment 1, D1 = 0.55D, D2 = 0.45D.

[0022] In Embodiment 1, the first well region 103 is formed by boron ion implantation, and its doping concentration is preferably 4e12 - 3e13 cm -2 .

[0023] In Embodiment 1, the second well region 104 is formed by boron ion or boron difluoride ion implantation, and its doping concentration is preferably 8e14 - 5e15 cm -2 In Embodiment 1, the third well region 105 is formed by phosphorus ion or arsenic ion implantation, and its doping concentration is preferably 5e15 - 1e16 cm-2 。

[0024] In the present invention, the selection of the doped ions and their doping concentrations in the first well region 103, the second well region 104, and the third well region 105 belongs to conventional techniques, and those skilled in the art can make selective settings according to actual requirements.

[0025] The design principle of the present invention is as follows: As Figure 1 shown, in the layout design of the present invention, the trench gate structure is optimized, and a small part of the straight (longitudinal) trench gates are changed to a groove-like structure. While retaining the main structure as Figure 3 shown (ensuring that the static characteristics of the device are not affected), by forming a groove segment 101b as Figure 2 shown, the local gate oxide layer is thickened. Since the capacitance value between the two endpoints of the gate oxide layer is inversely proportional to the oxide layer thickness, this partial thickening design effectively reduces the overall gate-source capacitance (Cgs) and gate-drain capacitance (Cgd) of the device, thereby significantly reducing the switching loss of the device.

[0026] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made. These improvements and refinements.

Claims

1. A trench MOSFET device for improving switching loss, characterized in that, Comprising: An epitaxial layer (100) formed above a substrate and having a first conductivity type; Groove gate structures arranged at intervals from each other and formed above the region of the epitaxial layer (100); A first well region (103) formed between the groove gate structures arranged at intervals from each other and having a second conductivity type; A second well region (104) formed above the first well region (103) and having a second conductivity type; A third well region (105) formed above the first well region (103) and located on both sides of the second well region (104), respectively contacting the vertical wall surfaces of the groove gate structures and having a first conductivity type; The groove gate structure includes a gate (102) and a gate oxide layer (101) covering the outer wall surface of the gate (102). Groove segments (101b) arranged at intervals are distributed along the longitudinal straight segment (101a) of the vertical wall surface of the gate oxide layer (101) in the longitudinal direction, and the groove segments (101b) are recessed outward in the transverse direction from the gate (102).

2. The trench MOSFET device for improving switching loss according to claim 1, wherein Each unit cell constituting the trench MOSFET device includes at least one set of groove segments (101b).

3. The trench MOSFET device for improving switching loss according to claim 1, wherein The gate (102) is a polysilicon layer with a doping concentration of 5e15 - 1e16 cm -2 .

4. The trench MOSFET device for improving switching loss according to claim 3, wherein The groove segments (101b) of the gate oxide layer (101) are formed by groove oxidation filled with polysilicon. The longitudinal width of the polysilicon-filled groove is denoted as D3, the transverse width of the straight segment (101a) of the gate oxide layer (101) is denoted as D, the thickness of the gate oxide layer formed by surface oxidation is denoted as D1, and the thickness of the gate oxide layer formed by consuming the polysilicon surface is denoted as D2. Then D = D1 + D2 and D3 ≤ 2×D2 are satisfied.

5. The trench MOSFET device for improving switching loss according to claim 1, wherein The first well region (103) is formed by boron ion implantation, and its doping concentration is 4e12 - 3e13 cm -2 .

6. The trench MOSFET device for improving switching loss according to claim 1, characterized in that, The second well region (104) is formed by implanting boron ions or boron difluoride ions, and its doping concentration is 8e14 - 5e15 cm -2 .

7. The trench MOSFET device for improving switching loss according to claim 1, characterized in that, The third well region (105) is formed by implanting phosphorus ions or arsenic ions, and its doping concentration is 5e15-1e16 cm -2 .

8. The trench MOSFET device for improving switching loss according to claim 1, wherein It further includes a dielectric layer (106) and a metal electrode layer (107). The dielectric layer (106) is formed on the upper surface of the device. The metal electrode layer (107) is formed on the upper surface of the dielectric layer (106) and passes through the dielectric layer (106) to contact the second well region (104) and the third well region (105) respectively.

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