Highly efficient dual drive power amplifier for high reliability applications

Abstract

A dual-drive power amplifier (PA), in which the PA core includes a differential pair of transistors M1 and M2 driven by a coupling network having two transmission line couplers, a first transmission line section of the coupler configured to carry an input signal Vin to drive the gate of the opposite transistor, and a second transmission line section grounded at one end, with a coupled portion αVin of the input signal Vin coupled to the first transmission line section to drive the source terminal of the corresponding transistor. The coupling network arrangement allows the source terminal to be driven at a voltage lower than ground potential. The embodiments disclosed herein further provide an input matching network, a driver, an interstage matching network, and an output network for practical implementation of the PA core.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 136,264, filed January 12, 2021, which is incorporated by reference herein as if set forth in its entirety.

[0002] FIELD OF THEINVENTION Various embodiments of the present disclosure relate generally to amplifiers, and more particularly to a dual drive power amplifier configuration for wireless communication applications. [Background technology]

[0003] (background) Conventional power amplifiers (PAs) implemented in CMOS can suffer from low efficiency, low output power, low gain, and limited maximum operating frequency due to factors such as low breakdown voltage, low quality factor of on-chip passive elements, and large intrinsic device signal loss at higher frequencies. Complex design techniques have been implemented to address some of these issues. For example, techniques such as load modulation, harmonic tuned loads, stacked PA cores, nonlinearity cancellation, neutralization techniques using passive networks, and mixed-signal reconfigurable architectures have been utilized to improve certain performance metrics of PAs, but the core unit is still primarily based on common source / common emitter (CS / CE) topology. Although transistors in most commercial semiconductor processes have a minimum of three terminals (gate, source, and drain), conventional PA design techniques only utilize transistors as two-terminal devices.

[0004] New spectrum availability is driving many new 5G transmitter systems operating at high Gb / s data rates. The PA offers opportunities for high-performance, high-power, and high-power radio (NR) applications. However, stringent efficiency and linearity requirements pose significant challenges to designers. Traditional PA designs and the design techniques mentioned above have focused primarily on increasing peak / power back-off (PBO), power-added efficiency (PAE), and output power (Pout). However, in highly scaled silicon processes with low supply voltages, such techniques reduce the return on PAE and output power because the transistor knee voltage (Vknee) becomes a significant fraction of the supply voltage. Furthermore, in practical applications, the supply voltage is often reduced to ensure device reliability. This is particularly relevant for array operation, where array element coupling results in substantial antenna impedance mismatch and undesirably large PA voltage swings. Previous techniques have improved PA efficiency overall, but fundamentally they cannot exceed the theoretical PA core efficiency at the same conduction angle (e.g., class B common source (CS) PA) without resorting to device switching or harmonic shaping. Performance challenges still exist in terms of improving PA efficiency, output power, linearity, data rate, and reliability. Summary of the Invention

[0005] The disclosed technology relates to a new power amplifier (PA) topology that employs a novel dual drive PA configuration, in which transistors in the PA core are driven out of phase at their gate and source terminals using a dual drive combining network while providing the correct DC bias at the gate and source terminals.

[0006] According to an exemplary implementation of the disclosed technology, the PA core includes a differential pair of transistors M1 and M2 driven by a coupling network having two transmission line-based couplers, a first transmission line section of the pair configured to carry an input signal Vin to drive the gate of the opposite transistor, and a second transmission line section grounded at one end, with a coupled portion αVin of the input signal Vin coupled to the first transmission line section to drive the source terminal of the corresponding transistor. The coupling network arrangement allows the source terminal to be driven at a voltage lower than ground potential. In the embodiments disclosed herein, an input matching network, a driver, an interstage matching network, and an output network are further provided for practical implementation of the PA core.

[0007] According to an exemplary implementation of the disclosed technology, a dual drive power amplifier core is provided that includes a first transistor M1 having at least three terminals: an M1 gate / base terminal, an M1 drain / collector terminal, and an M1 source / emitter terminal. The dual drive power amplifier core also includes a second transistor M2 having at least three terminals: an M2 gate / base terminal, an M2 drain / collector terminal, and an M2 source / emitter terminal. The dual drive power amplifier core also includes a first transmission line coupler comprising a first transmission line section T1 having a first end and a second end, the first end being grounded and the second end being connected to the M1 source / emitter terminal, and a second transmission line section T2 having a first end and a second end, the first end being configured to receive the core first input signal Vin+ and a first bias voltage, the second end being connected to the M2 gate / base terminal and coupled to the M1 drain / collector terminal, the second transmission line section T2 being electromagnetically coupled to the first transmission line section T1. The dual drive power amplifier core also includes a second transmission line coupler comprising a third transmission line section T3 having a first end and a second end, the first end being grounded and the second end being connected to the M2 source / emitter terminal, and a fourth transmission line section T4 having a first end and a second end, the first end being configured to receive the core second input signal Vin− and a first bias voltage, the second end being connected to the M1 gate / base terminal and coupled to the M2 drain / collector terminal, the fourth transmission line section T4 being electromagnetically coupled to the third transmission line section T3. The dual drive power amplifier core also includes a core first output terminal Vout+ connected to the M1 drain / collector terminal and configured to receive a second bias voltage, and a core second output terminal Vout- connected to the M2 drain / collector terminal and configured to receive a second bias voltage, the core first and core second output terminals configured to output an amplified differential signal corresponding to the difference between the core first input signal Vin+ and the core second input signal Vin-.

[0008] According to another exemplary implementation of the disclosed technology, a pair of transmission line-based couplers is provided, the transmission line-based couplers being configured to receive a differential input voltage signal at two input terminals and passively couple a scaled differential input voltage signal at four output terminals. The pair of transmission line-based couplers includes a first transmission line coupler having a first end and a second end, the first end being connected to ground and the second end being connected to V S1 a first transmission line section T1 configured to output a signal, the first end being configured to receive a core first input signal Vin+ and a first bias voltage, and the second end being configured to receive a core first input signal Vin+ and a first bias voltage, G2 a first end of the first transmission line section T1 configured to output a signal, the first end of the first transmission line section T1 being electromagnetically coupled to the first transmission line section T1 and configured to output a signal Vin+ in response to receiving the input signal Vin+ at the first end of the first transmission line section T1. S1 and a second transmission line section T2 for generating a signal. The transmission line based coupler pair includes a second transmission line coupler having a first end and a second end, the first end being grounded and the second end being connected to V. S2 a third transmission line section T3 configured to output a signal; and a third transmission line section T4 having a first end and a second end, the first end configured to receive a core second input signal Vin− and a first bias voltage, and the second end configured to receive a core second input signal Vin− and a first bias voltage, G1 a third transmission line section T3 configured to output a Vin− signal at a first end and to be electromagnetically coupled to the third transmission line section T4 in response to receiving an input signal Vin− at the first end. G1 and a fourth transmission line section T4 for generating the signal.

[0009] These and other aspects of the present disclosure are described in the following "Detailed Description" and the accompanying drawings. Other aspects and features of the embodiments will become apparent to those skilled in the art upon reviewing the following description of certain exemplary embodiments in conjunction with the drawings. Although features of the present disclosure may be discussed in connection with certain embodiments and figures, all embodiments of the present disclosure may include one or more of the features discussed herein. Furthermore, although one or more embodiments may be described as having certain advantageous features, one or more of such features may also be used with various embodiments described herein. Similarly, although exemplary embodiments may be described below as device, system, or method embodiments, it should be understood that such exemplary embodiments may be implemented in various devices, systems, and methods of the present disclosure. [Brief description of the drawings]

[0010] The following detailed description of certain embodiments of the present disclosure will be better understood when read in conjunction with the accompanying drawings. For the purpose of illustrating the present disclosure, certain embodiments are shown in the drawings. It should be understood, however, that the present disclosure is not limited to the precise arrangements and instrumentalities of the embodiments shown in the drawings. [Figure 1A] FIG. 1A is an exemplary diagram of a MOSFET transistor having a gate terminal driven by a first drive signal Vin, a source terminal driven by a second drive signal αVin, and a resulting output signal Vout, in accordance with an exemplary embodiment of the disclosed technology. [Figure 1B] FIG. 1B is a graph of a first drive signal Vin, a second drive signal αVin, and the resulting output signal Vout (as shown in FIG. 1A) versus ground and a knee voltage Vknee in accordance with an exemplary embodiment of the disclosed technology. [Diagram 2] FIG. 2 is a schematic diagram of a dual drive power amplifier (PA) core in accordance with an exemplary embodiment of the disclosed technology. [Figure 3A]FIG. 3A is a diagram of a coupled transmission line pair that allows passive generation of signals αVin+ from Vin+ and αVin− from Vin−, in accordance with an exemplary embodiment of the disclosed technology. [Figure 3B] FIG. 3B is a three-dimensional view of an example physical layout of a coupled transmission line pair as illustrated in FIG. 3A, in accordance with an example embodiment of the disclosed technology. [Figure 4A] FIG. 4A is an example block diagram of a power amplifier utilizing dual drive cores, in accordance with an example embodiment of the disclosed technology. [Figure 4B] FIG. 4B is a detailed schematic diagram of a power amplifier utilizing dual drive cores (corresponding to the block diagram of FIG. 4A) in accordance with an exemplary embodiment of the disclosed technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (Detailed Description) The disclosed technology includes a new power amplifier (PA) architecture that may overcome some of the above-mentioned challenges associated with conventional approaches. The disclosed PA topology employs a new dual drive configuration in which the PA core transistors are driven out of phase at the gate and source terminals. The term "transistor" as used herein may refer to any three-terminal signal amplifying device, including but not limited to MOSFET, CMOS, NMOS, PMOS, BJT, NPN, PNP, etc. (e.g., with corresponding terminals such as the base, collector, and emitter of a BJT).

[0012] The disclosed PA topology allows the source and drain of the transistor to swing in phase, thus artificially reducing the knee voltage of the transistor, thereby increasing the output voltage swing. This dual drive PA topology significantly increases the output power, linearity, and efficiency of the PA while allowing for a reduction in the supply voltage. Furthermore, the disclosed dual drive topology can be configured as a common gate and common source combination, which can significantly reduce the input impedance of the PA stage, allowing for a wideband and low loss interstage matching network. The PA topology disclosed herein can provide superior performance for high reliability commercial applications while allowing for the use of lower supply voltages.

[0013] In order to facilitate an understanding of the principles and features of the present disclosure, various exemplary embodiments are described below. The components, steps, and materials described below as constituting various elements of the embodiments disclosed herein are intended to be illustrative and not limiting. Many suitable components, steps, and materials that perform the same or similar functions as the components, steps, and materials described herein are intended to be encompassed within the scope of the present disclosure. Such other components, steps, and materials not described herein may include, but are not limited to, similar components or steps developed after the development of the embodiments disclosed herein.

[0014] 1A is an exemplary diagram of a dual drive MOSFET transistor having a gate terminal driven by a first drive signal Vin, a source terminal driven by a second drive signal αVin, and a resulting output signal Vout, in accordance with an exemplary embodiment of the disclosed technology. In this implementation, α can be negative to provide a source drive signal that is out of phase with the gate drive signal Vin.

[0015] FIG. 1B is a graph of a first drive signal Vin, a second drive signal αVin, and the resulting output signal Vout (as shown in FIG. 1A) versus ground and knee voltage in accordance with an exemplary embodiment of the disclosed technology.

[0016] The power efficiency of the dual drive transistors can be expressed as:

number

number

[0017] The bias current is expressed as follows:

number

[0018] The power efficiency of the dual-feed transistors for a typical class B amplifier can be expressed as:

number

number

[0019] As described herein, the transistors may be biased as Class B. However, according to some example implementations of the disclosed technology, the bias voltage at the gate of the transistor may be adjusted to put the device into either Class A, Class B, or Class C amplification, as needed for a particular application.

[0020] When a transistor is driven only at the gate, the maximum efficiency of the device is determined by the device conduction angle and the technology-specific V knee This is determined by, especially at lower V DD For values ​​of 0.1 V, the peak output voltage swing is reduced and the drain efficiency is limited. The disclosed technology utilizes a transistor that is a three or more terminal device, and further provides a coupling network for driving both the gate and source terminals with out-of-phase inputs Vin and αVin, respectively. The source voltage can swing below ground while having an in-phase relationship with the drain voltage, increasing the maximum drain output voltage swing by αVin without the need to increase the supply voltage.

[0021] Advantages of the dual-drive PA topology disclosed herein may include: (1) increased PA core-drain efficiency over that of a typical common-source topology at the same conduction angle due to increased source coupling coefficient; DD V below knee The effect of reducing V DD (3) The power saturation Psat can be increased while reducing device AM-PM and AM-AM distortion because the active device spends more time in its saturation region and less time in the triode. (4) The parallel input resistance of the transistor is reduced by coupling the device gate impedance in parallel with a low source impedance, which can also be designed by source coupling αVin to facilitate the design of wideband and low loss interstage matching networks. (5) Reliability issues of voltage peaking in complex harmonic shaping PAs can be mitigated (Class J or Continuous mode Class F PAs).

[0022] The dual drive PA topology disclosed herein is particularly suitable for high reliability commercial / defense applications requiring lower supply voltages. Certain exemplary implementations of the disclosed technology may also be suitable for power amplifiers with high supply voltages, such as satellite communication applications where the supply voltage may be 20 volts or more. It should also be emphasized that the dual drive PA topology disclosed herein is different from conventional stacked PAs. In such conventional stacked PA devices, the source terminals of the MOSFET transistors of the bottom layer in the stacked device are tied to ground, thus determining the swing of the total output voltage of the device. In contrast, the source terminals of the disclosed technology are connected to a coupled transmission line that allows the source voltage to be stepped down below ground, as described below.

[0023] 2 is a schematic diagram of a dual drive power amplifier (PA) core according to an exemplary embodiment of the disclosed technology, which may utilize a transistor differential pair including a first transistor M1 202 and a second transistor M2 204 along with a dual drive combining network 206. The dual drive combining network 206 may include transmission line segments T1 208, T2 210, T3 212, and T4 214, with T1 208 and T2 210 being electromagnetically coupled and T4 214 and T1 208 being electromagnetically coupled. The dual drive combining network 206 allows a first portion Vin− of a balanced input signal to be applied through T4 214 to drive the gate of M1 202, while a version of Vin− is coupled through T3 212 to drive the source terminal of M2 204. At the same time, a second portion Vin+ of the balanced input signal Vin+ may be applied through T2 210 to drive the gate of M2 204, while a version of Vin+ is coupled through T1 208 to drive the source terminal of M1 202. The implementations disclosed herein further allow for providing the correct DC bias point, such as a non-zero DC voltage for the gate and a DC ground for the source. Using this new PA topology, the sources of transistors 202 and 204 may swing in phase with the drain, thus allowing for an extended voltage knee / output swing that can linearly increase the output power and power-added efficiency while using a low supply voltage.

[0024] 3A is a diagram of a coupling network 300 including a pair of transmission line based couplers T1 208 and T2 210, T3 212 and T4 214 as shown in FIG. 2, where T1 208 is coupled to T2 210 (S 302) and T3 212 is coupled to T4 214 (S 304). While each of T1 208, T2 210, T3 212 and T4 214 can be considered an independent transmission line (alone), the proximity of T1 208 to T2 210 allows T1 208 and T2 210 to be electromagnetically coupled to form a first transmission line based coupler. Similarly, T3 212 and T4 214 can form a second transmission line based coupler. The couplings 302 and 304 can passively generate signals αVin+ and αVin− from Vin+ and Vin−, respectively. In some example implementations, the coupling network 300 can introduce degradation in inductive reactance sources that can degrade the overall device power gain. In some implementations, the inductive reactance reduces the even-mode impedance Z while maintaining a desired coupling coefficient α. 0e and odd-mode impedance Z 0o According to a particular implementation of the disclosed technology, the coupling coefficient α may be set by the transmission line geometry.

[0025] In one exemplary implementation of the disclosed technology, the coupling coefficient α may be set within a range of about 0.1 to about 0.9. In another exemplary implementation, the coupling coefficient α may be set within a range of about 0.2 to about 0.8. In another exemplary implementation, the coupling coefficient α may be set within a range of about 0.3 to about 0.7. In another exemplary implementation, the coupling coefficient α may be set within a range of about 0.4 to about 0.6. In another exemplary implementation, the coupling coefficient α may be set within a range of about 0.3 to about 0.4.

[0026] 3B is a three-dimensional view of an example physical layout of a coupling network 300 having coupled transmission line pairs T1 208 and T2 210, T3 212 and T4 214, corresponding to elements as shown in FIG. 3A and FIG. 2. This unique layout configuration allows a signal Vin+ (Vin−) to be input at one end of transmission line T2 210 (T4 214) and electromagnetically coupled to T1 208 (T3 212) over a length L. In accordance with some example implementations of the disclosed technology, the resulting signal V S1 , V G1 , V G2 , V S2 to the rest of the circuitry.

[0027] In some example implementations, the transmission lines 208, 210, 212, 214 of the coupling network 300 may be designed and manufactured using a number of different variables to control impedance, coupling coefficient, etc. Such variables may include the transmission line length L, width W1, thicknesses t2 and t1, gap tg, and / or ground plane opening width w2. In one example implementation of the disclosed technology, the length L may be about 50 microns, the width W1 may be about 10 microns, the thicknesses t1 and t2 may be about 3 microns, the gap tg may be about 1.6 microns, and the ground plane opening width W2 may be about 14 microns. As shown, one end of the bottom traces T1 208 and T3 212 may be connected to the ground plane 314. In these geometries, the even mode impedance Z 0e and odd-mode impedance Z 0o may be set to about 15 ohms and about 40 ohms, respectively, at 30 GHz. In some example implementations, the conduction angle may be adjusted to about 8.5 degrees, and the k factor may be about 0.47 at 30 GHz.

[0028] 4A is an example block diagram of a power amplifier 400 that can utilize a dual drive PA core 200 (as described above) in accordance with an example embodiment of the disclosed technology. Various configurations can be configured to utilize the dual drive core 200 without departing from the scope of the disclosed technology. FIG. 4A shows one example of how other stages (such as an input matching network 402, a driver 404, an inter-stage matching network 406, and / or an output network 408) can be utilized with the dual drive PA core 200. Specific example components of each stage in the example power amplifier 400 will now be described with reference to FIG. 4B.

[0029] Figure 4B is a detailed schematic diagram of an example power amplifier circuit 401 utilizing dual drive PA core 200, in accordance with an exemplary embodiment of the disclosed technology. Although other stages, components, and arrangements may be utilized without departing from the scope of the disclosed technology, the arrangement shown in Figure 4B illustrates the practical use of dual drive PA core 200 having stages 402, 404, 406, 408, which may correspond to similar stages shown in Figure 4A.

[0030] 2, 3A, and 3B, the dual drive power amplifier core 200 may include a first transistor M1 202 having at least three terminals: an M1 gate terminal, an M1 drain terminal, and an M1 source terminal. The dual drive power amplifier core 200 may include a second transistor M2 204 having at least three terminals: an M2 gate terminal, an M2 drain terminal, and an M2 source terminal.

[0031] The dual drive power amplifier core 200 may include a first transmission line coupler comprising a first transmission line section T1 208 having a first end and a second end, where the first end is grounded and the second end is connected to the M1 source terminal.

[0032] The dual drive power amplifier core 200 may include a first transmission line coupler comprising a second transmission line section T2 210 having a first end and a second end, where the first end may be configured to receive one or more of a core first input signal and / or a first bias voltage. The second end of the second transmission line section T2 210 may be connected to the M2 gate terminal and may be capacitively coupled to the M1 drain terminal. As described above, the first transmission line section T1 208 may be electromagnetically coupled to the second transmission line section T2 210.

[0033] The dual drive power amplifier core 200 may include a second transmission line coupler comprising a third transmission line section T3 212 having a first end and a second end, where the first end may be grounded and the second end may be connected to the M2 source terminal.

[0034] The dual drive power amplifier core 200 may include a fourth transmission line section T4 214 having a first end and a second end, where the first end may be configured to receive one or more of a core second input signal and / or a first bias voltage. The second end of the fourth transmission line section T4 214 may be connected to the M1 gate terminal and, in some implementations, may be capacitively coupled to the M2 drain terminal. As described above, the third transmission line section T3 212 may be electromagnetically coupled to the fourth transmission line section T4 214.

[0035] In some example implementations, as shown in FIG. 4B, the drain terminals of M1 202 and M2 204 may be configured as outputs and connected to VDD PA In some example implementations, the drain terminals of M1 202 and M2 204 may be considered as core 1 and core 2 output terminals, respectively, and may be configured to output an amplified differential signal corresponding to the difference between the core 1 and core 2 input signals at the gates of M1 202 and M2 204, respectively.

[0036] In some example implementations, the circuit 401 includes a cascode bias control terminal V 2 , which is configured to control the voltage applied to the M1 202 drain terminal and the M2 204 drain terminal. CAS In some exemplary implementations, the cascode current buffer may include a cascode current buffer having a voltage VOUT and a cascode bias control terminal VOUT. In some exemplary implementations, the cascode current buffer may increase the supply voltage and the output power. In some exemplary implementations, the cascode current buffer may be biased for 1.3V operation. The cascode current buffer may include a third transistor M3 414 having at least three terminals, an M3 gate terminal, an M3 drain terminal, and an M3 source terminal. The cascode current buffer may include a fourth transistor M4 416 having at least three terminals, an M4 gate terminal, an M4 drain terminal, and an M4 source terminal. In some exemplary implementations, the M3 source terminal may be connected to the core first output terminal, and the M4 source terminal may be connected to the core second output terminal. In some exemplary implementations, the M3 gate terminal may be connected to the M4 gate terminal and the cascode bias control terminal VOUT. CAS can be connected to

[0037] In some exemplary implementations, the circuit 401 may include an output network 408 having an output transformer 414 with a first terminal and a second terminal. In some exemplary implementations, the output transformer 414 may include a primary center-tap terminal. In some exemplary implementations, the first terminal may be connected to the M3 drain terminal and the second terminal may be connected to the M4 drain terminal. In some exemplary implementations, the primary center-tap terminal may be connected to a supply voltage VDD PA In some example implementations, the cascode bias control terminal V CAS may be configured to control a second bias voltage applied to the M1 drain terminal and the M2 drain terminal. In some example implementations, the second bias voltage is a supply voltage VDD PA can be derived from

[0038] 4B, the circuit 401 may include a transformer 420 having a first stage 1 terminal, a first stage 2 terminal, and a primary center-tap terminal, and an inter-stage matching network 406 that may include a secondary first terminal, a secondary second terminal, and a secondary center-tap terminal. In some example implementations, the secondary first terminal may be connected to a first end of the second transmission line section T2 210, and the secondary second terminal may be connected to a first end of the fourth transmission line section T4 214. In some example implementations, the secondary center-tap terminal may be connected to a first end of the fourth transmission line section T4 214. PA It may be configured to receive a bias voltage.

[0039] In communication with the inter-stage matching network 406 may be a common source driver 404 that may include a fifth transistor M5 422 having at least three terminals: an M5 gate terminal, an M5 drain terminal, and an M5 source terminal.

[0040] In some exemplary implementations, the common source driver 404 may include a sixth transistor M6 424 having at least three terminals: an M6 gate terminal, an M6 drain terminal, and an M6 source terminal. In some exemplary implementations, the common source driver 404 may include a gate resistor 414 having a first end and a second end. In some exemplary implementations, the M5 source terminal and the M6 ​​source terminal may be grounded, and the M5 drain terminal may be connected to a first terminal of the inter-stage matching network 406 and may be capacitively coupled to the M6 ​​gate terminal. In some exemplary implementations, the M6 ​​drain terminal may be connected to a second terminal of the inter-stage matching network 406 and may be capacitively coupled to the M5 gate terminal. In some exemplary implementations, the M5 gate terminal may be connected to a first end of the gate resistor 414, and the M6 ​​gate terminal may be connected to a second end of the gate resistor 414. In some example implementations, the gate resistor 414 may be selected to optimize the input impedance of the driver stage 404, for example, to minimize the S11 (input reflection) parameter.

[0041] A particular exemplary implementation of the disclosed technology is a VDD DR A terminal may be included and may be configured to receive a supply voltage to the common source driver 404 circuitry.

[0042] In some exemplary implementations, the input side of the power amplifier circuit 401 (shown on the left side of FIG. 4B ) can include an input matching network 402 that can include an input transformer 414 having a primary 1 terminal, a primary 2 terminal, a secondary 1 terminal, and a secondary 2 terminal. In one exemplary implementation of the disclosed technology, one or more of the RF input terminals can be capacitively coupled to a primary terminal of the input transformer 414. In some exemplary implementations, the transformer 414 can be coupled to a VGS 422 for biasing the gate-sources of M5 422 and M6 242 in the driver section 404. DR The transformer 414 may include a secondary center tap terminal that may be connected to a bias input terminal. In some example implementations, the secondary first terminal of the transformer 414 may be connected to a first end of the gate resistor 414 and the secondary second terminal may be connected to a second end of the gate resistor 414. In one example implementation, the gate resistor 414 may be approximately 550 ohms. Other resistance values ​​of the gate resistor 414 may be utilized as desired.

[0043] In some exemplary implementations, the input matching network 402 may be configured as a single-ended RF input (referenced to ground) as shown. Alternatively, the input ground connection may be open and a secondary first input of the input transformer 414 may be connected to another RF input connection 410 to accept a balanced input (or an input signal not referenced to ground). Similarly, on the output side (right-most side), the output network 408 may be configured as a single-ended RF output referenced to ground (as shown), or the output ground connection may be open and the corresponding output transformer terminal may be connected to a second RF output connection 412 to provide an output that is, for example, balanced, floating, and / or otherwise not referenced to ground.

[0044] Compared to conventional capacitive coupling networks, the coupled transmission lines (T1 208 coupled to T2 210, and T3 212 coupled to T4 214) can be configured to account for all routing parasitics and can be optimized for desired amplitude / phase coupling with flexibility. Furthermore, this input coupling network 206 naturally provides proper DC bias to each transistor M1 202 and M2 204 device terminal (assuming the interstage matching transformer 420 provides DC gate bias via a center tap) without requiring additional passive elements.

[0045] According to some exemplary implementations of the disclosed technology, neutralization capacitors may be used in one or more of the driver 404 and / or dual drive PA core 200 stages to increase stability and gain. In some exemplary implementations, the input matching network 402 may include additional capacitors and gate resistor termination for wideband S11 matching. According to some exemplary implementations of the disclosed technology, the inter-stage matching network 406 may use one transformer 420 without gate reverse Qing resistors due to the lower real impedance at the dual drive PA core input (748Ω for CS and 36Ω for dual drive PA).

[0046] Based on large signal CW simulations, the drain efficiency, OP1dB, and Psat of the dual-driven PA core may increase as the coupling coefficient α increases. Conversely, as α increases, the power gain may decrease due to the reduction in the PA core input impedance and source inductive degeneration. Therefore, there may be an optimal dual-driven operating region where the gain is sufficient to maintain the overall PA PAE. According to some example implementations of the disclosed technology, α may be selected to be 0.35.

[0047] Using a 45nm SOI CMOS process, the device is 1.3 x 1.2 mm 2A prototype of the disclosed dual-drive PA has been fabricated with a total area of ​​1.5 GHz. A maximum OP1dB of 19.1 dBm is achieved at 31 GHz, with less than 1 dB variation from 23 GHz to 34 GHz.

[0048] The dual drive PA prototype disclosed herein can achieve a maximum PAE (PAEmax) of 50% and a maximum DE (DEmax) of 59.7% at 29 GHz, which are the highest PAE and DE reported for a two-stage PA in silicon. From 24 GHz to 35 GHz, the PA also maintains a PAEmax ≧ 40%. OP1dB and Psat are within 1 dB across the entire bandwidth, and the maximum PAE at OP1dB (PAEOP1db) is 47.4%.

[0049] Single carrier signal and 5G NR FR2 modulation testing without DPD from 24 GHz to 36 GHz for 1.7 / 1.9V VDD shows that the disclosed technique provided the highest measured performance for average Pout / PAE (Pavg / PAEavg), which is 15.05 dBm / 30.13% for a 1.5G Sym / s 64-QAM signal with -25 dB rms EVM at 30 GHz for a 1.9V supply voltage. The best measured performance for Pavg / PAEavg is 11.39 dBm / 16.98% for a 5G NR FR2 200 MHz 1-CC 64-QAM signal with -25 dB rms EVM at 30 GHz for a 1.9V supply voltage.

[0050] Tables 1A, 1B, and 1C in the Appendix summarize the performance results of the dual drive PA technology disclosed herein versus previous studies. Certain exemplary implementations of the disclosed technology support efficient and linear wideband modulation, which outperforms conventional PAs and highlights the suitability of the disclosed dual drive PA for high reliability applications.

[0051] It is to be understood that the embodiments and claims disclosed herein, in their application, are not limited to the details of construction and arrangement of the components described in the description and shown in the drawings. Rather, the description and drawings provide examples of possible embodiments. The embodiments and claims disclosed herein are further capable of other embodiments and can be practiced and carried out in various ways. It is also to be understood that the phraseology and terminology used herein are for the purpose of description and should not be considered as limiting the scope of the claims.

[0052] As such, those skilled in the art will appreciate that the conception on which the present application and claims are based may be readily utilized as a basis for the designing of other structures, methods and systems for carrying out some of the purposes of the embodiments and claims presented herein, and it is important that the claims be regarded as including such equivalent constructions.

[0053] (appendix) [Table 1A] [1] T. Li et al., “A Continuous-Mode Harmonically Tuned 19-to-29.5GHz Ultra-Linear PA Supporting 18Gb / s at 18.4% Modulation PAE and 43.5% Peak PAE,” ISSCC, pp. 410-412, February 2018. [2] K. Ning and J.F. Buckwalter, “A 28-GHz, 18-dBm, 48% PAE Stacked-FET Power Amplifier with Coupled-Inductor Neutralization in 45-nm SOI CMOS,” 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018, pp. 85–88, DOI Code: 10.1109 / BCICTS.2018.8550832 [Table 1B] [3] F. Wang et al., “A Highly Linear Super-Resolution Mixed-Signal Doherty Power Amplifier for High-Efficiency mm-Wave 5G Multi-Gb / s Communications,” ISSCC, pp. 88-99, February 2019. [4] S. Ali et al., “A 28GHz 41%-PAE Linear CMOS Power Amplifier Using a Transformer-Based AM-PM Distortion-Correction Technique for 5G Phased Arrays,” ISSCC, pp. 406-408, February 2018. [5] M. Vigilante and P. Reynaert, “A Wideband Class-AB Power Amplifier With 29-57-GHz AM-PM Compensation in 0.9-V 28-nm Bulk CMOS,” IEEE JSSC, vol. 53, no. 5, pp. 1288-1301, May 2018. [Table 1C] [6] S. Shakib, M. Elkhholy, J. Dunmorth, V. Aparin, and K. Entesari, “2.7 a wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS,” 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 44–45, DOI: 10.1109 / ISSCC.2017, 7870252. [7] F. Wang and H. Wang, “An Instantaneously Broadband Ultra-Compact Highly Linear PA with Compensated Distributed-Balun Output Network Achieving >17.8dBm P1dB and >36.6% PAEP1dB over 24 to 40GHz and Continuously Supporting 64- / 256-QAM 5G NR Signals over 24 to 42GHz,” ISSCC, pp. 372-374, February 2020.

Claims

1. A dual drive power amplifier core, A first transistor M1, M1 gate terminal, M1 drain terminal, and a first transistor M1 having an M1 source terminal; a core first output terminal Vout+ configured to be connected to the M1 drain terminal; A second transistor M2, M2 gate terminal, M2 drain terminal, and a second transistor M2 having an M2 source terminal; A core second output terminal Vout− configured to be connected to the M2 drain terminal; 1. A transmission line coupler comprising: a first transmission line coupler, a first transmission line section T1 having a first end connected to ground and a second end connected to the M1 source terminal; a second transmission line section T2 having a first end configured to receive a core first input signal Vin+ and a second end connected to the M2 gate terminal and coupled to the M1 drain terminal; a second transmission line coupler, a third transmission line section T3 having a first end connected to ground and a second end connected to the M2 source terminal; a fourth transmission line section T4 having a first end configured to receive a core second input signal Vin− and a second end connected to the M1 gate terminal and coupled to the M2 drain terminal; Equipped with the core first output terminal Vout+ and the core second output terminal Vout− are configured to output an amplified differential signal corresponding to a difference between the core first input signal Vin+ and the core second input signal Vin−; the first transmission line section T1 is electromagnetically coupled to the second transmission line section T2; The third transmission line section T3 is electromagnetically coupled to the fourth transmission line section T4.

2. 1. A cascode current buffer, comprising: a cascode bias control terminal configured to control a bias voltage applied to the M1 drain terminal and the M2 drain terminal; A third transistor M3, M3 gate terminal, M3 drain terminal, and a third transistor M3 having a source terminal; A fourth transistor M4, M4 gate terminal, M4 drain terminal, and a fourth transistor M4 having a source terminal; a cascode current buffer comprising: The M3 source terminal is connected to the core first output terminal Vout+; The M4 source terminal is connected to the core second output terminal Vout-; 2. The dual drive power amplifier core of claim 1, wherein the M3 gate terminal is connected to the M4 gate terminal and the cascode bias control terminal.

3. an output transformer having a first terminal, a second terminal, and a primary center tap terminal; The first terminal is connected to the M3 drain terminal, The first terminal 2 is connected to the M4 drain terminal, The primary center tap terminal is connected to a supply voltage V ＤＤ The device is configured to receive the cascode bias control terminal is configured to control the second bias voltage applied to the M1 drain terminal and the M2 drain terminal; The second bias voltage is the supply voltage V ＤＤ 2. The dual drive power amplifier core of claim 1 , wherein:

4. an interstage matching network including an output transformer having a primary first terminal, a primary second terminal, and a primary center-tap terminal, a secondary first terminal, a secondary second terminal, and a secondary center-tap terminal; the secondary first terminal is connected to the first end of the second transmission line section T2; the secondary second terminal is connected to the first end of the fourth transmission line section T4; The dual drive power amplifier core of claim 1 , wherein the secondary center-tap terminal is configured to receive a first bias voltage.

5. A common source driver, A fifth transistor M5, M5 gate terminal, M5 drain terminal, and a fifth transistor M5 having a source terminal; A sixth transistor M6, M6 gate terminal, M6 drain terminal, and a sixth transistor M6 having a source terminal; a gate resistor having a first end and a second end; The M5 source terminal and the M6 ​​source terminal are connected to ground, the M5 drain terminal is connected to the first terminal of the interstage matching network and is coupled to the M6 ​​gate terminal; The M6 ​​drain terminal is connected to the first terminal of the inter-stage matching network and is capacitively coupled to the M5 gate terminal; the M5 gate terminal is connected to the first end of the gate resistor; The dual drive power amplifier core of claim 4 , wherein the M6 ​​gate terminal is connected to the second end of the gate resistor.

6. a V ＤＤ The dual drive power amplifier core of claim 5 further comprising a terminal.

7. 6. The dual drive power amplifier core of claim 5, further comprising an input balun network comprising a first terminal, a first terminal, a secondary terminal, a secondary first terminal, a secondary second terminal, and a secondary center tap terminal connected to a third bias input terminal, the secondary first terminal being connected to the first end of the gate resistor, the secondary second terminal being connected to the second end of the gate resistor, and the first terminal being capacitively coupled to a first RF input terminal configured to receive a first RF input signal.

8. 8. The dual drive power amplifier core of claim 7, wherein the first RF input terminal of the input balun network is connected to ground and coupled to the first RF input terminal, and the first RF input terminal is configured to receive an unbalanced RF input signal.

9. 8. The dual drive power amplifier core of claim 7, wherein the first RF input terminal and the second RF input terminal of the input balun network are capacitively coupled to a second RF input terminal and to the first RF input terminal, the first RF input terminal and the second RF input terminal being configured to receive a balanced RF signal.

10. 2. The dual drive power amplifier core of claim 1, wherein the second end of the second transmission line section T2 is capacitively coupled to the M1 drain terminal and the second end of the fourth transmission line section T4 is capacitively coupled to the M2 drain terminal.

11. The dual drive power amplifier core of claim 1 , further comprising a signal crossover region configured to cross-route the second transmission line section T2 and the fourth transmission line section T4.

12. 2. The dual drive power amplifier core of claim 1, wherein the second transmission line section T2 is stacked on the first transmission line section T1 and the fourth transmission line section T4 is stacked on the third transmission line section T3.

13. 2. The dual drive power amplifier core of claim 1, wherein the first transistor M1 and the second transistor M2 are fabricated using one or more of bulk CMOS, CMOS SOI, GaAs, and GaN processes.

14. The method of claim 13, wherein the first end of the second transmission line section T2 is further configured to receive a first bias voltage; the first end of the fourth transmission line section T4 is further configured to receive the first bias voltage; a core first output terminal Vout+ connected to the M1 drain terminal is further configured to receive a second bias voltage; 2. The dual drive power amplifier core of claim 1, wherein a core second output terminal Vout- connected to said M2 drain terminal is further configured to receive said second bias voltage.

15. A dual drive power amplifier core as described in claim 1, wherein the first transistor and the second transistor form a transistor differential pair, and the transistor differential pair is configured to be driven out of phase at the gate and source terminals.

16. The first transmission line coupler and the second transmission line coupler form a coupling network, The coupling network is driving the cores out of phase at the gate and source terminals of the differential pair of transistors; allowing the source and drain terminals of said differential pair of transistors to swing in phase; providing a non-zero DC voltage to each of said gate terminals and a DC ground to each of said source terminals; 16. A dual drive power amplifier core as claimed in claim 15, configured to do one or more of the following:

17. A core first output terminal Vout+ configured to be connected to a drain terminal of a first transistor; a core second output terminal Vout− configured to be connected to the drain terminal of the second transistor; transmission line couplers, a first transmission line coupler including a transmission line section having a first end configured to receive a core first input signal Vin+, and a second transmission line coupler including a transmission line section having a first end configured to receive a core second input signal Vin−; a first output terminal Vout+ and a second output terminal Vout- configured to output an amplified differential signal corresponding to a difference between the first input signal Vin+ and the second input signal Vin-;

18. 1. A pair of transmission line-based couplers configured to receive a differential input voltage signal at two input terminals and passively combine a scaled version of the differential input voltage signal at four output terminals, a first transmission line coupler, A first transmission line section T1 having a first end and a second end, the first end being grounded and the second end being connected to V Ｓ１ a first transmission line section T1 configured to output a signal; a second transmission line section T2 having a first end and a second end, the first end configured to receive a core first input signal Vin+ and the second end configured to receive a core first input signal Vin+; Ｇ２ a first end of the second transmission line section T2 configured to output a first input signal Vin+ in response to receiving the input signal Vin+ at the first end of the second transmission line section T2. Ｓ１ a second transmission line section T2 to which the first transmission line section T1 is electromagnetically coupled to generate a signal; a second transmission line coupler, a third transmission line section T3 having a first end and a second end, the first end being grounded and the second end being connected to V Ｓ２ a third transmission line section T3 configured to output a signal; and a fourth transmission line section T4 having a first end and a second end, the first end configured to receive a core second input signal Vin− and the second end configured to receive a core second input signal Vin−; Ｇ１ a first end of the fourth transmission line section T4 configured to output a first input signal Vin− in response to receiving the input signal Vin− at the first end of the fourth transmission line section T4, Ｇ１ a second transmission line coupler comprising a fourth transmission line section T4 electromagnetically coupled to the third transmission line section T3 to generate a signal.

19. The V Ｇ１ signal and the V Ｇ２ Cross-routing the signal to Ｇ１ signal and the V Ｇ２ The signals are respectively Ｓ１ signal and the V Ｓ２ 20. The transmission line-based coupler pair of claim 18, further comprising a signal crossover region configured for pairing with the signal.

20. 20. The transmission line-based coupler pair of claim 18, wherein the second transmission line section T2 is stacked on the first transmission line section T1 and the fourth transmission line section T4 is stacked on the third transmission line section T3.

21. The second transmission line section T2 comprises: ０～１、 ０．２～０．６、 0.3 to 0.4, or 20. The pair of transmission line-based couplers of claim 18 configured to couple the Vin+ signal to the first transmission line section T1 with a coupling coefficient having a range of one or more of 0.5 to 0.

8.

22. The fourth transmission line section T4 comprises: ０～１、 ０．２～０．６、 0.3 to 0.4, or 20. The pair of transmission line-based couplers of claim 18 configured to couple the Vin- signal to the third transmission line section T3 with a coupling coefficient having a range of one or more of 0.5 to 0.

8.

23. 20. The transmission line-based coupler pair of claim 18, wherein the second transmission line section T2 is configured to couple the Vin+ signal to the first transmission line section T1 with a coupling coefficient based on physical parameters including a length of the transmission line, a width of the transmission line, and a gap between the transmission lines.

24. 20. The pair of transmission line-based couplers of claim 18, wherein the fourth transmission line section T4 is configured to couple the Vin- signal to the third transmission line section T3 with a coupling coefficient based on physical parameters including a length of the transmission line, a width of the transmission line, and a gap between the transmission lines.

25. The method of claim 2, wherein the first end of the second transmission line section T2 is further configured to receive a first bias voltage; 20. The transmission line-based coupler pair of claim 18, wherein the first end of the fourth transmission line section T4 is further configured to receive the first bias voltage.

26. A power amplifier core comprising: a differential pair of transistors, each transistor having a gate terminal, a drain terminal, and a source terminal; a multifeed combining network; The multifeed combining network comprises: The differential pair of transistors are driven out of phase at the gate terminals and the source terminals, thereby driving the core out of phase at the gate terminals and the source terminals; A power amplifier core configured to allow the source and drain terminals to swing in phase.

27. A power amplifier core comprising: a differential pair of transistors including a first transistor and a second transistor, each transistor having a gate terminal, a drain terminal, and a source terminal; a multifeed combining network; The multifeed combining network comprises: The differential pair of transistors are driven out of phase at the gate terminals and the source terminals, thereby driving the core out of phase at the gate terminals and the source terminals; configured to allow the source and drain terminals to swing in phase; Furthermore, the multifeed combining network comprises: coupling an input signal from the gate terminal of the first transistor to the source terminal of the second transistor; coupling a gate terminal of the second transistor to a source terminal of the first transistor; and a power amplifier core configured to provide a non-zero DC voltage to each gate terminal and a DC ground to each source terminal.

28. A power amplifier comprising: a transistor having a gate terminal, a drain terminal, and a source terminal; a coupling network; The coupling network comprises: driving the gate terminal with a first signal; driving the source terminal with a second signal out of phase with the first signal; The power amplifier is configured to allow the source and drain terminals to swing in phase.

29. The power amplifier of claim 28, wherein the coupling network is further configured to provide a non-zero DC voltage to the gate terminal.

30. The power amplifier of claim 28, wherein the coupling network is further configured to provide a DC ground to the source terminal.

31. The coupling network comprises: a first section configured to drive the gate terminal with the first signal; a second section configured to drive the source terminal with the second signal; 30. The power amplifier of claim 28, comprising:

32. The power amplifier of claim 28, wherein the combining network is further configured to adjust the amplitude of the second signal.

33. The power amplifier of claim 28, wherein the combining network is further configured to adjust the bias of one or more of the first signal and the second signal.

34. The power amplifier of claim 28, wherein the transistor is fabricated using one or more of the following processes: bulk CMOS, CMOS SOI, GaAs, GaN.

35. The power amplifier of claim 28, wherein the transistor is characterized as one of an NMOS device, a PMOS device, an NPN device, or a PNP device.

36. The power amplifier of claim 29, wherein the non-zero DC voltage is configured to bias the first signal to swing above a ground reference.

37. The power amplifier of claim 30, wherein the coupling network is further configured to enable the second signal to swing below DC ground.

38. A power amplifier as described in claim 31, wherein the first section is electromagnetically coupled to the second section.

39. A method for improving the power efficiency of a power amplifier without increasing the supply voltage, comprising the steps of: coupling a first signal to a gate terminal of a transistor; coupling a second signal, out of phase with the first signal, to a source terminal of the transistor; and allowing a drain terminal of the transistor to swing in phase with the source terminal.

40. The method of claim 39, wherein coupling the first signal to the gate terminal includes providing a non-zero DC voltage to the gate terminal.

41. The method of claim 39, further comprising the step of outputting a signal from the drain terminal.

42. The method of claim 39, wherein the step of coupling the second signal to the source terminal includes swinging the second signal below a ground reference.

43. The method of claim 39, wherein the step of coupling the second signal to the source terminal includes adjusting an amplitude of the second signal.

44. The method of claim 39, wherein the step of coupling the second signal to the source terminal is configured to increase the time the transistor is in saturation.

45. The method of claim 39, wherein one or more of the steps of coupling the first signal to a gate terminal and coupling the second signal to a source terminal includes coupling with one or more of a transmission line, a transformer, and a balun.

46. ​​The method of claim 39, further comprising the step of outputting a signal from the drain terminal.

47. The method of claim 40, wherein the non-zero DC voltage is configured to bias the first signal to swing above a ground reference.

48. The method of claim 41, wherein the drain terminal is coupled to an antenna.

49. A power amplifier comprising: a passive transmission line based coupling network configured to receive an input voltage signal on an input terminal and passively couple a scaled version of the input voltage signal to an output terminal; a transistor having a gate terminal, a drain terminal, and a source terminal; the coupling network includes a first transmission line coupler; The first transmission line coupler comprises: a first transmission line section T1 having a first end and a second end, the first end being connected to ground and the second end being configured to output a V S1 signal; a second transmission line section T2 having a first end and a second end, the first end configured to receive a first input signal Vin+ and the second end configured to output a V G2 signal, the second transmission line section T2 electromagnetically coupled to the first transmission line section T1 to generate the V S1 signal in response to receiving the input signal Vin+ at the first end; The power amplifier, wherein the coupling network is further configured to drive the source terminal with the V S1 signal to enable the source and drain terminals to swing in phase.

50. The coupling network further comprising a second transmission line coupler; 50. The power amplifier of claim 49, wherein the second transmission line coupler comprises a transmission line section T4 having a first end and a second end, the first end configured to receive a second input signal Vin-, the second end configured to output a V G1 signal, and the V G1 signal configured to drive the gate terminal.

51. The power amplifier of claim 49, wherein the coupling network is configured to provide a non-zero DC voltage to the gate terminal, the non-zero DC voltage being configured to bias the first signal to swing above a ground reference.

52. The power amplifier of claim 49, wherein the coupling network is configured to provide a DC ground to the source terminal.

53. The power amplifier of claim 49, wherein the coupling network is further configured to enable the V S1 signal to swing below DC ground.

54. The power amplifier of claim 49, wherein the combining network is configured to adjust the amplitude of the V S1 signal.

55. The power amplifier of claim 49, wherein the combining network is configured to adjust the bias of the V S1 signal.

56. The power amplifier of claim 49, wherein the transistor is fabricated using one or more of the following processes: bulk CMOS, CMOS SOI, GaAs, GaN.

57. The power amplifier of claim 49, wherein the transistor is characterized as one of an NMOS device, a PMOS device, an NPN device, or a PNP device.

58. The method of claim 58, further comprising a third transmission line section T3 having a first end connected to ground and a second end configured to output a V S2 signal; 51. The power amplifier of claim 50, wherein the third transmission line section T3 is electromagnetically coupled to the transmission line section T4 to generate the V G1 signal in response to receiving the input signal Vin- at the first end of the transmission line section T4.

59. A method for improving power efficiency of a power amplifier without increasing a supply voltage, comprising the steps of: coupling the V G1 signal to a gate terminal of a transistor using a coupled transmission line pair; coupling a V S1 signal, out of phase with the V G1 signal, to a source terminal of the transistor using the coupled transmission line pair; and allowing the drain terminal of the transistor to swing in phase with the source terminal; The coupled transmission line pair includes: a first transmission line section T1 having a first end and a second end, the first end being connected to ground and the second end being configured to output a V S1 signal; a second transmission line section T2 having a first end and a second end, the first end configured to receive a first input signal Vin+, the second transmission line section T2 being electromagnetically coupled to the first transmission line section T1 to generate the V S1 signal in response to receiving the input signal Vin+ at the first end; a transmission line section T4 having a first end and a second end, the first end configured to receive a second input signal Vin-, the second end configured to output the V G1 signal, and the V G1 signal configured to drive the gate terminal.

60. The method of claim 59, wherein the step of coupling the V G1 signal to a gate terminal includes providing a non-zero DC voltage to the gate terminal.

61. The method of claim 60, wherein the non-zero DC voltage is configured to bias the V G1 signal to swing above a ground reference.

62. The method of claim 59, wherein the step of coupling the V S1 signal to a source terminal includes swinging the V S1 signal below a ground reference.

63. The method of claim 59, wherein the step of coupling the V S1 signal to a source terminal includes adjusting the amplitude of the V S1 signal.

64. The method of claim 59, wherein the step of coupling the V S1 signal to the source terminal is configured to increase the time the transistor is in saturation.

65. The method of claim 59, wherein one or more of the steps of coupling the V G1 signal to a gate terminal and coupling the V S1 signal to a source terminal includes coupling to one or more of a transmission line, a transformer, or a balun.

66. The method of claim 59, further comprising the step of outputting a signal from the drain terminal.

67. The method of claim 66, wherein the drain terminal is coupled to an antenna.

68. A power amplifier comprising: a transistor M1 having a gate terminal, a source terminal, and a drain terminal; a coupling network; The coupling network comprises: a first transmission line T1 having a first end connected to ground and a second end connected to the source terminal and configured to output a V S1 signal; a second transmission line T2 having a first end configured to receive a first input signal Vin+ and a second end configured to output a V G2 signal; A power amplifier, wherein the coupling network is configured to enable the V S1 signal to drop below ground in response to receiving the first input signal Vin+ at a first end of the second transmission line T2 by adjusting one or more electromagnetic coupling coefficients between the first transmission line T1 and the second transmission line T2.

69. The power amplifier of claim 68, wherein the V S1 signal comprises αVin+, where α is a coupling coefficient set by characteristics of the first transmission line T1 and characteristics of the second transmission line T2.

70. The power amplifier of claim 68, wherein the impedance of the coupling network is configured by setting one or more of the length, width, thickness, gap, and ground plane opening width of one or more of the first transmission line T1 and the second transmission line T2.

71. The coupling network, a third transmission line T3 having a first end and a second end, the first end being grounded and the second end being configured to output a V S2 signal; and a fourth transmission line T4 having a first end and a second end, the first end configured to receive a second input signal Vin-, the second end configured to output the V G1 signal, and the V G1 signal configured to drive the gate terminal of the transistor M1.

72. The power amplifier of claim 68, wherein the coupling network is further configured to enable the source terminal and the drain terminal to swing in phase with each other.

73. The power amplifier of claim 68, wherein the coupling network is further configured to provide a non-zero DC voltage, the non-zero DC voltage configured to bias the V G2 signal to swing above a ground reference.

74. The power amplifier of claim 68, wherein the coupling network is further configured to provide a DC ground to the source terminal.

75. The power amplifier of claim 68, wherein the combining network is further configured to adjust the amplitude of the V S1 signal.

76. A power amplifier as described in claim 69, wherein the coupling coefficient α is set in the range between 0 and 1.

77. The power amplifier of claim 69, wherein the coupling coefficient α is in the range between about 0.1 and about 0.

9.

78. The power amplifier of claim 69, wherein the coupling coefficient α is approximately 0.

35.

79. A power amplifier configured such that even mode impedance Z 0e and odd mode impedance Z 0o are set to approximately 15 ohms and approximately 40 ohms, respectively, at an operating frequency of approximately 30 GHz.

80. A power amplifier as described in claim 71, wherein the third transmission line T3 is electromagnetically coupled to the fourth transmission line T4 and generates the V S2 signal in response to receiving the input signal Vin- at the first end of the fourth transmission line T4.

81. The power amplifier of claim 71, wherein the coupling network is configured to enable the V S2 signal to drop below ground in response to receiving the input signal Vin− at a first end of the fourth transmission line T4 by adjusting an electromagnetic coupling coefficient between the third transmission line T3 and the fourth transmission line T4.

82. The power amplifier of claim 71, wherein the combining network is configured to cause the V S2 signal to be out of phase with the V G2 signal.

83. The power amplifier of claim 71, wherein the coupling network is further configured to provide a non-zero DC voltage, the non-zero DC voltage configured to bias the V G1 signal to swing above a ground reference.

84. A method for improving power efficiency of a power amplifier having at least one transistor with a gate, a source, and a drain without increasing a supply voltage, comprising: coupling a V G1 signal to a gate terminal of said transistor using a coupled transmission line pair; coupling a V S1 signal, out of phase with the V G1 signal, to a source terminal of the transistor using the coupled transmission line pair; swinging the V S1 signal below a ground reference.

85. The method of claim 84, wherein the step of coupling the V G1 signal to the gate terminal includes providing a non-zero DC voltage to the gate terminal.

86. The method of claim 84, wherein the step of coupling the V S1 signal to the source terminal is configured to increase the saturation time of the transistor.

87. The semiconductor laser according to claim 87, further comprising the step of swinging the drain terminal of the transistor in phase with the source terminal of the transistor; The coupled transmission line pair includes: a first transmission line T1 having a first end connected to ground and a second end configured to output the V S1 signal; a second transmission line T2 having a first end configured to receive a first input signal Vin+ and a second end, the second transmission line T2 being electromagnetically coupled to the first transmission line T1 to generate the V S1 signal in response to receiving the first input signal Vin+ at the first end of the second transmission line T2; 85. The method of claim 84, comprising a transmission line T4 having a first end configured to receive a second input signal Vin- and a second end configured to output the V G1 signal configured to drive the gate terminal.

88. The method of claim 85, wherein the non-zero DC voltage is configured to bias the V G1 signal to swing above a ground reference.

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