High-speed multi-port memory with collision support

Abstract

A multi-port memory is provided that supports collisions between read and write ports to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. A multiplexer selects an output bit from the sense amplifier when a read port to the multi-port bitcell is addressed during the same system clock signal.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Application No. 17 / 210,230, filed March 23, 2021, the entire contents of which are incorporated herein by reference.

[0002] This application relates to memories, and more particularly to high speed multi-port memories that support collisions. [Background technology]

[0003] A static random access memory (SRAM) bitcell contains a pair of cross-coupled inverters to store a bit. Each inverter requires two transistors, so four transistors are required to implement two cross-coupled inverters. In a conventional single-port SRAM bitcell, two additional access transistors complete the bitcell implementation, thereby requiring a total of six transistors. The two access transistors are controlled by a shared word line, whereby the two access transistors form a single read / write port to the bitcell. However, the single-port architecture is problematic for multiple processor applications, as contention occurs between multiple processors on the single access port. By adding additional access transistors, a multi-port SRAM bitcell may have an access (read) port for each processor.

[0004] Although multi-port SRAMs are advantageous for multiple processor architectures, collisions occur when a write operation occurs simultaneously with a read operation on the same multi-port SRAM bit cell. To avoid collisions, multi-port SRAM bit cells are conventionally accessed in a "double-pump" manner with respect to a system clock signal that controls memory access. In response to a transition (e.g., rising edge) of the system clock signal, a read operation may occur on one or more of the access ports during a first portion of a period of the system clock signal. After the read operation is completed, a write operation may then occur during a second portion of the system clock signal period. However, the double-pump operation reduces memory speed because the write and read operations must occur consecutively during the system clock signal period. Summary of the Invention [Means for solving the problem]

[0005] According to one aspect of the disclosure, a multi-port memory is provided that includes a multi-port bitcell including a first read port having a first read port bitline, the multi-port bitcell further including a pair of write port bitlines, a sense amplifier coupled to the pair of write port bitlines, a first inverter coupled to the first read port bitline, and a first multiplexer configured to select between a data output bit from the sense amplifier and a data output bit from the first inverter to provide a selected data output bit.

[0006] According to another aspect of the disclosure, there is provided a method of operation for a multi-port memory including: comparing a first read port address to a write port address to detect a first collision in response to the first read port address matching the write port address and detecting that the first collision does not occur in response to the first read port address not matching the write port address; selecting, in a first multiplexer, a data output bit resulting from a single-ended read through the first read port to the multi-port bitcell in response to detecting that the first collision does not occur; and selecting, in the first multiplexer, a data output bit resulting from a differential read through the write port to the multi-port bitcell in response to the first collision being detected.

[0007] According to yet another aspect of the present disclosure, a multi-port memory is provided that includes a multi-port bitcell including a first read port having a first read port bitline and a first read port wordline, the multi-port bitcell further including a write port or having a pair of write bitlines; an address comparator configured to detect a collision in response to the write port address indicating the write port and the read port address indicating the first read port; and a read port wordline controller configured to assert the first read port wordline in response to a collision being detected and to de-assert the first read port wordline in response to no collision being detected.

[0008] According to yet another aspect of the present disclosure, a multi-port memory is provided that includes an address comparator configured to detect a collision in response to a read port address and a write port address both pointing to a first multi-port bitcell; a sense amplifier configured to read a first data bit from the first multi-port bitcell through the write port; a write driver configured to write a second data bit to the first multi-port bitcell through the write port after the first data bit is read; and a multiplexer coupled to the sense amplifier and configured to select the first data bit in response to the collision being detected.

[0009] These and additional advantages may be more fully understood through the following detailed description. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 illustrates an example multi-port bitcell for a multi-port memory implementing collision support as disclosed herein. [Diagram 2] 1 is a flowchart illustrating an example of a collision support implementation according to one aspect of the present disclosure. [Diagram 3] FIG. 2 is a circuit diagram of a multi-port memory configured with collision support according to one aspect of the disclosure. [Figure 4] 1 is a flowchart illustrating a method of operation of a crash support according to one aspect of the present disclosure. [Diagram 5] FIG. 1 illustrates several example electronic systems, each incorporating collision support in a multi-port memory, in accordance with one aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The embodiments of the present disclosure and their advantages are best understood by referring to the following detailed description, it being understood that like reference numerals are used to identify like elements shown in one or more of the figures.

[0012] A multi-port SRAM is disclosed that supports collisions rather than avoiding them by double pumping or the like. To support collisions, the memory includes an address comparator for each read port. Each address comparator compares a read port address with a write port address. If the comparison indicates that the read port address points to a first multi-port bitcell and the write port address points to a second multi-port bitcell, a single-ended read operation is performed through the read port to the first multi-port bitcell. At the same time, a write operation is performed through the write port to the second multi-port bitcell. Thus, high speed operation is improved due to the simultaneous operation of the read and write ports (even though the operations are performed on different multi-port bitcells).

[0013] However, if the address comparison indicates that the read and write port addresses point to the same multi-port bitcell, the read port is not accessed. To perform a read, the multi-port SRAM takes advantage of the speed difference between single-ended and differential read operations. To do so, the write operation is delayed until a differential read is performed through the write port. This differential read operation may therefore be performed every time the write port is accessed. Although the write operation is delayed so that a differential read is performed first, the memory operation speed is not affected because a single-ended read through the read port is not as fast as a differential read. Thus, differential read and write operations (which are also differential operations) may be completed in approximately the same time as a single-ended read operation requires. Note the following advantages: If the multi-port bitcell does not have a collision, the single-ended read operation may proceed. Meanwhile, a differential read is performed for a multi-port bitcell that does have a collision. Thus, no delays are incurred as occurs in the double pump approach.

[0014] An exemplary multi-port bitcell will now be described, although it will be appreciated that an SRAM having any suitable multi-port bitcell architecture may implement the collision support disclosed herein. Additionally, the exemplary multi-port bitcell below has a pair of read ports, although alternative implementations may include only one read port in the multi-port bitcell. Thus, a multi-port SRAM bitcell includes at least one read port in addition to a write port. The write and read ports may be better appreciated by considering the exemplary three-port SRAM bitcell 100 shown in FIG. 1. The write port includes a write port access n-type metal-oxide semiconductor (NMOS) transistor M3 and another write port access NMOS transistor M4. A write word line (WWL) is connected to the gates of the write port access transistors M3 and M4, thereby switching the write port access transistors on when the write word line is charged to a power supply voltage. The write port also includes a pair of write bit lines formed by a true write bit line (WBL) and a complementary write bit line (WBLB). For simplicity, the true write bit line may simply be referred to as the write bit line in the following description. The write bit line WBL is connected to the drain / source terminal of the write port access transistor M3. The remaining drain / source terminal of the write port access transistor M3 is connected to the Q data output node of the bit cell 100. The terminals are referred to as "drain / source" terminals in that which terminal is the source and which terminal is the drain is determined by the binary state of the SRAM bit cell 100 before the write operation and by the binary state of the bit being written to the SRAM bit cell 100 during the write operation. The complementary write bit line WBLB is similarly arranged as it is connected to the drain / source terminal of the write port access transistor M4. The remaining drain / source terminal of the write port access transistor M4 is connected to the complementary data output node QB of the SRAM bit cell 100.

[0015] Prior to a write operation, the write bit lines WBL and WBLB are precharged to a power supply voltage. A write operation is performed in response to an edge (e.g., rising) of a system clock signal. A word line generator or controller (not shown in FIG. 1 but described further below) responds to the clock edge by charging the write word line WWL to a power supply voltage such that the write port access transistor is switched on. With the write word line asserted, a write driver (also not shown in FIG. 1 but described further below) then drives the write bit line pair with a data bit to be written to the multi-port bit cell. If the binary value of the data bit is true, the write driver discharges the complement write bit line WBLB while maintaining the true write bit line WBL in a charged state. Conversely, in response to the data bit being false, the write driver discharges the true write bit line WBL while maintaining the complement write bit line WBLB in a charged state.

[0016] Depending on which bit lines are charged and which write bit lines are discharged to ground by the write driver, the write driver determines which output node of the SRAM bitcell 100 is charged to a power supply voltage or discharged to ground. For example, if the write bit lines remain charged during a write operation, the Q output node is charged while the complementary QB output node is discharged. The Q output node is the output node of a first inverter cross-coupled to a second inverter in the SRAM bitcell 100. The first inverter includes a p-type metal oxide semiconductor (PMOS) transistor P1 whose source is connected to a power supply node for the power supply voltage. The drain of transistor P1 is connected to the drain of NMOS transistor M1. The source of transistor M1 is connected to ground. The drains of transistors P1 and M1 form the output node of the first inverter and also form the Q output node for the bitcell 100.

[0017] The second inverter is similarly arranged and therefore includes a PMOS transistor P2, whose source is connected to the power supply node and whose drain is connected to the drain of an NMOS transistor M2, whose source is connected to ground. The drains of transistors P2 and M2 form the output node of the second inverter and also form the QB output node. To complete the cross-coupling between the inverters, the Q output node is connected to the gates of transistors P2 and M2. Similarly, the QB output node is connected to the gates of transistors P1 and M2. Thus, the two inverters reinforce each other and latch the bit to be written into the SRAM bit cell 100.

[0018] The first read port A of the SRAM bitcell 100 includes an NMOS transistor M5, an NMOS access transistor M6, a read port A bitline (RBLA), and a read port A word (RWLA). The read port A bitline RBLA is connected to the drain of the access transistor M6. The source of the access transistor M6 is connected to the drain of the transistor M5. The source of the transistor M5 is connected to ground. The Q output node is connected to the gate of the transistor M5. The read port A wordline RWLA is connected to the gate of the access transistor M6. Before a read operation to the read port A, the read port A bitline RBLA is precharged to a power supply voltage. The read port A bitline RBLA then floats during a single-ended read operation to the read port A, so that the bitline voltage can be affected by a single-ended read operation to the SRAM bitcell 100 through the read port A. During a single-ended read operation for read port A, the read port A word line RWLA is charged to the power supply voltage and the access transistor M6 is switched on. If the Q output node is charged to the power supply voltage before the read operation for port A, the transistor M5 is switched on and the source of the transistor M6 is discharged. When the access transistor M6 is switched on by asserting the read port A word line RWLA, the read port A bit line RBLA discharges through the transistors M5 and M6. If the read operation to the read port A is single-ended (involving only one read bit line), the sense amplifier that senses the binary content of the SRAM bit cell 100 through the read port A may be formed by a simple inverter (not shown in FIG. 1, but described further below). When the read port A bit line RBLA discharges to the trip point of the sense amplifier inverter, the sense amplifier inverter asserts its output signal to the power supply voltage to successfully represent the binary 1 that was being read from the SRAM bit cell 100.Since each of the sense amplifier inverters disclosed herein is formed by an inverter that acts as a sense amplifier, the sense amplifier inverters are sometimes referred to herein simply as inverters.

[0019] If SRAM bitcell 100 instead stores a binary 0, the Q output node is discharged prior to the read operation. In that case, transistor M5 is switched off, causing read port A bitline RBLA to remain in a precharged state during a read operation to read port A. Thus, the sense amplifier inverter continues to emit an output signal representing a binary 0 being read from SRAM bitcell 100.

[0020] The remaining read port B is similarly configured to include NMOS transistors M7 and M8 and a read port B word line (RWLB) and a read port B bit line (RBLB). The read port B bit line RBLB is connected to the drain of the access transistor M8. The source of the access transistor M8 is connected to the drain of the transistor M7. The source of the transistor M7 is connected to ground. The QB output node is connected to the gate of the transistor M7. The read port B word line RWLB is connected to the gate of the access transistor M8. Before a single-ended read operation to the read port B, the read port B bit line RBLB is precharged to a power supply voltage. The read port B bit line RBLB then floats, so that the voltage of the read port B bit line RBLB can be affected by a read operation to the SRAM bit cell 100 through the read port B. During a single-ended read operation through the read port B, the read port B word line RWLB is charged to a power supply voltage and the access transistor M8 is switched on. If the QB output node is charged to the supply voltage prior to a read operation for port B, transistor M7 is switched on and the source of access transistor M8 is discharged. When access transistor M8 is switched on by asserting the read port B word line RWLB, the read port B bit line RBLB discharges through transistors M7 and M8. Conversely, the read port B bit line RBLB remains precharged during a read port B access when the QB node is discharged.

[0021] Single-ended read operations to read ports A and B are performed only without collisions. A collision occurs if a write operation to the multi-port bitcell 100 through a write port occurs in the same system clock cycle as a read operation to read port A and / or read port B. The read operation attempts to read the binary state of the bit stored in the SRAM bitcell 100, possibly while a write operation is changing this binary state. The resulting collision disrupts the read operation. As mentioned above, collision mitigation is conventionally performed via a double pump operation that separates the system clock period into two parts. In the first part, a read operation to either read port A and / or B (or both) occurs. The write port is not accessed during this first part. During the second part of the system clock period, a write operation occurs. If the double pump operation is performed properly, no write operation can occur during a read operation, so no collisions can occur. However, this division of the system clock period in a double pump operation reduces memory operation speed.

[0022] To eliminate the timing penalty of the double pump operation, a multi-port memory is provided in which the system clock period is not divided into separate portions for read and write operations. Instead, an address comparison is performed for each active read port to determine whether the write port of the SRAM bit cell is also addressed by a write operation. If the address comparison indicates that the addressed SRAM bit cell is not undergoing a write operation, a single-ended read operation is performed through the corresponding read port. This single-ended read operation is performed as described with respect to SRAM bit cell 100. Thus, the corresponding read port bit line is precharged and then floats while the corresponding read word line is charged, whereby the resulting voltage on the read port bit line is sensed by a sense amplifier inverter to generate a read port data output bit or a complement read port data output bit depending on whether read port A or read port B is being addressed. However, if the address comparison indicates that the write port of the SRAM bit cell is also being accessed, no read operation is performed through the read port. Because a read port is not in use, the corresponding read port bitline is not floated and the corresponding read wordline voltage is not asserted. Instead, if the write port is accessed for a multi-port SRAM bitcell during the same system clock period in which one (or both) of the read ports are accessed, a read operation is performed through the write port.

[0023] A read operation through the write port takes advantage of the differences between the read and write ports. In particular, note that a write operation to the write port involves a pair of write port bit lines, whereas a read operation to either of the read ports A and B is single-ended and occurs through only one read port bit line. Given the differential nature of the write port access, a differential read of a bit stored in a multi-port SRAM bit cell may occur relatively quickly through the write port compared to a single-ended read on the read port. In that respect, the threshold voltage for the sense amplifier inverter to perform a single-ended read is approximately one-half the power supply voltage. For example, assume that the power supply voltage is 0.8V. Then, the threshold voltage for the sense amplifier inverter to perform a single-ended read through the read port is approximately 400mV. Then, the precharged read port bit line must be discharged from 800mV to the trigger point of 400mV before the sense amplifier inverter can make its bit decision. However, a differential read via the write port bitlines does not require such a relatively large voltage change before a differential sense amplifier coupled to the write port bitlines can make a bit decision.

[0024] When a write port is addressed in a given system clock period, the driving of the write bit lines with the data bits to be written during the write operation is delayed until a differential read operation can be performed. Before the write port access, the write bit lines may be precharged in a default state. During a differential read through the write port, one of the write bit lines begins to discharge from the default precharge state depending on the binary value of the stored bit in the multi-port SRAM bit cell. A voltage difference then occurs between the write port bit lines that is sensed by the differential sense amplifier. Compared to the threshold voltage of the sense amplifier inverter, the differential sense amplifier may make a bit decision when the voltage difference is only a small fraction of the power supply voltage (e.g., 100 mV or 80 mV or even lower). The voltage difference across the write port bit lines to make a differential bit decision in the differential sense amplifier is significantly smaller compared to the threshold voltage for the sense amplifier inverter to make a single-ended bit decision. Thus, a sufficient voltage difference across the write port bit lines to perform a differential read occurs quickly compared to a single-ended read operation.

[0025] Given this relative speed for the differential read, driving the differential read and write bit lines to complete a write operation may still be performed in substantially the same time as it would take for a single-ended read operation. Thus, the operation performed is significantly faster than a double pump operation in that the write operation (including the initial differential read) may begin at substantially the same time that the single-ended read operation is being performed, but the address comparison will show that the write port was also addressed.

[0026] In general, it is more common for the read port to be accessed without collisions for a multi-port SRAM bitcell. In such a case, a single-ended read is performed through the addressed read port. The write port is not accessed, and therefore the write bit lines remain in a default precharge state. However, both the read port and the write port may be addressed for a given multi-port SRAM bitcell in the same system clock period. In that case, no single-ended read operation is performed through the addressed read port, but instead a differential read operation is performed through the write port before the write operation begins and completes. The differential read operation senses both the stored data bit in the multi-port SRAM bitcell and its complement. Thus, the multiplexer may select the bit decision from the sense amplifier inverter for the addressed read port if the write port is not addressed (no collisions occur), or select the bit decision from the differential sense amplifier if the write port is addressed (a collision exists). A latch may then latch the bit decision selection from the multiplexer.

[0027] A flowchart 200 for collision mitigation for a multi-port SRAM is shown in FIG. 2. In this context, the multiplexed bitcell 100 is an example of a suitable multi-port bitcell, but it will be appreciated that the collision mitigation disclosed herein may be implemented using any suitable multi-port bitcell architecture. The flowchart 200 begins in response to a triggering edge of a clock signal 205 initiating a read and / or write operation. In relation to the flowchart 200, the write port is shown as port C to distinguish it from the read ports A and B. Following the triggering edge of the clock signal 205, the write port may be addressed, although this may not be true for every cycle of the clock signal 205. If the write port is addressed, then the write word line (port C word line) is asserted in step 220. After the write word line is asserted, the stored bit in the multi-port bitcell corresponding to the write port C is retrieved to the write port C through a pair of write bit lines via a differential read 240. A differential sense amplifier then senses the binary value of the retrieved bit. After the differential read is completed, the write driver then drives the data bit to be written into the corresponding bit cell through write port C in step 265. Once the write operation is completed, the write word line is discharged (closed) and step 265 is completed.

[0028] To determine if a collision occurs for read port A in the same clock cycle, the addresses of read port A and write port C are compared in step 210. If the addresses point to the same multi-port bit cell (e.g., the addresses may be equal), then a collision occurs, shown as a yes decision in flowchart 200. Conversely, if the addresses of read port A and write port C point to different multi-port bit cells, then no collision occurs for read port A (shown as a no decision in flowchart 200). If no collision occurs at read port A, then the read port A word line may be charged in step 225, so that a single-ended read operation may occur through read port A in step 235. Multiplexer 250 then selects the single-ended read result (assuming no collision occurs), so that the output bit may be latched in step 260. However, if a collision occurs between port A and port C, the read port A word line is not asserted and multiplexer 250 selects the output bit from the differential read operation in step 240. Thus, the selection by multiplexer 250 may be controlled by whether the yes determination for the collision between port A and port C in step 210 is true or false.

[0029] A similar address comparison is performed for read port B in step 215. If the addresses of port B and port C point to the same multi-port bit cell, then a collision has occurred (yes decision). Conversely, if the addresses of read port A and write port C point to different multi-port bit cells, then there is no collision for read port B (no decision). If there is no collision at read port B, then the read port B word line may be charged in step 230, so that a single-ended read operation may be performed through read port B in step 245. Multiplexer 255 may then select the port B single-ended read result (assuming there is no collision), so that the complementary output bit may be latched in step 270. However, if there is a collision between port B and port C, then the read port B word line is not asserted and multiplexer 255 selects the complementary output bit from the differential read operation in step 240. Thus, the selection by multiplexer 255 may be controlled by whether the yes determination for the collision between port B and port C in step 215 is true or false.

[0030] An SRAM 300 configured for collision avoidance will now be described with respect to Figure 3. Address comparator 305 performs an address comparison between the port A address and the port C address in response to a triggering edge of a system clock signal (CLK). If the comparison indicates that no collision occurs between port A and port C, address comparator 305 sends the system clock signal as a clock A signal (CLKA) to precharge and port A wordline controller 310, and in response to an assertion of the precharge A signal, triggers the assertion (charging) of the port A wordlines and the floating of the precharge of the port A bitlines. The state of precharge signal A (true or false) may control the selection by multiplexer 250 as described further herein.

[0031] Address comparator 315 performs an address comparison between the Port B address and the Port C address in response to a triggering edge of the system clock signal (CLK). If the comparison indicates that no collision occurs between Port B and Port C, address comparator 315 sends the system clock signal as the Clock B signal (CLKB) to the Precharge and Port B wordline controller 311 and triggers the assertion (charging) of the Port B wordlines and the float of the precharge of the Port B bitlines in response to the assertion of the Precharge B signal. The state of the Precharge signal A (true or false) may control the selection by multiplexer 255 as described further herein.

[0032] The write port in the multiport bitcell 100 includes the write word line WWL and the write bit lines WBL and WBLB, as described above. The differential sense amplifier 320 is coupled to the write bit lines WBL and WBLB, such that when the write word line WWL is asserted to open the write port, the differential sense amplifier 320 can sense both the data bit and its complement stored in the multiport bitcell 100. The sensed data bit is denoted as Sout, while the sensed complement data bit is denoted as SoutB. Sensing by the sense amplifier 320 is performed in response to assertion of a sense enable signal. The sense amplifier 320 is also integrated with a write driver (Din driver), which can then drive the write bit lines WBL and WBLB with the data bit Din to be written after the differential read operation is completed.

[0033] The Precharge A signal drives the gate of a PMOS transistor P4, whose source is coupled to a power supply voltage node and whose drain is connected to a read port A bit line. The Precharge A signal controls whether the read port A bit line floats or remains in a default precharge state. When the Precharge A signal is deasserted, the read port A bit line is precharged due to conduction by transistor P4. As used herein, a signal is considered to be "asserted" when it is true, regardless of whether a logical high or logical low convention is used. The Precharge A signal is active high, and is thereby asserted by being charged to the power supply voltage. The Precharge A signal also controls the floating of the global read port A bit line (GRBLA). To do so, the Precharge A signal also drives the gate of a PMOS transistor P5, whose drain is connected to the global read port A bit line and whose source is connected to a power supply node. Thus, deasserting the Precharge A signal also causes transistor P5 to conduct, precharging global read bitline A to the supply voltage. Inverter INV C inverts the binary state of the read port A bitline to drive the gate of NMOS transistor M9, whose source is connected to ground and whose drain is connected to the global read port A bitline. Transistor M9 is therefore turned off while the read port A bitline is precharged. When read port A is addressed, the Precharge A signal is asserted to switch off both transistors P4 and P5, thereby causing both read port A bitline RBLA and global read port A bitline GRBLA to float. If the data bit stored in multiport bitcell 100 is a binary 0 (assuming logic high convention), the precharge state of the RBLA and GRBLA lines is not affected, even though the RBLA and GRBLA lines are floating. The read port A sense amplifier inverter (INV A) inverts the binary state of the GRBLA line to provide the sensed data output bit.The sensed data output bit is selected by multiplexer 250 due to the assertion of the Precharge A signal. However, during a collision, the Precharge A signal is not asserted, causing multiplexer 250 to select the Sout data bit from the differential sense amplifier 320. The data output latch 325 may then latch the sensed bit (DoutA) regardless of whether it was generated by read port A or write port C.

[0034] Read port B is similar. The Precharge B signal drives the gate of PMOS transistor P6, whose source is coupled to the power supply voltage node and whose drain is connected to the read port B bit line B (RBLB). The Precharge B signal controls whether the read port B bit line floats or remains in a default precharged state. When the Precharge B signal is deasserted, precharging of the read port B bit line occurs due to conduction by transistor P6. The Precharge B signal also controls the floating of the global read port B bit line (GRBLB). To do so, the Precharge B signal also drives the gate of PMOS transistor P7, whose drain is connected to the global read port B bit line and whose source is connected to the power supply node. Thus, deasserting the Precharge B signal also causes transistor P7 to conduct to precharge the global read port B bit line to the power supply voltage. Inverter INV D inverts the binary state of the read port B bit line to drive the gate of NMOS transistor M10, whose source is connected to ground and whose drain is connected to the global read port B bit line. Thus, transistor M10 is turned off while the read port B bit line is precharged. When read port B is addressed, the precharge B signal is asserted to switch off both transistors P6 and P7, thereby causing both read port B bit line RBLB and global read port B bit line GRBLB to float. If the data bit stored in multiport bitcell 100 is a binary 0 (again, assuming logic high convention), the precharge state of the RBLB and GRBLB lines is unaffected, even though the RBLB and GRBLB lines are floating. The read port B sense amplifier inverter (INV B) inverts the binary state of the GRBLB line to provide the sensed data output bit. The sensed data output bit is selected by multiplexer 255 due to the assertion of the Precharge B signal.However, during a collision, the Precharge B signal is not asserted, causing the multiplexer 255 to instead select the SoutB complementary data bit from the differential sense amplifier 320. The data output latch 325 may then latch the sensed bit (DoutB) regardless of whether it was generated by read port B or write port C.

[0035] A method for collision support will now be described with reference to the flow chart shown in FIG. 4. The method includes an act 400 of comparing a first read port address to a write port address to detect a first collision in response to the first read port address matching the write port address and to detect a first absence of a collision in response to the first read port address not matching the write port address. The comparison in either of the address comparators 305 and 315 is an example of act 400. The method further includes an act 405 performed in a first multiplexer and including selecting a data output bit resulting from a single-ended read to the multi-port bitcell through the first read port in response to detecting the absence of a first collision. The selection in either of the multiplexers 250 or 255 with the absence of a collision is an example of act 405. Finally, the method includes an act 410 also performed in the first multiplexer and including selecting a data output bit resulting from a differential read to the multi-port bitcell through the write port in response to detecting the first collision. A selection in either multiplexer 250 or 255 involving a conflict is an example of an act 410 .

[0036] The multi-port memory with crash support disclosed herein may be incorporated into a variety of electronic systems. For example, as shown in Figure 5, a mobile phone 500, a laptop computer 505, and a tablet PC 510 may all include a multi-port memory with crash support according to the present disclosure. Other exemplary electronic systems, such as music players, video players, communication devices, and personal computers, may also be configured with a multi-port memory constructed according to the present disclosure.

[0037] The disclosure is now summarized in the following series of clauses. Clause 1. A multi-port memory, comprising: a multiport bitcell including a first read port having a first read port bitline, the multiport bitcell further including a pair of write port bitlines; a sense amplifier coupled to the pair of write port bit lines; a first inverter coupled to the first read port bit line; and a first multiplexer configured to select between the data output bit from the sense amplifier and the data output bit from the first inverter to provide a selected data output bit. Clause 2. The multi-port bitcell further includes a second read port having a second read port bitline, and the multi-port memory further includes: a second inverter coupled to the second read port bit line; 13. The multi-port memory of claim 1, further comprising: a second multiplexer configured to select between the complementary data output bit from the sense amplifier and the complementary data output bit from the second inverter to provide a selected complementary data output bit. Clause 3. The multi-port memory of clause 2, further comprising a data latch configured to latch the selected data output bit and the selected complement data output bit. Clause 4. An address comparator configured to detect a collision in response to the read port address being the same as the write port address and to detect no collision in response to the read port address being different from the write port address; A multi-port memory as described in any of clauses 1 to 3, further comprising a read word line controller configured to assert a read port word line to the first read port in response to detecting no collision, and to not assert the read port word line in response to detecting a collision. Clause 5. The multi-port memory of clause 4, wherein the read word line controller is further configured to assert a precharge signal in response to detecting no collision and to not assert the precharge signal in response to detecting a collision. Clause 6. The multi-port memory of clause 5, further comprising a transistor coupled between the first read port bitline and a power supply node for a power supply voltage, the transistor configured to switch on in response to assertion of a precharge signal and to switch off in response to the precharge signal not being asserted. Clause 7. The multi-port memory of clause 6, wherein the transistors comprise p-type metal oxide semiconductor (PMOS) transistors. Clause 8. The multi-port memory of any of clauses 1-7, further comprising a write driver configured to drive the pair of write bit lines in response to a bit being written to the multi-port bit cell after completion of a sensing operation by the sense amplifier. Clause 9. The multiport memory of clause 4, wherein the multiport bitcell comprises a pair of cross-coupled inverters configured to drive a data output node and a complementary data output node, and the first read port further includes an access transistor configured to be controlled by a read port word line. Clause 10. The multi-port memory of clause 9, wherein the first read port further includes a second transistor coupled between ground and the terminal of the access transistor, a gate of the second transistor coupled to the data output node, and wherein the multi-port memory is incorporated into a cellular telephone. Clause 11. A method of operating a multi-port memory, comprising: comparing the first read port address to the write port address to detect a first collision in response to the first read port address matching the write port address and to detect no first collision in response to the first read port address not matching the write port address; selecting, in a first multiplexer, in response to detecting a first absence of a collision, a data output bit resulting from a single-ended read through a first read port into the multi-port bit cell; and selecting, in a first multiplexer, in response to detecting the first collision, a data output bit resulting from a differential read through the write port to the multi-port bit cell. Clause 12. The method of clause 11, further comprising triggering a comparison of the first read port address and the write port address in response to an edge of a clock signal. Clause 13. Comparing the second read port address to the write port address, detecting a second collision in response to the second read port address matching the write port address and detecting no second collision in response to the second read port address not matching the write port address; selecting, in a second multiplexer, in response to detecting a second absence of a collision, a complementary data output bit resulting from a single-ended read into the multi-port bit cell through a second read port; 13. The method of any of clauses 11 and 12, further comprising: in a second multiplexer, in response to detecting a second collision, selecting a complementary data output bit resulting from a differential read through the write port to the multi-port bit cell. Clause 14. Precharging a first bit line at a first read port before comparing the first read port address to a write port address; in response to detecting a first collision, floating a first bit line; 14. The method of any of clauses 11-13, further comprising: in response to detecting the absence of the first collision, maintaining a precharge of the first bit line. Clause 15. The method of clause 14, further comprising the step of asserting a precharge signal in response to detecting the absence of the first collision, wherein the floating of the first bit line is effected in response to asserting the precharge signal. Clause 16. The method of clause 15, further comprising switching off a transistor coupled between the first bit line and a power supply node for a power supply voltage in response to assertion of a precharge signal. Clause 17. The method of clause 16, further comprising: in response to detecting the first collision, maintaining the precharge signal deasserted to maintain the transistor in an on state. Clause 18. The method of any of clauses 11-17, further comprising latching the data output bits from the first multiplexer. Clause 19. A multi-port memory, comprising: a multiport bitcell including a first read port having a first read port bitline and a first read port wordline, the multiport bitcell further including a write port having a pair of write port bitlines; an address comparator configured to detect a collision in response to the write port address pointing to the write port and the read port address pointing to the first read port; a read port word line controller configured to assert a first read port word line in response to no collision being detected, and configured to de-assert the first read port word line in response to detecting a collision. Clause 20. The multi-port memory of clause 19, wherein the read port wordline controller is further configured to assert a precharge signal for the first read port in response to no collision being detected, and the first read port is further configured to float the first read port bitline in response to assertion of the precharge signal. Clause 21. The multi-port memory of any of clauses 19 and 20, further comprising a sense amplifier configured to perform a differential read through the write port in response to a write port address pointing to the write port. Clause 22. The multi-port memory of clause 21, further comprising a data driver configured to drive the pair of write bit lines such that a data bit is written to the multi-port bit cell after the differential read is completed. Clause 23. An inverter coupled to a first read port bit line; 23. The multi-port memory of any of clauses 21 and 22, further comprising a multiplexer configured to select between the output of the inverter and the sense amplifier. Clause 24. A multi-port memory, comprising: an address comparator configured to detect a collision in response to both the read port address and the write port address pointing to the first multi-port bit cell; a sense amplifier configured to read a first data bit from the first multi-port bit cell through a write port; a write driver configured to write a second data bit to the first multi-port bitcell through the write port after the first data bit has been read; a multiplexer coupled to the sense amplifier and configured to select the first data bit in response to detecting a collision. Clause 25. The multi-port memory of clause 24, further comprising an inverter coupled to a read port bitline at a first read port in the first multi-port bitcell, the multiplexer further configured to select an output of the inverter in response to detecting no collision. Clause 26. The multi-port memory of clause 25, further comprising a data latch configured to latch an output bit from the multiplexer. Clause 27. The multi-port memory of any of clauses 25 and 26, wherein the first multi-port bitcell includes a second read port. Clause 28. The multi-port memory of any of clauses 25-27, further comprising a read port word line controller configured to assert a word line to the first read port in response to detecting no collision. Clause 29. The multi-port memory of clause 28, wherein the read port wordline controller is further configured to assert a precharge signal to the first read port in response to detecting no collision. Clause 30. The multiport memory of any of clauses 24 to 29, wherein the address comparator is configured to be triggered to detect a collision in response to an edge of a clock signal.

[0038] As will be appreciated by those skilled in the art at present, depending on the particular application at hand, numerous modifications, substitutions, and variations can be made in and to the materials, apparatus, configurations, and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the specific embodiments shown and described herein are merely some examples thereof, and the scope of the present disclosure should not be limited to the scope of such specific embodiments, but rather should be entirely within the scope of the following appended claims and their functional equivalents. [Explanation of symbols]

[0039] 100 SRAM bit cells 200 Flowchart 205 Clock Signal 240 Differential Read 250, 255 multiplexer 300 SRAM 305 Address Comparator 310 Port A Word Line Controller 311 Port B Word Line Controller 315 Address Comparator 320 Differential Sense Amplifier 325 Data Output Latch 500 Mobile Phones 505 Laptop Computer 510 Tablet PC M1, M2, M3, M4, M5, M6, M7, M8, M9, M10 NMOS transistors P1, P2, P4, P5, P6, P7 PMOS transistors RBLA Read Port A Bit Line RBLB Read Port B Bit Line RWLA Read Port A Word Line RWLB Read Port B Word Line WBL True Write Bit Line WBLB Write Bit Line WWL Write Word Line

Claims

1. A multi-port memory that is a static random access memory (SRAM), comprising: a multi-port bitcell including a first single-ended read port having a first read port bitline, the multi-port bitcell further including a differential write port with a pair of write port bitlines; a differential sense amplifier coupled to the pair of write port bit lines; a first inverter coupled to the first read port bit line; a first multiplexer configured to select either a data output bit from a sense amplifier in response to a read port address being different from a write port address and a data output bit from the first inverter in response to the read port address being the same as the write port address to provide a selected data output bit.

2. The multi-port bitcell further includes a second read port having a second read port bitline, and the multi-port memory further includes: a second inverter coupled to the second read port bit line; 2. The multi-port memory of claim 1, further comprising: a second multiplexer configured to select between a complementary data output bit from the sense amplifier and a complementary data output bit from the second inverter to provide a selected complementary data output bit.

3. 3. The multi-port memory of claim 2 further comprising a data latch configured to latch the selected data output bit and the selected complement data output bit.

4. an address comparator configured to detect a collision in response to a read port address being the same as a write port address and to detect no collision in response to the read port address being different from the write port address; 2. The multi-port memory of claim 1, further comprising: a read word line controller configured to assert a read port word line to the first read port in response to detecting the absence of a collision and to de-assert the read port word line in response to detecting the collision.

5. 5. The multi-port memory of claim 4, wherein the read word line controller is further configured to assert a precharge signal in response to the detection of the absence of the collision and to not assert the precharge signal in response to the detection of the collision.

6. 6. The multi-port memory of claim 5, further comprising a transistor coupled between the first read port bit line and a power supply node for a power supply voltage, the transistor configured to switch on in response to assertion of the precharge signal and to switch off in response to the precharge signal not being asserted.

7. The multi-port memory of claim 6 , wherein the transistors comprise p-type metal oxide semiconductor (PMOS) transistors.

8. 2. The multi-port memory of claim 1, further comprising a write driver configured to drive the pair of write bit lines in response to a bit being written to the multi-port bit cell after completion of a sensing operation by the sense amplifier.

9. 5. The multi-port memory of claim 4, wherein the multi-port bitcell comprises a pair of cross-coupled inverters configured to drive a data output node and a complementary data output node, and the first read port further includes an access transistor configured to be controlled by the read port wordline.

10. 10. The multi-port memory of claim 9, wherein the first read port further includes a second transistor coupled between ground and a terminal of the access transistor, a gate of the second transistor coupled to the data output node, and the multi-port memory is incorporated into a cellular phone.

11. A method of operating a multi-port memory that is a static random access memory (SRAM), comprising the steps of: comparing a first read port address to a write port address to detect a first collision in response to the first read port address matching the write port address and to detect no first collision in response to the first read port address not matching the write port address; inverting, in an inverter, a data output bit resulting from a single-ended read into the multi-port bitcell through a first read port and selecting, in a first multiplexer, an output of the inverter in response to detecting the first absence of a collision; and selecting, in the first multiplexer, in response to detecting the first collision, a data output bit resulting from a differential read through a write port to the multi-port bit cell.

12. 12. The method of claim 11, further comprising triggering the comparison of the first read port address and the write port address in response to an edge of a clock signal.

13. comparing a second read port address to the write port address to detect a second collision in response to the second read port address matching the write port address and to detect no second collision in response to the second read port address not matching the write port address; selecting, in a second multiplexer, in response to detecting the second absence of a collision, a complementary data output bit resulting from a single-ended read into the multi-port bit cell through a second read port; and selecting, in the second multiplexer, a complementary data output bit resulting from the differential read through the write port to the multi-port bit cell in response to detecting the second collision.

14. precharging a first bit line at the first read port prior to comparing the first read port address to the write port address; in response to said detecting said first collision, floating said first bit line; and in response to the detection of the absence of the first collision, maintaining the precharge of the first bit line; asserting a precharge signal in response to detecting the absence of a first collision, the floating of the first bit line being in response to asserting the precharge signal; further comprising switching off a transistor coupled between the first bit line and a power supply node for a power supply voltage in response to the assertion of the precharge signal; 12. The method of claim 11, further comprising: in response to the detection of the first collision, maintaining the precharge signal deasserted to maintain the transistor in an on state.

15. 12. The method of claim 11, further comprising the step of latching a data output bit from the first multiplexer.

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