Write Masked Latch Bit Cell
JP2024516394A5Active Publication Date: 2025-04-14ADVANCED MICRO DEVICES INC
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Patent Information
- Application Number
- JP2023565477
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2021-06-25
- Filing Date
- 2022-05-05
- Publication Date
- 2025-04-14
- Estimated Expiration
- 2042-05-05
AI Technical Summary
Technical Problem
8T static random access memory (SRAM) arrays have not scaled well in area within newer technology nodes, and existing SRAM bit cells face inefficiencies in write operations, leading to increased area overhead and performance issues.
Method used
Implementing a write masked latch bit cell with a write mask circuit and keeper circuit to control data states during writes, using standard cell design rules to reduce area and improve efficiency by enabling selective writing and maintaining data integrity.
Benefits of technology
The write masked latch bit cell reduces area overhead and improves write efficiency by allowing selective writing and maintaining data integrity, while utilizing standard cell design rules to scale with newer technology nodes.
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Abstract
The SRAM write masked latch bitcell includes a write mask circuit that forces the value of the write data node to a first value in response to assertion of a first write mask signal and forces the value of the write data node to a second value in response to assertion of a second write mask signal. A pass gate provides data on the write data node to an internal node of the bitcell in response to a write word line signal being asserted. A keeper circuit maintains the value of the first node regardless of the value of the write word line signal while the first write mask signal and the second write mask signal are deasserted.
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