Conformal titanium silicon nitride based thin films and methods for forming same

Abstract

The disclosed technology relates generally to the formation of titanium nitride-based thin films, and more particularly to conformal, smooth titanium nitride-based thin films and methods of forming same. In one aspect, a method of forming a diffusion barrier comprising TiSiN includes exposing a semiconductor substrate to one or more first deposition phases alternating with one or more second deposition phases. Exposing the semiconductor substrate to the one or more first deposition phases includes exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor alternating. Exposing the semiconductor substrate to the one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor successively, with no N precursor therebetween, and subsequently exposing the semiconductor substrate to an N precursor.

Description

[Technical field]

[0001] Any or all applications for which a foreign or domestic priority claim is identified in an Application Data Sheet filed with this application are hereby incorporated by reference pursuant to 37 CFR 1.57.

[0002] This application is a continuation-in-part of U.S. application Ser. No. 16 / 595,916, entitled "CONFORMAL TITANIUM NITRIDE-BASED THIN FILMS AND METHODS OF FORMING THE SAME," filed on October 8, 2019, and claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Application No. 63 / 171,970, entitled "CONFORMAL TITANIUM NITRIDE-BASED THIN FILMS AND METHODS OF FORMING THE SAME," filed on April 7, 2021, and claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Application No. 63 / 172,002, entitled "CONFORMAL TITANIUM NITRIDE-BASED THIN FILMS AND METHODS OF FORMING THE SAME," filed on April 7, 2021. This application claims priority to "NITRIDE-BASED THIN FILMS AND METHODS OF FORMING THE SAME," the contents of each of which are expressly incorporated herein by reference in their entireties.

[0003] The disclosed technology relates generally to the formation of titanium nitride-based thin films, and more particularly to conformal, smooth titanium nitride-based thin films. [Background technology]

[0004] Titanium nitride (TiN) based thin films have been widely used in the fabrication of various structures within integrated circuits (ICs). For example, TiN has been used in diffusion barriers, various electrodes, and metallization structures. Such widespread use of TiN in IC fabrication can be attributed to its structural, thermal, and electrical properties. As the size of various IC structures shrinks, TiN is formed on features with ever-decreasing sizes and complex topologies. For example, as technology nodes scale beyond the 10 nm node, there is a need for thin films, e.g., diffusion barriers, that can conformally line high aspect ratio trenches and vias with sizes as small as a few nanometers. Techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) have been used in the IC industry to form TiN diffusion barriers, but the increasing need for conformality of TiN films deposited in smaller trenches and vias may ultimately limit their use. While atomic layer deposition (ALD) has demonstrated conformal films of TiN films, some electrical (e.g., electrical conductivity) and physical (e.g., surface roughness) properties of the films may be inferior to TiN films formed using other methods, such as physical vapor deposition (PVD). Thus, there is a need for deposition methods for forming TiN-based films with superior properties, including barrier properties, surface smoothness, and step coverage, compared to TiN films formed by, for example, PVD and CVD, in IC manufacturing. Summary of the Invention [Means for solving the problem]

[0005] In one embodiment, a method of forming a diffusion barrier comprising TiSiN includes exposing a semiconductor substrate to one or more alternating and non-overlapping first and one or more second deposition phases, wherein exposing the semiconductor substrate to the one or more first deposition phases includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor with no intervening exposure to an N precursor, and subsequently exposing the semiconductor substrate to an N precursor.

[0006] In another aspect, a method of forming a diffusion barrier comprising TiSiN includes exposing a semiconductor substrate to one or more alternating and non-overlapping first and one or more second deposition phases, wherein exposing the semiconductor substrate to the one or more first deposition phases includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor.

[0007] In another aspect, a method of forming a diffusion barrier comprising TiSiN includes exposing a semiconductor substrate to one or more alternating and non-overlapping first and one or more second deposition phases, wherein exposing the semiconductor substrate to the one or more first deposition phases includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor for a Ti precursor exposure time, followed by a silicon (Si) precursor for a Si precursor exposure time, followed by a N precursor. The ratio of the Si precursor exposure time to the Ti precursor exposure time is between 2 and 130.

[0008] In another aspect, a method of forming a diffusion barrier comprising TiSiN includes exposing a semiconductor substrate to one or more alternating and non-overlapping first and one or more second deposition phases, wherein exposing the semiconductor substrate to the one or more first deposition phases includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor, a silicon (Si) precursor, and a N precursor. Exposing the semiconductor substrate to one or more of a Ti precursor, a Si precursor, and a N precursor during the one or more second deposition phases includes undersaturating a major surface of the semiconductor substrate.

[0009] In another aspect, a method includes forming a diffusion barrier comprising TiSiN having an elastic modulus greater than 290 GPa and a Si content greater than 2.7 atomic % by alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. Exposing the semiconductor substrate to one or more first deposition phases includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor.

[0010] In another aspect, a method includes forming a diffusion barrier comprising TiSiN having a hardness greater than 20 GPa and a Si content greater than 2.7 atomic % by alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases, wherein exposing the semiconductor substrate to the one or more first deposition phases includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor.

[0011] In another aspect, a method includes exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases to form a diffusion barrier comprising TiSiN having a crystalline texture such that a ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in a grazing incidence x-ray diffraction spectrum of the diffusion barrier is greater than 0.4, and a Si content greater than 2.7 atomic %. Exposing the semiconductor substrate to one or more first deposition phases includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor.

[0012] In another aspect, a method includes forming a diffusion barrier comprising TiSiN having a nanocrystalline structure with an average grain size less than about 6.5 nm and a Si content greater than 2.7 atomic % by alternatingly exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. Exposing the semiconductor substrate to one or more first deposition phases includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor.

[0013] In another aspect, a semiconductor structure includes a semiconductor substrate having a plurality of trenches or vias thereon, the trenches or vias having dielectric sidewall surfaces and an aspect ratio greater than 5. A diffusion barrier layer comprising TiSiN conformally lines the surfaces of the trenches or vias, the diffusion barrier layer having a Si content of 2.7-9 atomic % and an elastic modulus of 290-350 GPa.

[0014] In another aspect, a semiconductor structure includes a semiconductor substrate having a plurality of trenches or vias thereon, the trenches or vias having dielectric sidewall surfaces and an aspect ratio greater than 5. A diffusion barrier layer comprising TiSiN conformally lines the surfaces of the trenches or vias, the diffusion barrier layer having a Si content of 2.7-9 atomic % and a hardness of 20-40 GPa.

[0015] In another aspect, a semiconductor structure includes a semiconductor substrate having a plurality of trenches or vias thereon, the trenches or vias having dielectric sidewall surfaces and an aspect ratio greater than 5. A diffusion barrier layer comprising TiSiN conformally lines the surfaces of the trenches or vias, the diffusion barrier layer having a Si content of 2.7-9 atomic % and a crystalline texture such that the ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in a grazing incidence x-ray diffraction spectrum is 0.4-4.5.

[0016] In another aspect, a semiconductor substrate includes a semiconductor substrate having a plurality of trenches or vias thereon, the trenches or vias having dielectric sidewall surfaces and an aspect ratio greater than 5. A diffusion barrier layer comprising TiSiN conformally lines the surfaces of the trenches or vias, the diffusion barrier layer having a Si content of 2.7-9 atomic % and a nanocrystalline structure with an average grain size of about 5.0-6.5 nm.

[0017] Embodiments of the present disclosure will now be described, by way of non-limiting example, with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0018] [Figure 1] 1A-1D show schematic diagrams of different nucleation and growth mechanisms of thin films under different growth modes. [Diagram 2] FIG. 2 is a cross-sectional transmission electron micrograph of a TiN layer grown by atomic layer deposition on a silicon substrate having a topography. [Diagram 3] FIG. 3 illustrates a schematic cross-sectional view of a semiconductor structure having a thin film including TiSiN or TiAlN formed on a semiconductor substrate, according to an embodiment. [Figure 4] FIG. 4 shows a schematic cross-sectional view of a via lined with a thin film comprising TiSiN or TiAlN having different thicknesses in different parts of the via. [Figure 5A] FIG. 5A is a flow diagram illustrating a method of forming a thin film comprising TiSiN or TiAlN, according to an embodiment. [Figure 5B]FIG. 5B is a flow diagram illustrating a deposition cycle for forming a thin film comprising TiSiN or TiAlN, according to an embodiment. [Figure 5C] FIG. 5C illustrates a deposition cycle for forming a thin film including TiSiN or TiAlN, according to an embodiment. [Figure 5D] FIG. 5D illustrates a sequence of deposition cycles for forming a thin film including TiSiN or TiAlN, according to an embodiment. [Figure 6A] FIG. 6A shows a cross-sectional transmission electron micrograph and corresponding selected area diffraction pattern obtained from a thin film including TiSiN lining the top of a high aspect ratio via, according to an embodiment. [Figure 6B] FIG. 6B shows a cross-sectional transmission electron micrograph and corresponding selected area diffraction pattern obtained from a thin film including TiSiN lining a middle portion of the high aspect ratio via shown in FIG. 6A, according to an embodiment. [Figure 6C] FIG. 6C shows a cross-sectional transmission electron micrograph and corresponding selected area diffraction pattern obtained from a thin film including TiSiN lining the bottom of the high aspect ratio via shown in FIGS. 6A and 6B, according to an embodiment. [Figure 7A] FIG. 7A shows a selected area diffraction pattern obtained from a substantially amorphous thin film including TiSiN lining a high aspect ratio, according to an embodiment. [Figure 7B] FIG. 7B shows a selected area diffraction pattern obtained from a partially crystalline thin film including TiSiN lining a high aspect ratio, according to an embodiment. [Figure 7C] FIG. 7C shows a selected area diffraction pattern obtained from a substantially crystalline thin film including TiSiN lining a high aspect ratio, according to an embodiment. [Figure 8] FIG. 8 shows a grazing incidence x-ray diffraction spectrum obtained from a substantially amorphous thin film including TiSiN, according to an embodiment. [Figure 9] FIG. 9 is a graph of experimentally measured resistivity as a function of silicon content in thin films including TiSiN, according to an embodiment. [Figure 10A] FIG. 10A is a cross-sectional transmission electron micrograph obtained from a substantially homogeneous thin film including TiSiN, according to an embodiment. [Figure 10B] FIG. 10B is a cross-sectional transmission electron micrograph taken from a nanolaminate thin film including alternating regions or layers of SiN and TiN, according to an embodiment. [Figure 11] FIG. 11 illustrates a schematic cross-sectional view of a portion of a semiconductor device having contact or metal lines formed by filling holes lined with a thin film comprising TiSiN or TiAlN with a metal, according to an embodiment. [Figure 12] FIG. 12 is a cross-sectional transmission electron micrograph of an ultra-thin TiN layer grown by atomic layer deposition on a substrate having topography. [Figure 13] FIG. 13 is a flow diagram illustrating a vapor deposition cycle for forming a thin film comprising TiSiN, according to some embodiments. [Figure 14] FIG. 14 is a flow diagram illustrating a vapor deposition cycle for forming a thin film comprising TiSiN, according to an embodiment. [Figure 15] FIG. 15 is a flow diagram illustrating a vapor deposition cycle for forming a thin film comprising TiSiN, according to an embodiment. [Figure 16] FIG. 16 is a flow diagram illustrating a vapor deposition cycle for forming a thin film comprising TiSiN, according to an embodiment. [Figure 17] FIG. 17 is a flow diagram illustrating a vapor deposition cycle for forming a thin film comprising TiSiN, according to some embodiments. [Figure 18A] FIG. 18A is a graph of experimentally measured Si content of TiSiN thin films, plotted as a function of the ratio of the number of first deposition phases to the number of second deposition phases. [Figure 18B] FIG. 18B is a graph of experimentally measured grazing incidence X-ray diffraction spectra of TiSiN thin films, with different curves corresponding to TiSiN thin films having different ratios of the number of first deposition phases to the number of second deposition phases. [Figure 18C] FIG. 18C is a graph of experimentally measured electrical resistivity from TiSiN thin films measured for the Si content shown in FIG. 18A. [Figure 19] 19A-19B are graphs of experimentally measured electrical resistivity as a function of Ti exposure time during the second deposition phase of the deposition cycle shown in FIG. 17, with exposure times to dichlorosilane as the Si precursor fixed at 60 s and 90 s, respectively. [Figure 20] 20A-20C are cross-sectional transmission electron micrographs taken from high aspect ratio structures lined with TiSiN thin films formed using different Ti exposure times in the second deposition phase of the deposition cycle shown in FIG. 17. [Figure 21] 21A-21C are graphs of experimentally measured electrical resistivity as a function of Ti exposure time in the second deposition phase of the deposition cycle shown in FIG. 17, where the exposure times to dichlorosilane as the Si precursor are fixed at 3.5 s, 30 s, and 90 s, respectively. [Figure 22] 22A-22C are cross-sectional transmission electron micrographs taken from high aspect ratio structures lined with TiSiN thin films formed using different Ti exposure times in the second deposition phase of the deposition cycle shown in FIG. 17. [Figure 23] 23A-23B are graphs of experimentally measured electrical resistivity as a function of Ti exposure time during the second deposition phase of the deposition cycle shown in FIG. 17, where the exposure times to dichlorosilane as the Si precursor are fixed at 5 s and 30 s, respectively. [Figure 24] 24A-24B are cross-sectional transmission electron micrographs taken from high aspect ratio structures lined with TiSiN thin films formed using different Ti exposure times in the second deposition phase of the deposition cycle shown in FIG. 17. [Diagram 25] 25A and 25B are low-resolution and high-resolution cross-sectional transmission electron micrographs obtained from a high aspect ratio structure lined with a thin TiSiN film. [Figure 26A] FIG. 26A is a flow diagram illustrating a method for forming a nanolaminate thin film according to some embodiments. [Figure 26B] FIG. 26B is a flow diagram illustrating a method of forming a nanolaminate thin film using a vapor deposition cycle similar to that shown in FIG. 13, according to some embodiments. [Figure 26C] FIG. 26C is a flow diagram illustrating a method of forming a nanolaminate thin film using a vapor deposition cycle similar to that shown in FIG. 17, according to some embodiments. [Figure 27A] FIG. 27A is a graph of experimentally measured electrical resistivity for various nanolaminate thin films deposited according to the methods illustrated in FIGS. 26A and 26C, according to some embodiments. [Figure 27B] FIG. 27B is a graph of experimentally measured grazing incidence x-ray diffraction spectra measured from various nanolaminate thin films deposited according to the methods illustrated in FIGS. 26A and 26C, according to some embodiments. [Figure 28] 28A and 28B are cross-sectional transmission electron micrographs taken from high aspect ratio structures lined with nanolaminate thin films, according to some embodiments. [Figure 29] FIG. 29 is a flow diagram illustrating a vapor deposition cycle for forming a thin film comprising TiSiN, according to some embodiments. [Diagram 30] FIG. 30 is a graph illustrating the tunability of the Si content of TiSiN thin films by adjusting the precursor exposure time and / or the ratio of the number of first and second deposition phases, according to some embodiments. [Diagram 31] 31A-31I are grazing incidence X-ray diffraction spectra (XRD) of experimentally measured TiSiN thin films, according to an embodiment. [Diagram 32] FIG. 32 is a graph showing the ratio (R) of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks as a function of Si content measured from TiSiN thin films, according to an embodiment. [Diagram 33] FIG. 33 is a graph of estimated average nanocrystalline grain size as a function of Si content calculated from the measured grazing incidence X-ray diffraction spectra (XRD) of FIGS. 31A-31I. [Diagram 34] FIG. 34 is a graph of hardness values ​​as a function of Si content measured on TiSiN thin films, according to an embodiment. [Diagram 35] FIG. 35 is a graph of elastic modulus values ​​as a function of Si content for TiSiN thin films, according to an embodiment. [Diagram 36] FIG. 36 shows low-resolution and high-resolution cross-sectional transmission electron micrographs obtained from a high aspect ratio structure lined with a TiSiN thin film, according to an embodiment. [Figure 37A] FIG. 37A is an atomic force microscope image of a deposited TiSiN thin film, according to an embodiment. [Figure 37B] FIG. 37B is an atomic force microscope image of a TiN thin film as a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] As discussed above, there is a need in the integrated circuit (IC) industry for conformal thin films, e.g., TiN-based thin films, with good physical barrier properties and methods for forming such thin films. To address these and other needs, disclosed herein are thin films comprising TiSiN and / or TiAlN, which may be at least partially amorphous, and cyclic vapor deposition methods, which may be atomic layer deposition (ALD), for forming such thin films. The thin films exhibit the conformality of ALD-deposited films, while also having barrier properties that are better than or comparable to those of existing physical vapor deposition (PVD) and chemical vapor deposition (CVD)-deposited TiN films. The thin films comprising TiSiN and / or TiAlN may be used as conformal diffusion barriers. The thin films are formed by methods adapted for substrates with relatively large areas due to the presence of topography, e.g., holes in dielectrics, such as vias and trenches, which may be vias and trenches with high aspect ratios (e.g., >1), where the exposed surface area is at least twice as dense as the planar substrate surface area. The method includes exposing a semiconductor substrate to one or more vapor deposition cycles at relatively high pressures (e.g., >1 Torr), where the vapor deposition cycles include exposure to a titanium (Ti) precursor, a nitrogen (N) precursor, and one or both of a silicon (Si) precursor or an aluminum (Al) precursor. Thin films comprising TiSiN and / or TiAlN deposited by the methods disclosed herein advantageously have excellent conformality, step height coverage, and low surface roughness while having excellent diffusion barrier properties. These and other properties of the thin films can be advantageously tuned by controlling the morphology of the thin films at the nanoscale to vary the degree of crystallinity and / or homogeneity by adjusting process conditions.

[0020] As described herein, compounds referred to by their constituent elements without specific stoichiometric ratios are understood to include all possible non-zero concentrations of each element unless expressly limited. For example, titanium nitride (TiN) has the general formula Ti xThis definition is understood to encompass all possible stoichiometric and non-stoichiometric compositions of titanium nitride that can be expressed as Ti, N, x>0, including TiN, Ti3N4, Ti4N3, Ti6N5, Ti2N, and TiN2, as well as other non-stoichiometric compositions of Ti and N. Similarly, silicon nitride (SiN) has the general formula Si y It is understood to include all possible stoichiometric and non-stoichiometric compositions of silicon nitride that can be expressed by N, y>0, including Si3N4. Aluminum nitride (AlN) has the general formula Al y It is understood to include all possible stoichiometric and non-stoichiometric compositions of aluminum nitride that can be expressed as N, y>0, including AlN. Titanium silicon nitride (TiSiN) has the general formula Ti x S y It is understood that the term "titanium silicon nitride" encompasses all possible stoichiometric and non-stoichiometric compositions of titanium silicon nitride that can be expressed by the formula Ti, x>0, and y>0. Titanium aluminum nitride (TiAlN) has the general formula Ti x Al y It is understood to encompass all possible stoichiometric and non-stoichiometric compositions of titanium aluminum nitride that can be expressed by N, x>0, and y>0.

[0021] As mentioned above, titanium nitride based thin films play an important role in integrated circuit (IC) manufacturing. While techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) have been used to deposit TiN in the IC industry, there is an increasing need for deposition methods to form TiN based films, e.g., ternary or quaternary alloys containing Ti, N and one or more additional metals, including Si and / or Al, with high conformality without significant loss of electrical and / or physical properties.

[0022] In addition, while plasma-enhanced processes such as plasma-enhanced atomic layer deposition (PE-ALD) can be effective in forming conformal films on surfaces with relatively low aspect ratios, they may not be effective in depositing films inside vias or cavities with high aspect ratios. Without being bound by any theory, one possible reason for this is that under certain circumstances, the plasma may not reach the deep portions of high aspect ratio vias. In such circumstances, different portions of the via may be exposed to different amounts of plasma, which can lead to undesirable structural effects resulting from non-uniform deposition. For example, a thicker film may be deposited near the opening of the via compared to deeper portions (often referred to as cush or keyhole formation). For these reasons, thermally cycled vapor deposition such as thermal ALD may be more advantageous because these thermal processes do not rely on the ability of the plasma to reach each portion of the surface to be deposited.

[0023] However, while thermal ALD techniques can be suitable for forming relatively conformal TiN-based thin films over topographies, particularly over topographies having relatively high aspect ratios (e.g., greater than 1:1), the inventors have recognized that TiN-based thin films formed by thermal ALD may be inferior in some respects to TiN-based thin films formed by PVD or CVD, for example in terms of film roughness and electrical resistivity. In this regard, the inventors have found that some electrical and / or physical properties of ALD grown TiN-based films may be adversely affected by the mode of growth. In particular, the inventors have found that while it may be desirable to grow TiN-based films in a two-dimensional layer-by-layer growth mode in ALD, such a layer-by-layer growth mode may not be readily achievable in some circumstances. The inventors have further found that growing TiN-based thin films by ALD in a layer-by-layer growth mode poses particular challenges in IC manufacturing when forming TiN-based thin films on non-metallic surfaces, particularly insulating surfaces such as oxide and nitride surfaces or doped and undoped silicon surfaces. Without being bound by any theory, the inventors have recognized that the degree to which TiN-based thin films can be grown in a layer-by-layer growth mode can depend on the initial growth mode, which in turn depends on the type and crystallinity of the surface, as disclosed herein with reference to Figures 1A-1D.

[0024] FIG. 1A shows a schematic representation of the nucleation of a TiN-based layer, and FIGS. 1B-1D show different growth modes of a TiN-based layer on different surfaces. With reference to FIG. 1A, once the precursor molecules 104 reach the substrate 100, they are physically adsorbed on the substrate. Some of the adsorbed molecules 104 can diffuse along the surface of the substrate 100 until they reach energetically favorable positions where they are chemisorbed. Surface diffusion is governed by, among other things, the substrate temperature, the substrate material, and the kinetic energy of the adsorbed molecules. When the size of the nuclei formed by the chemisorbed molecules exceeds a certain size (sometimes called the "critical size"), determined by a trade-off between the volume free energy and the surface energy, the nuclei become energetically stable and can start to grow in size. The layer 108 of stable nuclei thus formed continues to grow by incorporating further precursor molecules 104. The subsequent film growth can be classified according to different growth modes, as shown diagrammatically in FIGS. 1B-1D.

[0025] 1B shows a schematic diagram of a three-dimensional island growth mode, sometimes referred to as the Volmer-Weber growth mode, in which a layer 112 of three-dimensional islands is formed. Without being bound by any theory, the island growth mode may dominate when the net surface free energy associated with the three-dimensional islands is positive, indicating that the deposited atoms are more strongly bound to each other than to the substrate. It will be appreciated that, for example, when a metallic TiN-based layer is deposited on a given semiconductor and / or insulating material surface, the energetics of the ALD growth of the TiN-based layer favors the island growth mode.

[0026] 1C shows a layer-by-layer growth mode, sometimes referred to as the Frank-van der Merwe growth mode, which results in the formation of a relatively smooth two-dimensional layer 116. Without being bound by any theory, the layer-by-layer growth mode may dominate when the deposited atoms are more strongly bonded to the substrate than to each other, making a stable two-dimensional layer 116 energetically favorable. The layer-by-layer growth mode may be sustained when the bond energy between the layers decreases continuously from the initial monolayer of the TiN-based layer to the value of the bulk crystal.

[0027] 1B and 1C are two different possible growth modes of TiN-based thin films, although under certain circumstances, growth modes intermediate between the layer-by-layer and three-dimensional growth modes are possible. FIG. 1D shows an example of an intermediate growth mode known as the Stranski-Krastanov (SK) growth mode. Without being bound by any theory, the SK growth mode can occur in thin film growth that starts with the layer-by-layer growth mode. If, after the formation of one or more monolayers, the layer-by-layer growth mode becomes unfavorable, the island growth mode starts and becomes dominant over the layer-by-layer growth mode, resulting in a thin film structure 120 in which three-dimensional islands are formed on top of a two-dimensional initial layer. The SK growth mode can occur as a strain relaxation mechanism (strain-induced roughening).

[0028] In addition to the interaction between the deposited material and the substrate, other factors such as substrate temperature, pressure, and deposition rate can have a significant effect on the nucleation and initial growth process, which in turn affects the final nano- or microstructure of the resulting thin film. For example, deposition at a relatively high substrate temperature and / or a slow deposition rate may promote the growth of relatively large grains, while a relatively low substrate temperature and a fast deposition rate may favor the growth of smaller grains.

[0029] It has been discovered that when TiN-based thin films are grown by ALD on a variety of intended surfaces, dielectric and semiconductor surfaces, in IC manufacturing, the ALD growth can be initiated in a three-dimensional island growth mode or an SK growth mode. For example, under given circumstances, ALD growth of TiN-based thin films on substrate surfaces including doped and undoped Si, SiO2, Si3N4, and other high-K or low-K materials can proceed in an island growth mode or an SK growth mode. The inventors have found that, in part, due to the initial growth mode, either the island growth mode or the SK growth mode, the subsequent growth of TiN-based layers by ALD often results in undesirable film morphology in a variety of applications of ultra-thin conformal diffusion barriers for high aspect ratio structures, such as that shown in FIG. 2.

[0030] FIG. 2 is a cross-sectional transmission electron micrograph of a TiN layer grown by thermal ALD on a topography that includes an insulating (Si3N4) surface. After initial film growth in either 3D island or SK growth modes, ALD growth of TiN is often characterized by competitive growth of adjacent crystals with different orientations. This results in V-shaped grains near the nucleation layer under certain circumstances, leading to a columnar morphology at larger film thicknesses. As shown in FIG. 2, the resulting film morphology includes cut-end columnar heads that result in high surface roughness, and columnar boundaries that are less dense than the grains. It can be seen that the columnar boundaries may have significantly poorer diffusion barrier properties compared to the grains themselves, and may act as paths of least resistance to transport undesired contaminants through the TiN layer. Furthermore, the columnar morphology may require the deposition of a relatively thick TiN layer to observe sufficient diffusion barrier properties. Thus, an effective TiN barrier for acceptable overall contact or line conductivity may become too thick, leaving little room for low resistivity filler materials such as W or Cu.

[0031] The inventors have found that when thin films comprising at least partially amorphous TiSiN and / or TiAlN are formed on non-metallic surfaces by thermal cyclic vapor deposition processes such as thermal ALD, the 3D or SK growth mode can be substantially suppressed and the layer-by-layer growth mode can be promoted. Among other reasons, this is believed to be because when the TiN-based thin film has Si or Al added as an alloying element and / or an amorphous phase is present therein, the nuclei may wet the non-metallic surface with a relatively low contact angle. The resulting thin film covers a relatively large area of ​​the non-metallic surface and island formation is reduced, for example because the growth of the thin film tends to proceed more favorably in a layer-by-layer growth mode on the substrate surface. As mentioned above, TiN-based thin films usually prefer the 3D island or SK growth mode on substrates in ALD. Thus, unlike TiN layers grown by ALD directly on some non-metallic surfaces, which tend to be dominated by columnar growth as described above, thin films including at least partially amorphous TiSiN and / or TiAlN formed on non-metallic surfaces according to embodiments tend to be dominated by a layer-by-layer growth mode, resulting in higher conformality and surface smoothness. Furthermore, the presence of the amorphous phase reduces grain boundaries, thereby suppressing fast diffusion paths for some elements such as Cu and W. The presence of the amorphous phase, higher conformality, and / or surface smoothness can reduce the thickness of the diffusion barrier. When formed for lining high aspect ratio vias or trenches, the thinner thickness allows for larger pores for subsequent metal filling of the vias or trenches for the formation of contact vias and / or reduced contact resistance.

[0032] 3 shows a schematic cross-sectional view of a semiconductor structure 300 having a thin film 320 comprising TiSiN and / or TiAlN that can be formed using the methods according to various embodiments disclosed herein. The semiconductor thin film structure 300 includes a substrate 310, e.g., a semiconductor substrate. The substrate 310 includes a non-metallic surface, e.g., a dielectric and / or semiconductor surface, on which a thin film 320 comprising at least partially amorphous TiSiN and / or TiAlN is formed by the methods disclosed herein. The thin film 320 has excellent conformality, step coverage, and low surface roughness while having excellent diffusion barrier properties. These and other properties of the thin film can be advantageously tailored by controlling the degree of crystallinity and / or homogeneity of the thin film at the nanoscale, which in turn can be tailored by tailoring various process conditions as disclosed herein.

[0033] Although the TiSiN and / or TiAlN comprising thin films are shown in Figure 3 as being formed on a flat substrate for clarity, embodiments are not so limited. Thin films comprising TiSiN and / or TiAlN have particular advantages when formed on substrates having topography, such as substrates having high aspect ratio (e.g., >1) vias and trenches and / or a relatively high density of features, thereby providing a relatively large surface area (e.g., more than twice the surface area of ​​a flat substrate) exposed to precursors during cyclic vapor deposition, e.g., ALD.

[0034] One measure of conformality in the context of high aspect ratio structures is referred to herein and in the industry as step coverage. A high aspect ratio structure can be, for example, a via, hole, trench, hole, cavity, or similar structure. As an illustrative example, FIG. 4 shows a schematic of a semiconductor structure 400 having an example high aspect ratio structure 416 formed therein, thereby illustrating some exemplary metrics for defining and / or measuring the conformality of a thin film formed on the high aspect ratio structure. The illustrated high aspect ratio structure 416 has an inner surface lined with a thin film 412, for example a thin film including TiSiN and / or TiAlN having different thicknesses in different portions. As mentioned above, a high aspect ratio structure has an aspect ratio, for example the ratio of the depth or height (H) divided by the width (W) in the hole region of the high aspect ratio structure 416, which is greater than 1. In the illustrated example, the high aspect ratio structure 416 is a via formed through a dielectric layer 408, e.g., an inter-layer dielectric (ILD) layer formed on the semiconductor material 404. In the illustrated example, the bottom surface of the high aspect ratio structure 416 exposes the underlying semiconductor substrate 404. The thin film 412 can coat different surfaces of the high aspect ratio structure 416 with different thicknesses. As discussed above, step coverage can be defined as the ratio between the thickness of the thin film at the bottom or bottom region of the high aspect ratio structure and the thickness of the thin film at the top or top region of the high aspect ratio structure. The top or top region can be a region of the high aspect ratio structure that is relatively shallow, e.g., 0-10% or 0-25% deep, measured from the top surface of the hole. The bottom or bottom region can be a region of the high aspect ratio structure that is relatively deep, e.g., 90-100% or 75-100% deep, measured from the top surface of the hole. In some high aspect ratio structures, step coverage can be defined or measured by the ratio of the thickness of the thin film 412A formed on the bottom surface to the thickness of the thin film 412C formed on the top or upper sidewall surfaces of the high aspect ratio structure. However, it will be appreciated that some high aspect ratio structures may not have a well-defined bottom surface or a bottom surface with a small radius of curvature.In such structures, step coverage can be more consistently defined or measured by the ratio of the thickness of the thin film 412A formed on the bottom surface to the thickness of the thin film 412C formed on the top or upper sidewall surface in a high aspect ratio structure.

[0035] [Cyclic vapor deposition of thin films containing TiSiN and / or TiAlN] 5A shows a flow diagram of a method 500 for forming a thin film comprising TiSiN and / or TiAlN, according to an embodiment. The method 500 includes providing 510 a substrate. The substrate can be a flat semiconductor substrate, or a semiconductor substrate having a surface topography such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the unpatterned semiconductor substrate is greater than 2, as described above. The surface topography that results in a relatively large surface area can be a plurality of holes, such as trenches or vias, formed on the substrate, as described above. The holes can have a dielectric sidewall surface and an aspect ratio greater than 5.

[0036] The method 500 further includes forming 520 a thin film capable of functioning as a diffusion barrier comprising titanium silicon nitride (TiSiN) or titanium aluminum nitride (TiAlN). The thin film is formed by exposing the semiconductor substrate to multiple vapor deposition cycles at a pressure in a reaction chamber greater than 1 Torr, where the vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

[0037] As described above and throughout the specification, it will be understood that the semiconductor substrate on which the thin film, e.g., diffusion barrier layer, comprising TiSiN and / or TiAlN is formed can be implemented as a variety of substrates, including, but not limited to, doped semiconductor substrates, including Group IV elemental materials (e.g., Si, Ge, C, or Sn) or alloys formed from Group IV materials (e.g., SiGe, SiGeC, SiC, SiSn, SiSnC, GeSn, etc.); Group III-V compound semiconductor materials (e.g., GaAs, GaN, InAs, etc.) or alloys formed from Group III-V materials; Group II-VI semiconductor materials (CdSe, CdS, ZnSe, etc.) or alloys formed from Group II-VI materials.

[0038] According to certain embodiments, the substrate may also be implemented as a semiconductor on insulator, such as a silicon-on-insulator (SOI) substrate. SOI substrates typically include a silicon-insulator-silicon structure in which the various structures described above are insulated from a supporting substrate using an insulator layer, such as a buried SiO2 layer (BOX). It will be further understood that the various structures described above may be formed at least in part in an epitaxial layer formed at or near the surface region.

[0039] With further reference to FIG. 5A, it will be appreciated that the method 500 may be performed on a substrate processed by a front-end line and may include various devices, such as, for example, transistors. Additionally, the semiconductor substrate may include one or more various structures preformed thereon, such as, for example, diffusion regions, insulating regions, electrodes, and metallization structures, such as contacts and metal lines, on which the method 500 may be performed. Thus, a diffusion barrier comprising TiSiN and / or TiAlN may be formed on various topographical structures, including vias, cavities, holes, or trenches. Surfaces on which a diffusion barrier comprising TiSiN and / or TiAlN may be formed according to embodiments include metal surfaces, such as surfaces of metallization structures; semiconductor surfaces, such as doped or undoped Si surfaces; and / or dielectric surfaces, such as inter-layer dielectric (ILD) surfaces, mask or hard mask surfaces, or gate dielectric surfaces.

[0040] According to certain embodiments, when formed as a diffusion barrier, the thin film including TiSiN and / or TiAlN can be interposed between a dielectric layer, e.g., an interlayer dielectric (e.g., 408 in FIG. 4), and a metallization structure formed by filling a via or trench (e.g., 416 in FIG. 4), and / or between the semiconductor substrate 404 and a metallization structure formed by filling a via or trench, thereby acting as a diffusion barrier therebetween, among other functions, such as electrical contact. In these embodiments, the dielectric material can be any dielectric material used in integrated circuit fabrication, such as silicon oxide, silicon nitride, high-k dielectrics or low-k dielectrics, etc. The metallization structure can include metal lines, contact structures, or other conductive structures formed of metal or metallic materials for electrically connecting the underlying semiconductor material 404, e.g., a diffusion region, to other parts of the integrated circuit device being fabricated. The metallization structure can include metal lines, contact structures, or other conductive structures made of metal or metallic materials for electrically connecting the underlying semiconductor material 404, e.g., a diffusion region, to other parts of the integrated circuit device being fabricated. The metallization structure may be formed from any suitable metal or metallic material, including, for example, metals including Al, Cu, Ni, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, and titanium silicide; and conductive metal oxides including RuO2, and the like.

[0041] 5A, the method 500 of forming a thin film, e.g., a diffusion barrier layer, further includes forming a thin film comprising TiSiN and / or TiAlN by exposing the semiconductor substrate to multiple vapor deposition cycles, which may be atomic layer deposition (ALD) cycles, in a reaction chamber 520. The vapor deposition cycles include one or more exposures to a titanium (Ti) precursor, one or more exposures to a nitrogen (N) precursor, and one or more exposures to one or both of a silicon (Si) precursor or an aluminum (Al) precursor. At least one of the vapor deposition cycles may be performed under a pressure in the reaction chamber greater than about 1 Torr.

[0042] As stated above and throughout the specification, a reaction chamber refers to any reaction chamber including a single wafer processing reaction chamber or a batch wafer processing reaction chamber suitably configured for cyclic vapor deposition, which may be atomic layer deposition (ALD), e.g., thermal cyclic vapor deposition or ALD. In a thermal cyclic vapor deposition or ALD reaction chamber, a substrate may be placed on a suitable base, such as a susceptor or carrier boat. The substrate may be directly heated by thermal conduction from a heated susceptor, or indirectly heated by radiation from a radiation source, such as a lamp, or by convection from heated chamber walls.

[0043] Generally, in a cyclic vapor deposition or ALD process, reactants or precursors, e.g., an oxidation reactant and a reduction reactant, are alternately introduced into a reaction chamber having a substrate disposed therein. The introduction of one or more reactants or precursors may be alternated with a purge and / or pumping step to remove excess reactants or precursors from the reaction chamber. The reactants may be introduced into the reaction chamber for a suitable period of time and under predetermined conditions such that the surface on which the diffusion barrier is to be deposited is exposed to the reactants. Thereby, the surface of the substrate may become at least partially saturated with the precursors or reactants and / or with the reaction products of the reactants. The excess or remaining precursors or reactants may then be purged and / or pumped out of the reaction chamber. The pumping step may be performed by a suitable vacuum pumping step, and the purging step may be performed by introducing a non-reactive or inert gas, e.g., nitrogen or a noble gas, into the reaction chamber. There are other techniques to prevent reactants that react with each other from mixing in the gas phase.

[0044] FIG. 5B is a flow diagram and FIGS. 5C and 5D are block diagrams illustrating a method of forming a diffusion barrier comprising TiSiN and / or TiAlN, according to an embodiment. FIG. 5C illustrates a deposition phase including exposure to a precursor and a cycle including exposure to a deposition phase. FIG. 5D illustrates a sequence of cycle deposition phases as part of multiple cycles. With reference to FIGS. 5B-5D, in various embodiments, exposing a semiconductor substrate to one or more vapor deposition cycles, which may be ALD cycles 520 (FIG. 5A), includes exposing the substrate to one or more first vapor deposition phases ("first deposition phases") 525, where at least one first deposition phase includes exposure to a Ti precursor and exposure to a N precursor. Exposing the semiconductor substrate to one or more vapor deposition cycles, which may be ALD cycles 520 (FIG. 5A), further includes exposing the substrate to one or more second vapor deposition phases ("second deposition phases") 530, where at least one second deposition phase includes exposure to Si and / or Al precursors, or a combination of exposure to Si and / or Al precursors and an additional N precursor. One or more first deposition phases and one or more second deposition phases can be combined to form a cycle, which can be repeated in sequence, multiple times or multiple cycles. Different cycles can have the same or different numbers of first and second deposition phases. The combination of exposing the substrate to one or more first deposition phases 525 and exposing the substrate to one or more second deposition phases 530 results in a diffusion barrier layer that includes a layer or region of TiSiN and / or TiAlN. Each of exposing the substrate to one or more first deposition phases 525 and exposing the substrate to one or more second deposition phases 530 can include, in sequence, exposing the individual precursors one or more times, such as in a pulsed manner, as described below.

[0045] 5B-5D, in various embodiments, exposing the substrate to each of one or more first deposition phases 525 can include exposing the substrate to one or more Ti precursors and one or more N precursors. Each exposure to a Ti precursor is performed such that the surface of the substrate on which the diffusion barrier is to be deposited is exposed to the Ti precursor. The surface can thereby become substantially fully or partially saturated with the Ti precursor. After exposing the substrate to the Ti precursor, excess or residual Ti precursor or its reaction products that have not been retained on the surface of the substrate by physisorption or chemisorption can be removed from the substrate surface, such as by pumping or purging the process chamber. Similarly, each exposure to the N precursor is performed such that the surface of the substrate on which the diffusion barrier is deposited is exposed to the N precursor, thereby allowing the surface to become substantially fully or partially saturated with the N precursor. After the substrate is exposed to the N precursor, excess or residual N precursor or its reaction products that are not retained on the surface of the substrate by physisorption or chemisorption can be removed from the substrate surface, such as by pumping or purging the process chamber. The substrate can be exposed to one or more first deposition phases, each comprising one or more exposures to Ti precursors and one or more exposures to N precursors, to locally form one or more monolayers or regions formed substantially from deposited TiN.

[0046] In some embodiments, the exposure to the Ti precursor in a given first deposition phase can be performed multiple times in succession. Similarly, the exposure to the N precursor in a given first deposition phase can be performed multiple times in succession. Advantageously, under certain circumstances, exposing the substrate to the Ti and / or N precursor more than once can result in a higher level of surface saturation by exposing more reactive sites for adsorption or reaction of the individual precursors, for example when large steric hindrance effects are present.

[0047] 5B-5D, in various embodiments, exposing the substrate to one or more second deposition phases 530 includes exposing the substrate to one or more Si or Al precursors. Each exposure to the Si and / or Al precursors is performed such that the surface of the substrate on which the diffusion barrier is to be deposited is exposed to the Si and / or Al precursors. The surface can thereby be substantially fully or partially saturated with the Si and / or Al precursors. After exposing the substrate to the Si and / or Al precursors, excess or residual Si and / or Al precursors or reaction products thereof that have not been retained on the substrate surface by physisorption or chemisorption can be removed from the substrate surface, such as by pumping or purging the process chamber. Exposing the substrate to one or more second deposition phases, each of which includes one or more exposures to the Si and / or Al precursors, can locally form one or more monolayers or regions formed substantially from the deposited Si or Al.

[0048] In some embodiments, multiple successive exposures to the Si and / or Al precursors in a given second deposition phase can be performed. Advantageously, under certain circumstances, exposing the substrate to the Si and / or Al precursors more than once can result in a higher level of surface saturation by exposing more reactive sites for adsorption or reaction of the individual precursors, for example when large steric hindrance effects are present.

[0049] 5B-5D, in some embodiments, exposing the substrate to each of one or more second deposition phases 530 includes exposing the substrate to Si and / or Al precursors one or more times and further exposing the substrate to N precursors one or more times. The N precursors can be the same or different from the N precursors of the first deposition phase. Each exposure to the Si and / or Al precursors is performed such that the surface of the substrate on which the diffusion barrier is to be deposited is exposed to the Si and / or Al precursors. The surface can thereby be substantially fully or partially saturated with the Si and / or Al precursors. After exposing the substrate to the Si and / or Al precursors, excess or residual Si and / or Al precursors or reaction products thereof that have not been retained on the surface of the substrate by physisorption or chemisorption can be removed from the substrate surface, such as by pumping or purging the process chamber. Each exposure to the N precursor is performed such that the surface of the substrate on which the diffusion barrier is to be deposited is exposed to the N precursor, thereby allowing the surface to be substantially fully or partially saturated with the N precursor. After the substrate is exposed to the N precursor, excess or residual N precursor or its reaction products that have not been retained on the surface of the substrate by physisorption or chemisorption can be removed from the substrate surface, such as by pumping or purging the process chamber. The substrate can be exposed to one or more second deposition phases, each comprising one or more exposures to a Si precursor and one or more exposures to a N precursor, to locally form one or more monolayers or regions formed substantially from deposited SiN or AlN.

[0050] In some embodiments, multiple successive exposures to the Si precursor in a given second deposition phase can be performed. Similarly, multiple successive further exposures to the N precursor can be performed. Advantageously, under certain circumstances, exposing the substrate to the Si and / or Al and / or N precursors more than once as described above can result in a higher level of surface saturation by exposing more reactive sites for the adsorption of the individual precursors, for example when large steric hindrance effects are present.

[0051] It will be appreciated that in various embodiments, the number of cycles each comprising one or both of the first and second deposition phases, the frequency and number of repetitions of the first deposition phase and the frequency and number of repetitions of the second deposition phase, the frequency and number of repetitions of exposure of the substrate to Ti precursors and N precursors during the first deposition phase, and the frequency and number of repetitions of exposure of the substrate to Si and / or Al precursors or Si and / or Al precursors and N precursors during the second deposition phase, as described above, can be varied based on a variety of considerations, including the susceptibility of the precursors to steric hindrance effects, to obtain the desired thickness, stoichiometry, and other properties, as described above, in the resulting diffusion barrier layer comprising TiSiN and / or TiAlN.

[0052] 5B-5D, depending on the circumstances or film properties desired, it may be advantageous to initiate deposition of the diffusion barrier comprising TiSiN and / or TiAlN by one or the other of exposing the substrate to a first or second deposition phase. For example, the inventors have found that first exposing the substrate to one or more second deposition phases (Si and / or Al precursors or N precursors) 530, followed by exposing the substrate to the first deposition phase (Ti precursor or N precursor) 525, may be particularly advantageous in promoting a layer-by-layer growth mode of the diffusion barrier, thereby improving conformality and reducing surface roughness, for example when the substrate surface has a non-metallic surface that is an insulating surface, such as the sidewalls of a trench or via formed in an interlayer dielectric (ILD) layer, or a semiconductor surface, such as a Si diffusion region.

[0053] However, embodiments are not so limited, and in other embodiments, first exposing the substrate 525 to one or more first deposition phases (Ti precursor or N precursor) and then exposing the substrate 530 to one or more second deposition phases (Si and / or Al precursor or N precursor) may be more advantageous, for example, to maintain good conformality and surface roughness while lowering contact resistance, for example when the substrate surface includes a metal surface (e.g., W, Al, or Cu metal metallization).

[0054] 5D, under some circumstances, depending on the sequence described above, the sequence of the first and second deposition phases may result in a thin film having regions appreciably enriched in TiN and Si and / or Al or SiN and / or AlN, however, under other circumstances, as will be described below, the resulting thin film may be substantially homogenous TiSiN and / or TiAlN despite different sequences of exposure to the first and second deposition phases.

[0055] In various embodiments, non-limiting examples of Ti precursors for forming thin films, e.g., diffusion barrier layers or regions, include titanium tetrachloride (TiCl4), tetrakis(dimethylamino)titanium (TDFMAT), or tetrakis(diethylamino)titanium (TDEAT).

[0056] In various embodiments, non-limiting examples of N precursors for forming thin films, e.g., diffusion barrier layers or regions, include ammonia (NH), hydrazine (N2H4), or monomethylhydrazine (CH3(NH)NH2, "MMH"). As noted above, different N precursors can be used for the first and second deposition phases, and entirely different precursors can be used in different cycles of the same phase.

[0057] In various embodiments, non-limiting examples of inert gases for purging include nitrogen, N2, or a noble gas, such as Ar.

[0058] In some embodiments, the Si precursor for forming the diffusion barrier layer can be a hydride precursor. Examples of hydride precursors include silane (SiH4) and disilane (Si2H6). In some other embodiments, the Si precursor for forming the diffusion barrier can be a chlorine-containing precursor, such as a silicon chloride or a chlorosilane. Examples include silicon tetrachloride (SiCl4), monochlorosilane (SiH3Cl, "MCS"), dichlorosilane (SiH2Cl2, "DCS"), trichlorosilane (SiHCl3), hexachlorodisilane (Si2Cl6, "HCDS"), and octachlorotrisilane (Si3Cl8, "OCTS"). The inventors have found that a diffusion barrier layer comprising TiSiN can be desirably formed using silicon and chlorine-containing Si precursors when a higher level of saturation of the surface with the precursor is desired, due to the lower steric hindrance compared to organosilicon precursors under a wide range of conditions.

[0059] In some embodiments, the Al precursor for forming the diffusion barrier layer can be an organometallic precursor. Examples of organometallic precursors include trimethylaluminum ("TMA"), triisobutylaluminum, and tris(dimethylamido)aluminum. In some other embodiments, the Al precursor for forming the diffusion barrier layer can be a chlorine-containing Al precursor, for example, AlCl3.

[0060] Without being bound by any theory, the inventors have found that these Si and Al precursors, when introduced as the first non-nitrogen precursor, can be particularly advantageous for promoting a layer-by-layer growth mode of TiSiN or TiAlN layers compared to other Si or Al precursors. The layer-by-layer growth mode is obtained by improving the wetting of the substrate surface by the nuclei of the TiSiN or TiAlN layer in the early stages of growth, which can be characterized by a small contact angle between the nuclei and the substrate surface. As a result of the layer-by-layer growth mode, improved conformality and reduced surface roughness can be achieved, which can be particularly advantageous for forming diffusion barriers with small size high aspect ratio depositions. Furthermore, without being bound by any theory, chlorine-containing Si and / or Al precursors can enable more precise control of the composition in the growth direction by suppressing or self-limiting adsorption.

[0061] To achieve various advantages disclosed herein, for example to function as an effective diffusion barrier, thin films including TiSiN and / or TiAlN, according to embodiments, can have thicknesses not exceeding about 25 nm, 20 nm, 15 nm, 10 nm, 7 nm, 4 nm, 2 nm, 1 nm, or having a value within a range defined by any of these values ​​or values ​​other than these values, which can be substantially less than TiN barriers with similar effectiveness as diffusion barriers.

[0062] To achieve various advantages disclosed herein, e.g., to function as an effective diffusion barrier, thin films comprising TiSiN and / or TiAlN, according to embodiments, can be formed at substrate temperatures of 250°C-300°C, 300°C-400°C, 350°C-400°C, 400°C-450°C, 450°C-500°C, 500°C-550°C, 550°C-600°C, 600°C-650°C, or a value within a range defined by any of these values, e.g., about 400°C.

[0063] To achieve the various advantages disclosed herein, for example to act as an effective diffusion barrier, the exposure times or pulse durations of the various precursors, according to embodiments, are between about 0.1-5 seconds, 5-10 seconds, 10-20 seconds, 20-30 seconds, 30-40 seconds, 40-50 seconds, 50-60 seconds, or durations within a range defined by any of these values ​​or greater.

[0064] In summary, the formation of a thin film, e.g., a diffusion barrier layer, comprising TiSiN and / or TiAlN includes exposing a substrate to one or more cycles, each cycle including one or more first deposition phases and / or one or more second deposition phases. Each of the first deposition phases includes, in sequence, alternating exposure to one or more Ti precursors and one or more N precursors. In some embodiments, each of the second deposition phases includes, in sequence, alternating exposure to one or more Si precursors and / or Al precursors and one or more N precursors. The resulting diffusion barrier layer includes a layer or region of TiSiN or a layer or region of TiAlN. In various embodiments, the frequency and number of exposures of the substrate to each of the Ti precursors, N precursors, and Si and / or Al precursors, as well as the frequency and number of exposures of the substrate to each of the cycles, first deposition phases, and second deposition phases, and the sequence of exposure can be adjusted to obtain a desired stoichiometry, thickness, and crystallinity, as described herein.

[0065] Deposition on substrates with large surface area and / or high aspect ratio structures The inventors have found that when a substrate has a relatively large surface area, e.g., resulting from a relatively large areal density of high aspect ratio structures, coating the exposed surface with a thin film using an ALD process recipe developed based on characterization of thin films formed on flat or unpatterned substrates or substrates with a relatively small surface area or density of high aspect ratio structures can result in a thin film having different properties at different portions of the exposed surface. For example, the conformality and step coverage discussed above can be significantly worse in high aspect ratio structures on substrates with a relatively large areal density. Other properties that can also be different at different portions of the exposed surface include film stoichiometry, surface roughness, electrical resistivity, and film density. Without being bound by any theory, one reason for the less uniform properties can be due to the significantly increased exposed surface area of ​​the substrate compared to a flat substrate. Due to the increased exposed surface area, different portions of the exposed surface can receive different magnitudes of precursor fluxes, which can result in different amounts of precursor adsorbing on different portions of the exposed surface. In just a simple example, a 330mm semiconductor substrate may have hundreds of dies formed on it, each measuring 1×10 10 For example, if a substrate has a deep trench or via with a diameter of 10-100 nm and one or more vias with aspect ratios of 1-100, the surface area exposed to the precursor during deposition of the thin film may exceed the surface area of ​​the corresponding unpatterned substrate by 10, 100, 1000 or more times. Furthermore, the local deposition conditions at different portions of the exposed surface may be different. For example, the local pressure inside a deep trench or via may be different, e.g., lower, compared to the area outside the deep trench or via. Furthermore, under vacuum conditions, gas molecules collide more with the sidewalls of the trench or via, and therefore the upper portion of the deep trench or via may adsorb more precursor molecules due to exposure to a greater flux.

[0066] In various embodiments described herein, the inventors have found that the deposition methods disclosed herein are particularly advantageous in forming thin films comprising TiSiN and / or TiAlN that have greater uniformity over different portions of an exposed surface with respect to various physical properties, including conformality, step coverage, film stoichiometry, surface roughness, electrical resistivity, film density, etc. Thus, thin films comprising TiSiN and / or TiAlN formed by the deposition methods disclosed herein have greater uniformity with respect to one or more of these physical properties, both at a local (e.g., within a trench or via) and global (e.g., within a wafer) level. Thus, deposition methods according to embodiments are particularly advantageous for forming thin films comprising TiSiN and / or TiAlN on substrates having a surface topography whereby the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2, 5, 10, 20, 50, 100, 200, 500, 1000, or within a range defined by any one or more of these values.

[0067] Alternatively or additionally, the deposition method according to the embodiment is further particularly advantageous in forming a thin film on a substrate comprising high aspect ratio structures with an opening width within a range defined by 1 micron, 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, or any of these values ​​or less, an aspect ratio exceeding a value within a range defined by these values ​​of 5, 10, 20, 50, 100, 200, or any of these values, and an areal density such that the surface area is greater than that of the flat substrates described above. Substrates with such topography can be conformally coated with a thin film comprising TiSiN and / or TiAlN according to the embodiment, in which case the step coverage as defined above has a value greater than 50%, 60%, 70%, 80%, 90%, 95%, or within a range defined by any of these values ​​or more. As discussed above, the inventors have found that process conditions for conformally coating substrates having a relatively large areal density of high aspect ratio structures can be optimized in embodiments to achieve these results. The inventors have found that these results can be achieved by controlling, among other things, the reaction chamber pressure or partial pressure of the precursor during exposure of the substrate, the deposition rate, the temperature or partial pressure of the precursor introduced to the reaction chamber, the flow rate of the precursor, and the exposure time.

[0068] The inventors have found that when coating substrates having a relatively large areal density of high aspect ratio structures according to embodiments, a relatively high total or partial pressure can result in improved conformality and step coverage. Without being bound by any theory, such improvements may be related, inter alia, to reducing the effect of locally low precursor partial pressures inside high aspect ratio vias or trenches. 5B and 5C, during exposure 525 of the substrate to one or more first deposition phases (Ti precursor and / or N precursor) and / or during exposure 530 of the substrate to one or more second deposition phases (Si and / or Al precursor and / or N precursor), the total or partial pressure of any individual precursor can be 1.0-3.0 Torr, 3.0-5.0 Torr, 5.0-7.0 Torr, 7.0-9.0 Torr, 9.0-11.0 Torr, 11.0-13.0 Torr, 13.0-15.0 Torr, or a pressure within a range defined by any of these values. During each exposure to Ti precursor, N precursor, and / or Si and / or Al precursor, the individual precursor can comprise 1-2%, 2-5%, 5-10%, 10-20%, 20-50%, 50-100%, or a percentage within a range defined by any of these values ​​of the total amount of gas molecules in the reaction chamber. The inventors have found that, under given circumstances, if the total or partial pressures are outside of these values, among other things, step coverage may begin to degrade.

[0069] According to embodiments, a relatively high total or partial pressure can be controlled during exposure of the substrate to one or more first deposition phases 525 (Ti precursor and / or N precursor) and / or during exposure of the substrate to one or more second deposition phases 530 (Si and / or Al precursor and / or N precursor) in conjunction with the flow rates of the individual precursors and inert gases and the pumping capacity of the reaction chamber to provide a relatively high deposition rate per first and / or second deposition phase of 0.20-0.30 Å / deposition phase, 0.30-0.40 Å / deposition phase, 0.40-0.50 Å / deposition phase, 0.50-0.60 Å / deposition phase, 0.60-0.70 Å / deposition phase, 0.70-0.80 Å / deposition phase, or a value within a range defined by any of these values.

[0070] The inventors have found, in part, that to allow for a relatively high throughput while providing a relatively large amount of precursor to the reaction chamber for deposition at a relatively high total or partial pressure, the flow rate of the precursor into the reaction chamber should be much higher than the flow rate used for process conditions forming thin films on flat substrates or substrates with low (e.g., <1) aspect ratio structures. The high flow rate can be achieved by increasing one or both of the temperature or pressure of the precursor prior to introduction into the reaction chamber. For example, for precursors in liquid form under manufacturing conditions, the precursor bottle can be heated to a temperature above room temperature, e.g., 30-60°C, 60-80°C, 80-100°C, 100-120°C, 120-150°C, or a temperature within a range defined by any of these values, to increase the rate of vapor generation. Bottle temperatures below or above these ranges can be determined, in part, based on the vapor pressure of the precursor and the decomposition temperature of the precursor, respectively. By way of example, TiCl4 is heated to about 60-80°C. On the other hand, high flow rates can be achieved by increasing the gas line pressure to increase the delivery pressure for precursors in gaseous form under manufacturing conditions to values ​​much higher than the gas line pressures used to form thin films on substrates with relatively small or flat areas and / or low (e.g., <1) aspect ratio structures. It will be appreciated that the relatively high flow rates at which the various advantages described herein can be obtained may depend, among other things, on pumping speed, exposure time, and reactor volume. To achieve flow rates suitable for depositing thin films on substrates with large surface areas and / or high aspect ratio structures, flow rates of each of the Ti, N, Si, and Al precursors may be, for example, between 100 and 1000 standard cm 3 The temperature and / or pressure of the precursor, among others, can be adjusted to be within a range defined by, for example, 1000-2000 sccm, 2000-5000 sccm, 5000-10000 sccm, 10000-15000 sccm, 15000-20000 sccm, or any of these values ​​or greater. It will be appreciated that the appropriate flow rate may depend, among other things, on the volume of the reactor, and that some of these flow rates are suitable for a single wafer reactor having a volume of about 1-2 liters.

[0071] 6A-6C show experimental transmission electron microscope (TEM) images of conformal TiSiN films lining high aspect ratio vias formed by the deposition techniques described herein. The high aspect ratio vias have a deposited silicon oxide surface. FIGS. 6A, 6B, and 6C are TEM images taken of the top, middle, and bottom of TiSiN films formed in vias having an aspect ratio of about 40, respectively. In each of FIGS. 6A-6C, the left image is a bright field image of each portion of the high aspect ratio via, and the right image shows the selected area diffraction (SAD) pattern obtained from the film formed on each portion of the high aspect ratio via, using an electron beam with a spot diameter comparable to the thickness of the TiSiN film. Unlike the polycrystalline TiN shown in FIG. 2, which has a rough surface due to columnar growth, the bright field TEM images in FIGS. 6A-6C show that the deposited TiSiN is much smoother and more conformal. The inventors have found that these and other improvements can be attributed, in part, to the presence of at least some amorphous phases of TiSiN, which may be present along with some nanocrystalline layers of TiSiN, as shown by the SAD patterns. The TiSiN thin films are substantially amorphous and conformal throughout substantially the entire via depth, with good step height coverage (~60%).

[0072] [Control of thin film morphology at the nanoscale] Advantageously, the ability to control precursor adsorption at the sub-monolayer level using various process parameters described herein allows the various embodiments of the cyclic vapor deposition process, which may be an ALD process, disclosed herein to control and improve the film morphology and structure of thin films comprising TiSiN and / or TiAlN at the nanoscale. The controlled morphology and structure include the degree of crystallinity, homogeneity, and surface roughness. In particular, the inventors have found that the degree of crystallinity and / or homogeneity at the nanoscale can be advantageously controlled in thin films comprising TiSiN and / or TiAlN by controlling various parameters of the exposure cycle as described herein.

[0073] In various embodiments, when forming a thin film, e.g., a diffusion barrier layer, comprising TiSiN and / or TiAlN, in addition to the various parameters described above, a specific ratio of the number of times the substrate is exposed to a first deposition phase (including a combination of exposure to a Ti precursor and an N precursor) to the number of times the substrate is exposed to a second deposition phase (including a combination of exposure to a Si and / or Al precursor or a combination of exposure to a Si and / or Al precursor and an N precursor) can be used to control the thin film morphology. The ratio can be about 1:30 to 1:15, 1:15 to 1:6, 1:6 to 1:3, 1:3 to 1:2, 1:2 to 2:3, 2:3 to 5:6, 5:6 to 1:1, 1:1 to 6:5, 6:5 to 3:2, 3:2 to 2:1, 2:1 to 3:1, 3:1 to 6:1, 6:1 to 15:1, 15:1 to 30:1, or a ratio within a range defined by any of these values. For example, the ratio may be any of the following: 2:3, 3:2, 5:4, 7:3, 7:5, 7:1, 10:1, and 15:1. Alternatively, the exposure to the Ti precursor and the Si and / or Al precursor can have these ratios. Under the combination of process conditions described herein to form a diffusion barrier comprising TiSiN and / or TiAlN, the ratio of exposure to the first deposition phase to the second deposition phase is such that Si or Al is present in the diffusion barrier at an average concentration greater than about 3%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or a value within a range defined by any of these values, based on the total number of atoms in the diffusion barrier.

[0074] The inventors have found that by controlling the ratio of the number of times the substrate is exposed to the first deposition phase (i.e., Ti precursor) and the number of times the substrate is exposed to the second deposition phase (i.e., Si or Al precursor), the crystallinity of the resulting TiSiN and / or TiAlN-containing thin film can be continuously tuned, as shown in Figures 7A-7C. Figures 7A-7C show selected area diffraction (SAD) patterns obtained from conformal thin films containing TiSiN deposited on the sidewalls of high aspect ratio vias at different crystallinity levels, similar to those shown in Figures 6A-6C. Figures 7A-7C show SAD patterns of a substantially completely amorphous TiSiN thin film, a partially amorphous TiSiN thin film, and a substantially polycrystalline or nanocrystalline TiSiN thin film, respectively. It will be appreciated that the presence of nanocrystalline or polycrystalline domains and the quantitative degree of crystallinity can be determined from the location and relative sharpness of the diffraction spots and / or rings that can be indexed to the (111), (200) and (220) crystal planes of crystalline TiSiN as shown in FIG. 7C. For example, a SAD pattern dominated by diffuse rings can be associated with substantially amorphous TiSiN, while a SAD pattern dominated by spots can be associated with substantially polycrystalline TiSiN with domain sizes comparable to the limited field of view used to obtain the SAD pattern. SAD patterns of nanocrystalline and amorphous phase TiSiN can include a mixture of both diffuse rings and spots. The inventors have found that, among other things, an increase in the proportion of the amorphous phase contributes to improved smoothness, conformality and step coverage of TiSiN thin films.

[0075] 8 is a grazing incidence X-ray diffraction pattern of a blanket TiSiN layer formed on a substantially completely amorphous Si substrate, according to an embodiment. The measured TiSiN layer is similar to the TiSiN layer imaged in the SAD patterns of FIG. 7A and FIG. 6A-6C. The lack of distinct crystallographic peaks attributable to crystalline phases in the TiSiN layer indicates that the TiSiN layer is substantially completely amorphous.

[0076] As described herein, the relative crystallinity of thin films comprising TiSiN and / or TiAlN can be tailored to optimize various material properties, such as, for example, diffusion barrier properties. In some circumstances, a low degree of crystallinity may be preferred, for example, to reduce grain boundaries, which can inhibit diffusion of a given element through the thin film and improve smoothness. However, in other circumstances, a high degree of crystallinity may be preferred, for example, to reduce the electrical resistivity of the thin film. FIG. 9 is a graph of experimentally measured resistivity as a function of silicon content for TiSiN-containing thin films according to the embodiment. The graph shows that the resistivity of TiSiN thin films can be tuned over a wide range of values ​​by adjusting the relative Si content (atomic %) in the film. In turn, the tuning can also be achieved by adjusting the number of exposures to the Si precursor in the cyclic vapor deposition or ALD cycles. The inventors have found that at relatively low Si contents, the resistivity of the TiSiN layer increases relatively slowly as a function of Si content, while at relatively high Si contents, the resistivity increases relatively quickly as a function of Si content. The inventors have found that the relatively fast increase in resistivity as a function of Si content generally coincides with the onset 910 of the appearance of an amorphous layer of TiSiN, which was experimentally verified by transmission electron microscopy as described above. It will be appreciated that the onset 910 and the electrical resistivity may depend, among other things, on the deposition temperature and the precursors used. As described above, it may be desirable to have more than about 10% Si to form an at least partially amorphous TiSiN layer. As a result, the resistivity may be increased while the overall thickness may be reduced compared to a fully crystalline layer such as a TiN layer.

[0077] Thus, in situations where a thin film having relatively high diffusion barrier properties and / or relatively low surface roughness is advantageous, it is advantageous to be able to tailor the composition of the electrode layer such that the thin film comprising TiSiN and / or TiAlN is at least partially amorphous. In such embodiments, the thin film may be substantially entirely amorphous or may comprise nanocrystalline regions surrounded by an amorphous matrix. For example, the electrode may comprise one or more TiSi / TiAl, TiN, and TiAlN / TiSiN nanocrystals in an amorphous matrix comprising Ti, Al / Si, and N. In the illustrated embodiment, the starting point 910 at about 1600 μΩ·cm corresponds to an average atomic concentration of Si of about 10%. However, in other embodiments, depending on the deposition conditions and precursors used, the starting point may correspond to an average atomic concentration of Si of about 10%, 15%, 20%, or 25%, or a value within a range defined by any of these values. Alternatively, starting point 910 corresponds to a ratio of the number of exposures of the substrate to one or more first deposition phases (each including a combination of exposure to a Ti precursor and exposure to an N precursor, and no exposure to a Si and / or Al precursor) to one or more second deposition phases (each including exposure to a Si and / or Al precursor or a combination of exposure to a Si and / or Al precursor and an N precursor) that is between 1:1 and 2:1, between 2:1 and 3:1, between 3:1 and 6:1, between 6:1 and 15:1, between 15:1 and 30:1, or a ratio within a range defined by any of these values. Alternatively, these ratios can represent the ratio of the number of exposures to a Ti precursor to the number of exposures to an N precursor.

[0078] The composition of the thin film including TiSiN and / or TiAlN can be tailored to have an electrical resistivity of <1000 μΩ·cm, 1000-2000 μΩ·cm, 2000-300 μΩ·cm, 3000-4000 μΩ·cm, 4000-5000 μΩ·cm, 5000-6000 μΩ·cm, 6000-7000 μΩ·cm, 7000-8000 μΩ·cm, 8000-9000 μΩ·cm, 9000-10000 μΩ·cm, or ≧10000 μΩ·cm, or a value within a range defined by any of these values.

[0079] In addition to the degree of crystallinity, the inventors have found that the degree of nanoscale homogeneity can also be controlled by controlling the number of exposures to the first deposition phase and / or the number of exposures to the second deposition phase. In some circumstances, the sequence of the first and second deposition phases can be controlled to form thin films having TiN and Si and / or Al or SiN and / or AlN rich regions or layers, such as nanolaminates that include alternating TiN rich regions or layers with Si and / or Al rich regions or layers or SiN / AlN rich regions or layers. In some other circumstances, despite different sequences of exposure to the first and second deposition phases, the resulting thin film may be a substantially homogeneous TiSiN and / or TiAlN thin film, as described below. An example is shown with reference to Figures 10A and 10B. Figure 10A shows a TEM image of a substantially homogeneous TiSiN layer, while Figure 10B shows a TEM image of a TiSiN layer in the form of a nanolaminate that includes alternating TiN-rich and SiN-rich regions or layers.

[0080] In various embodiments, when forming a thin film including, for example, TiSiN and / or TiAlN, which is a diffusion barrier layer, to form a substantially homogeneous layer, as shown in FIG. 10A, the number of successive runs of the first and / or second deposition phases can be less than about 50, 30, 25, 20, 15, 10, 5, or a value within a range defined by any of these values ​​when the film is deposited at the temperatures described above. The thin film can have a nanolaminate structure when the number of successive runs of the first and / or second deposition phases exceeds these values. It will be understood that the number of successive runs of the first and / or second deposition phases to form a substantially homogeneous or laminate structure can depend on various factors, including temperature, pressure, and precursors used. For example, at relatively high temperatures, homogeneous composition can prevail due to enhanced diffusion mixing of atoms. In contrast, at relatively low temperatures, nanolaminate formation can prevail due to weakened diffusion mixing of atoms.

[0081] The inventors have found that advantageously, when thin films comprising TiSiN and / or TiAlN are formed according to the embodiments disclosed herein, the surface roughness may also be reduced compared to other diffusion barrier materials such as TiN or TiSiN formed using other techniques such as CVD or PVD. The reduced surface roughness is particularly advantageous compared to other materials or techniques when the surface on which the diffusion barrier is deposited includes non-metallic surfaces such as dielectric surfaces and / or semiconductor surfaces exposed by holes such as vias or trenches. The deposited diffusion barriers having the thicknesses described above can have a root mean square (RMS) surface roughness within a range defined by 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, and 5%, or any of these values ​​or less. Alternatively, a diffusion barrier having the thicknesses described above as deposited may have a root-mean-square (RMS) surface roughness of less than 0.5 nm, 0.4 nm, 0.3 nm, 0.2 nm, 0.1 nm, or a value within a range defined by any of these values ​​or less. Reduced RMS roughness may in turn improve the conformality of the diffusion barrier layer.

[0082] [Application] The TiSiN or TiSiN-containing thin films formed using the various process parameters according to the various embodiments disclosed herein can be used in a variety of applications, particularly where the substrate comprises a topography having relatively large areas, relatively high aspect ratio structures, and / or non-metallic surfaces that can benefit from the various advantageous properties disclosed herein. Exemplary applications include deposition for lining vias, holes, trenches, cavities, or similar structures having an aspect ratio, e.g., a ratio defined as the depth divided by the width of the top surface, that exceeds 1, 2, 5, 10, 20, 50, 100, 200, or a value within a range defined by any of these values.

[0083] FIG. 11 illustrates one exemplary application of the concept of forming a diffusion barrier for a contact structure, such as a source or drain contact, formed on an active semiconductor substrate region, which may be heavily doped. A portion of a semiconductor device 1100 is shown including a material 1104 on which a dielectric layer 1108, such as an interlayer dielectric (ILD) layer, including a dielectric material such as silicon oxide or silicon nitride, is formed. Vias or trenches may be formed through the dielectric layer 1108 to form contacts to various regions of the substrate 1104, including various doped regions, such as source and drain regions. The vias or trenches may expose various non-metallic surfaces, such as an exposed bottom surface, including a substrate surface, such as a silicon substrate surface, and dielectric sidewalls of the via. The bottom and side surfaces of the via may then be conformally coated with a thin film including TiSiN and / or TiAlN in a manner similar to that shown in FIGS. 6A-6C, according to various embodiments described herein. The lined via may then be filled with a more conductive material, such as a metal or metal alloy, such as W, Al, or Cu, among others, to form a contact plug 1116. For example, the vias can be filled with tungsten by CVD using WF6 or the like.

[0084] The barrier layer 1112 formed according to the embodiment may be advantageous for various reasons as described above. In addition, the conformal nature of the barrier layer 1112 can significantly reduce pinching during the subsequent metal filling process. Furthermore, as described above, the barrier layer 1112 can effectively prevent cross-transport of materials such as dopant (B, P) out-diffusion and reactant, etchant, and metal (such as F, Cl, W, or Cu) in-diffusion from the substrate 1104 during the contact plug formation process. The barrier effect may be enhanced by reduced surface roughness, improved step coverage, partially amorphous morphology (which may be partially nanocrystalline), and / or homogeneous / nano-laminate morphology. These advantageous effects can be achieved at a smaller thickness compared to TiN thin films. Furthermore, as described above, the layer-by-layer growth mode can reduce the overall contact resistance of the barrier layer 1112.

[0085] Other applications of thin films comprising TiSiN and / or TiAlN formed according to various embodiments disclosed herein include a variety of conductive structures such as recessed substrates (such as buried electrodes or lines), electrodes (such as DRAM capacitor electrodes or gate electrodes), higher metal level metallization barriers (such as barriers in vias / trenches for Cu contacts / lines), high aspect ratio vertical rod electrodes or vias for 3D memory, and through silicon vias (TSVs), to name a few.

[0086] [TiSiN film deposition including Ti surface treatment before Si precursor exposure] Various embodiments described herein address the need for improved diffusion barriers for industrial use, such as the TiN-based diffusion barriers described above with respect to Figure 2. As discussed above, low resistivity and high step coverage, among other properties, of TiSiN-containing thin films are desirable in many applications, such as forming diffusion barriers lining electrodes and / or high aspect ratio vias and trenches. As discussed above, the process conditions, such as those described with respect to Figures 5A-5D, can be optimized, among other things, to conformally coat substrates having a relatively large areal density of high aspect ratio structures, by controlling the reaction chamber pressure or partial pressure of precursors during deposition, the deposition rate, the temperature or pressure of precursors introduced to the reaction chamber, the flow rate of precursors, and exposure time.

[0087] In addition to the above-mentioned improvements offered by TiSiN over other diffusion barrier materials such as TiN, the inventors have found that TiSiN may offer another advantage for advanced technology nodes. FIG. 12 shows a cross-sectional transmission electron micrograph of an ultra-thin TiN layer grown by atomic layer deposition on a substrate having a topography. The inventors have found that even when grown by atomic layer deposition, ultra-thin (e.g., <5 nm) TiN layers may not continuously cover the underlying surface and may have discontinuities. Such discontinuities may limit the effectiveness of the TiN layer as a diffusion barrier. In contrast, the inventors have found that when deposited under certain deposition conditions described herein, TiSiN provides continuous and uniform coverage even down to these ultra-thin sizes, e.g., less than 5 nm, which may be particularly important in applications in ultra-thin diffusion barriers for advanced technology nodes. As described herein, to enhance step coverage and / or reduce electrical resistivity of TiSiN films, the inventors have found alternative and / or further improved methods of the various methods described above, for example with respect to FIGS. 5A-5D. In particular, in the alternative or further improved methods described herein, the semiconductor substrate is exposed to one or more first deposition phases and one or more second deposition phases in alternating and non-overlapping fashion. In that case, exposing the semiconductor substrate to one or more first deposition phases includes exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor in alternating fashion. And exposing the semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor. That is, in the second deposition phase, exposure to the Ti precursor precedes exposure to the Si precursor, and exposure to the Si precursor is followed by exposure to the N precursor. This alternative method further reduces roughness and enhances layer-by-layer growth, thereby maintaining the continuity of the TiSiN film even at ultra-thin (e.g., <5 nm) sizes. In addition, the inventors have found that this method allows for more precise control of Ti incorporation even when one or more precursors are undersaturated at the substrate surface during growth. As a result, the inventors have found that this method allows for significant reductions in resistivity values ​​and enhanced stability of resistivity values.

[0088] FIG. 13 is a flow diagram illustrating a method of forming a thin film comprising TiSiN, similar to that described above with respect to FIGS. 5B-5D. The method of depositing a thin film comprising TiSiN includes exposing 525 a semiconductor substrate to one or more (m) first deposition phases and exposing 530 the semiconductor substrate to one or more (n) second deposition phases. Each of the first deposition phases includes multiple alternating exposures to a Ti precursor and a N precursor, and each of the second deposition phases includes multiple alternating exposures to a Si precursor and a N precursor. Further details of the method illustrated in FIG. 13 are described above with respect to FIGS. 5B-5D, and those details will not be repeated here for brevity.

[0089] 14-16 show an alternative or further improved method of forming a diffusion barrier comprising TiSiN, where resistivity can be reduced with less variability due to further improvements in roughness and continuity at ultra-thin thicknesses and precise control of Ti content.

[0090] 14 is a flow diagram illustrating a method of forming a diffusion barrier comprising TiSiN, according to an embodiment. The method includes step 1402 of alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. In the method, exposing the semiconductor substrate to one or more first deposition phases 1404 includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. In the method, exposing the semiconductor substrate to one or more second deposition phases 1406 includes sequentially exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor with no intervening exposure to an N precursor therebetween, and then exposing the semiconductor substrate to an N precursor.

[0091] 15 is a flow diagram illustrating a method of forming a diffusion barrier comprising TiSiN according to another embodiment. The method includes step 1502 of alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. In the method, exposing the semiconductor substrate to one or more first deposition phases 1504 includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. In the method, exposing the semiconductor substrate to one or more second deposition phases 1506 includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor.

[0092] 16 is a flow diagram illustrating a method of forming a diffusion barrier comprising TiSiN according to another embodiment. The method includes step 1602 of alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. In the method, exposing the semiconductor substrate to one or more first deposition phases 1604 includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. In the method, exposing the semiconductor substrate to one or more second deposition phases 1606 includes exposing the semiconductor substrate to a Ti precursor for a Ti precursor exposure time, followed by a silicon (Si) precursor for a Si precursor exposure time, followed by a N precursor, where the ratio of the Si precursor exposure time to the Ti precursor exposure time is between 2 and 130.

[0093] FIG. 17 is a flow diagram illustrating a method for forming a thin film comprising TiSiN according to an embodiment showing a precursor exposure sequence compatible with any of the embodiments described above with respect to FIGS. 14-16. In this case, unlike the method described above with respect to FIG. 13, in the second deposition phase, the Ti precursor precedes the Si precursor exposure, and the Si precursor exposure is followed by the N precursor exposure. The illustrated method includes exposing the substrate to one or more (x) vapor deposition cycles 1720, each of which includes exposing the semiconductor substrate to one or more (m) first deposition phases 1725 and exposing the semiconductor substrate to one or more (n) second deposition phases 1730. In the illustrated embodiment, the first and second deposition phases alternate with each other without overlapping in time. In the illustrated method, exposing the semiconductor substrate to one or more first deposition phases 1725 may be substantially the same as exposing the semiconductor substrate to one or more (m) first deposition phases 525 described above with respect to FIGS. 5B-5D and 13. In particular, exposing the semiconductor substrate to one or more first deposition phases 1725 includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor in a manner similar to that described above with respect to Figures 5B-5D and 13, the details of which will not be repeated here for brevity.

[0094] However, unlike the method described above with respect to Figure 13 (and Figures 5B-5D), exposing the semiconductor substrate to each second deposition phase in the method illustrated in Figure 17 further includes exposing the substrate to a titanium (Ti) precursor. In particular, exposing the semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor.

[0095] Additionally or alternatively, exposing the semiconductor substrate 1730 includes sequentially exposing the semiconductor substrate to a Ti precursor and a Si precursor, with no intervening exposure to an N precursor, followed by exposing the semiconductor substrate to an N precursor. In the embodiment shown in Figure 17, when the second deposition phase immediately follows the first deposition phase, exposing the semiconductor substrate to a first deposition phase 1725 includes exposing the semiconductor substrate to an N precursor as the last precursor and exposing the semiconductor substrate to a Ti precursor as the first precursor for the second deposition phase.

[0096] Although not detailed here for the sake of brevity, the various process parameters used in the embodiment illustrated in Figure 17 may be similar to those used in the methods described above with respect to Figure 13 and / or Figures 5B-5D, including the precursors, chamber pressure during deposition, and deposition temperature, each of which will not be repeated here for the sake of brevity.

[0097] The inventors have found that the Ti precursor exposure preceding the Si precursor exposure described herein can be advantageous for a variety of reasons discussed above. To enhance the advantageous effect, the Ti precursor exposure during the second deposition phase can be optimized with respect to various parameters including precursor flow rate and exposure time relative to the other exposures.

[0098] To achieve flow rates suitable for depositing TiSiN thin films on substrates with large surface area and / or high aspect ratio structures using a deposition process with Ti surface treatment prior to Si precursor exposure, the flow rates of each of the Ti and Si precursors may be adjusted below or above 1000 standard cubic centimeters per minute (sccm), 800 sccm, 600 sccm, 400 sccm, 200 sccm, or values ​​within a range defined by any of these values. The flow rate of the N precursor may be adjusted to a larger value, for example below or above 10000 standard cubic centimeters per minute (sccm), 8000 sccm, 6000 sccm, 4000 sccm, 2000 sccm, or values ​​within a range defined by any of these values. It will be understood that suitable flow rates may depend, inter alia, on the volume of the reactor, and that these flow rates may be suitable for a single wafer reactor with a volume of about 1-2 liters. For a reactor including multiple processing stations, these flow rates may be appropriate for each processing station.

[0099] 17, the inventors have found that exposing the semiconductor substrate to a Ti precursor during exposure 1730 to the second deposition phase can be particularly effective when the exposure time is shorter than the exposure time of the Si precursor. Advantageously, in certain embodiments, a relatively short exposure time of the Ti precursor during the second deposition phase results in surprisingly large improvements in electrical resistivity and / or step coverage. In various embodiments, the ratio of exposure times of the semiconductor substrate to the Si precursor and the semiconductor substrate to the Ti precursor during the second deposition phase is greater than 0.05, 0.1, 0.5, 1, 2, 5, 10, 20, 50, 100, 130, 200, 240, or a value within a range defined by any of these values. For example, in the embodiment shown in FIG. 17, the Si precursor exposure time in the second deposition phase can be less than 120 seconds, 90 seconds, 60 seconds, 30 seconds, 10 seconds, 5 seconds, 3 seconds, 2 seconds, 1 second, 0.5 seconds, 0.1 seconds, or a value within a range defined by any of these values, while the Ti exposure time in the second deposition phase can be less than 2 seconds, 1.5 seconds, 1.2 seconds, 1.0 seconds, 0.7 seconds, 0.5 seconds, or a value within a range defined by any of these values.

[0100] 17, the inventors have found that exposing the semiconductor substrate to the Ti precursor during exposure to the second deposition phase 1730 can be particularly effective when the exposure time is longer than the exposure time of the Ti precursor during exposure to the first deposition phase 1725. Advantageously, in various embodiments, the ratio of exposure times of the semiconductor substrate to the Ti precursor during the second deposition phase to the exposure of the semiconductor substrate to the Ti precursor during the first deposition phase is greater than 0.5, 1, 3, 5, 10, 20, 30, 40, or a value within a range defined by any of these values. For example, in the embodiment shown in FIG. 17, the Ti precursor exposure time of the first deposition phase can be less than 1 second, 0.5 seconds, 0.2 seconds, 0.1 seconds, 0.05 seconds, or a value within a range defined by any of these values, while the Ti exposure time of the second deposition phase can be less than 2 seconds, 1.5 seconds, 1.2 seconds, 1.0 seconds, 0.7 seconds, 0.5 seconds, or a value within a range defined by any of these values.

[0101] 17, the inventors have further found that exposing the semiconductor substrate to the N precursor during the exposure to the second deposition phase 1730 can be particularly effective when the exposure time is longer than the exposure time of the N precursor during the exposure to the first deposition phase 1725. Advantageously, in various embodiments, the ratio of the exposure time of the semiconductor substrate to the N precursor during the second deposition phase to the exposure time of the semiconductor substrate to the N precursor during the first deposition phase is greater than 1, 2, 5, 10, 20, 50, 100, 200, 500, 600, or a value within a range defined by any of these values. For example, in the embodiment shown in FIG. 17, the N precursor exposure time of the first deposition phase can be less than 1 second, 0.5 seconds, 0.2 seconds, 0.1 seconds, or a value within a range defined by any of these values, while the N precursor exposure time of the second deposition phase can be less than 60 seconds, 30 seconds, 10 seconds, 5 seconds, 2 seconds, 1 second, 0.5 seconds, 0.2 seconds, or a value within a range defined by any of these values.

[0102] With further reference to FIG. 17 , by way of example only, typical durations of the Ti precursor pulse / Ti precursor purge / N precursor pulse / N precursor purge in the first deposition phase may be 0.05-1 sec / 0.2-1 sec / 0.1-1 sec / 0.2-1 sec, respectively, while typical durations of the Ti precursor pulse / Ti precursor purge / Si precursor pulse / Si precursor purge / N precursor pulse / N precursor purge in the second deposition phase may be 0.5-2 sec / 0.2-1 sec / 0.2-120 sec / 0.5-5 sec / 0.2-120 sec / 0.5-5 sec, respectively.

[0103] By controlling the various Ti precursor exposure conditions in the second deposition phase as described herein, TiSiN films formed using methods according to embodiments may have a resistivity that is at least 200 μΩ·cm, 500 μΩ·cm, 1000 μΩ·cm, 1500 μΩ·cm, or a value within a range defined by any of these values, that is less than a diffusion barrier formed using the same method except that the semiconductor substrate is exposed to a Ti precursor as part of one or more second deposition phases. TiSiN films so formed may have a resistivity that is less than 2500 μΩ·cm, 2000 μΩ·cm, 1500 μΩ·cm, 1000 μΩ·cm, 500 μΩ·cm, or a value within a range defined by any of these values.

[0104] In addition to the exposure time, the ratio (m / n) of the number of times of the first deposition phase (m) to the number of times of the second deposition phase (n) can be adjusted to tailor various properties of the resulting TiSiN thin film.

[0105] FIG. 18A is a graph of experimentally measured Si content of TiSiN thin films deposited by the method shown in FIG. 17. The Si content is plotted as a function of the ratio of the number of first deposition phases to the number of second deposition phases. As shown, the Si content of the deposited TiSiN thin films was observed to decrease as a function of increasing m / n ratio. As shown, the rate of decrease in Si content as a function of m / n ratio unexpectedly decreases (showing an inflection point) when the m / n ratio is greater than about 7. This decrease is consistent with the resistivity trend (FIG. 18C). The experimental results shown indicate that m / n ratios greater than 7 are important to form TiSiN thin films with low resistivity (e.g., less than about 2000 μΩ·cm), corresponding to Si contents of 15% or less. At Si contents of 15% and greater, corresponding to m / n ratios greater than about 7, the TiSiN nanostructure becomes substantially amorphous, as shown in FIG. 18B.

[0106] FIG. 18B is a graph of experimentally measured grazing incidence X-ray diffraction (XRD) spectra of TiSiN thin films deposited by the method shown in FIG. 17. The different curves correspond to TiSiN thin films with different ratios of the number of first and second deposition phases. As shown, the XRD peak intensities of (111), (002), and (220) domains are observed to decrease with decreasing m / n ratio. As shown by the signal / noise ratio, the amount of amorphous phase in TiSiN thin films increases with decreasing m / n ratio.

[0107] FIG. 18C is a graph of experimentally measured electrical resistivity for TiSiN films measured for the Si content shown in FIG. 18A. As shown, the resistivity of TiSiN films was observed to decrease with increasing m / n ratio. As shown and as described above, there is an unexpected increase in resistivity when the m / n ratio is decreased below 7. The experimental results shown indicate that it may be important to adjust the m / n ratio to greater than 7 to form TiSiN films with resistivities of 2000 μΩ·cm. Below this ratio, the large resistivity values, as well as resistivity variations for small changes in Si content, make it unsuitable for mass production.

[0108] The inventors have found that by preceding the Si precursor exposure in the second deposition phase, the resistivity of the resulting TiSiN thin film can be reduced with a relatively small variation in resistivity as a function of exposure time, even when one or more of the exposures to Ti, Si and N precursors in the second deposition phase undersaturate the substrate surface. This results in reduced run-to-run variability of TiSiN thin films, improving their manufacturability. This is shown below for a variety of precursors. Furthermore, throughput can be improved since there is no need for unnecessary long exposure times during the second deposition phase. Thus, according to an embodiment, exposing the semiconductor to one or more Ti precursors, Si precursors and N precursors one or more times during one or more second deposition phases includes undersaturating a major surface of the semiconductor substrate, as shown in any of Figures 14-17.

[0109] As described herein, precursor surface saturation refers to a state in which increasing the exposure time of a particular precursor does not substantially change the surface saturation by that precursor. Conversely, unsaturated refers to a state in which increasing the exposure time of a particular precursor substantially changes the surface saturation by that precursor. Surface saturation is difficult to measure absolutely, but can be estimated by measuring the relevant electrical or physical parameters. For example, for a given parameter, if a given value of the parameter is obtained using exposure of a certain duration, and if further exposure of the same or longer duration does not change the value of the parameter by more than, for example, 10%, then the surface can be inferred to be substantially saturated.

[0110] 19A-19B are graphs of experimentally measured electrical resistivity of TiSiN thin films as a function of Ti precursor (TiCl4) exposure time in the second deposition phase of the deposition cycle shown in FIGS. 14-17. The exposure to dichlorosilane (SiH2Cl2, "DCS") as the Si precursor was fixed at 60 and 90 seconds, respectively. As shown, a decrease in electrical resistivity of TiSiN thin films can be observed as the Ti precursor exposure time in the second deposition phase increases. It can be shown that TiSiN thin films deposited with a short Ti precursor exposure time of 0.7 seconds in the second deposition phase have substantially smaller resistivity compared to TiSiN thin films deposited using the same process except for omitting the Ti precursor exposure in the second deposition phase. It can be seen that while longer exposure times further decrease the resistivity, a substantial decrease is achieved with a short Ti precursor pulse duration of 0.7 seconds. As shown, compared to the 60 s exposure to DCS without initial Ti exposure (zero value on the x-axis) in the second deposition phase, the 90 s exposure to DCS increases the resistivity by more than 10%, from about 2800 μΩ·cm to about 3200 μΩ·cm. That is, it can be inferred that the 60 s exposure to DCS is not sufficient to substantially saturate the surface. However, regardless of the DCS saturation degree, it was observed that the short exposure to Ti precursor for 0.7 s was effective to substantially reduce the resistivity. Finally, the change in resistivity was very small with further increase in Ti precursor exposure time. As shown, compared to the TiSiN thin film obtained with the Ti precursor exposure time of 0.7 s in the second deposition phase, the TiSiN thin film obtained with the Ti exposure time of 1.2 s has a relatively small change in electrical resistivity, e.g., about 10% or less. These results show that by inserting a relatively short Ti precursor prior to the Si precursor in the second deposition phase, two advantageous technological effects are obtained: a substantial reduction in resistivity and a substantial reduction in resistivity variability.

[0111] 20A-20C are cross-sectional transmission electron micrographs obtained from high aspect ratio structures lined with TiSiN thin films formed using different Ti precursor (TiCl4) exposure times in the second deposition phase of a deposition cycle similar to that shown in FIG. 17. FIGS. 20A-20C were obtained after lining high ratio structures having an aspect ratio of 57:1 (measured using the width of the top opening) with TiSiN thin films of equivalent thickness of about 4 nm on a flat semiconductor substrate. The TiSiN thin films imaged in the micrographs of FIGS. 20A-20C were formed using a method according to the method shown in FIGS. 14-17, where in the second deposition phase, the Si precursor (dichlorosilane) exposure time was fixed at 90 seconds, while the Ti precursor exposure times were 0 seconds, 0.7 seconds, and 1.2 seconds, respectively. As shown, the step coverage was measured to be 83%, 85%, and 87% from the micrographs of FIGS. 20A-20C, respectively.

[0112] 21A-21C are graphs of experimentally measured electrical resistivity as a function of Ti precursor (TiCl4) exposure time in the second deposition phase of the deposition cycle shown in FIGS. 14-17. The exposure time to monochlorosilane (SiH3Cl, "MCS") as the Si precursor was fixed at 3.5 seconds, 30 seconds, and 90 seconds, respectively. As shown, it can be observed that the electrical resistivity of the TiSiN thin films decreases with increasing Ti precursor exposure time in the second deposition phase. It can be seen that the resistivity is much lower for TiSiN thin films deposited with a short Ti precursor exposure time of 0.7 seconds in the second deposition phase compared to TiSiN thin films deposited using the same process except for omitting the Ti precursor exposure in the second deposition phase. It can be seen that although longer exposure times can further reduce the resistivity, a substantial reduction is achieved with a pulse duration as short as 0.7 seconds. Similar observations can now be made as discussed above with respect to FIGS. 19A and 19B. As shown, without the initial Ti exposure in the second deposition phase (zero value on the x-axis), it is observed that a short duration Ti precursor exposure of 0.7 seconds is effective in significantly reducing the resistivity, regardless of the MCS saturation. Ultimately, the change in resistivity with further increase in Ti precursor exposure time is a small change in the resistivity change. As shown, compared to the TiSiN thin film obtained with a Ti precursor exposure time of 0.7 seconds in the second deposition phase, the TiSiN thin film obtained with a Ti exposure time of 1.2 seconds changes in electrical resistivity by a relatively small amount, e.g., about 10% or less. This result indicates that the insertion of a relatively short Ti precursor before the Si precursor in the second deposition phase can obtain two advantageous technical effects, namely a significant reduction in resistivity and a significant reduction in resistivity variability.

[0113] 22A-22C are cross-sectional transmission electron micrographs obtained from high aspect ratio structures lined with TiSiN thin films formed using different Ti precursor (TiCl4) exposure times in the second deposition phase of a deposition cycle similar to that shown in FIG. 17. The micrographs in FIGS. 22A-22C were obtained after lining high ratio structures having an aspect ratio of 57:1 (measured using the width of the topside opening) with TiSiN thin films of equivalent thickness 4 nm on flat semiconductor substrates. The TiSiN thin films imaged in the micrographs in FIGS. 22A and 22B were formed using a method similar to that shown in FIGS. 14-17, where in the second deposition phase, the Si precursor (monochlorosilane) exposure time is fixed at 3.5 seconds, while the Ti exposure times are 0 seconds and 1.2 seconds, respectively. The TiSiN thin films imaged in the micrographs of Figure 22C were formed using a method similar to that shown in Figures 14-17, where the Si precursor (monochlorosilane) exposure time was fixed at 90 s while the Ti exposure time was 1.2 s in the second deposition phase. As can be seen, the step coverage was measured to be 86%, 93%, and 96% from the micrographs of Figures 22A-22C, respectively.

[0114] 23A-23B are graphs of experimentally measured electrical resistivity as a function of Ti precursor (TiCl4) exposure time in the second deposition phase of the deposition cycle shown in FIGS. 14-17. The exposure times to monochlorosilane (SiH3Cl, "MCS") as the Si precursor were fixed at 5 seconds and 30 seconds, respectively. As shown, it can be observed that increasing the Ti precursor exposure time in the second deposition phase decreases the electrical resistivity of the TiSiN thin films. Compared to TiSiN thin films deposited using the same process except for omitting the Ti precursor exposure in the second deposition phase, TiSiN thin films deposited with a short Ti precursor exposure time of 1.2 seconds have significantly smaller resistivity. Here, a similar observation can be made to that discussed above with respect to FIGS. 19A and 19B. As shown, without the initial Ti exposure in the second deposition phase (zero value on the x-axis), it was observed that a short duration Ti precursor exposure time of 1.2 seconds is effective in significantly reducing the resistivity, regardless of the OTCS saturation. Similarly, the relatively short insertion of the Ti precursor before the Si precursor in the second deposition phase results in two advantageous technical effects: a significant reduction in resistivity and a significant reduction in resistivity variability.

[0115] 24A-24B are cross-sectional transmission electron micrographs obtained from high aspect ratio structures lined with TiCl4 thin films formed using different Ti precursor (TiCl4) exposure times in the second deposition phase of a deposition cycle similar to that shown in FIG. 17. FIGS. 24A-24B were obtained after lining high ratio structures with an aspect ratio of 57:1 (measured using the width of the top opening) with TiSiN thin films of equivalent thickness 4 nm on a flat semiconductor substrate. The TiSiN thin films imaged in the micrographs of FIGS. 24A-24B were formed using a method similar to that shown in FIGS. 14-17, where the Si precursor (OTCS) exposure time in the second deposition phase was fixed at 5 seconds, while the Ti precursor exposure times were 0 seconds and 1.2 seconds, respectively. As can be seen, the step coverage was measured to be 96% and 100% from the micrographs of FIGS. 24A-24B.

[0116] Advantageously, the transmission electron micrographs shown with respect to Figures 20A-20C, 22A-22C, and 24A-24B show that TiSiN significantly improves the smoothness of the ultra-thin diffusion barrier compared to the ALD TiN film (see Figure 12). In each of the transmission electron micrographs shown in Figures 20A-20C, 22A-22C, and 24A-24B, the TiSiN film continuously covers the substrate surface with a thickness of less than 5 nm.

[0117] An aspect ratio of 57:1 was measured for the height to width of the top opening in each of the transmission electron micrographs shown in Figures 20A-20C, 22A-22C, and 24A-24B. A general view of the trench structure is shown in Figure 25A. It will be appreciated that the aspect ratio may be defined in a variety of ways. For example, the ratio of the height to the width of the bottom opening is about 171:1.

[0118] [TiN / TiSiN nanolaminate diffusion barrier deposition] Referring back to the methods described above with respect to Figures 13-17, the inventors have found that the ratio (m / n) of the number of first deposition phases (m) to the number of second deposition phases (n) can be adjusted to form either a substantially uniform film comprising TiSiN, or a nanolaminate comprising TiN and TiSiN as separate layers.

[0119] FIG. 26A is a flow diagram illustrating a method of forming a nanolaminate thin film according to some embodiments. As shown in FIG. 26A, the method includes depositing a thin film including TiN by exposing a semiconductor substrate to a first deposition phase one or more times (y1), depositing a thin film including TiSiN by exposing the semiconductor substrate to a second deposition phase one or more times (x), and forming another thin film including TiN by exposing the semiconductor substrate to a first deposition phase one or more times (y2). In some embodiments, y1 and y2 are different. FIG. 26B is a flow diagram illustrating a method of forming a nanolaminate thin film using a vapor deposition cycle similar to those shown in FIGS. 5B-5D and 13 according to some embodiments. FIG. 26C is a flow diagram illustrating a method of forming a nanolaminate thin film using a vapor deposition cycle similar to those shown in FIGS. 14-17 according to some embodiments.

[0120] In various embodiments, when forming a thin film, for example a diffusion barrier layer comprising TiSiN, in order to form a substantially uniform layer, the number of successive runs of the first and / or second deposition phases may be less than about 50, 30, 25, 20, 15, 10, 5 times, or a value within a range defined by any of these values, when the thin film is deposited at the temperatures mentioned above, whereas when the number of successive runs of the first and / or second deposition phases exceeds these values, the thin film may include a nanolaminate structure.

[0121] FIG. 27A is a graph of experimentally measured electrical resistivity for various nanolaminate thin films deposited by the method shown in FIGS. 26A and 26C according to some embodiments. The measured nanolaminate thin films include a TiSiN thin film interposed between two TiN thin films. It can be seen that the electrical resistivity can be tuned by independently adjusting the thickness of the upper and lower TiN thin films. Surprisingly, while the total thickness of the TiN thin film combination was the same for the three nanolaminates measured, the electrical resistivity unexpectedly decreased when the lower TiN thin film was thinner than the upper TiN thin film. At least the various advantages described above for uniform TiSiN thin films were equally observed for nanolaminates according to embodiments.

[0122] FIG. 27B is a graph of experimentally measured grazing incidence x-ray diffraction spectra from various nanolaminate thin films deposited by the methods illustrated in FIGS. 26A and 26C, according to some embodiments.

[0123] 28A and 28B are cross-sectional transmission electron micrographs taken of a high aspect ratio structure lined with a nanolaminate thin film according to some embodiments. It can be seen that the step coverage is comparable to a uniform TiSiN thin film.

[0124] [TiSiN thin film with excellent mechanical properties including high elastic modulus and hardness] As discussed above, thin films comprising TiSiN are desirable in many applications, such as for forming electrodes and / or diffusion barriers lining high aspect ratio vias and trenches. As discussed above, to conformally coat substrates having a relatively large areal density of high aspect ratio structures, the process conditions, e.g., as described with respect to Figures 5A-5D, can be optimized by controlling, among other things, the reaction chamber pressure and precursor partial pressures during deposition, the deposition rate, the temperature and pressure of the precursors introduced to the reaction chamber, the precursor flow rates and exposure times, etc.

[0125] Various applications of TiSiN require improved structural and mechanical properties of thin films comprising TiSiN, in addition to electrical and barrier properties. For example, as integrated circuit device features continue to shrink in size and / or increase in aspect ratio, the physical demands on thin films used as diffusion barriers and / or electrodes continue to increase. Thin film thicknesses also shrink with shrinking feature sizes, and thin films may be subjected to correspondingly higher levels of thermomechanical stress. TiN is one of the pioneering materials in many applications, but structural failure of TiN in high aspect ratio structures is a major issue in the reliability and yield of integrated circuit devices. Failure modes such as defects, bending, and buckling are associated with insufficient physical properties of TiN films, such as hardness and modulus of elasticity. Thus, as the demand for complex three-dimensional structures increases, alternative barrier materials with superior physical properties are needed. To address these and other needs, methods of forming and tailoring thin films comprising TiSiN with superior physical properties, and thin films formed using the methods, are described herein.

[0126] As described herein, the inventors have found alternatives and / or further improvements to the various methods described above to improve the electrical and structural properties of TiSiN films as well as their mechanical and structural properties. As described above, the inventors have discovered that ultra-thin (e.g., <5 nm) TiN layers, even when grown by atomic layer deposition, do not continuously cover the underlying surface and can be discontinuous. In addition to limiting the effectiveness of the TiN layer as a diffusion barrier, such discontinuities can severely impair the mechanical and structural properties of the TiN film.

[0127] Unlike TiN thin films, the inventors have discovered that TiSiN, when deposited under certain deposition conditions described herein, can provide continuous and uniform coverage even when scaled down to these ultra-thin dimensions, e.g., <5 nm. This is particularly important for providing superior mechanical and structural properties for ultra-thin diffusion barrier applications at advanced technology nodes. For example, in a manner similar to that described with respect to Figs. 14-17, a semiconductor substrate is exposed to one or more first deposition phases in alternating and non-overlapping fashion and one or more second deposition phases, where exposing the semiconductor substrate to one or more first deposition phases includes exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor in alternating fashion, and exposing the semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor. That is, in the second deposition phase, exposure to a Ti precursor precedes exposure to a S precursor, which is followed by exposure to a N precursor. This method improves the mechanical integrity and enhances the continuity and structural properties of the TiSiN film, even when scaled to ultra-thin (eg, <5 nm) dimensions.

[0128] 29 is a flow diagram illustrating a method of forming a thin film comprising TiSiN with improved mechanical and structural properties according to some embodiments. In these embodiments, the method includes forming a diffusion barrier comprising TiSiN 2902 by exposing a semiconductor substrate to one or more alternating first and one or more second deposition phases. The diffusion barrier has: an elastic modulus of greater than 290 GPa and a Si content of greater than 2.7 atomic %; or a hardness of greater than 20 GPa and a Si content of greater than 2.7 atomic %; or a ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in the grazing incidence x-ray diffraction spectrum of the diffusion barrier of greater than 0.4 and a Si content of greater than 2.7 atomic %; or a nanocrystalline structure with an average grain size of less than about 6.5 nm and a Si content of greater than 2.7 atomic %. Exposing the semiconductor substrate to one or more first deposition phases 2904 includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases 2906 includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor.

[0129] Various embodiments of the method illustrated in Figure 29 can include features described above with respect to Figures 5B-5D and 13 or Figures 14-17, and the details thereof will not be repeated here for the sake of brevity. For example, according to embodiments, the exposure times for each of the Ti precursor exposure time of the first deposition phase, the N precursor exposure time of the first deposition phase, and the N precursor exposure time of the second deposition phase can be less than 1.0 seconds, 0.8 seconds, 0.6 seconds, 0.4 seconds, 0.2 seconds, 0.1 seconds, or a value within a range defined by any of these values. The thin film deposition system can be configured to introduce each of the precursors at a respective flow rate such that within their exposure time the surface of the substrate reaches a predetermined degree of saturation, for example, greater than 40%, 60%, 80%, or a value within a range defined by any of these values. In the embodiment in which the exposure to the precursors shown in Figure 17 is followed by a rapid purge, the duration of the rapid purge step can be less than 1.0 seconds, 0.8 seconds, 0.6 seconds, 0.4 seconds, 0.2 seconds, 0.1 seconds, or a value within a range defined by any of these values.

[0130] 17, in another example, the inventors have found that exposing the semiconductor substrate to a Ti precursor during exposing the semiconductor substrate to a second deposition phase 1730 is particularly effective when the exposure time is equal to or shorter than the exposure time to the N precursor. In various embodiments, the ratio of the exposure time of the semiconductor substrate to the Ti precursor to the exposure time of the semiconductor substrate to the Si precursor in the second deposition phase is greater than 1, 0.2, 0.4, 0.6, 0.8, and 1.0, or a value within a range defined by any of these values. For example, in the embodiment shown in FIG. 17, the Si precursor exposure time in the second deposition phase can be less than 30 seconds, 15 seconds, 10 seconds, 5 seconds, 1 second, 0.5 seconds, or a value within a range defined by any of these values, while the Ti precursor exposure time in the second deposition phase can be 0 seconds or less than 2 seconds, 1.5 seconds, 1.0 seconds, 0.5 seconds, 0.2 seconds, or a value within a range defined by any of these values.

[0131] 17, by way of example only, in one particular embodiment, typical durations for the Ti precursor pulse / Ti precursor purge / N precursor pulse / N precursor purge in the first deposition phase may be 0.15 seconds / 0.53 seconds / 0.2 seconds / 0.32 seconds, respectively, while typical durations for the Ti precursor pulse / Ti precursor purge / Si precursor pulse / Si precursor purge / N precursor pulse / N precursor purge in the second deposition phase may be 0-1.0 seconds / 0.3 seconds / 1-10 seconds / 0.5 seconds / 0.5 seconds / 0.5 seconds, respectively.

[0132] In addition to the exposure time, the ratio (m / n) of the number of times of the first deposition phase (m) to the number of times of the second deposition phase (n) can be adjusted to adjust various properties of the resulting TiSiN thin film, where m / n can be greater than 5, 10, 20, 40, 60, 80, and 100.

[0133] FIG. 30 is a graph showing the tunability of the Si content of TiSiN thin films by adjusting precursor exposure time and / or the ratio of the number of first and second deposition phases, according to embodiments. The x-axis plots the m:n ratio, and the y-axis plots the Si content in TiSiN thin films as measured by X-ray photoelectron spectroscopy (XPS). The three curves showing the decrease in Si content with increasing m / n ratio correspond to Si precursor exposure times of 1, 0.5, and 10 seconds, with the Ti precursor exposure time fixed at 1 second. It can be seen that different combinations of m / n ratio and Si precursor exposure time produce TiSiN thin films with Si content in the range of about 2.7-9 atomic %. This range has been shown to be particularly effective in providing good mechanical properties.

[0134] The areas under the peaks of the grazing incidence X-ray diffraction spectrum can be monitored as an indication of a predetermined structural performance parameter of the TiSiN thin film deposited according to the embodiments. In particular, the inventors have discovered that the TiSiN thin films deposited according to the embodiments have a crystalline structure such that the grazing incidence X-ray diffraction spectrum of the TiSiN thin film exhibits a ratio (R) of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks that can be monitored as an indication of a predetermined structural performance parameter of the TiSiN thin film. Without being bound by any theory, the ratio R may be related to the preferential (002) texture of the nanocrystalline domains of the TiSiN thin film. Figures 31A-31I are grazing incidence X-ray diffraction (XRD) spectra of TiSiN thin films with different Si contents measured experimentally.

[0135] FIG. 32 is a graph summarizing the XRD spectra shown in FIGS. 31A-31I. Table 1 summarizes the results of the ratio (R) for TiSiN films with different Si contents. According to various embodiments, the ratio (R) of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks for TiSiN films with Si contents greater than 2.7 atomic % can be greater than 0.4, 1.0, 2.0, 3.0, 4.0, 4.5, or can have a value within a range defined by any of these values. As shown, for TiSiN films with a Si content of about 7 atomic %, the R ratio peaks at about 4.5 and then drops unexpectedly. As described below, the inventors have discovered that higher values ​​of the R ratio can be correlated with improved hardness and elastic modulus.

[0136] [Table 1]

[0137] FIG. 33 is a graph of the estimated average nanocrystalline grain size as a function of Si content, calculated from the grazing incidence X-ray diffraction (XRD) spectra shown in FIGS. 31A-31I. The average grain size was calculated using the broadened peaks of the XRD spectra using the Scherrer method known in the art. The TiSiN thin films have a nanocrystalline structure with an average grain size less than about 6.5 nm, 6.0 nm, 5.5 nm, 5.0 nm, or a value within a range defined by any of these values. As described below, the inventors have found that for grain sizes greater than about 5.5 nm, corresponding to about 7 atomic % Si, smaller grain sizes result in improved hardness and modulus.

[0138] FIG. 34 is a graph of hardness values ​​as a function of Si content measured on TiSiN thin films corresponding to the process conditions shown in FIG. 30. FIG. 35 is a graph of elastic modulus values ​​as a function of Si content measured on TiSiN thin films corresponding to the process conditions shown in FIG. 30. Hardness and elastic modulus values ​​were measured using nanoindentation techniques. As shown, the hardness and elastic modulus values ​​are generally proportional to the R-ratio and follow the same general trend (FIG. 32). As shown, the hardness and elastic modulus values ​​peak at a TiSiN thin film with a Si content of about 7 atomic % and then drop off unexpectedly, coinciding with the peak in the R-ratio. In addition, the hardness and elastic modulus values ​​are generally inversely proportional to the grain size up to a grain size of about 5.5 nm, which corresponds to about 7 atomic % Si.

[0139] Without being bound by any theory, the increase in hardness and elastic modulus may be related to the grain boundary hardening effect, where an increase in the Si content reduces the grain size and therefore increases the grain boundary density. The grain boundaries may interact with each other to form a dense three-dimensional network of grain boundaries. Under such circumstances, the three-dimensional network of grain boundaries may severely restrict the movement of the grains under external forces, resulting in a high hardness and elastic modulus. However, as shown, this effect peaks around 7 atomic % Si content, above which the hardness and elastic modulus actually decrease. Without being bound by any theory, this may be attributed to an increase in the proportion of amorphous phase, which may reduce the grain boundary hardening effect. Thus, increasing the Si content to improve the hardness and elastic modulus values ​​may be effective up to a critical value of about 7 atomic %. In various embodiments, TiSiN thin films according to embodiments have a Si content that exceeds any of the values ​​listed in Table 1 to achieve the elastic modulus and hardness described herein. In certain embodiments, the Si content does not exceed 7%.

[0140] FIG. 36 shows low and high resolution cross-sectional transmission electron micrographs obtained from a high aspect ratio structure lined with a TiSiN thin film, according to an embodiment. The high aspect ratio structure is similar to that described above with respect to FIGS. 25A-25B. According to an embodiment, the TiSiN thin film with high modulus and hardness described herein also exhibits excellent uniformity and step coverage, which can be greater than 85%, as measured using the cross-sectional transmission electron micrograph of the high aspect ratio structure shown in FIG. 36. As an example of how to measure step coverage, the distances indicated as (top top side) TT, (top left side) TS-L, (top right side) TS-R, (bottom left side) BS-L, and (bottom right side) BS-R were measured by averaging multiple measurements using an image processing software program. For the particular high aspect ratio structure shown in Figure 36, the measurements were: TT = 12.87 nm, TS-L = 11.96 nm, TS-R = 11.81 nm, BS-L = 10.67 nm, BS-R = 11.11 nm. The step coverage was calculated as SC = (BS-L + BS-R) / (TS-L + TS-R) = 21.78 nm / 23.77 nm = 92%. Alternatively, the step coverage can be calculated as (BS-L + BS-R)2 / (TT) = 10.89 / 12.87 nm / 23.77 nm = 85%.

[0141] TiSiN diffusion barriers deposited for high modulus and hardness according to embodiments may have a root mean square (RMS) surface roughness of less than 0.4 nm, 0.3 nm, 0.2 nm, 0.1 nm, or a value within a range defined by any of these values ​​or less. A reduction in RMS roughness may in turn improve the conformality of the diffusion barrier layer. FIG. 37A is an atomic force microscope image of a TiSiN thin film deposited according to an embodiment. The measured RMS roughness was 0.27 nm. FIG. 37B is an atomic force microscope image of a comparative TiN thin film. For a TiN thin film of comparable thickness, the RMS roughness was significantly higher at 0.67 nm.

[0142] [Another embodiment I] 1. A method for forming a diffusion barrier, the method comprising: forming a thin film comprising one or both of TiSiN or TiAlN by exposing the semiconductor substrate to multiple vapor deposition cycles at a pressure in a reaction chamber greater than 1 Torr; the vapor deposition cycle includes exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor; The method of claim 1, wherein the semiconductor substrate has a surface topography such that a ratio of a surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to a surface area of ​​a corresponding unpatterned semiconductor substrate is greater than two. 2. The method of embodiment 1, wherein the surface topography comprises a plurality of trenches or vias having an aspect ratio of greater than 5. 3. The method of embodiment 2, wherein the number and size of the trenches or vias are such that the surface area ratio is greater than 20. 4. The method of embodiment 1, wherein forming the thin film comprises exposing the semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber of 3 to 10 Torr. 5. The method of embodiment 1, wherein one or more of the Ti precursor, the N precursor, and the Si or Al precursor are liquid at room temperature and atmospheric pressure. 6. Exposing the semiconductor substrate to one or more vapor deposition cycles; exposing the semiconductor substrate to a first deposition phase multiple times; exposing the semiconductor substrate to a second deposition phase multiple times; Each of the first deposition phases includes exposure to the Ti precursor and exposure to the N precursor; and 2. The method of embodiment 1, wherein each of the second deposition phases includes exposure to one or both of the Si precursor or the Al precursor. 7. The method of embodiment 6, wherein at least one of the second deposition phases further comprises further exposure to the N precursor. 8. The method of embodiment 6, wherein the ratio of the number of the first deposition phase to the number of the second deposition phase is such that the thin film is at least partially amorphous. 9. The method of embodiment 8, wherein the ratio of the number of times of the first deposition phase to the number of times of the second deposition phase is equal to or less than 15:1. 10. The method of embodiment 8, wherein the thin film comprises TiSiN having a silicon concentration greater than about 10 atomic %. 11. The method of embodiment 6, wherein the number of times of the first deposition phase and the number of times of the second deposition phase are such that the thin film is substantially uniform across the depth of the layer. 12. The method of embodiment 11, wherein the number of the first deposition phases or the number of the second deposition phases does not exceed about 50 cycles. 13. The method of embodiment 1, wherein the thin film comprises TiSiN and the Si precursor is a compound selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH2Cl, Si2Cl6, and Si3Cl8. 14. The method of embodiment 1, wherein the thin film comprises TiAlN and the Al precursor is a compound selected from the group consisting of trimethylaluminum, triisobutylaluminum, and tris(dimethylamido)aluminum. 15. The method of embodiment 1, wherein exposing the semiconductor substrate to the vapor deposition cycle is performed at a substrate temperature of between 450°C and 650°C. 16. A method for forming a diffusion barrier comprising the steps of: providing a semiconductor substrate having a plurality of holes formed thereon; lining the surfaces of the holes with a diffusion barrier layer comprising one or both of TiSiN or TiAlN that is at least partially amorphous by exposing the semiconductor substrate to a plurality of vapor deposition cycles; the hole has a dielectric sidewall and an aspect ratio greater than 5; The method, wherein the vapor deposition cycle comprises exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor. 17. The method of embodiment 16, wherein the pores have an aspect ratio of greater than 5. 18. The method of embodiment 17, wherein lining the surface of the hole results in a ratio of the thickness of the diffusion barrier formed in the lower 25% of the hole height to the upper 25% of the hole height that is greater than 0.6. 19. The method of embodiment 16, wherein the number and size of the holes are set such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 20. The method of embodiment 16, wherein lining the surfaces of the holes comprises exposing the semiconductor substrate to the vapor deposition cycle at a pressure in a reaction chamber of 3 to 10 Torr. 21. The method of embodiment 16, wherein the hole further has an exposed semiconductor bottom surface. 22. Exposing the semiconductor substrate to the vapor deposition cycle comprises: exposing the semiconductor substrate to a first deposition phase multiple times; exposing the semiconductor substrate to a second deposition phase multiple times; the first deposition phase includes exposure to the Ti precursor and exposure to the N precursor; and 17. The method of embodiment 16, wherein the second deposition phase comprises exposure to one or both of the Si precursor or the Al precursor. 23. The method of embodiment 22, wherein the second deposition phase further comprises further exposure to the N precursor. 24. The method of embodiment 22, wherein the ratio of the number of the first deposition phase to the number of the second deposition phase is such that the diffusion barrier layer is at least partially amorphous. 25. The method of embodiment 24, wherein the ratio of the number of times of the first deposition phase to the number of times of the second deposition phase is 2:3, 3:2, 5:4, 7:3, 7:5, 7:1, 10:1, or 15:1. 26. The method of embodiment 22, wherein the number of times of the first deposition phase and the number of times of the second deposition phase are such that the diffusion barrier layer is substantially uniform across the depth of the layer. 27. The method of embodiment 26, wherein the number of the first deposition phases or the number of the second deposition phases does not exceed about 50 cycles. 28. The method of embodiment 22, wherein the number of times of the first deposition phase and the number of times of the second deposition phase are such that the diffusion barrier layer has a nanolaminate structure. 29. The method of embodiment 16, wherein the root mean square surface roughness of the diffusion barrier layer is less than about 5% based on the average thickness of the diffusion barrier layer. 30. The method of embodiment 16, wherein the diffusion barrier layer comprises TiSiN and the Si precursor is a compound selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH2Cl, Si2Cl6, and Si3Cl8. 31. The method of embodiment 16, wherein the diffusion barrier layer comprises TiAlN and the Al precursor is a compound selected from the group consisting of trimethylaluminum, triisobutylaluminum, and tris(dimethylamido)aluminum. 32. The method of embodiment 16, wherein exposing the semiconductor substrate to the vapor deposition cycle is performed at a substrate temperature of between 450°C and 650°C. 33. A method for forming a thin film, the method comprising: forming a thin film comprising TiSiN and / or TiAlN by exposing the semiconductor substrate to multiple vapor deposition cycles at a pressure in a reaction chamber greater than 5 Torr; 13. A method according to claim 12, wherein the vapor deposition cycle comprises exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor. 34. The method of embodiment 33, wherein the pressure in the reaction chamber is less than 10 Torr. 35. The method of embodiment 33, wherein the semiconductor substrate has a topography such that the ratio of a surface area of ​​the semiconductor substrate exposed to one or more of the vapor deposition cycles to a surface area of ​​a corresponding unpatterned semiconductor substrate is greater than 2. 36. The method of embodiment 35, wherein the semiconductor substrate has a plurality of trenches or vias formed thereon, the trenches or vias having dielectric sidewalls and an aspect ratio greater than 5. 37. Exposing the semiconductor substrate to one or more vapor deposition cycles exposing the semiconductor substrate to a first deposition phase multiple times; exposing the semiconductor substrate to a second deposition phase multiple times; the first deposition phase includes exposure to the Ti precursor and exposure to the N precursor; and 34. The method of embodiment 33, wherein the second deposition phase comprises exposure to one or more of the Si precursor or the Al precursor. 38. The method of embodiment 37, wherein the second deposition phase further comprises further exposure to the N precursor. 39. The method of embodiment 37, wherein the ratio of the number of the first deposition phase to the number of the second deposition phase is such that the thin film is at least partially amorphous. 40. The method of embodiment 39, wherein the ratio of the number of times of the first deposition phase to the number of times of the second deposition phase is equal to or less than 15:1. 41. The method of embodiment 37, wherein the number of times of the first deposition phase and the number of times of the second deposition phase are such that the diffusion barrier layer is substantially uniform across the depth of the layer. 42. The method of embodiment 41, wherein the number of first deposition phases and the number of second deposition phases does not exceed about 50 cycles. 43. The method of embodiment 33, wherein the thin film comprises TiSiN and the Si precursor is a compound selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH2Cl, Si2Cl6, and Si3Cl8. 44. The method of embodiment 33, wherein the thin film comprises TiAlN and the Al precursor is a compound selected from the group consisting of trimethylaluminum, triisobutylaluminum, and tris(dimethylamido)aluminum. 45. The method of embodiment 33, wherein exposing the semiconductor substrate to the vapor deposition cycle is performed at a substrate temperature of between 450°C and 650°C. 46. ​​A semiconductor substrate having a plurality of trenches or vias thereon, the trenches or vias having dielectric sidewall surfaces and an aspect ratio greater than 5; a diffusion barrier layer comprising one or both of TiSiN or TiAlN conformally lining a surface of the trench or via, the diffusion barrier layer being at least partially amorphous. 47. The semiconductor structure of embodiment 46, wherein the aspect ratio of the trench or via is greater than 5. 48. The semiconductor structure of embodiment 47, wherein the diffusion barrier layer conformally lining the surface is such that the ratio of the thickness of the diffusion barrier layer formed in the lower 25% of the hole's height to the upper 25% of the hole's height is greater than 0.6. 49. The semiconductor structure of embodiment 46, wherein the areal density of the trenches or vias is such that the ratio of the surface area on which the diffusion barrier layer is formed to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 50. The semiconductor structure of embodiment 49, wherein the surface area ratio is greater than 100. 51. The semiconductor structure of embodiment 46, wherein the diffusion barrier layer is substantially completely amorphous. 52. The semiconductor structure of embodiment 46, wherein the diffusion barrier layer is substantially uniform across the depth of the hole. 53. The semiconductor structure of embodiment 46, wherein the diffusion barrier layer has a nanolaminate structure. 54. The semiconductor structure of embodiment 46, wherein the root mean square surface roughness of the diffusion barrier layer is less than about 5% based on the average thickness of the diffusion barrier layer. 55. The semiconductor structure of embodiment 46, wherein the diffusion barrier layer comprises TiSiN having a silicon concentration greater than about 10 atomic %. 56. The semiconductor structure of embodiment 46, wherein the trench or via further has a semiconductor bottom surface. 57. The semiconductor structure of embodiment 46, wherein the trench or via is filled with tungsten or copper. 58. The semiconductor structure of embodiment 46, wherein the diffusion barrier layer has a thickness of about 1 to 10 nm. 59. The semiconductor structure of embodiment 46, wherein the trench or via has a width of about 10 to 1000 nm. 60. The semiconductor structure of embodiment 23, wherein the diffusion barrier layer has an electrical resistivity of less than about 1600 μΩ·cm.

[0143] [Alternative embodiment II] 1. A method for forming a diffusion barrier comprising TiSiN, the method comprising: alternatingly exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases; exposing the semiconductor substrate to one or more of the first deposition phases comprises alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and The method, wherein exposing the semiconductor substrate to one or more of the second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor, with no intervening exposure to an N precursor therebetween, and subsequently exposing the semiconductor substrate to an N precursor. 2. A method of forming a diffusion barrier comprising TiSiN, the method comprising: alternatingly exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases; exposing the semiconductor substrate to one or more of the first deposition phases comprises alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and The method, wherein exposing the semiconductor substrate to one or more of the second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor. 3. A method of forming a diffusion barrier comprising TiSiN, the method comprising: alternatingly exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases; exposing the semiconductor substrate to one or more of the first deposition phases comprises alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and exposing the semiconductor substrate to one or more of the second deposition phases comprises exposing the semiconductor substrate to a Ti precursor during a Ti precursor exposure time, followed by a silicon (Si) precursor during a Si precursor exposure time, followed by a N precursor; and A method wherein the ratio of said Si precursor exposure time to said Ti precursor exposure time is between 2 and 130. 4. The method of any of the above embodiments, wherein the diffusion barrier formed using the method has a resistivity of 2000 μΩ·cm or less. 5. The method of any of the above embodiments, wherein the diffusion barrier formed using the method has a resistivity that is at least 500 μΩ·cm less than a diffusion barrier formed using the same method except for exposing the semiconductor substrate to a Ti precursor as part of the one or more second deposition phases. 6. The semiconductor substrate has an aspect ratio of greater than 50, and forming the diffusion barrier is 4. The method of any of the previous embodiments, wherein the step of forming a diffusion barrier comprises lining the surface of the hole such that the ratio of the thickness of the diffusion barrier formed in the lower 25% of the hole height to the upper 25% of the hole height is greater than 0.9. 7. The method of any of the previous embodiments, wherein exposing the semiconductor substrate to one or more first deposition phases comprises exposing the semiconductor substrate to a N precursor as a final precursor in one or more first deposition phases. 8. The method of any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases comprises exposing the semiconductor substrate to a Ti precursor as an initial precursor for one or more second deposition phases. 9. The method of any of the above embodiments, wherein exposure of the semiconductor substrate to a Ti precursor as the first precursor in the second deposition phase immediately follows exposure of the semiconductor substrate to a N precursor as the last precursor in the first deposition phase, without any intervening precursor exposure. 10. The method of any of the previous embodiments, wherein the ratio of exposure times of the semiconductor substrate to a Si precursor and the semiconductor substrate to a Ti precursor in the second deposition phase is greater than 2. 11. The method of any of the previous embodiments, wherein the ratio of exposure times of the semiconductor substrate to a Si precursor and the semiconductor substrate to a Ti precursor in the second deposition phase is less than 130. 12. A method according to any of the above embodiments, wherein the ratio of exposure times of the semiconductor substrate to a Si precursor and the semiconductor substrate to a Ti precursor in the second deposition phase is between 2 and 130. 13. A method according to any of the above embodiments, wherein the ratio of exposure times of the semiconductor substrate to a Ti precursor in the second deposition phase and the semiconductor substrate to a Ti precursor in the first deposition phase is between 3 and 34. 14. The method of any of the previous embodiments, wherein the ratio of exposure times of the semiconductor substrate to an N precursor in the second deposition phase and the semiconductor substrate to an N precursor in the first deposition phase is between 5 and 50. 15. A method according to any of the above embodiments, wherein the exposure time of the semiconductor substrate to a Si precursor in the second deposition phase is longer than 3 seconds and the exposure time of the semiconductor substrate to a Ti precursor is less than 2 seconds. 16. The method of any of the previous embodiments, wherein exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases comprises exposing under a pressure in the reaction chamber of greater than 1 Torr. 17. The method of any of the previous embodiments, wherein the semiconductor substrate has a surface topography such that the ratio of a surface area of ​​the semiconductor substrate exposed to one or more first deposition phases and one or more second deposition phases to a corresponding surface area of ​​the unpatterned semiconductor substrate is greater than 2. 18. The method of embodiment 17, wherein the surface topography comprises a plurality of trenches or vias having an aspect ratio of greater than 5. 19. The method of embodiment 17 or 18, wherein the number and size of the trenches or vias are such that the surface area ratio is greater than 20. 20. The method of any of the previous embodiments, wherein exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases comprises exposing at a pressure in a reaction chamber of 3 to 10 Torr. 21. The method of any of the previous embodiments, wherein the ratio of the number of the first deposition phase to the number of the second deposition phase is such that the diffusion barrier is at least partially amorphous. 22. The method according to any of the previous embodiments, wherein the ratio of the number of first deposition phases to the number of second deposition phases is greater than 3. 23. The method according to any of the previous embodiments, wherein the ratio of the number of first deposition phases to the number of second deposition phases is 3 to 60. 24. The method of any of the previous embodiments, wherein the diffusion barrier comprises TiSiN having a silicon content greater than 5 atomic %. 25. The method of any of the previous embodiments, wherein the diffusion barrier comprises TiSiN having a silicon content of 5-30 atomic %. 26. The method of any of the above embodiments, wherein the Si precursor is a compound selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH2Cl, Si2Cl6, and Si3Cl8. 27. The method of any of the above embodiments, wherein the Ti precursor comprises TiCl4. 28. The method of any of the above embodiments, wherein the N precursor is NH3. 29. The method of any of the previous embodiments, wherein exposing the semiconductor substrate to a vapor deposition cycle is performed at a substrate temperature of 400°C to 600°C. 30. A method according to any of the previous embodiments, wherein the number of times of the first deposition phase and the number of times of the second deposition phase are provided such that the diffusion barrier layer is substantially uniform across the depth of the layer. 31. The method of embodiment 30, wherein the number of times the first deposition phase and the number of times the second deposition phase do not exceed about 50. 32. A method according to any of the previous embodiments, wherein the number of times of the first deposition phase and the number of times of the second deposition phase are arranged such that the diffusion barrier layer has a nanolaminate structure comprising alternating TiN and TiSiN layers. 33. The method of embodiment 32, wherein one or both of the first and second deposition phases occur more than about 50 times. 34. The method of embodiment 32 or 33, wherein one or both of the TiN layer and the TiSiN layer have a thickness greater than 1.5 nm. 35. The method of any one of embodiments 32-34, wherein the nanolaminate has a TiSiN layer between TiN layers. 36. The method of any of the above embodiments, wherein the semiconductor substrate has a plurality of holes formed thereon, the holes having dielectric sidewall surfaces and an aspect ratio greater than 5, and forming the diffusion barrier includes lining surfaces of the holes. 37. The method of embodiment 36, wherein lining the hole has a ratio of the thickness of the diffusion barrier layer formed in the lower 25% of the hole's height to the thickness of the diffusion barrier layer formed in the upper 25% of the hole's height that is greater than 0.8. 38. The method of embodiment 37, wherein the Si precursor is SiH2Cl2 and the ratio is greater than 83%. 39. The method of embodiment 37, wherein the Si precursor is SiH3Cl and the ratio is greater than 86%. 40. The method of embodiment 37, wherein the Si precursor is Si3Cl8 and the ratio is greater than 86%. 41. The method of any one of embodiments 38 to 40, wherein the aspect ratio is greater than 50. 42. A method according to any of the above embodiments, wherein the number and size of the holes are such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 43. The method of any of the previous embodiments, wherein lining the surfaces of the holes comprises exposing the semiconductor substrate to a vapor deposition cycle at a pressure in a reaction chamber of 3-10 Torr. 44. The method of any of the above embodiments, wherein the hole further comprises an exposed semiconductor bottom surface. 45. The method of any of the above embodiments, wherein the one or more first deposition phases do not overlap with the one or more second deposition phases. 46. ​​The method of any of the above embodiments, wherein exposing the semiconductor substrate to a Ti precursor, a Si precursor, and a N precursor during one or more second deposition phases comprises undersaturating a surface of the semiconductor substrate. 47. The method of embodiment 42, wherein the diffusion barrier comprises TiSiN and has a resistivity that is greater than 10% relative to a reference diffusion barrier comprising TiSiN obtained using the same method but without being saturated. 48. A nanolaminate comprising alternating TiN-rich regions or layers with Si-rich and / or Al-rich regions or layers or SiN / AlN-rich regions or layers.

[0144] [Alternative embodiment III] 1. A method for forming a diffusion barrier, the method comprising: forming a diffusion barrier comprising TiSiN having an elastic modulus greater than 290 GPa and a Si content greater than 2.7 atomic % by alternately exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases; exposing the semiconductor substrate to one or more first deposition phases includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and The method of claim 1, wherein exposing the semiconductor substrate to one or more second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor. 2. A method of forming a diffusion barrier, said method comprising: forming a diffusion barrier comprising TiSiN having a hardness greater than 20 GPa and a Si content greater than 2.7 atomic % by alternately exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases; exposing the semiconductor substrate to one or more first deposition phases includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and The method of claim 1, wherein exposing the semiconductor substrate to one or more second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor. 3. A method of forming a diffusion barrier, said method comprising: forming a diffusion barrier comprising TiSiN having a crystalline texture exhibiting a ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in a grazing incidence x-ray diffraction spectrum of said diffusion barrier of greater than 0.4 and a Si content of greater than 2.7 atomic %, by alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases; exposing the semiconductor substrate to one or more first deposition phases includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and The method of claim 1, wherein exposing the semiconductor substrate to one or more second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor. 4. A method of forming a diffusion barrier, said method comprising: forming a diffusion barrier comprising TiSiN having an average grain size less than about 6.5 nm and a Si content greater than 2.7 atomic % by alternately exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases; exposing the semiconductor substrate to one or more first deposition phases includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and The method of claim 1, wherein exposing the semiconductor substrate to one or more second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor. 5. The method according to any of the previous embodiments, wherein the diffusion barrier has a Si content of 2.7-9 atomic %. 6. The method according to any of the previous embodiments, wherein the diffusion barrier has a Si content of 2.7-7 atomic %. 7. The method of any of the previous embodiments, wherein the diffusion barrier has an elastic modulus of 290-350 GPa. 8. The method according to any of the previous embodiments, wherein the diffusion barrier has a hardness of 20-40 GPa. 9. The method according to any of the previous embodiments, wherein the diffusion barrier has a crystalline texture exhibiting a ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in a grazing incidence X-ray diffraction spectrum of 0.4 to 4.5. 10. The method of any of the above embodiments, wherein the diffusion barrier has a nanocrystalline structure with an average grain size of about 5.0-6.5 nm. 11. The method of any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor, without an intervening N precursor therebetween, and subsequently exposing the semiconductor substrate to an N precursor. 12. The method of any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor as a first precursor, followed by a silicon (Si) precursor, followed by a N precursor as a last precursor. 13. The method of any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases comprises exposing the semiconductor substrate to a Ti precursor during a Ti precursor exposure time, followed by a silicon (Si) precursor during a Si precursor exposure time, followed by a N precursor, and wherein the ratio of Ti precursor exposure time to Si precursor exposure time is between 0 and 1. 14. The method of any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases comprises exposing the semiconductor substrate to a Ti precursor for a Ti precursor exposure time of 0 to 1 seconds, followed by a silicon (Si) precursor for a Si precursor exposure time of 1 to 10 seconds. 15. The method of any of the previous embodiments, wherein the ratio of the number of times of the first deposition phase to the number of times of the second deposition phase is greater than 10. 16. The method according to any of the previous embodiments, wherein the ratio of the number of times of the first deposition phase to the number of times of the second deposition phase is 10 to 50. 17. The method of any of the above embodiments, wherein the semiconductor substrate has a hole with an aspect ratio greater than 5 and forming the diffusion barrier is such that the ratio of the thickness of the diffusion barrier formed in the bottom 25% of the hole's height to the thickness of the diffusion barrier formed in the top 25% of the hole's height is greater than 0.80. 18. The method of any of the previous embodiments, wherein exposing the semiconductor substrate to one or more first deposition phases comprises exposing the semiconductor substrate to a N precursor as a final precursor. 19. The method of any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases comprises exposing the semiconductor substrate to a Ti precursor as an initial precursor. 20. The method of any of the previous embodiments, wherein exposure of the semiconductor substrate to a Ti precursor as the first precursor of the second deposition phase immediately follows exposure of the semiconductor substrate to a N precursor as the last precursor of the first deposition phase, without an intervening exposure to a N precursor. 21. The method of any of the previous embodiments, wherein exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases comprises exposing under a pressure in a reaction chamber greater than 1 Torr. 22. The method of any of the previous embodiments, wherein the semiconductor substrate has a surface topography such that the ratio of a surface area of ​​the semiconductor substrate exposed to one or more first deposition phases and one or more second deposition phases to a corresponding surface area of ​​an unpatterned semiconductor substrate is greater than 2. 23. The method of embodiment 22, wherein the surface topography comprises a plurality of trenches or vias having an aspect ratio greater than 5. 24. The method of embodiment 22 or 23, wherein the number and size of the trenches or vias are such that the surface area ratio is greater than 20. 25. The method of any of the previous embodiments, wherein exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases comprises exposing at a pressure in a reaction chamber of 3 to 10 Torr. 26. The method of any of the previous embodiments, wherein the ratio of the number of the first deposition phase to the number of the second deposition phase is such that the diffusion barrier is at least partially amorphous. 27. The method of any of the above embodiments, wherein the Si precursor is a compound selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH2Cl, Si2Cl6, and Si3Cl8. 28. The method of any of the above embodiments, wherein the Ti precursor comprises TiCl4. 29. The method of any of the above embodiments, wherein the N precursor is NH3. 30. The method of any of the previous embodiments, wherein exposing the semiconductor substrate to a vapor deposition cycle is performed at a substrate temperature of 400°C to 600°C. 31. The method of any of the previous embodiments, wherein the number of times of the first deposition phase and the number of times of the second deposition phase are provided such that the diffusion barrier layer is substantially uniform across the depth of the layer. 32. The method of any of the above embodiments, wherein the semiconductor substrate has a plurality of holes formed thereon, the holes having dielectric sidewall surfaces and an aspect ratio greater than 5, and forming the diffusion barrier includes lining surfaces of the holes. 33. The method of embodiment 32, wherein lining the surface of the hole includes conformally lining such that the ratio of the thickness of the diffusion barrier layer formed in the lower 25% of the hole's height to the thickness of the diffusion barrier layer formed in the upper 25% of the hole's height is greater than 0.8. 34. The method of embodiment 32 or 33, wherein the number and size of the holes are such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 35. The method of any one of embodiments 32-34, wherein lining the surfaces of the holes comprises exposing the semiconductor substrate to a vapor deposition cycle at a pressure in a reaction chamber of 3-10 Torr. 36. The method of any of the above embodiments, wherein the hole further comprises an exposed semiconductor bottom surface. 37. A semiconductor structure comprising: a semiconductor substrate having a plurality of trenches or vias formed thereon, the trenches or vias having dielectric sidewall surfaces and an aspect ratio greater than 5; a diffusion barrier layer comprising TiSiN conformally lining a surface of said trench or via, said diffusion barrier layer having a Si content of 2.7-9 atomic % and an elastic modulus of 290-350 GPa. 38. A semiconductor structure comprising: a semiconductor substrate having a plurality of trenches or vias formed thereon, the trenches or vias having dielectric sidewall surfaces and an aspect ratio greater than 5; a diffusion barrier layer comprising TiSiN conformally lining a surface of said trench or via, said diffusion barrier layer having a Si content of 2.7-9 atomic % and a hardness of 20-40 GPa. 39. A semiconductor structure comprising: a semiconductor substrate having a plurality of trenches or vias formed thereon, the trenches or vias having dielectric sidewall surfaces and an aspect ratio greater than 5; a diffusion barrier layer comprising TiSiN conformally lining a surface of said trench or via, said diffusion barrier layer having a Si content of 2.7-9 atomic % and a crystalline texture exhibiting a ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in a grazing incidence X-ray diffraction spectrum of 0.4-4.5. 40. A semiconductor structure comprising: a semiconductor substrate having a plurality of trenches or vias formed thereon, the trenches or vias having dielectric sidewall surfaces and an aspect ratio greater than 5; a diffusion barrier layer comprising TiSiN conformally lining a surface of said trench or via, said diffusion barrier layer having a Si content of 2.7-9 atomic % and a nanocrystalline structure with an average grain size of about 5.0-6.5 nm. 41. The semiconductor structure of any one of embodiments 37 to 41, wherein the Si content is 2.7 to 7 atomic %. 42. The semiconductor structure of any one of embodiments 37-41, wherein the trench or via has an aspect ratio of greater than 10. 43. A semiconductor structure described in any of embodiments 37 to 42, wherein the diffusion barrier layer conformally lining the surface is provided such that the ratio of the thickness of the diffusion barrier layer formed in the lower 25% of the height of the trench or via to the thickness of the diffusion barrier layer formed in the upper 25% of the height of the trench or via is greater than 0.8. 44. A semiconductor structure described in any of embodiments 37 to 43, wherein the area density of the trenches or vias is such that the ratio of the surface area on which the diffusion barrier is formed to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 45. The semiconductor structure of any one of embodiments 37-44, wherein the surface area ratio is greater than 100. 46. ​​The semiconductor structure of any one of embodiments 37-45, wherein the diffusion barrier layer has a root mean square surface roughness of less than about 0.3 nm. 47. The semiconductor structure of any one of embodiments 37-46, wherein the trench or via further has a semiconducting bottom surface. 48. The semiconductor structure of any one of embodiments 37-47, wherein the trench or via is filled with tungsten or copper. 49. The semiconductor structure of any one of embodiments 37-44, wherein the diffusion barrier has a thickness of about 1-10 nm. 49. The semiconductor structure of any one of embodiments 37-48. 50. The semiconductor structure of any one of embodiments 37 to 49, wherein the trench or via has a width of about 10 to 1000 nm. 51. The semiconductor structure of any one of embodiments 37-50, wherein the diffusion barrier layer has an electrical resistivity of less than about 1600 μΩ·cm.

[0145] Although the invention has been described herein with reference to particular embodiments, these embodiments do not serve to limit the invention, but are set forth for purposes of illustration. It will be apparent to those skilled in the art that modifications and improvements can be made without departing from the spirit and scope of the invention.

[0146] Such simple modifications and improvements of the various embodiments disclosed herein are within the scope of the disclosed technology, the particular scope of the disclosed technology will be further defined by the appended claims.

[0147] In the above, it will be understood that the features of any one of the embodiments can be combined with or substituted for the features of any other one of the embodiments.

[0148] Unless the context clearly requires otherwise, words such as "comprise," "consisting," "include," "including," and the like, throughout this specification and claims, are to be construed in an inclusive sense, i.e., "including but not limited to," as opposed to an exclusive or exhaustive sense. The term "coupled," as generally used herein, refers to two or more elements that are directly connected or connected through one or more intermediate elements. Similarly, the term "connected," as generally used herein, refers to two or more elements that are directly connected or connected through one or more intermediate elements. Additionally, in this specification, the terms "herein," "above," "below," and similar terms refer to this specification as a whole, rather than to any particular portion of this specification. Additionally, in the above description of the preferred embodiment of the invention, words using the singular or plural number may include the plural or singular number, respectively, as the context permits. The word "or" referring to a list of two or more items includes all of the following interpretations of the word: any of the items in the list, every item in the list, and any combination of the items in the list.

[0149] Additionally, as used herein, particularly conditional terms such as "can," "could," "might," "may," "eg," "for example," "such as," and the like, are generally intended to convey that certain embodiments include certain features, elements and / or conditions and that other embodiments do not include them, unless otherwise specified or understood within the context in which they are used. Thus, such conditional terms are generally not intended to imply that features, elements and / or conditions are in any way required by one or more embodiments or that these features, elements and / or conditions may or may not be included in or implemented in any particular embodiment.

[0150] Although specific embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in other various forms, and various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, although functions are shown in a given mechanism, in alternative embodiments, similar functions may be performed with different components and / or sensor topologies, and some functions may be deleted, moved, added, subdivided, combined, and / or modified. Each of these functions may be implemented in a variety of different ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The various functions and processes described above may be implemented independently of each other or may be combined in various ways. All possible combinations and subcombinations of features of the present disclosure are intended to be within the scope of the present disclosure.

Claims

1. 1. A method of forming a diffusion barrier comprising TiSiN, the method comprising: exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases in alternating and non-overlapping fashion; exposing the semiconductor substrate to the one or more first deposition phases comprises alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and the exposing the semiconductor substrate to one or more second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor with no intervening exposure to an N precursor, and subsequently exposing the semiconductor substrate to an N precursor.

2. 2. The method of claim 1, wherein exposing the semiconductor substrate to the first deposition phase comprises exposing the semiconductor substrate to an N precursor as a final precursor in each of the first deposition phases.

3. 3. The method of claim 2, wherein exposing the semiconductor substrate to the second deposition phases comprises exposing the semiconductor substrate to a Ti precursor as a first precursor in each of the second deposition phases.

4. 4. The method of claim 3, wherein exposing the semiconductor substrate to a Ti precursor as the first precursor of each of the second deposition phases immediately follows exposing the semiconductor substrate to a N precursor as the last precursor of an immediately preceding first deposition phase, without intervening exposure to any other precursor.

5. 5. The method of claim 4, wherein exposing the semiconductor substrate to one or more of a Ti precursor, a Si precursor, and a N precursor during the one or more second deposition phases comprises undersaturating a surface of the semiconductor substrate.

6. The method of claim 1 , wherein the method is carried out without the assistance of a plasma.

7. 7. The method of claim 6, wherein exposing the semiconductor substrate to the one or more first deposition phases and the one or more second deposition phases comprises exposing under a pressure in a reaction chamber greater than 1 Torr.

8. 2. The method of claim 1, wherein in the second deposition phase, a ratio of exposure times of exposing the semiconductor substrate to a Si precursor and exposing the semiconductor substrate to a Ti precursor is between 2 and 130.

9. 2. The method of claim 1, wherein a ratio of exposure times of exposing the semiconductor substrate to a Ti precursor in the second deposition phase and exposing the semiconductor substrate to a Ti precursor in the first deposition phase is between 3 and 34.

10. 2. The method of claim 1, wherein a ratio of exposure times of exposing the semiconductor substrate to an N precursor in the second deposition phase and exposing the semiconductor substrate to an N precursor in the first deposition phase is between 5 and 50.

11. 1. A method of forming a diffusion barrier comprising TiSiN, the method comprising: exposing the semiconductor substrate to one or more first deposition phases and one or more second deposition phases in alternating and non-overlapping fashion; exposing the semiconductor substrate to the one or more first deposition phases comprises alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and The method, wherein exposing the semiconductor substrate to the one or more second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by a N precursor.

12. The method of claim 11 , wherein the method is carried out without the assistance of a plasma.

13. 13. The method of claim 12, wherein exposing the semiconductor substrate to the one or more first deposition phases and the one or more second deposition phases comprises exposing under a pressure in a reaction chamber greater than 1 Torr.

14. 12. The method of claim 11, wherein exposing the semiconductor substrate to the first deposition phases comprises exposing the semiconductor substrate to an N precursor as a final precursor in each of the first deposition phases.

15. 15. The method of claim 14, wherein exposing the semiconductor substrate to the second deposition phases comprises exposing the semiconductor substrate to a Ti precursor as a first precursor in each of the second deposition phases.

16. 16. The method of claim 15, wherein exposing the semiconductor substrate to a Ti precursor as the first precursor of each of the second deposition phases immediately follows exposing the semiconductor substrate to a N precursor as the last precursor of an immediately preceding first deposition phase, without intervening exposure to any other precursor.

17. 17. The method of claim 16, wherein exposing the semiconductor substrate to one or more of a Ti precursor, a Si precursor, and a N precursor in the one or more second deposition phases comprises undersaturating a surface of the semiconductor substrate.

18. 20. The method of claim 17, wherein exposing the semiconductor substrate to one or more of a Ti precursor, a Si precursor, and a N precursor in the one or more second deposition phases comprises undersaturating a surface of the semiconductor substrate.

19. 12. The method of claim 11, wherein the semiconductor substrate has a hole with an aspect ratio greater than 50, and forming the diffusion barrier comprises lining a surface of the hole such that a ratio of a thickness of the diffusion barrier formed in the lower 25% of the hole's height to a thickness of the diffusion barrier formed in the upper 25% of the hole's height is greater than 0.

9.

20. 12. The method of claim 11, wherein the diffusion barrier formed using the method has a resistivity of 2000 μΩ·cm or less.

21. 12. The method of claim 11 , wherein the diffusion barrier formed using the method has a resistivity that is at least 500 μΩ cm less than a diffusion barrier formed using the same method except for exposing the semiconductor substrate to a Ti precursor as part of the one or more second deposition phases.

22. 12. The method of claim 11, wherein the semiconductor substrate is exposed to a Si precursor for a duration greater than 3 seconds and the semiconductor substrate is exposed to a Ti precursor in the second deposition phase for a duration less than 2 seconds.

23. 12. The method of claim 11, wherein exposing the semiconductor substrate to the one or more first deposition phases and the one or more second deposition phases comprises exposing under a pressure in a reaction chamber greater than 1 Torr.

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