Frequency divider based on ring oscillator

Abstract

An aspect of the disclosure relates to a ring oscillator (RO) divider configured to divide an input clock by a programmable division ratio to generate an output clock. In this regard, the RO divider receives an input clock and, in response to the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time and outputs a second clock from an output of one stage of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another aspect, each stage includes two PMOS FETs and one NMOS FET.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority to pending U.S. application Ser. No. 17 / 361,217, entitled "RING OSCILLATOR BASED FREQUENCY DIVIDER," filed June 28, 2021, which is assigned to the assignee of the present application and is expressly incorporated by reference herein as if fully set forth below and for all applicable purposes.

[0002] Aspects of the present disclosure relate generally to frequency dividers, and more particularly, to frequency dividers based on ring oscillators. [Background technology]

[0003] A frequency divider is used to divide an input clock to generate an output clock. Some frequency dividers may be part of the feedback path of a phase locked loop (PLL) to divide an output clock generated by a voltage controlled oscillator (VCO) to generate a feedback clock for phase-frequency comparison with a reference clock. The frequency of the VCO's output clock is controlled based on the comparison such that the feedback clock is substantially phase and frequency synchronized with the reference clock. In such cases, the frequency divider may be called a frequency prescaler. In other cases, the frequency divider may not be part of the feedback path of the PLL and may simply be used to divide the clock. Summary of the Invention [Means for solving the problem]

[0004] The following presents a simplified summary of one or more implementations to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0005] One aspect of the present disclosure relates to an apparatus that includes a ring of N cascaded inverter stages, where N is a positive integer, and a control circuit that includes a set of N independent outputs respectively coupled to the ring of N cascaded inverter stages.

[0006] Another aspect of the disclosure relates to an apparatus, the apparatus including a ring of N cascaded inverter stages, N being a positive integer, each stage of the ring of N cascaded inverter stages comprising a first p-channel metal oxide semiconductor field effect transistor (PMOS FET), a second PMOS FET, and an n-channel metal oxide semiconductor field effect transistor (NMOS FET) coupled in series between a first voltage rail and a second voltage rail, where for an integer “i” ranging from 0 to N−1, the second PMOS FET of the i-th cascaded inverter stage includes a gate coupled to a drain of the second PMOS FET of the i-1(mod N)-th cascaded inverter stage, and for an integer “i” ranging from 0 to N−1, the first PMOS FET of the i-th cascaded inverter stage includes a gate coupled to a drain of the second PMOS FET of the i-2(mod N)-th cascaded inverter stage, and the NMOS FET of the i-th cascaded inverter stage includes a gate coupled to a drain of the second PMOS FET of the i-2(mod N)-th cascaded inverter stage. Each of the FETs includes a gate for receiving the first clock, and a drain of one of the second PMOS FETs of the N cascaded inverter stages outputs a second clock.

[0007] Another aspect of the disclosure relates to a method including receiving a first clock, enabling each stage of a ring of N cascaded inverter stages substantially one at a time in response to the first clock in a first mode, where N is a positive integer, and outputting a second clock from an output of a stage of the ring of N cascaded inverter stages.

[0008] Another aspect of the present disclosure relates to a wireless communication device, the wireless communication device includes a phase-locked loop (PLL) including a frequency prescaler, the frequency prescaler including a ring of N cascaded inverter stages, where N is a positive integer, and circuitry for enabling each stage of the ring of N cascaded inverters substantially one at a time based on a first clock, where an output of one of the N cascaded inverter stages produces a second clock, a local oscillator (LO) configured to generate a LO signal based on the second clock, and an upconverter or downconverter configured to upconvert or downconvert a frequency of the first signal, respectively, to generate the second signal based on the LO signal.

[0009] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed, and the description of the implementations is intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0010] [Figure 1A] 1 is a schematic diagram of an exemplary ring oscillator (RO) divider according to one embodiment of the present disclosure. [Figure 1B] 1B is a timing diagram of an example operation of the ring oscillator (RO) divider of FIG. 1A according to another aspect of the disclosure. [Figure 2A] 1 is a schematic diagram of another exemplary ring oscillator (RO) divider in accordance with another aspect of the present disclosure. [Figure 2B]FIG. 2B is a timing diagram of an exemplary sequence for turning on each stage of a ring of N cascaded inverter stages of the ring oscillator (RO) of FIG. 2A substantially one at a time, according to another aspect of the disclosure. [Figure 3A] FIG. 4 is a schematic diagram of an exemplary control circuit according to another aspect of the present disclosure. [Figure 3B] 3B is a timing diagram of an example operation of the control circuit of FIG. 3A according to another aspect of the disclosure. [Figure 3C] FIG. 4 is a schematic diagram of an exemplary control circuit according to another aspect of the present disclosure. [Figure 4A] 1 is a schematic diagram of another exemplary ring oscillator (RO) divider in accordance with another aspect of the present disclosure. [Figure 4B] 4B is a timing diagram of an example operation of the ring oscillator (RO) divider of FIG. 4A according to another aspect of the disclosure. [Figure 5A] 1 is a schematic diagram of another exemplary ring oscillator (RO) divider in accordance with another aspect of the present disclosure. [Figure 5B] 1 is a table of various operating frequencies and supply voltages according to another aspect of the present disclosure. [Figure 6] 1 is a schematic diagram of another exemplary ring oscillator (RO) divider in accordance with another aspect of the present disclosure. [Figure 7] FIG. 1 is a schematic diagram of another exemplary ring oscillator (RO) divider in accordance with another aspect of the present disclosure. [Figure 8] 1 is a schematic diagram of another exemplary ring oscillator (RO) divider in accordance with another aspect of the present disclosure. [Figure 9] 1 is a schematic diagram of another exemplary ring oscillator (RO) divider in accordance with another aspect of the present disclosure. [Figure 10A] 2 is a block diagram of an example phase-locked loop (PLL) according to another aspect of the disclosure. [Figure 10B] FIG. 10B is a block diagram of an example N divider of the phase-locked loop (PLL) of FIG. 10A according to another aspect of the disclosure. [Figure 11] 2 is a block diagram of another example phase-locked loop (PLL) in accordance with another aspect of the present disclosure. [Figure 12] FIG. 13 is a block diagram of an example wireless communication device according to another aspect of the present disclosure. [Figure 13] 4 is a flow diagram of an example method for dividing a first clock to generate a second clock according to another aspect of the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The detailed description set forth below, together with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0012] 1A is a schematic diagram of an exemplary ring oscillator (RO) divider 100 according to one aspect of the disclosure. The RO divider 100 is configured to divide an input clock (CLK_IN) to generate an output clock (CLK_OUT) with a division ratio N defined as the frequency of the input clock CLK_IN relative to the frequency of the output clock CLK_OUT.

[0013] In this example, RO divider 100 includes a ring of N (e.g., N is 5, but may be other positive integers) cascaded inverter stages 105-0 to 105-4, each including a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET) between an upper voltage rail VDD and a lower voltage rail (e.g., ground). In this example and in the embodiments described below, N may represent a positive integer greater than or equal to 2 or greater than or equal to 3. For example, embodiments in which N is equal to 3, 5, or 7 are described below, but in the embodiments described, N may be other positive integers greater than or equal to 2 or greater than or equal to 3. Cascaded inverter stage 105-0 includes PMOS FET MP0 and NMOS FET MN0. Cascaded inverter stage 105-1 includes PMOS FET MP1 and NMOS FET MN1. Cascaded inverter stage 105-2 includes a PMOS FET MP2 and an NMOS FET MN2. Cascaded inverter stage 105-3 includes a PMOS FET MP3 and an NMOS FET MN3. Cascaded inverter stage 105-4 includes a PMOS FET MP4 and an NMOS FET MN4. In a round robin or modulo-N (modN) scheme, for every stage (e.g., for an integer "i" from 0 to N-1), the gate of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain of the PMOS FET of the i-1(modN)-th cascaded inverter stage.

[0014] The RO divider 100 includes an input buffer 110 with an input for receiving the input clock CLK_IN and an output coupled to the gates of NMOS FETs MN0 through MN4. The RO divider 100 further includes an output buffer 130 with an input coupled to the drain of PMOS FET MP4 or the output n4 of the cascaded inverter stage 105-4 and an output for producing the output clock CLK_OUT. As shown, the set of N cascaded inverter stages 105-0 through 105-4 includes respective inputs at the gates of PMOS FETs MP0 through MP4, respectively. The set of N cascaded inverter stages 105-0 through 105-4 includes respective outputs at the drains of PMOS FETs MP0 through MP4, or at nodes n0 through n4, respectively.

[0015] 1B illustrates a timing diagram of an example operation of RO divider 100 according to another aspect of the disclosure. The x-axis or horizontal axis of the timing diagram represents time. The y-axis or vertical axis of the timing diagram represents, from top to bottom, the input clock CLK_IN and the voltages V at the outputs n0 to n4 of cascaded inverter stages 105-0 to 105-4, respectively. n0 From V n4 The left side of the timing diagram (between times t1 and t7) represents an example of normal operation of RO divider 100. The right side of the timing diagram (between times t8 and t12) represents an example of abnormal operation of RO divider 100.

[0016] RO divider 100 operates by turning on all of NMOS FETs MN0 through MN4 substantially simultaneously (enabling all of inverter stages 105-0 through 105-4) in response to each rising or high state of the input clock CLK_IN. For example, referring to the left side of the timing diagram, a rising edge of the input clock CLK_IN at time t1 turns on NMOS FET MN0 while PMOS FET MP0 is off, thereby supplying a high voltage V n0 (e.g., at VDD) to low (e.g., ground). n0When goes low, at time t2, PMOS FET MP1 turns on and voltage V n1 The next rising edge of the input clock CLK_IN at time t3 turns on the NMOS FET MN2 and the PMOS FET MP2 is off, so the high voltage V n2 Set low to apply voltage V n2 When goes low, at time t4, the PMOS FET MP3 turns on and the voltage V n3 The rising edge of the input clock CLK_IN at time t5 turns on the NMOS FET MN4 and the PMOS FET MP4 is off, so the high voltage V n4 Set low to apply voltage V n4 When goes low, at time t6, the PMOS FET MP0 turns on and the voltage V n0 Set the voltage V n0 Note that the half period of spans 2.5 periods of the input clock CLK_IN. Thus, RO divider 100 divides the input clock CLK_IN by 5 or by N.

[0017] In this implementation, the voltage at one node must remain high even if the corresponding NMOS FET is turned on by the input clock CLK_IN. For example, as shown in the timing diagram, the voltage V n2 and V n4 remain high from time t1 to t2 during the high state of the input clock CLK_IN when the corresponding NMOS FETs MN2 and MN4 are on. This is because the corresponding PMOS FETs MP2 and MP4 are on during this time interval t1 to t2. In order to keep the output voltage high when the corresponding NMOS FET is on, the PMOS FETs may be made stronger or larger than the NMOS FETs. As a result, in some embodiments, RO divider 100 may have several disadvantages.

[0018] First, larger sized PMOS FETs may introduce additional parasitic capacitance and smaller NMOS FETs may have weaker pull-downs, both of which may add significant delay to the division operation of RO divider 100. Thus, RO divider 100 may have a maximum operating frequency limited by the size disparity between PMOS FETs and NMOS FETs. Second, since PMOS FETs and NMOS FETs are turned on substantially simultaneously, a large current may flow through the cascaded inverter stages. Thus, RO divider 100 may consume a large amount of power. Third, at low input frequencies, each cascaded inverter stage of RO divider 100 may generate multiple pull-downs to pull down the corresponding output voltage from a high state (e.g., VDD) to a low state (e.g., ground). Thus, the minimum operating frequency of RO divider 100 may also be affected. The right side of the timing diagram illustrates this issue.

[0019] For example, the rising edge of the input clock CLK_IN at time t9 turns on the NMOS FET MN0, supplying a high voltage V n0 (e.g., at VDD) to low (e.g., ground). n0 When goes low, the PMOS FET MP1 turns on and supplies the voltage V n1 Then, the voltage V n1 When goes high, the voltage V n2 goes low to some extent (e.g., VDD / 2), all of which occurs during the high state of the input clock CLK_IN, between times t9 and t10. This is because the frequency FIN of the input clock CLK_IN is low enough that the corresponding period is longer than the voltage V n0 From V n2 Then, the next rising edge of the input clock CLK_IN at time t11 turns on the NMOS FET MN2, causing the voltage V n2 Pull the voltage V completely low (for example, to ground). n2When goes low, the PMOS FET MP3 turns on and voltage V n3 Set the voltage V n3 When goes high, PMOS FET MP4 turns off and NMOS FET MN4 is connected to voltage V n4 As shown, the voltage V n0 Since the half period of is about 1.5 to 2 clock periods of the input clock CLK_IN, RO divider 100 did not divide the input clock CLK_IN by exactly 5. Therefore, RO divider 100 may have a minimum operating frequency.

[0020] 2A illustrates a schematic diagram of an exemplary ring oscillator (RO) divider 200 according to another aspect of the disclosure. In summary, rather than the input clock CLK_IN turning on the NMOS FETs of the cascaded inverter stages substantially simultaneously, as in RO divider 100, RO divider 200 includes a control circuit that is driven by the input clock CLK_IN to turn on the NMOS FETs substantially one at a time (or in a substantially non-overlapping manner). Thus, NMOS FETs MN0 through MN4 are each driven by a different control voltage V generated by the control circuit. A From V E Powered by.

[0021] More specifically, RO divider 200 includes a ring of N (e.g., N=5 in the illustrated example) cascaded inverter stages 205-0 to 205-(N-1), each stage including a PMOS FET coupled in series with an NMOS FET between an upper voltage rail VDD and a lower voltage rail (e.g., ground). For example, cascaded inverter stage 205-0 includes PMOS FET MP0 and NMOS FET MN0. Cascaded inverter stage 205-1 includes PMOS FET MP1 and NMOS FET MN1. Cascaded inverter stage 205-2 includes PMOS FET MP2 and NMOS FET MN2. Cascaded inverter stage 205-3 includes PMOS FET MP3 and NMOS FET MN3. Cascaded inverter stage 205-4 includes PMOS FET MP4 and NMOS FET MN4. In the round robin or modN scheme, for every stage (e.g., for an integer i from 0 to N-1), the gate of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain of the PMOS FET (and the drain of the NMOS FET) of the i-1(modN)-th cascaded inverter stage.

[0022] RO divider 200 further includes a control circuit 210 including an input for receiving input clock CLK_IN and a set of N (e.g., N=5) independent outputs coupled to the gates of NMOS FETs MN0 through MN4, respectively. Control circuit 210 controls a set of control voltages V at the set of N independent outputs to turn on each of the set of NMOS FETs MN0 through MN4 substantially one at a time (e.g., in a substantially non-overlapping manner). A From V E As shown, RO divider 200 further includes an output buffer 230 that includes an input coupled to an output (e.g., node n4) of one of the cascaded inverter stages (e.g., stage 205-4) and an output at which the output clock CLK_OUT is produced.

[0023] 2B illustrates a timing diagram of an exemplary sequence for turning on NMOS FETs MN0 through MN4 of a set of N cascaded inverter stages 205-0 through 205-4 substantially one at a time according to another embodiment of the disclosure. The x-axis or horizontal axis of the timing diagram represents time. The y-axis or vertical axis of the timing diagram represents, from top to bottom, an input clock CLK_IN, a control voltage V A , V C , V E , V B , and V D , as well as voltages Vn0 to Vn4 at nodes n0 to n4 (outputs) of cascaded inverter stages 205-0 to 205-4, respectively.

[0024] As shown, in response to a first positive pulse of the input clock CLK_IN, the control circuit 210 increases the control voltage V A During the first positive pulse of the input clock CLK_IN, the control circuit 210 generates another control voltage V B From V E Therefore, the control voltage V A turns on the NMOS FET MN0 of the cascaded inverter stage 205-0, but the control voltage V B From V E maintain the NMOS FETs MN1 to MN4 of the cascaded inverter stages 205-1 to 205-4 off, respectively. Thus, during a first positive pulse of the input clock CLK_IN, the control circuit 210 enables the first cascaded inverter stage 205-0 but disables the remaining cascaded inverter stages 205-1 to 205-4 (e.g., enables one cascaded inverter stage at a time). In response to the turned-on NMOS FET MN0, the output voltage V of the first cascaded inverter stage 205-0 increases as indicated by the arrowed line. n0 Also, the voltage V n0In response to the first cascaded inverter stage 205-1 going low, the output voltage V n1 gets high.

[0025] Similarly, in response to a second positive pulse of the input clock CLK_IN, the control circuit 210 increases the control voltage V C While generating the other control voltage V A , V B , V D , and V E Therefore, the control voltage V C turns on the NMOS FET MN2 of the cascaded inverter stage 205-2, but the control voltage V A , V B , V D , and V E maintain NMOS FETs MN0 to MN1 and MN3 to MN4 off, respectively. Thus, during the second positive pulse of the input clock CLK_IN, the control circuit 210 enables cascaded inverter stage 205-2 but disables the remaining cascaded inverter stages 205-0, 205-1, 205-3, and 205-4 (e.g., enables one cascaded inverter stage at a time). In response to NMOS FET MN2 being turned on, the output voltage V of cascaded inverter stage 205-2 increases as indicated by the arrowed line. n2 Also, the voltage V n2 In response to going low, the output voltage V n3 gets high.

[0026] In a similar manner, only the other cascaded inverter stages 205-4, 205-1, and 205-3 are turned on or enabled during the third, fourth, and fifth positive pulses of the input clock CLK_IN, respectively, as indicated by the corresponding arrowed lines. As shown, the output voltage V of cascaded inverter stage 205-0 isn0 has a period extending from the first positive pulse to the fifth positive pulse of the input clock CLK_IN. n1 From V n4 is the output voltage V n0 Therefore, the frequency of the output clock CLK_OUT is 1 / 5 or (1 / N) of the frequency of the input clock CLK_IN (in other words, the division ratio is 5 or N).

[0027] The N cascaded inverter stages are enabled substantially one at a time, so that the PMOS FET and NMOS FET of each stage are not turned on at the same time. Thus, the PMOS FETs do not need to be configured stronger or larger than the NMOS FETs to implement ratio logic as in RO divider 100, and in some embodiments of RO divider 200, each of the PMOS FETs MP0 to MP(N-1) is approximately the same size as the respective NMOS FETs MN0 to MN(N-1). This reduces the large parasitic capacitance of the PMOS FETs, as well as the relatively weak pull-down of the NMOS FETs. This may reduce the propagation delay of the cascaded inverter stages 205-0 to 205-(N-1), allowing RO divider 200 to operate at higher frequencies and potentially with less power consumption. At low frequencies, the NMOS FETs are able to fully pull down the corresponding output voltage during each clock period, since there is no turned-on PMOS FET to resist the pull-down. Thus, RO divider 200 may eliminate the multiple pull-downs per clock period that may occur in RO divider 100.

[0028] It should be understood that the timing diagram shown in Figure 2B is only an example. For example, while the diagram in Figure 2B corresponds to a configuration in which a high pulse on the clock triggers a certain operation of the divider (e.g., enabling one of the stages), in other embodiments, the operation (e.g., enabling one of the stages) may be triggered by the clock being a low value or transitioning to a low value. One such embodiment is described below with respect to Figures 3A and 3B. Other such embodiments are described below with respect to subsequent figures.

[0029] 3A illustrates a schematic diagram of an exemplary control circuit 300 according to another aspect of the disclosure. The control circuit 300 may be one exemplary implementation of the control circuit 210 discussed previously. The control circuit 300 includes an input buffer 305 and a set of N (e.g., N=5 in the illustrated example) NOR gates 320-0 to 320-4. The input buffer 305 includes an input for receiving an input clock CLK_IN. The set of NOR gates 320-0 to 320-4 includes respective first inputs coupled to an output of the input buffer 305. The set of NOR gates 320-0 to 320-4 includes respective second inputs coupled to output nodes n3, n4, n0, n1, and n2 of the cascaded inverter stages 205-3, 205-4, 205-0, 205-1, and 205-2, respectively. The set of NOR gates 320-0 to 320-4 includes a set of outputs, at which a control voltage V A , V B , V C , V D , and V E are generated and coupled to the gates of NMOS FETs MN0 through MN4 of cascaded inverter stages 205-0 through 205-4, respectively.

[0030] In general, for "i" from 0 to N-1, the second input of the i-th NOR gate (e.g., 320-i) is coupled to the drain (output) of the PMOS (and NMOS) FETs of the i-2 (modN)-th cascaded inverter stage. Considering some examples, for i=0, NOR gate 320-0 has a second input (output voltage V n3 ) coupled to output node n4 of cascaded inverter stage 205-4, where i-2(mod5)=0-2(mod5)=-2(mod5)=3. Similarly, for i=1, NOR gate 320-1 includes a second input (for receiving output voltage V n4 ) coupled to output node n0 of cascaded inverter stage 205-0, where i-2(mod5)=1-2(mod5)=-1(mod5)=4. For i=2, NOR gate 320-2 includes a second input (for receiving output voltage V n0 ), where i-2(mod5)=2-2(mod5)=0(mod5)=0, and so on.

[0031] In another embodiment (not shown), for "i" from 0 to N-1, the second input of the i-th NOR gate (e.g., 320-i) is coupled to the drain (output) of the PMOS (and NMOS) FETs of the i-4 (modN)-th cascaded inverter stage. For example, for i=0, NOR gate 320-0 has a second input (output voltage V n1 , where i-4(mod5)=0-4(mod5)=-4(mod5)=1. In some embodiments, for "i" from 0 to N-1, the second input of the i-th NOR gate is coupled to the drain (output) of the PMOS (and NMOS) FET of the iE(modN)-th cascaded inverter stage, where E represents a positive even integer less than N.

[0032] 3B illustrates a timing diagram of an example operation of the control circuit 300 according to another aspect of the disclosure. The x-axis or horizontal axis of the timing diagram represents time. The y-axis or vertical axis of the timing diagram represents, from top to bottom, the input clock CLK_IN, the control voltage V A , V C , V E , V B , and V D , as well as voltages Vn0 to Vn4 at output nodes n0 to n4 of cascaded inverter stages 205-0 to 205-4, respectively.

[0033] As shown, NOR gate 320-0 of control circuit 300 detects the first negative pulse of the input clock CLK_IN and the output voltage V n3 In response to V being in a low logic state, the control voltage V is asserted with a positive pulse substantially simultaneous with the first negative pulse of the input clock CLK_IN, as indicated by the arrowed line. A During the first negative pulse of the input clock CLK_IN, other NOR gates 320-1 to 320-4 of the control circuit 300 generate other control voltages V B From V E Therefore, the control voltage V A turns on the NMOS FET MN0 of the cascaded inverter stage 205-0, but the control voltage V B From V E keeps NMOS FETs MN1 to MN4 off. In response to NMOS FET MN0 being turned on, the output voltage V n0 Also, the voltage V n0 In response to going low, the output voltage V of the cascaded inverter stage 205-1 n1 gets high.

[0034] Similarly, NOR gate 320-2 of control circuit 300 detects a second negative pulse of input clock CLK_IN and an output voltage V n0In response to V being in a low logic state, the control voltage V is asserted with a positive pulse substantially simultaneous with a second negative pulse of the input clock CLK_IN, as indicated by the arrowed line. C During the second negative pulse of the input clock CLK_IN, the other NOR gates 320-0, 320-1, 320-3, and 320-4 of the control circuit 300 generate other control voltages V A , V B , V D , and V E Therefore, the control voltage V C turns on the NMOS FET MN2 of the cascaded inverter stage 205-2, but the control voltage V A , V B , V D , and V E keeps NMOS FETs MN0, MN1, MN3, and MN4 off. In response to NMOS FET MN2 being turned on, the output voltage V n2 Also, the voltage V n2 In response to going low, the output voltage V n3 gets high.

[0035] In a similar fashion, only the other cascaded inverter stages 205-4, 205-1, and 205-3 are turned on or enabled during the third, fourth, and fifth negative pulses of the input clock CLK_IN, as shown by the corresponding arrowed lines. As shown, the output voltage V of the first cascaded inverter stage n0 has a period extending from the first negative pulse to the fifth negative pulse of the input clock CLK_IN. n1 From V n4 is the output voltage V n0 Therefore, the frequency of the output clock CLK_OUT is 1 / 5 or 1 / N of the frequency of the input clock CLK_IN (in other words, the division ratio is 5 or N).

[0036] The voltage V at the second input of NOR gates 320-0 to 320-4 no From V n4 Note that ROUT is in a low logic state substantially one clock period before NOR gates 320-0 through 320-4 generate their respective positive pulses. Thus, control circuit 300 does not introduce any additional delay into the division operation of RO divider 200.

[0037] 3C illustrates a schematic diagram of an example control circuit 350 according to another aspect of the disclosure. The control circuit 350 may be one example implementation of the previously discussed control circuit 210. In contrast to the control circuit 300, as described, for example, in connection with FIG. 2, the control circuit 350 is configured such that a high pulse of the clock triggers some operation of the divider (e.g., enabling one of the stages 205 of the divider 200).

[0038] The control circuit 350 includes an input buffer 305 and a set of N (e.g., N=5 in the illustrated example) AND gates 370-0 through 370-4. The input buffer 305 includes an input for receiving an input clock CLK_IN. The set of AND gates 370-0 through 370-4 include respective first inputs coupled to an output of the input buffer 305. The set of AND gates 370-0 through 370-4 include respective second inputs coupled to output nodes n2, n3, n4, n0, and n1 of the cascaded inverter stages 205-2, 205-3, 205-4, 205-0, and 205-1, respectively. The set of AND gates 370-0 through 370-4 includes a set of outputs at which a control voltage V A , V B , V C , V D , and V E are generated and coupled to the gates of NMOS FETs MN0 through MN4 of cascaded inverter stages 205-0 through 205-4, respectively.

[0039] In general, for "i" from 0 to N-1, the second input of the ith AND gate (e.g., 370-i) is coupled to the drain (output) of the PMOS (and NMOS) FETs of the ith (modN) cascaded inverter stage. Considering some examples, for i=0, the AND gate 370-0 has a second input (output voltage V n2 ) for receiving output voltage V n3 ) coupled to output node n4 of cascaded inverter stage 205-4, where i-2(mod5)=1-3(mod5)=-2(mod5)=3. For i=2, AND gate 370-2 includes a second input (for receiving output voltage V n4 ), where i-3(mod 5) = 2-3(mod 5) = -1(mod 5) = 4, and so on.

[0040] In another embodiment (not shown), for "i" from 0 to N-1, the second input of the ith AND gate (e.g., 370-i) is coupled to the drain (output) of the PMOS (and NMOS) FETs of the i-1 (modN)th cascaded inverter stage. For example, for i=0, AND gate 370-0 has a second input (output voltage V n4 , where i-1(mod5)=0-1(mod5)=-1(mod5)=4. In some embodiments, for "i" from 0 to N-1, the second input of the i-th AND gate is coupled to the drain (output) of the PMOS (and NMOS) FET of the iR(modN)-th cascaded inverter stage, where R represents a positive odd integer less than N-1.

[0041] FIG. 4A shows a schematic diagram of an exemplary RO divider 400 according to another embodiment of the present disclosure. The RO divider 400 is similar to the RO divider 200, but includes a pre-discharge NMOS FET to configure the RO divider 400 to an initial state by explicitly pre-discharging the output nodes of every other N cascaded inverter stage at start-up. Furthermore, to balance the load of each cascaded inverter stage, a dummy NMOS FET is coupled to the output node that does not have a pre-discharge NMOS FET of the remaining cascaded inverter stage. In addition, the RO divider 400 is configured to divide by 5 or divide by 4 (e.g., divide by N or divide by N-1) based on a division ratio mode signal. Thus, the RO divider 400 may be referred to as a dual modulus divider, or more generally, a multi-modulus divider. Although not explicitly shown in some subsequent figures, pre-discharge FETs and dummy FETs may be implemented in any of the RO dividers illustrated and / or described in this application.

[0042] More specifically, RO divider 400 includes a ring of N (e.g., N=5 in the illustrated embodiment) cascaded inverter stages 405-0 through 405-4, each stage comprising a PMOS FET coupled in series with an NMOS FET between an upper voltage rail VDD and a lower voltage rail (e.g., ground). As in RO divider 200, for every stage (e.g., for an integer i from 0 to N-1), the gate of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain of the PMOS FET (and to the drain of the series NMOS FET) of the i-1(modN)-th cascaded inverter stage.

[0043] In addition to the PMOS FETs coupled in series with the NMOS FETs, the cascaded inverter stages 405-1 and 405-3 each include an NMOS FET MN7 and MN9 coupled between the drains of the PMOS FETs MP1 and MP3 and a lower voltage rail (e.g., ground). The NMOS FETs MN7 and MN9 include gates for receiving a pre-discharge signal P. The cascaded inverter stages 405-0, 405-2, and 405-4 each include dummy NMOS FETs MN6, MN8, and MN10 coupled between the drains of the PMOS FETs MP0, MP2, and MP4 and a lower voltage rail (e.g., ground) such that the loads presented to the output nodes n0 to n4 of the cascaded inverter stages 405-0 to 405-4 are substantially balanced. The dummy NMOS FETs MN6, MN8, and MN10 include gates coupled to the lower voltage rail (e.g., ground) to turn off these devices. A dummy FET, as defined herein, is a dummy FET that is normally turned off, for example, by setting the gate-source voltage to zero or below the threshold voltage of the dummy FET.

[0044] To achieve the dual modulus functionality, the cascaded inverter stage 405-4 further couples the gate of the NMOS FET MN4 to a corresponding output of the control circuit 410 (e.g., V E output) or the drain (output n3) of the PMOS FET MP3 of the previous cascaded inverter stage 405-3. In general, a jth cascaded inverter stage, including such one or more switching devices to achieve dual or multi-modulus functionality, includes an NMOS FET having its gate coupled to either the jth output of the control circuit 410 or the drain of the PMOS FET of the j-1th cascaded inverter stage based on the state of the one or more switching devices, where "j" is a positive integer less than or equal to N-1 or zero.

[0045] More specifically, in the cascaded inverter stage 405-4 in the illustrated embodiment, the one or more switching devices include a PMOS FET MP6 coupled between the drain of the PMOS FET MP3 and the gate of the NMOS FET MN4 of the previous cascaded inverter stage 405-3. The one or more switching devices are further coupled to the V E and an NMOS FET MN11 coupled between the output and the gate of NMOS FET MN4. PMOS FET MP6 and NMOS FET MN11 include gates coupled together to receive a division ratio mode signal. It will be understood that other configurations of one or more switching devices configured to perform the functions described herein may be implemented (e.g., as illustrated / described with respect to subsequent figures).

[0046] When the division ratio mode signal is in a high logic state (e.g., VDD), the PMOS FET MP6 is turned off and the NMOS FET MN11 is turned on. Thus, the gate of the NMOS FET MN4 is connected to the V E 1. When the divider mode signal is in a low logic state, PMOS FET MP6 is turned on and NMOS FET MN11 is turned off. Thus, the gate of NMOS FET MN4 is coupled to the drain of PMOS FET MP3 of the previous cascaded inverter stage 405-3, and the last stage 405-4 receives the clock phase or V associated with the previous cascaded inverter stage 405-3. D, so that the RO divider 400 operates as a divide-by-4 (a divide-by-(N-1)) divider. For example, in this configuration, the last stage 405-4 may be configured to function as an inverter. Thus, the division ratio, which is the frequency of the input clock to the frequency of the output clock, is greater when the gate of the NMOS FET of the jth cascaded inverter stage is coupled to the jth output of the control circuit compared to when the gate of the NMOS FET of the jth cascaded inverter stage is coupled to the drain of the PMOS FET of the j-1th cascaded inverter stage.

[0047] RO divider 400 further includes a control circuit 410, which may be similar to control circuits 210, 300, or 350 discussed in detail above, but includes additional logic circuitry for asserting / deasserting a pre-discharge signal P in response to a start signal and the input clock CLK_IN. Similar to RO divider 200, RO divider 400 further includes an output buffer 430 that includes an input coupled to the output (e.g., node n0) of one of the cascaded inverter stages (e.g., stage 405-0) and an output at which the output clock CLK_OUT is produced.

[0048] 4B illustrates a timing diagram of an example operation of the RO divider 400 according to another aspect of the disclosure. The x-axis or horizontal axis of the timing diagram represents time. The y-axis or vertical axis of the timing diagram represents, from top to bottom, the start signal, the pre-discharge signal P, the input clock CLK_IN, the control voltage V A , V C , V E , V B , and V D , and the voltages V at the output nodes n0 to n4 of the cascaded inverter stages 405-0 to 405-4, respectively. n0 From V n4 In this example, the division ratio mode signal is in a low state, configuring RO divider 400 to divide by four.

[0049] For example, when the start signal is deasserted before the pulse "0" of the input clock CLK_IN, the control circuit 410 insulates the input clock CLK_IN from the logic circuit (e.g., NOR gate) of the control circuit 410. In response to the assertion of the start signal and the rising edge or pulse "0" of the input clock CLK_IN, the control circuit 410 asserts the pre-discharge signal P (e.g., sets it to the high logic state) to turn on the NMOS FETs MN7 and MN9. As indicated by the arrow lines in the timing diagram, this clearly discharges the nodes n1 and n3, as indicated by the fact that the voltages V n1 and V n3 are in the low logic state.

[0050] In response to the rising edge of the pulse "1" of the input clock CLK_IN, the control circuit 410 deasserts the pre-discharge signal P to turn off the NMOS FETs MN7 and MN9, enabling the nodes n1 and n3 to reach appropriate voltage levels in response to the frequency division operation. Also, in response to the rising edge of the pulse "1", the control circuit 410 generates a control voltage V A with a pulse substantially simultaneous with the pulse "1" of the input clock CLK_IN. In response to the high state of the control voltage V A , the NMOS MN0 turns on, the output voltage V n0 of the cascaded inverter stage 405-0 goes low, and when the output voltage V n0 goes low, the PMOS FET MP1 of the cascaded inverter stage 405-1 turns on and the output voltage V n1 goes high.

[0051] In response to the rising edge of the pulse "2", the control circuit 410 generates a control voltage V C with a pulse substantially simultaneous with the pulse "2" of the input clock CLK_IN. In response to the high state of the control voltage V C , the NMOS MN2 turns on, the output voltage V n2 of the cascaded inverter stage 405-2 goes low, and the output voltage V n2When goes low, the PMOS FET MP3 of the cascaded inverter stage 405-3 turns on, and when the PMOS FET MP3 turns on, the output voltage V n3 goes high and the output voltage V n3 When goes high, the cascaded inverter stage 405-4 is coupled to the node n3 in a divide-by-four mode, so that the NMOS FET MN4 of the cascaded inverter stage 405-4 is turned on, and when the NMOS FET MN4 is turned on, the output voltage V n4 goes low and the output voltage V n4 When the PMOS FET MP0 is turned on, the output voltage V n0 becomes high.

[0052] In response to the rising edge of pulse "3", the control circuit 410 increases the control voltage V with a pulse substantially coincident with pulse "3" of the input clock CLK_IN. B Generates a control voltage V B In response to the high state of n1 goes low and the output voltage V n1 When goes low, the PMOS FET MP2 of the cascaded inverter stage 405-2 turns on, thereby increasing the output voltage V n2 becomes high.

[0053] In response to the rising edge of pulse "4", the control circuit 410 increases the control voltage V D Generates a control voltage V D In response to the high state of n3 goes low and the output voltage V n3 When goes low, the PMOS FET MP4 of the cascaded inverter stage 405-4 turns on, causing the output voltage Vn4 to go high.

[0054] In response to the rising edge of pulse "5", the division process shown with respect to pulses 1 through 4 is repeated. As shown, the output voltage V of cascaded inverter stage 405-0 n0 has a period equal to substantially four periods of the input clock CLK_IN, so that RO divider 400 performs a divide-by-four operation. In the divide-by-four mode, control circuit 410 increases or decreases the control voltage V A , V C , V B , and V D Note that in some embodiments, the control voltage V E Since is not used in the divide-by-four mode, the control circuit 410 controls the control voltage V E Skip (or V E 3A (or as shown in FIG. 3C when a clock high trigger is implemented) and may be configured to pass an input mode signal to the divider 400 or generate a mode signal for the divider 400 based on a mode control input to the control circuit 410. In some embodiments, for example, a first input of the NOR gate 320-4 is selectively coupled to either the output of the input buffer 305 or a constant input voltage (e.g., VDD, such that the NOR gate 320-4 outputs a low voltage) based on a mode signal or a mode control input received at the control circuit. In other embodiments, the pulse is generated by the NOR gate 320-4 but is substantially blocked by the NMOS FET MN11.

[0055] 5A illustrates a schematic diagram of another exemplary RO divider 500 according to another embodiment of the present disclosure. RO divider 500 is similar to RO divider 400 and includes many of the same elements, indicated by the same labels and reference numbers, but with a most significant digit (MSD) of "5" instead of "4". Subsequent figures also use this numbering convention. RO divider 500 further includes a low-dropout (LDO) voltage regulator 550 for selectively varying a supply voltage Vreg (the difference in supply voltage between a first voltage rail and a second voltage rail) provided to a ring of N (e.g., N=5 in the illustrated example) cascaded inverter stages 505-0 to 505-4 using a programmable reference voltage Vref.

[0056] More specifically, the LDO voltage regulator 550 includes an operational amplifier 555 and a PMOS FET MP7. The PMOS FET MP7 is coupled between an upper voltage rail VDD and a mid-voltage rail at the sources of the PMOS FETs MP0 to MP4 of the cascaded inverter stages 505-0 to 505-4. The operational amplifier 555 includes a first (e.g., negative) input for receiving a programmable voltage Vref, a second (e.g., positive) input coupled to the mid-voltage rail, and an output coupled to the gate of the PMOS FET MP7. The LDO voltage regulator 550 is configured to generate and control a supply voltage Vreg at the mid-voltage rail for the cascaded inverter stages 505-0 to 505-4 such that the supply voltage Vreg is substantially the same as the programmable reference voltage Vref.

[0057] The supply voltage Vreg effectively sets the range of operating frequencies of the RO divider 500. For example, if a relatively high frequency range or the highest operating frequency is desired, the programmable voltage Vref may be set relatively high to provide a relatively high supply voltage Vreg for the cascaded inverter stages 505-0 to 505-4. The higher supply voltage Vreg reduces the individual delays of each of the cascaded inverter stages 505-0 to 505-4, allowing the RO divider 500 to operate better at higher frequencies. If a relatively low frequency range or the lowest operating frequency is desired, the programmable reference voltage Vref may be set relatively low to provide a relatively low supply voltage Vreg for the cascaded inverter stages 505-0 to 505-4. The lower supply voltage Vreg increases the individual delays of each of the cascaded inverter stages 505-0 to 505-4, allowing the RO divider 500 to operate better at lower frequencies. In some configurations, the shown configuration of LDO voltage regulator 550 allows for an improvement in the minimum operating frequency without compromising the maximum operating frequency of RO divider 500. LDO voltage regulator 550 may be coupled between a voltage rail (e.g., VDD) and an inverter stage of any of the RO dividers illustrated and / or described in this application (e.g., divider 200 or any of the dividers in subsequent figures).

[0058] 5B illustrates a table of example operating frequencies and supply voltages according to another aspect of the disclosure. The top row represents the supply voltage Vreg in volts (V), the second row from the top represents an example minimum operating frequency when the divider 500 operates in a divide-by-4 mode with the supply voltages in the top row, the third row from the top represents an example maximum operating frequency when the divider 500 operates in a divide-by-4 mode with the supply voltages in the top row, the fourth row from the top represents an example minimum operating frequency when the divider 500 operates in a divide-by-5 ​​mode with the supply voltages in the top row, and the fifth row from the top represents an example maximum operating frequency when the divider 500 operates in a divide-by-5 ​​mode with the supply voltages in the top row.

[0059] As the table shows, the operating frequency and / or range can be changed by adjusting the supply voltage Vreg. In some examples, when the supply voltage is 0.5V, the minimum operating frequency for divide-by-4 and divide-by-5 ​​may be about 17.5GHz, and the maximum operating frequency for divide-by-4 and divide-by-5 ​​may be about 25GHz and 32.5GHz, respectively. Thus, the operating frequency range at Vreg of 0.5V may be at least 17.5GHz to 25GHz, and in some cases, depending on the mode, may extend to 32.5GHz in the example shown. Considering another example, when the supply voltage is 0.7V, the minimum operating frequency for divide-by-4 and divide-by-5 ​​may be about 27.5GHz to 30GHz, and the maximum operating frequency for divide-by-4 and divide-by-5 ​​may be about 47.5GHz and 55GHz, respectively. Thus, the operating frequency range at Vreg of 0.5V may be at least 27.5GHz to 47.5GHz, and in some cases, depending on the mode, may extend to 55GHz in the example shown.

[0060] Thus, it can be seen that the minimum operating frequency of the example shown in FIG. 5B can be improved from 30 GHz to 17.5 GHz (e.g., in divide-by-5 ​​mode) or less by adjusting the supply voltage. Furthermore, it can be seen that in some embodiments, the maximum operating frequency can go as high as 55 GHz or more. Thus, the minimum operating frequency and / or the maximum operating frequency (and frequency range) can be improved, for example, without one adversely affecting the other. In some such embodiments, this improved performance can be achieved with the same or lower power consumption compared to known configurations. Furthermore, in some embodiments, the improved operating frequency can be achieved at a smaller process node compared to known configurations. For example, the embodiments described herein can enable operation at relatively high frequencies (e.g., 50-55 GHz or more) using 8 nm or less processes (e.g., 8 nanometer (nm) FinFET process technology using 8LPP (Low Power Plus) or the like).

[0061] It will be understood that the values ​​described herein are merely examples of some embodiments, and that frequencies, ranges, supply voltages, process nodes, etc. may vary from those shown in Figure 5B and / or described herein. Additionally, it will be understood that, although some examples are shown in Figure 5B, such examples are not necessarily linked or associated with the examples shown in Figure 5A. For example, elements of Figure 5B may be associated with a similar configuration as dividers 200 and / or 400.

[0062] 6 shows a schematic diagram of another exemplary ring oscillator (RO) divider 600 according to another embodiment of the present disclosure. In the previous example, the RO divider was configured to perform a divide-by-5 ​​or divide-by-4 because the RO divider has five cascaded inverter stages, which result in a divide ratio of 5 or N when all operate with separate clocks, and a divide ratio of 4 or N-1 when the last stage is bypassed or operates with the phase of the clock provided to the previous stage. However, it should be understood that the RO divider does not need to be limited to N being 5, but can be any other positive integer.

[0063] For example, RO divider 600 includes a ring of N (N=3 in the illustrated embodiment) cascaded inverter stages 605-0 to 605-2, each including a PMOS FET (e.g., MP0 to MP2) coupled in series with an NMOS FET (e.g., MN0 to MN2) between an upper voltage rail VDD and a lower voltage rail (e.g., ground). In a round robin or modN fashion, for every stage (e.g., for "i" from 0 to N-1), the gate (input) of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain (output) of the PMOS FET of the i-1 (modN)-th cascaded inverter stage. RO divider 600 includes an output buffer 630 including an input coupled to the output of one of the cascaded inverter stages, such as output node n2 of cascaded inverter stage 605-2, and an output at which the output clock CLK_OUT is produced.

[0064] RO divider 600 further includes a control circuit 610 including an input buffer 615 and a set of N (N=3) NOR gates 620-0 through 620-2. Input buffer 615 includes an input for receiving an input clock CLK_IN. The set of NOR gates 620-0 through 620-2 include respective first inputs coupled to an output of input buffer 615. The set of NOR gates 620-0 through 620-2 include respective second inputs (voltage V n1 , V n2 , and V n0 The set of NOR gates 620-0 through 620-2 includes a set of outputs, at which a control voltage V A , V B , and V C are generated and coupled to the gates of NMOS FETs MN0 to MN2 of cascaded inverter stages 605-0 to 605-2, respectively.

[0065] In general, for "i" from 0 to N-1, the second input of the ith NOR gate (e.g., 620-i) is coupled to the drain (output node) of the PMOS FET of the i-2(modN)th cascaded inverter stage. For example, for i=0, NOR gate 620-0 has a second input (output voltage V n1 ) coupled to output node n2 of cascaded inverter stage 605-2, where i-2(mod3)=0-2(mod3)=-2(mod3)=1. Similarly, for i=1, NOR gate 620-1 includes a second input (for receiving output voltage V n2 ) coupled to output node n0 of cascaded inverter stage 605-0, where i-2(mod3)=1-2(mod3)=-1(mod3)=2. For i=2, NOR gate 620-2 includes a second input (for receiving output voltage V n0, where i-2(mod3)=2-2(mod3)=0(mod3)=0.

[0066] However, it will be understood that the control circuit 610 may be implemented in configurations other than that shown in Figure 6. For example, the control circuit 610 may be implemented with AND gates rather than NOR gates, and the second input of the i-th AND gate, for "i" from 0 to N-1, may be coupled to the drain (output node) of the PMOS FET of the i-1(modN)-th cascaded inverter stage.

[0067] The cascaded inverter stage 605-2 couples the gate of the NMOS FET MN2 to a corresponding V C A switching device 625 (e.g., single-pole-double-throw (SPDT)) for selectively coupling to the output or the drain (output) of the PMOS FET MP1 of the previous (i-1th) cascaded inverter stage 605-1. More specifically, the SPDT switching device 625 has a pole coupled to the gate of the NMOS FET MN2, a first throw (labeled “1”) coupled to the drain (output) of the PMOS FET MP1 of the previous (i-1th) cascaded inverter stage 605-1, and a second throw (labeled “2”) coupled to the V C Includes a second throw (labeled "2") coupled to the output.

[0068] The SPDT switching device 625 includes a control input for receiving a division ratio mode signal. When the mode signal sets the SPDT device 625 to couple the pole to the second throw, the RO divider 600 divides the frequency of the input clock CLK_IN by 3 or N to generate the output clock CLK_OUT (e.g., the division ratio is 3). When the mode signal sets the SPDT device 625 to couple the pole to the first throw, the RO divider 600 divides the frequency of the input clock CLK_IN by 2 or N-1 to generate the output clock CLK_OUT (e.g., the division ratio is 2). Thus, in this example, the RO divider 600 is a dual modulus divider or a multi-modulus divider.

[0069] 7 illustrates a schematic diagram of another exemplary ring oscillator (RO) divider 700 according to another aspect of the disclosure. The RO divider 700 is an example implementation of N=7 cascaded inverter stages. Specifically, the RO divider 700 includes a ring of N (N=7 in the illustrated example) cascaded inverter stages 705-0 through 705-6, each of which includes a PMOS FET (e.g., MP0 through MP6) coupled in series with an NMOS FET (e.g., MN0 through MN6) between an upper voltage rail VDD and a lower voltage rail (e.g., ground). In a round robin or modN fashion, for every stage (e.g., for "i" from 0 to N-1), the gate (input) of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain (output) of the PMOS FET of the i-1 (modN)-th cascaded inverter stage. The RO divider 700 includes an output buffer 730 that includes an input coupled to the output of one of the cascaded inverter stages, such as output node n6 of the cascaded inverter stage 705-6, and an output at which the output clock CLK_OUT is produced.

[0070] RO divider 700 further includes a control circuit 710 including an input buffer 715 and a set of N (N=7) NOR gates 720-0 through 720-6. Input buffer 715 includes an input for receiving an input clock CLK_IN. The set of NOR gates 720-0 through 720-6 includes respective first inputs coupled to an output of input buffer 715. The set of NOR gates 720-0 through 720-6 includes respective second inputs coupled to output nodes n5, n6, n0, n1, n2, n3, and n4 of cascaded inverter stages 705-5, 705-6, 705-0 through 705-4, respectively. The set of NOR gates 720-0 through 720-6 includes a set of outputs at which a control voltage V A From V G are generated and coupled to the gates of NMOS FETs MN0 to MN6 of cascaded inverter stages 705-0 to 705-6, respectively.

[0071] In general, as previously discussed, for "i" from 0 to N-1, the second input of the i-th NOR gate (e.g., 720-i) is coupled to the drain (output node) of the PMOS FET of the i-2(modN)-th cascaded inverter stage. Considering some examples, for i=0, NOR gate 720-0 has a second input (output voltage V n5 ) coupled to output node n6 of cascaded inverter stage 705-6, where i-2(mod 7)=0-2(mod 7)=-2(mod 7)=5. Similarly, for i=1, NOR gate 720-1 includes a second input (for receiving the output voltage V n6 , where i-2(mod 7)=1-2(mod 7)=-1(mod 7)=6. For i=2, NOR gate 720-2 includes a second input (for receiving output voltage V n0 ), where i-2(mod7)=2-2(mod7)=0(mod7)=0, and so on.

[0072] However, it will be understood that the control circuit 710 may be implemented with a configuration other than that shown in FIG. 7. For example, in some embodiments, for "i" from 0 to N-1, the second input of the i-th NOR gate (e.g., 720-i) may be coupled to the drain (output) of the PMOS (and NMOS) FET of the (i-4 (mod N))-th cascaded inverter stage. In some embodiments, for "i" from 0 to N-1, the second input of the i-th NOR gate is coupled to the drain (output) of the PMOS (and NMOS) FET of the (i-E (mod N))-th cascaded inverter stage, where E is an even number and 0 < E < N. As another example, the control circuit 710 may be implemented with AND gates instead of NOR gates. The second input of the i-th AND gate may, in some embodiments, for "i" from 0 to N-1, be coupled to the drain (output node) of the PMOS FET of the (i-1 (mod N))-th cascaded inverter stage, in other embodiments, for "i" from 0 to N-1, be coupled to the drain (output node) of the PMOS FET of the (i-3 (mod N))-th cascaded inverter stage, or in yet other embodiments, for "i" from 0 to N-1, be coupled to the drain (output node) of the PMOS FET of the (i-5 (mod N))-th cascaded inverter stage. In some embodiments, for "i" from 0 to N-1, the second input of the i-th AND gate is coupled to the drain (output) of the PMOS (and NMOS) FET of the (i-R (mod N))-th cascaded inverter stage, where R is an odd number and 0 < R < N.

[0073] The cascaded inverter stage 705-6 controls the gate of the NMOS FET MN6 with the corresponding V of the control circuit 710 GA switching device 725 (e.g., SPDT) may be included for selectively coupling to the output or the drain (output) of the PMOS FET MP5 of the previous (i-1th) cascaded inverter stage 705-5. More specifically, the SPDT switching device 725 has a pole coupled to the gate of the NMOS FET MN6, a first throw (labeled “1”) coupled to the drain (output) of the PMOS FET MP5 of the previous (i-1th) cascaded inverter stage 705-5, and a V G Includes a second throw (labeled "2") coupled to the output.

[0074] The SPDT switching device 725 includes a control input for receiving a division ratio mode signal. When the division ratio mode signal configures the SPDT device 725 to couple the pole to the second throw, the RO divider 700 divides the frequency of the input clock CLK_IN by 7 or N to generate the output clock CLK_OUT (e.g., the division ratio is 7). When the division ratio mode signal configures the SPDT device 725 to couple the pole to the first throw, the RO divider 700 divides the frequency of the input clock CLK_IN by 6 or N-1 to generate the output clock CLK_OUT (e.g., the division ratio is 6). Thus, in this example, the RO divider 700 is a dual modulus divider or a multi-modulus divider.

[0075] 8 shows a schematic diagram of an example multi-modulus RO divider 800 and associated mode table according to another aspect of the disclosure. Previous RO dividers discussed have been either single-divide or dual-modulus dividers, since they provide two selected division ratios, N and N-1. In contrast, RO divider 800 includes N=7 stages, with a subset of stages 4-6 selectively bypassed to achieve additional division ratios 4-6 or N-3-N-1.

[0076] Specifically, RO divider 800 includes a ring of N (N=7) cascaded inverter stages 805-0 through 805-6, each including a PMOS FET (e.g., MP0 through MP6) coupled in series with an NMOS FET (e.g., MN0 through MN6) between an upper voltage rail VDD and a lower voltage rail (e.g., ground). In a round robin or modN fashion, for every stage (e.g., for "i" from 0 to N-1), the gate (input) of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain (output) of the PMOS FET of the i-1 (modN)-th cascaded inverter stage. RO divider 800 includes an output buffer 830 including an input coupled to the output of one of the cascaded inverter stages, such as output node n6 of cascaded inverter stage 805-6, and an output at which the output clock CLK_OUT is produced.

[0077] The RO divider 800 further includes inputs for receiving an input clock CLK_IN and a control voltage V A From V G and a set of N independent outputs for producing, respectively, the set of N independent outputs of the control circuit 810 are coupled to the gates of the NMOS FETs MN0 to MN6 of the cascaded inverter stages 805-0 to 805-6.

[0078] In this example, the cascaded inverter stages 805-4 to 805-6 each correspond to a corresponding V E From V G5. The control circuit 810 includes switching devices 825-2 to 825-0 (e.g., each configured as an SPDT) for selectively coupling the gates of NMOS FETs MN4 to MN6 to the output, or the drains (outputs) of PMOS FETs MP3 to MP5 of a respective previous (i-1th) cascaded inverter stage 805-3 to 805-5. More specifically, the SPDT switching devices 825-2 to 825-0 each include a pole coupled to the gates of NMOS FETs MN4 to MN6, a first throw (labeled “1”) coupled to the drains (outputs) of PMOS FETs MP3 to MP5 of a respective previous (i-1th) cascaded inverter stage 805-3 to 805-5, and a second throw (labeled “2”) coupled to the drains (outputs) of PMOS FETs MP3 to MP5 of a respective previous (i-1th) cascaded inverter stage 805-3 to 805-5. E From V G Includes a second throw (labeled "2") coupled to the output.

[0079] In the embodiment shown, the SPDT switching devices 825-0 through 825-2 switch between different bits MV <0> From MC <2> With reference to the mode table provided in FIG. 8, the bit MC of the mode signal <0> From MC <2> is 000, the RO divider 800 divides the frequency of the input clock CLK_IN by 7 or by N to generate the output clock CLK_OUT (for example, when the division ratio is N DIV (The bit MC of the mode signal is 7.) <0> From MC <2> is 100, the RO divider 800 divides the frequency of the input clock CLK_IN by 6 or N-1 to generate the output clock CLK_OUT (for example, when the division ratio N DIV (The bit MC of the mode signal is 6.) <0> From MC <2> is 110, the RO divider 800 divides the frequency of the input clock CLK_IN by 5 or N-2 to generate the output clock CLK_OUT (for example, when the division ratio N DIV (The bit MC of the mode signal is 5.) <0> From MC <2> is 111, the RO divider 800 divides the frequency of the input clock CLK_IN by 4 or N-3 to generate the output clock CLK_OUT (for example, when the division ratio N DIV(wherein m is 4). In other embodiments (not shown), switching devices 825-0 through 825-2 may each receive separate or independent control signals.

[0080] 9 shows a schematic diagram of another exemplary RO divider 900 according to another aspect of the disclosure. In summary, the RO divider 900 includes cascaded inverter stages configured differently that substantially eliminate the control circuitry of the previous implementation. More specifically, the RO divider 900 includes a ring of N (N=5 in the illustrated example) cascaded inverter stages 905-0 to 905-4, each stage including a first PMOS FET, a second PMOS FET, and an NMOS FET coupled in series between an upper voltage rail VDD and a lower voltage rail (e.g., ground). In other embodiments, more or fewer stages may be implemented.

[0081] For example, cascaded inverter stage 905-0 includes a first PMOS FET MP0A and a second PMOS FET MP0B and an NMOS FET MN0. Cascaded inverter stage 905-1 includes a first PMOS FET MP1A and a second PMOS FET MP1B and an NMOS FET MN1. Cascaded inverter stage 905-2 includes a first PMOS FET MP2A and a second PMOS FET MP2B and an NMOS FET MN2. Cascaded inverter stage 905-3 includes a first PMOS FET MP3A and a second PMOS FET MP3B and an NMOS FET MN3. Cascaded inverter stage 905-4 includes a first PMOS FET MP4A and a second PMOS FET MP4B and an NMOS FET MN4.

[0082] In a round robin or modN fashion, for every stage (e.g., for i from 0 to N-1), the gate of the second PMOS FET of the i-th cascaded inverter stage is coupled to the drain of the second PMOS FET (and the drain of the NMOS FET) of the i-1(modN)-th cascaded inverter stage. In addition, in a round robin or modN fashion, for every stage (e.g., for i from 0 to N-1), the gate of the first PMOS FET of the i-th cascaded inverter stage is coupled to the drain of the second PMOS FET of the i-2(modN)-th cascaded inverter stage. In other embodiments (not shown), in a round robin or modN fashion, for every stage (e.g., for i from 0 to N-1), the gate of the first PMOS FET of the i-th cascaded inverter stage may be coupled to the drain of the second PMOS FET of the i-4(modN)-th cascaded inverter stage.

[0083] The RO divider 900 includes an input buffer 910 including an input for receiving the input clock CLK_IN and an output coupled to the gates of NMOS FETs MN0 through MN4, respectively. Thus, a rising edge or high state of the input clock CLK_IN simultaneously turns on the NMOS FETs MN0 through MN4. However, due to the coupling of the gates of the first PMOS FETs MN0A through MP4A to the output nodes n3, n4, n0, n1, and n2, respectively, the cascaded inverter stages 905-0 through 905-5 are enabled substantially one at a time each clock period. The stages enabled each clock period are those whose first and second PMOS FETs are off.

[0084] In addition, RO divider 900 includes an output buffer 930 including an input coupled to one of the outputs of the N cascaded inverter stages, such as output node n4 of cascaded inverter stage 905-4. Output buffer 930 includes an output at which output clock CLK_OUT is produced. RO divider 900 is configured to divide input clock CLK_OUT by 5 or by N to generate output clock CLK_OUT. Although not shown in FIG. 9, as described with respect to various examples above, RO divider 900 may be implemented as a multi-modulus divider using one or more switching devices.

[0085] 10A illustrates a block diagram of an exemplary phase-locked loop (PLL) 1000 according to another aspect of the disclosure. Any of the previously discussed ring oscillator (RO) dividers may be used in the feedback loop of a PLL such as PLL 1000. In such cases, the RO divider may be referred to as a frequency prescaler with dual or multi-modulus division functionality.

[0086] Specifically, the PLL 1000 includes a phase-frequency detector (PFD) 1010, a charge pump (CP) 1020, a low pass filter (LPF) 1030, a voltage-controlled oscillator (VCO) 1040, and a frequency divider (÷N DIV ) 1050. Divider 1050 may include any of the RO dividers discussed previously. Thus, divider 1050 operates with a division ratio N DIV , is located in the feedback loop of the PLL 1000 to divide the clock Fvco generated by the VCO 1040 to generate the feedback clock Ffb, which can be the CLK_OUT of the divider 1050.

[0087] As discussed further herein, the divider 1050 may be configured to select N DIVThe division ratio mode signal may include a dual modulus divider configured to divide by either 1000=4 or 1000=5. The division ratio mode signal may be generated by a sequence generator, such as a sigma-delta modulator, to achieve fractional division by the divider 1050. For example, if the target division is 4.5, the division ratio mode signal may be a sequence that averages 0.5 (e.g., for half the sequence period, the divider 1050 divides by 5 and for the other half of the sequence period, the divider 1050 divides by 4). If the target division is 4.2, the division ratio mode signal may be a sequence that averages 0.2 (e.g., for 80 percent of the sequence period, the divider 1050 divides by 5 and for 20% of the sequence period, the divider 1050 divides by 4). In other embodiments, the divider 1050 is a single modulus divider.

[0088] The PFD 1010 compares the phase-frequency of the feedback clock Ffb with the phase-frequency of the reference clock Fref to generate a phase-frequency error signal. The CP 1020 charges and discharges a capacitor based on the phase-frequency error signal to generate a charge pump voltage related to the phase-frequency error. The LPF 1030 filters the charge pump voltage to remove high frequency components from it and generates a control voltage for the VCO 1040. The VCO 1040 generates a clock Fvco based on the control voltage. When the loop is locked, the phase-frequency of the feedback signal Ffb is substantially the same as the phase-frequency of the reference clock Fref, and the frequency of the VCO clock Fvco is N times the frequency of the reference clock Fref. DIV It is double.

[0089] FIG. 10B illustrates a block diagram of an example of a divider 1050 of a phase-locked loop (PLL) 1000 according to another aspect of the disclosure. The divider 1050 includes a frequency prescaler 1052 (e.g., DIV4 / 5), which may be configured by any of the RO dividers discussed previously. The frequency prescaler 1052 is thus configured to divide the clock Fvco of the VCO 1040 based on the division ratio mode signal to generate the intermediate clock Fint. The output of the VCO 1040 may thus be the CLK_IN for the divider 1050 / frequency prescaler 1052. The divider 1050 further includes a counter 1054 configured to generate a feedback clock Ffb based on the intermediate clock Fint. The counter 1054 may be a modulo-Q counter, which essentially operates as a divider to divide the intermediate clock Fint by modulo-Q. The CLK_OUT of the prescaler 1052 may be provided to a counter 1054 .

[0090] 11 illustrates a block diagram of another exemplary phase-locked loop (PLL) 1100 according to another aspect of the disclosure. The PLL 1100 is similar to the previously discussed PLL 1000 and includes a phase frequency detector (PFD) 1110, a charge pump 1120, a low pass filter 1130, a voltage controlled oscillator (VCO) 1140, and a divider 1150. As discussed with respect to the PLL 1000, the divider 1150 in the feedback loop of the PLL 1100 determines a first division ratio N based on a first division ratio mode signal. DIV1 The feedback clock Ffb is generated by dividing the frequency of the VCO clock Fvco.

[0091] The PLL 1100 further determines a second division ratio N based on the second division ratio mode signal. DIV2The PLL 1100 includes an additional divider 1160 configured to divide the clock Fvco of the VCO 1140 by CLK_IN to generate the output clock Fout. The divider 1160 may be configured by any of the RO dividers discussed previously. Thus, the output of the VCO 1140 may be the CLK_IN for the divider 1160. In this example, the divider 1160 is not in the feedback loop of the PLL 1100. In some such examples, the divider 1160 is included in a local oscillator (LO) divider, and the CLK_OUT of the divider is provided to another part of the LO or to a mixer. Thus, the RO dividers described herein may be used in many applications and in various functions or locations throughout the device.

[0092] 12 illustrates a block diagram of an example wireless communication device 1200 according to another aspect of the disclosure. As discussed, the RO divider described herein may be used in many applications, including in a transceiver of a wireless communication device such as the wireless communication device 1200. The wireless communication device 1200 includes a digital signal processing core 1202 that includes a set of one or more digital-to-analog converters (DACs) 1204 and 1206 and a set of one or more analog-to-digital converters (ADCs) 1208 and 1210. In some embodiments, the digital signal processing core 1202 may set or adjust a programmable reference voltage Vref.

[0093] The wireless communication device 1200 further includes a set of one or more low pass filters (LPFs) 1212 and 1214, a set of one or more amplifiers 1224 and 1226, an upconverter 1232, a transmitter (Tx) phase locked loop (PLL) 1216, a transmitter (Tx) local oscillator (LO) 1234, a radio frequency (RF) filter 1240, a power amplifier (PA) 1244, a duplexer 1248, and at least one antenna 1250.

[0094] The wireless communication device 1200 further includes a low noise amplifier (LNA) 1246, an RF filter 1242, a downconverter 1238, a receiver (Rx) phase locked loop (PLL) 1218, a receiver (Rx) local oscillator (LO) 1236, a set of one or more amplifiers 1228 and 1230, and a set of one or more low pass filters (LPFs) 1220 and 1222.

[0095] Any of the RO dividers described herein may be used in the transmitter (Tx) PLL 1216 and / or the receiver (Rx) PLL 1218. For example, the transmitter (Tx) LO 1234 may provide a division ratio mode signal to the Tx PLL 1216 to cause the PLL to generate an output clock with a particular frequency. In other examples, the division ratio mode signal may be provided by another component or circuit, for example, the processor / core 1202. The division ratio mode signal controls the division ratio of the RO divider in the Tx PLL 1216. The Tx LO 1234 generates a transmit LO for the upconverter 1232 using the output clock of the Tx PLL 1216.

[0096] Similarly, the receiver (Rx) LO 1236 (or processor / core 1202) may provide a divider mode signal to the Rx PLL 1218 to cause the PLL to generate an output clock with a particular frequency. The divider mode signal controls the division ratio of the RO divider in the Rx PLL 1218. The Rx LO 1236 uses the output clock of the Rx PLL 1218 to generate a receive LO for the downconverter 1238.

[0097] Additionally, any of the RO dividers described herein may be used in the transmitter (Tx) LO 1234 and / or the receiver (Rx) LO 1236. An RO divider may be used in any other circuitry of the wireless device 1200 that implements a divider.

[0098] 13 illustrates a flow diagram of an example method 1300 for dividing a first clock to generate a second clock according to another aspect of the disclosure. The method 1300 includes receiving a first clock (block 1310), enabling each stage of a ring of N cascaded inverter stages substantially one at a time in response to the first clock (block 1320), and outputting a second clock from an output of one stage of the ring of N cascaded inverter stages, where N is a positive integer (block 1330).

[0099] The following provides a summary of aspects of the disclosure.

[0100] Aspect 1: An apparatus including a ring of N cascaded inverter stages, where N is a positive integer, and a control circuit including a set of N independent outputs respectively coupled to the ring of N cascaded inverter stages.

[0101] Aspect 2: The apparatus of aspect 1, wherein the control circuit is configured to generate a set of N control signals at a set of N independent outputs, respectively, in response to a first clock to enable each of the N cascaded inverter stages substantially one at a time, and wherein a second clock is generated at an output of one of the N cascaded inverter stages, and wherein a division ratio of the frequency of the first clock to the frequency of the second clock is an integer less than or equal to N.

[0102] Aspect 3: The apparatus of aspect 2, wherein each stage of the ring of N cascaded inverter stages includes a p-channel metal-oxide-semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal-oxide-semiconductor field effect transistor (NMOS FET) between a first voltage rail and a second voltage rail, each of the NMOS FETs having a gate, the PMOS FET of the i-th cascaded inverter stage includes a gate coupled to a drain of the PMOS FET of the i-1(mod N)-th cascaded inverter stage, for an integer i between 0 and N-1, and a set of N independent outputs of the control circuit are respectively coupled to the gates of the NMOS FETs of the ring of N cascaded inverter stages.

[0103] Aspect 4: The apparatus of aspect 3, wherein the control circuit includes: a set of N NOR gates with outputs each functioning as the set of N independent outputs of the control circuit, where each of the set of N NOR gates includes a first input for receiving a first clock and where the i-th NOR gate includes a second input coupled to a drain of the PMOS FET of the iE(mod N)-th cascaded inverter stage, for i, from 0 to N-1, where E is a positive even number less than N; or a set of N AND gates with outputs each functioning as the set of N independent outputs of the control circuit, where each of the set of N AND gates includes a first input for receiving the first clock and where the i-th AND gate includes a second input coupled to a drain of the PMOS FET of the iR(mod N)-th cascaded inverter stage, for i, from 0 to N-1, where R is a positive odd number less than N.

[0104] Embodiment 5: The apparatus of embodiment 3 or 4, wherein a subset of one or more of the N cascaded inverter stages each includes a switching device for selectively coupling a gate of the NMOS FET of a jth cascaded inverter stage of the subset to either a jth output of the control circuit or a drain of the PMOS FET of a j-1th cascaded inverter stage, for an integer j between 0 and the number of one or more cascaded inverter stages in the subset, the switching device selectively coupling based on a division ratio mode signal.

[0105] Aspect 6: The apparatus of aspect 5, wherein a division ratio of the frequency of the first clock to the frequency of the second clock is greater when the gate of the NMOS FET of the jth cascaded inverter stage is coupled to the jth output of the control circuit than when the gate of the NMOS FET of the jth cascaded inverter stage is coupled to the drain of the PMOS FET of the j-1th cascaded inverter stage.

[0106] Aspect 7: The apparatus of Aspect 5 or 6, wherein the switching device includes a second PMOS FET coupled between a drain of the PMOS FET of the j-1th cascaded inverter stage and a gate of the NMOS FET of the jth cascaded inverter stage, and a second NMOS FET coupled between a gate of the NMOS FET of the jth cascaded inverter stage and a jth output of the control circuit, wherein a gate of the second PMOS FET and a gate of the second NMOS FET are coupled together to receive the division ratio mode signal.

[0107] Example 8: The apparatus of any one of Examples 3 to 7, wherein one or more of every other N cascaded inverter stage includes a second NMOS FET coupled between a drain of a corresponding PMOS FET and a second voltage rail, the second NMOS FET including a gate for receiving a pre-discharge signal.

[0108] Embodiment 9: The apparatus of embodiment 8, wherein one or more of every other N cascaded inverter stages that does not include a second NMOS FET includes a dummy NMOS FET coupled between a corresponding PMOS FET and a second voltage rail, the dummy NMOS including a gate coupled to the second voltage rail.

[0109] Example 10: The apparatus of any one of Examples 1 to 9, wherein the N cascaded inverter stages are coupled between a first voltage rail and a second voltage rail, and further comprising a voltage regulator for selectively varying a difference in supply voltages between the first voltage rail and the second voltage rail.

[0110] Example 11: The apparatus of example 10, wherein the voltage regulator comprises a low dropout (LDO) voltage regulator.

[0111] Example 12: The apparatus of example 11, wherein the LDO voltage regulator includes a PMOS FET coupled between a third voltage rail and the first voltage rail, and an operational amplifier including a first input for receiving a programmable voltage, a second input coupled to the first voltage rail, and an output coupled to a gate of the PMOS FET.

[0112] Example 13: The apparatus of any one of Examples 2 to 12, further comprising a voltage controlled oscillator (VCO) including an output for generating the first clock.

[0113] Example 14: The apparatus of example 13, wherein the ring of N cascaded inverter stages and control circuit is part of a frequency prescaler in a feedback loop of a phase-locked loop (PLL) that includes the VCO.

[0114] Aspect 15: An apparatus including a ring of N cascaded inverter stages, where N is a positive integer, each stage of the ring of N cascaded inverter stages includes a first p-channel metal-oxide semiconductor field effect transistor (PMOS FET), a second PMOS FET, and an NMOS FET coupled in series between a first voltage rail and a second voltage rail, where for an integer i from 0 to N-1, the second PMOS FET of the i-th cascaded inverter stage includes a gate coupled to a drain of the second PMOS FET of the i-1(mod N)-th cascaded inverter stage, where for i from 0 to N-1, the first PMOS FET of the i-th cascaded inverter stage includes a gate coupled to a drain of the second PMOS FET of the i-2(mod N)-th cascaded inverter stage, and The apparatus, wherein each of the FETs includes a gate for receiving a first clock, and a drain of one of the N cascaded inverter stages is coupled to output a second clock.

[0115] Example 16: The apparatus of example 15, further comprising a buffer including an input for receiving the first clock and an output coupled to a gate of each of the NMOS FETs of the ring of N cascaded inverter stages.

[0116] Example 17: The apparatus of example 15 or 16, further comprising: a buffer including an input coupled to a drain of one of the N cascaded inverter stages to output a second clock.

[0117] Aspect 18: The apparatus of any one of aspects 15 to 17, wherein a division ratio of the frequency of the first clock to the frequency of the second clock is an integer less than or equal to N.

[0118] Example 19: The apparatus of any one of examples 15 to 18, further comprising a voltage controlled oscillator (VCO) including an output for generating the first clock.

[0119] Example 20: The apparatus of example 19, wherein the ring of N cascaded inverter stages is part of a frequency prescaler in a feedback loop of a phase-locked loop (PLL) that includes the VCO.

[0120] Aspect 21: A method comprising: receiving a first clock; enabling each stage of a ring of N cascaded inverter stages substantially one at a time in response to the first clock in a first mode, where N is a positive integer; and outputting a second clock from an output of one stage of the ring of N cascaded inverter stages.

[0121] Aspect 22: The method of aspect 21, wherein the step of enabling each of the rings of N cascaded inverter stages substantially one at a time includes the step of turning on field effect transistors (FETs) in the N cascaded inverter stages in response to a set of N pulses of the first clock, respectively.

[0122] Example 23: The method of example 22, wherein each of the respectively turned-on FETs in the N cascaded inverter stages comprises an n-channel metal-oxide-semiconductor field effect transistor (NMOS FET).

[0123] Example 24: The method of example 22, wherein each of the respectively turned-on FETs in the N cascaded inverter stages comprises a p-channel metal-oxide-semiconductor field effect transistor (PMOS FET).

[0124] Aspect 25: The method of any one of aspects 21 to 24, further comprising the step of enabling two or more of the N cascaded inverter stages in response to a same phase of the first clock in the second mode.

[0125] Example 26: The method of example 25, wherein a division ratio of the frequency of the first clock to the frequency of the second clock is greater in the first mode than in the second mode.

[0126] Aspect 27: The method of any one of aspects 21 to 26, further comprising varying a supply voltage to the ring of N cascaded inverter stages to vary a maximum operating frequency or a minimum operating frequency of the first clock.

[0127] Aspect 28: The method of any one of aspects 21 to 27, further comprising operating a voltage controlled oscillator (VCO) to generate the first clock.

[0128] Aspect 29: A wireless communications device comprising: a phase-locked loop (PLL) including a frequency prescaler, the frequency prescaler including a ring of N cascaded inverter stages, where N is a positive integer, and circuitry for enabling each stage of the ring of N cascaded inverters substantially one at a time based on a first clock, where an output of one of the N cascaded inverter stages produces a second clock; a local oscillator (LO) configured to generate a LO signal based on the second clock; and an upconverter or downconverter configured to upconvert or downconvert a frequency of the first signal, respectively, to generate the second signal based on the LO signal.

[0129] Example 30: The wireless communication device of example 29, wherein each of the N cascaded inverter stages includes a PMOS FET coupled in series with an NMOS FET between the first voltage rail and the second voltage rail.

[0130] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications of the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein. [Explanation of symbols]

[0131] 105 Cascaded Inverter Stages 110 Input Buffer 130 Output Buffer 205 Cascaded Inverter Stages 210 Control circuit 230 Output Buffer 305 Input Buffer 320 NOR Gate 370 AND Gate 405 Cascaded Inverter Stages 410 Control circuit 430 Output Buffer 505 Cascaded Inverter Stages 510 Control circuit 550 LDO Voltage Regulator 555 Operational Amplifier 605 Cascaded Inverter Stages 610 Control circuit 615 Input Buffer 620 NOR Gate 625 Switching Devices 630 Output Buffer 705 Cascaded Inverter Stages 710 Control circuit 715 Input Buffer 720 NOR Gate 725 Switching Devices 730 Output Buffer 805 Cascaded Inverter Stages 810 Control circuit 825 Switching Devices 830 Output Buffer 905 Cascaded Inverter Stages 910 Input Buffer 930 Output Buffer 1010 Phase Frequency Detector 1020 Charge Pump 1030 Low Pass Filter 1040 Voltage Controlled Oscillator 1050 frequency divider 1052 Prescaler 1054 Counter 1110 Phase Frequency Detector 1120 Charge Pump 1130 Low-pass filter 1140 Voltage Controlled Oscillator 1150 frequency divider 1160 frequency divider 1202 Digital Signal Processing Core 1204DAC 1206 DAC 1208 ADC 1210 ADC 1212 LPF 1214 LPF 1216TX PLL 1218 RX PLL 1220 LPF 1222 LPF 1224 IFA 1226 IFA 1228 IFA 1230 IFA 1232 Upconverter 1234 TX LO 1236 RX LO 1238 Down Converter 1240 Filter 1242 Filter 1244 PA 1246 LNA 1248 Duplexer 1250 Antenna

Claims

**Claim 1**: A ring oscillator frequency divider, comprising: A ring of N cascaded inverter stages, where N is a positive integer, and each stage of the ring of N cascaded inverter stages includes a first p-channel metal oxide semiconductor field effect transistor (PMOS FET), a second PMOS FET, and an NMOS FET connected in series between a first voltage rail and a second voltage rail. The drain of the first PMOS FET is connected to the source of the second PMOS FET, and the drain of the second PMOS FET is connected to the drain of the NMOS FET. For an integer i from 0 to N - 1, the second PMOS FET of the i-th cascaded inverter stage includes a gate directly connected to the drain of the second PMOS FET of the (i - 1 (mod N))-th cascaded inverter stage. For i from 0 to N - 1, the first PMOS FET of the i-th cascaded inverter stage includes a gate directly connected to the drain of the second PMOS FET of the (i - 2 (mod N))-th cascaded inverter stage. Each of the NMOS FETs includes a gate for receiving a first clock, and the drain of one of the N cascaded inverter stages is coupled to output a second clock having a frequency divided from the first clock. A ring oscillator frequency divider. **Claim 2** The ring oscillator frequency divider according to claim 1, further comprising a buffer including an input for receiving the first clock and an output coupled to each of the gates of the NMOS FETs of the ring of N cascaded inverter stages. **Claim 3** The ring oscillator frequency divider according to claim 1, further comprising a buffer including an input coupled to the drain of one of the N cascaded inverter stages for outputting the second clock. **Claim 4** The ring oscillator frequency divider according to claim 1, wherein the division ratio of the frequency of the first clock to the frequency of the second clock is an integer not exceeding N. **Claim 5** The ring oscillator frequency divider according to claim 1, further comprising a voltage controlled oscillator (VCO) including an output for generating the first clock. **Claim 6** The ring oscillator according to claim 5, wherein the ring of N cascaded inverter stages is part of a frequency prescaler in a feedback loop of a phase-locked loop (PLL) including the VCO. **Claim 7**: A method for dividing a first clock by a second clock, comprising: receiving the first clock by the ring oscillator according to claim 1; outputting the second clock by the ring oscillator. **Claim 8**: A phase-locked loop (PLL) including the ring oscillator according to claim 1; a local oscillator (LO) configured to generate an LO signal based on the second clock; an upconverter or a downconverter configured to upconvert or downconvert the frequency of a first signal, respectively, to generate a second signal based on the LO signal.

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