System and method for power conversion using an LC filter with an additional capacitor - Patents.com

Abstract

Systems and methods for a high efficiency power converter incorporating a half-bridge topology with one or more additional upper and drain-source capacitors. The converter includes a DC voltage terminal and a DC link capacitor coupled across the positive and negative DC terminals of the DC voltage terminal. The converter further includes a pair of power switching elements including a high-side switch and a low-side switch coupled together at a midpoint node. The converter further includes an LC filter having a switched-side inductor, a lower-side capacitor coupled between a second end of the switched-side inductor and the negative DC terminal, and an upper-side capacitor coupled between the second end of the switched-side inductor and the positive DC terminal. The converter may further include a drain-source capacitor coupled across the drain and source terminals of the switch.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Application No. 63 / 226,136, filed July 27, 2021, U.S. Provisional Application No. 63 / 242,840, filed September 10, 2021, U.S. Provisional Application No. 63 / 345,896, filed May 25, 2022, U.S. Provisional Application No. 63 / 351,768, filed June 13, 2022, U.S. Provisional Application No. 63 / 226,059, filed July 27, 2021, U.S. Provisional Application No. 63 / 270,311, filed October 21, 2021, and U.S. Provisional Application No. 63 / 319,122, filed March 11, 2022. Each of these provisional applications is incorporated herein by reference in its entirety.

[0002] (Statement regarding federally funded research) This invention was made with Government support under 1653574 awarded by the National Science Foundation. The Government has certain rights in this invention. [Background technology]

[0003] Various types of power converters are manufactured and used in many industries and situations. Exemplary power converters include alternating current (AC) to direct current (DC) rectifiers, DC-AC inverters, and DC-DC converters. AC-DC rectifiers, also called AC / DC rectifiers, convert AC power to DC power. DC-AC inverters, also called DC / AC inverters, convert DC power to AC power. DC-DC converters, also called DC / DC converters, convert input DC power from a first DC voltage level to a second DC voltage level.

[0004] Power converters can be used for a variety of purposes, such as rectifying AC power from an AC grid source into DC power for charging a battery, or converting DC power from a battery back into AC power to drive a motor or to supply AC power to an AC grid, etc. Additionally, power converters can be found in electric vehicles, engine generators, solar panels, industrial equipment that can be used or connected to in a variety of situations (e.g., to drive motors in industrial equipment), and the like. Summary of the Invention

[0005] A power converter can be described in terms of power conversion efficiency, power density, and cost, among other characteristics. In general, it is desirable to have a power converter with higher power efficiency, higher power density, and lower cost. A highly efficient power converter can convert power (e.g., AC to DC, DC to AC, and / or DC to DC) without significant energy loss. A less efficient power converter experiences higher energy losses during power conversion. Such energy losses may manifest, for example, as heat generated by the power converter while converting power. The power efficiency of a power converter, inductor, or other electronic component is expressed as a percentage between 0 and 100% and may be determined based on the power input to and power output from the component using the following formula:

number

number

[0006] Energy costs, including monetary and environmental costs, continue to be a significant factor across many industries that incorporate power converters. Thus, even small increases (e.g., tenths of a percent) in the power efficiency of a power converter are significant and highly desirable. Similarly, even modest reductions in the materials and size of a power converter can be significant and highly desirable, allowing for reductions in the cost and physical space required to house the power converter in systems that incorporate the power converter.

[0007] Additionally, power converters may include features such as filters to control voltage and current ripple at both the input and output nodes of the power converter. Such ripple can cause undesirable electromagnetic interference (EMI). For example, voltage ripple at the input to a power converter can result in an input current that, if not adequately filtered, can generate high frequency harmonic emissions that can couple into other circuits. Various electromagnetic compatibility (EMC) standards exist to regulate these emissions in power line, information technology, aerospace, and commercial electronic applications.

[0008] Typical EMI reduction solutions come at the expense of increased power converter volume (and therefore reduced power density) and increased cost due to increased component quantity and volume. Other EMI reduction methods include control strategies, layout techniques, and topological solutions. However, these solutions focus on EMI reduction and do not mitigate the problem of capacitor ripple currents present in power converters that utilize large inductor current ripples. Power converters that utilize large inductor current ripples, such as those with variable frequency critical soft switching (VFCSS), can provide power converters with both improved efficiency and power density. However, they may require large filter components that can also withstand these high ripple currents.

[0009] When designing filters for some power converters, the filter capacitance value may be selected to be the minimum value that meets the desired ripple voltage and ripple current. In some cases, the switching frequency can be increased to reduce the ripple voltage and therefore the capacitor and overall filter size. However, at some point, further increases in switching frequency to reduce the physical size of the output filter become ineffective because the capacitor ripple current specification becomes the limiting factor.

[0010] In some embodiments disclosed herein, systems and methods are provided for a power converter having a topology change that reduces both the EMI and total ripple current handling requirements of the power converter without increasing the total capacitance or volume. The topology change may include the addition of a high-side capacitor connecting the input node and the output node. Thus, such systems and methods may include power converters with improved efficiency and power density.

[0011] A power switching element (e.g., a field effect transistor (FET)) of a power converter can experience losses at each switching event. In some embodiments disclosed herein, an additional drain-source capacitor can be coupled across the drain and source terminals of the power switching element to slow the voltage rise during an on-off transition. This slower voltage rise can reduce switching losses of the power switching element. Such systems and methods can thus include power converters with improved efficiency.

[0012] Designing a power converter can be difficult due to the number of adjustable variables, even after a particular topology and control scheme is selected. In some embodiments disclosed herein, a design method or process is provided for identifying and selecting a particular combination of components (e.g., inductors of a particular inductance, capacitors of a particular capacitance) and / or switching frequencies to provide a power converter.

[0013] Moreover, the various systems and methods provided herein may be combined or used independently to provide improvements in power converters.

[0014] In one embodiment, the half-bridge power converter comprises direct current (DC) voltage terminals including a positive DC terminal and a negative DC terminal. The DC voltage terminals are located on a DC side of the power converter. The power converter also includes a DC link capacitor coupled across the positive DC terminal and the negative DC terminal, and a power switching element pair including a high side power switching element coupled to the positive DC terminal and a low side power switching element coupled to the negative DC terminal. The high side power switching element and the low side power switching element are coupled to each other at a midpoint node. The power converter also includes interface terminals including a positive interface terminal and a negative interface terminal. The interface terminals are located on a second interface side of the power converter. The power converter also includes an LC filter including a switch-side inductor coupled at a first end to the midpoint node and a lower side capacitor coupled between a second end of the switch-side inductor and the negative DC terminal. The LC filter also includes an upper side capacitor coupled between the second end of the switch-side inductor and the positive DC terminal.

[0015] In one embodiment, a method of power conversion is introduced. The method includes a first step of receiving an input DC voltage at a direct current (DC) voltage terminal, the DC voltage terminal including a positive dc terminal and a negative dc terminal located on a dc side of the power converter. The method includes a second step of driving a power switching element pair by a controller to convert the input DC voltage to an intermediate output voltage at a midpoint node, the power switching element pair including a high-side power switching element coupled to the positive DC terminal and a low-side power switching element coupled to the negative DC terminal, the high-side power switching element and the low-side power switching element being coupled to each other at the midpoint node. The method includes a third step of filtering the intermediate output voltage with an LC filter to provide a filtered output voltage to an interface terminal, the filtered output voltage being either an AC voltage or a DC voltage, the interface terminal including a positive interface terminal and a negative interface terminal located on a second interface side of the power converter. The LC filter includes a switch-side inductor coupled at a first end to the midpoint node and a lower-side capacitor coupled between a second end of the switch-side inductor and the negative DC terminal. An upper capacitor coupled between the second end of the switched-side inductor and the positive DC terminal.

[0016] In one embodiment, another method of power conversion is introduced. The method includes a first step of receiving an AC input voltage at an interface terminal, the interface terminal including a positive interface terminal and a negative interface terminal located on an interface side of the power converter. The method includes a second step of filtering the AC input voltage by an LC filter to provide a filtered voltage to a mid-point node. The LC filter includes a switch-side inductor coupled at a first end to the mid-point node and a lower-side capacitor coupled between a second end of the switch-side inductor and the negative DC terminal. An upper-side capacitor coupled between the second end of the switch-side inductor and the positive DC terminal. The method includes a third step of driving a power switching element pair by a controller to convert the filtered voltage to a DC output voltage at a DC terminal, the power switching element pair including a high-side power switching element coupled to a positive DC terminal of the DC terminal and a low-side power switching element coupled to a negative DC terminal of the DC terminal, the high-side power switching element and the low-side power switching element being coupled to each other at the mid-point node.

[0017] In one embodiment, a power inverter includes a direct current (DC) voltage input including a positive input terminal and a negative input terminal. The inverter includes a DC input capacitor coupled across the positive input terminal and the negative input terminal. A power switching element pair including a high side power switching element coupled to the positive input terminal and a low side power switching element coupled to the negative input terminal, the high side power switching element and the low side power switching element coupled to each other at a midpoint node. A high side capacitor is coupled across a source and a drain of the high side power switching element and a low side capacitor is coupled across a source and a drain of the low side power switching element. An LC filter including a switch side inductor and a capacitor, the LC filter coupled to the midpoint node and an AC output terminal coupled to the LC filter. An electronic controller configured to drive the power switching element pair with a variable frequency critical soft switching control signal.

[0018] In one embodiment, yet another power conversion method is introduced. The method also includes a first step of receiving an input DC voltage at a direct current (DC) voltage terminal, the DC voltage terminal including a positive DC terminal and a negative DC terminal disposed on a DC side of the power converter. The method also includes a second step of driving a pair of power switching elements by an electronic controller to convert the input DC voltage to an intermediate output voltage at a midpoint node with a variable frequency critical soft switching control signal. The method also includes a pair of power switching elements including a high-side power switching element coupled to the positive DC terminal and a low-side power switching element coupled to the negative DC terminal. The high-side power switching element and the low-side power switching element are coupled to each other at the midpoint node, a high-side capacitor is coupled across a source and a drain of the high-side power switching element, and a low-side capacitor is coupled across a source and a drain of the low-side power switching element. The method includes a third step of filtering the intermediate output voltage by an LC filter and providing a filtered output voltage to an ac output terminal coupled to the LC filter, the filtered output voltage being either an AC voltage or a DC voltage, the interface terminals including a positive interface terminal and a negative interface terminal located on a second interface side of the power converter, and the LC filter is coupled to the midpoint node and includes a switch-side inductor and a capacitor.

[0019] In one embodiment, a method of inverter optimization for a multi-phase inverter including a half bridge and an LC filter for each phase is introduced. The method includes a first step of determining, by an electronic processor, a capacitance of a drain-source capacitor (CDS) coupled across a drain and a source of each power switching element of each pair of power switching elements. The method includes a second step of determining, by the electronic processor, switching energy versus drain current values ​​of the power switching elements of the pair of power switching elements. The method includes a third step of sweeping, by the electronic processor, inductance values ​​of the LC filter inductors (LSW) and switching frequencies of the power switching elements to generate a plurality of potential combinations of sizes of the inductors (LSW), high-side capacitors (CA), and low-side capacitors (CB) of each lc filter, and plotting data points for the calculated losses versus LC filter volume for each potential combination of sizes.

[0020] In one embodiment, a system for inverter optimization for a multi-phase inverter includes a half bridge and an LC filter for each phase. The system also includes an electronic controller including a memory storing instructions and a processor configured to execute the instructions. The instructions cause the electronic controller to determine a capacitance of a drain-source capacitor (CDS) coupled across a drain and a source of each power switching element of each pair of power switching elements, and to determine switching energy versus drain current values ​​of the power switching elements of the pair of power switching elements. The system also sweeps inductance values ​​of the inductors (LSW) of the LC filter and switching frequencies of the power switching elements to generate multiple potential combinations of sizes of the inductors (LSW), high-side capacitors (CA), and low-side capacitors (CB) of each LC filter. The system also plots data points for the calculated losses versus LC filter volume for each potential size combination.

[0021] The above and other aspects and advantages of the present disclosure will become apparent from the following description. In the description, reference is made to the accompanying drawings, which form a part of this specification and show one or more embodiments by way of example. However, these embodiments do not necessarily represent the full scope of the invention, and therefore, reference should be made to the claims and this specification to interpret the scope of the invention. In the following description, like reference numerals are used to refer to like parts from figure to figure. [Brief description of the drawings]

[0022] [Figure 1] 1 illustrates a power converter system according to some embodiments. [Figure 2A] 1 shows a prior art half-bridge converter circuit. [Figure 2B] 1 illustrates a modified half-bridge converter circuit according to some embodiments. [Figure 3A] 2C illustrates a process for decomposing the modified half-bridge topology of FIG. 2B to provide a circuit analysis model. [Figure 3B] 2C illustrates a process for decomposing the modified half-bridge topology of FIG. 2B to provide a circuit analysis model. [Figure 3C] 2C illustrates a process for decomposing the modified half-bridge topology of FIG. 2B to provide a circuit analysis model. [Figure 3D] 2C illustrates a process for decomposing the modified half-bridge topology of FIG. 2B to provide a circuit analysis model. [Figure 3E] 2C illustrates a process for decomposing the modified half-bridge topology of FIG. 2B to provide a circuit analysis model. [Figure 3F] 2C illustrates a process for decomposing the modified half-bridge topology of FIG. 2B to provide a circuit analysis model. [Figure 4] 3A to 3F show waveforms related to the circuit analysis model. [Figure 5A] 2C shows a circuit model of the modified half-bridge topology of FIG. 2B. [Figure 5B]5B shows a current waveform in the circuit model of FIG. 5A. [Figure 5C] 5B shows a current waveform in the circuit model of FIG. 5A. [Figure 5D] 5B shows a current waveform in the circuit model of FIG. 5A. [Figure 6] 1 shows experimental and simulated data waveforms for a half-bridge power converter circuit. [Figure 7] 1 shows experimental and simulated data waveforms for a half-bridge power converter circuit. [Figure 8] 1 shows experimental and simulated data waveforms for a half-bridge power converter circuit. [Figure 9] 1 shows experimental and simulated data waveforms for a half-bridge power converter circuit. [Figure 10] 1 shows experimental and simulated data waveforms for a half-bridge power converter circuit. [Figure 11] 1 illustrates a process of power conversion according to some embodiments. [Figure 12] 4 illustrates a timing diagram for controlling switches using soft switching in accordance with some embodiments. [Figure 13] 4 illustrates another process of power conversion according to some embodiments. [Figure 14] 1 illustrates a multi-phase power converter according to some embodiments. [Figure 15] 1 illustrates a cascaded half-bridge power converter according to some embodiments. [Figure 16] 1 illustrates timing diagrams and boundary conditions for soft switching according to some embodiments. [Figure 17] FIG. 2 illustrates a control diagram for controlling a pair of switching elements of a power converter in accordance with some embodiments. [Figure 18] 4 illustrates another control diagram for controlling a pair of switching elements of a power converter in accordance with some embodiments. [Figure 19]1 illustrates a power converter incorporating an upper capacitor and a drain-source capacitor in accordance with some embodiments. [Figure 20] 4 illustrates current, voltage, and power waveforms in a power converter according to some embodiments. [Figure 21] 1 illustrates a process for optimizing a power inverter according to some embodiments. [Figure 22A] 1 illustrates a plot of time, capacitance, and switching frequency according to some embodiments. [Figure 22B] 1 illustrates a plot of switching losses versus current according to some embodiments. [Diagram 23] 1 illustrates a Pareto frontier of points for combinations of inductance and switching frequency according to some embodiments. [Figure 24] 1 illustrates a process for sweeping inductance values ​​and switching frequencies to determine potential combinations of LC filter components and their characteristics, according to some embodiments. [Diagram 25] 1 illustrates a process for sweeping inductance values ​​and switching frequencies to determine potential combinations of LC filter components and their characteristics, according to some embodiments. [Figure 26] 1 illustrates a control diagram for controlling a power converter using variable frequency critical soft switching according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] One or more embodiments are described and illustrated in the following description and accompanying drawings. These embodiments are not limited to the specific details provided herein and may be modified in various ways. Furthermore, there may be other embodiments not described herein. Also, functions performed by multiple components may be integrated and performed by a single component. Similarly, functions described herein as being performed by one component may be distributed and performed by multiple components. Furthermore, components described as performing a particular function may also perform additional functions not described herein. For example, a device or structure that is "configured" in a particular way may be configured in at least that way, but may also be configured in a way not recited.

[0024] As used in this application, "non-transitory computer-readable medium" includes all computer-readable media, but not consisting of a transitory propagating signal. Thus, non-transitory computer-readable media can include, for example, hard disks, CD-ROMs, optical storage devices, magnetic storage devices, Read Only Memory (ROM), Random Access Memory (RAM), register memory, processor cache, or any combination thereof.

[0025] Furthermore, the phraseology and terminology used herein are for purposes of explanation and should not be considered limiting. For example, the use of "comprising," "including," "containing," "having," and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Furthermore, the terms "connected" and "coupled" are used broadly and include both direct and indirect connections and couplings and can refer to physical or electrical connections or couplings. Furthermore, the stage "and / or" used in conjunction with two or more items is intended to cover the items individually and both items together. For example, "a and / or b" is intended to cover a (and not b), b (and not a), and a and b.

[0026] Disclosed herein are systems and methods for power converters that can provide power conversion with increased power efficiency, increased power density, and / or reduced cost.

[0027] In some embodiments disclosed herein, systems and methods are provided for a power converter having a topology change that reduces both the EMI and total ripple current handling requirements of the power converter without increasing the total capacitance or volume. The topology change may include the addition of a high-side capacitor connecting the input node and the output node. Thus, such systems and methods may include power converters with improved efficiency and power density, among other advantages.

[0028] A power switching element (e.g., a field effect transistor (FET)) of a power converter can experience losses at each switching event. In some embodiments disclosed herein, an additional drain-source capacitor can be coupled across the drain and source terminals of the power switching element to slow the voltage rise during an on-off transition. This slower voltage rise can reduce switching losses of the power switching element. Such systems and methods can thus include power converters with improved efficiency.

[0029] Designing a power converter can be difficult due to the number of adjustable variables, even after a particular topology and control scheme is selected. In some embodiments disclosed herein, a design method or process is provided for identifying and selecting a particular combination of components (e.g., inductors of a particular inductance, capacitors of a particular capacitance) and / or switching frequencies to provide a power converter.

[0030] This application includes descriptions of these and other embodiments in the following sections: (I) Power Converter System; (II) Upper Capacitor for Half-Bridge Switching Converter Topology; (III) Exemplary Method of Operation; (IV) Variable Frequency Critical Soft Switching (VFCSS); (V) Additional Drain-Source Capacitor; and (VI) Design Method for Inverter.

[0031] I. Power Converter Systems 1 illustrates a power converter system 100 according to some embodiments. The power converter system 100 includes an electronic controller 105, a first load / source 110, a power converter 115, an LC filter 120, a contactor 125, a second source / load 130, a third source / load 135, and one or more sensors 140.

[0032] In operation, generally, the electronic controller 105 controls the power switching elements of the power converter 115 with high frequency control signals to convert power either (i) from the first load / power source 110, acting as a power source, to either the second power source / load 130 or the third power source / load 135, acting as a load (depending on the state of the contactor 125), or (ii) from the second power source / load 130 or the third power source / load 135, acting as a power source (depending on the state of the contactor 125), to the first load / power source 110, acting as a load. Thus, when the first load / power source 110 is acting as a power source for the power converter 115, the second power source / load 130 (or the third power source / load 135, depending on the state of the contactor 125) is acting as a load for the power converter 115. Conversely, when the first load / source 110 is acting as a load for the power converter 115, the second source / load 130 (or the third source / load 135, depending on the state of the contactor 125) is acting as a source for the power converter 115.

[0033] The first load / source 110 may be a direct current (DC) load, a DC source, or both a DC load and a DC source (i.e., depending on the mode of the power converter 115, it functions as a DC source in some cases and as a DC load in other cases). In some examples, the first load / source 110 is a battery. The second source / load 130 and the third source / load 135 may be a DC load, a DC source, both a DC load and a DC source, an AC load, an AC source, or both an AC load and an AC source (i.e., depending on the mode of the power converter 115, it functions as an AC source in some cases and as an AC load in other cases). In some examples, the second source / load 130 is an electric motor and the third source / load 135 is an AC generator or an AC power grid. In some examples, the second source / load 130 and the third source / load 135 are both DC batteries. In some examples of the system 100 , the second power source / load 130 is connected to the LC filter 120 without an intermediate contactor 125 , and the contactor 125 and the third power source / load 135 are not present in the system 100 .

[0034] The first load / source 110 is coupled to the power converter 115 on a first side of the power converter 115, and the second source / load 130 (or the third source / load 135, depending on the state of the contactor 125) is coupled to the power converter 115 on a second side of the power converter 115. The first side may be referred to as the input side or the output side of the power converter 115, depending on the mode of the power converter, and may be referred to as the DC side of the power converter 115. The second side may be referred to as the input side or the output side of the power converter, depending on the mode of the power converter, the DC side or the AC side of the power converter 115, or the interface side, depending on the power type of the second and / or third source / load 130, 135. In some embodiments, the second side of the power converter 115 may be an AC side having single-phase AC power, three-phase AC power, or AC power with another number of phases.

[0035] In some embodiments, power converter 115 operates at high DC voltage levels. For example, during operation, the DC side of power converter 115 has a DC voltage (e.g., between the input terminals of power converter 115) of at least 200V, at least 600V, at least 800V, at least 1000V, at least 1200V, between 200V and 1200V, between 600V and 1200V, between 800V and 1200V, or another range. Such high DC voltage levels may be desirable in some situations, such as some electric vehicles. For example, some current electric vehicles (e.g., passenger cars and hybrid electric vehicles) operate with a DC bus voltage of about 200V to 400V. This DC bus voltage for passenger electric vehicles may increase in the future. Additionally, some current electric vehicles (e.g., class 4-8, off-road, or other larger electric vehicles) can operate with DC bus voltages in excess of 1000V, but the high DC voltage levels can introduce challenges to typical power converter systems, such as increased leakage currents, increased common mode voltages, and higher rates of change of common mode voltages. When the second or third power source / load is a motor (e.g., a traction motor in an electric vehicle), these challenges can lead to shaft voltages and bearing currents (e.g., from discharge events when lubricant breakdown occurs) that can result in bearing failure. However, embodiments described herein can mitigate such challenges, for example, by variable frequency soft switching, well-designed LC filters, and / or additional capacitors, as described herein. For example, in the context of an electric vehicle, embodiments described herein can reduce bearing currents and shaft voltages by controlling the common mode voltage of the system to remain below a threshold and / or maintaining the change in common mode voltage below a rate of change threshold.

[0036] The sensors 140 may include, for example, one or more current sensors and / or one or more voltage sensors. For example, the sensors 140 may include respective current and / or voltage sensors for monitoring the current and / or voltage of each phase of one or more of the first load / source 110, the second source / load 130, the third source / load 135, the LC filter 120, or the power converter 115. For example, if the LC filter 120 is a three-phase LC filter, the sensors 140 may include at least three current sensors, one for sensing the current of each phase of the three-phase LC filter 120. In some embodiments, additional or fewer sensors 140 are included in the system 100. For example, the sensors 140 may also include one or more vibration sensors, temperature sensors, etc. In some examples, rather than directly sensing a characteristic, the controller 105 infers or estimates a characteristic (e.g., current or voltage) at one or more nodes or components of the power converter 115 based on another characteristic sensed at another node or component.

[0037] Input / output (I / O) interface 142 includes or is configured to receive input from one or more inputs (e.g., one or more buttons, switches, a touch screen, a keyboard, etc.) and / or includes or is configured to provide output to one or more outputs (e.g., LEDs, a display screen, a speaker, a haptic generator, etc.). Other electronic devices and / or a user may communicate with system 100, and in particular controller 105, via I / O interface 142. For example, controller 105 may receive commands (e.g., from a user or another device) for power converter system 100 indicating a target torque, a target speed, a target power level, a conversion type, etc. In response, controller 105 may drive power converter 115 to achieve the target and / or conversion type indicated by the command.

[0038] The electronic controller 105 comprises an electronic processor 145 and a memory 150. The memory 150 includes one or more of a read-only memory (ROM), a random access memory (RAM), or other non-transitory computer-readable medium. The electronic processor 145 is configured to, among other things, receive instructions and data from the memory 150 and execute the instructions to perform the functions of the controller 105 described herein, including, for example, the processes described below. For example, the memory 150 includes control software. As described in more detail below, in general, the electronic processor 145 can be configured to execute the control software to monitor the system 100 including the power converter 115 (e.g., based on sensor data from the sensor 140), receive commands (e.g., via the input / output interface 142), and drive the power converter 115 (e.g., in accordance with the sensor data and / or commands). In some embodiments, instead of or in addition to executing software from the memory 150 to perform the functions of the controller 105 described herein, the electronic processor 145 includes one or more hardware circuit elements configured to perform some or all of these functions.

[0039] Although the controller 105, the electronic processor 145, and the memory 150 are each shown as a single unit, in some embodiments, one or more of these components are distributed components. For example, in some embodiments, the electronic processor 145 includes one or more microprocessors and / or hardware circuit elements. For example, the controller 105 or the electronic processor 145 can include a processor and a gate driver circuit, where the processor provides a PWM duty cycle and / or frequency to the gate driver circuit, and the gate driver circuit drives the power switching elements according to the PWM duty cycle and / or frequency.

[0040] II. Upper Capacitor for Half-Bridge Switching Converter Topology 2A-2B show half-bridge switching converters, each of which is an example of a power converter circuit that can function as power converter 115 of system 100 of FIG. 1. More specifically, FIG. 2A shows a typical half-bridge switching converter 200, and FIG. 2B shows a modified half-bridge converter 210 that includes an additional upper capacitor 215. As described herein, upper capacitor 215 improves electromagnetic interference (EMI) performance and reduces the capacitance required for converter 210 compared to the typical half-bridge converter 200.

[0041] This upper capacitor 215 allows the ripple current at both the input and output nodes of the converter to be shared. Because there is an element of correlation between the ripple current on the input node and the ripple current on the output node, the differential mode currents at these input and output nodes can be cancelled through this capacitance. This reduction in differential mode current can result in improved EMI performance and reduced total capacitor ripple current when compared to a typical half-bridge converter (e.g., when the total capacitance between the two converters is held constant). Furthermore, the reduction in total capacitor ripple current can allow for a reduction in capacitor size, for example, when the capacitor ripple current drives the capacitor sizing.

[0042] The differential mode current cancellation effect of this additional upper capacitor can also allow a reduction in the required or specific internal ripple current handling capability of the converter. Reducing the required or specific internal ripple current handling capability for a given inductor current ripple can reduce passive filter sizing. This reduction can have the following implications, for example: (1) for the total capacitance in the converter, allocating a portion of it to this additional upper capacitance allows a reduction in the required ripple current handling capability; (2) for a given required ripple current handling capability, the total capacitance in the converter can be reduced if the additional upper capacitor is present. The inclusion of the upper capacitor can also have the effect of reducing conducted EMI (both high and low frequency). This effect is a continuation of the cancellation of the ripple current that occurs in the additional upper capacitor.

[0043] The modified converter 210 includes a DC terminal 220 (also referred to as a DC node, DC link, DC rail, etc.) having a positive DC terminal 222 and a negative DC terminal 224. The modified converter 210 further includes an interface terminal 225 (also referred to as an interface node) having a positive interface terminal 227 and a negative interface terminal 229. The modified converter 210 can operate as a bidirectional converter or a unidirectional converter (in either direction), depending on the configuration and control of the system in which it is implemented. Thus, in some examples, the DC terminal 220 may be an input terminal and the interface terminal 225 may be an output terminal (e.g., DC / DC conversion and DC / AC inversion), and in some examples, the DC terminal 220 may be an output terminal and the interface terminal 225 may be an input terminal (e.g., AC / DC rectification). Furthermore, the interface terminal 225 may be an AC input terminal (for example, for AC / DC rectification), an AC output terminal (for example, for a DC / AC inverter), or a DC output terminal (for example, for DC / DC conversion).

[0044] The modified converter 210 includes a DC link capacitor (C DC 1. The system further includes a high side (upper) power switching element (M1) 235 (also referred to as an upper switch 235), a low side (lower) power switching element (M2) 240 (also referred to as a lower switch 240), a midpoint node 242 connecting the drain terminal of the upper switch 235 and the source terminal of the lower switch 240, and an LC filter 245. The LC filter 245 is an example of the LC filter 120 of the system 100 of FIG.

[0045] The power switching elements 235 and 240 may each be a field effect transistor (FET) having respective gate, source, and drain terminals. The FETs may be, for example, MOSFETs, silicon carbide (SiC) FETs, gallium nitride (GaN) FETs, among other types of FETs.

[0046] The LC filter 245 is connected to the switch-side inductor L F 250 and the lower capacitor C B 255 and the upper capacitor C A 215. The switch side inductor L F 250 is coupled between the midpoint node 242 and a filter node 260. For example, the switch-side inductor L F A first end of the lower capacitor C250 is coupled to the midpoint node 242 and a second end is coupled to the filter node 260. B 255 is coupled between the filter node 260 and the negative DC terminal 224. For example, the lower capacitor C B A first end of 255 is coupled to the filter node 260 and a second end is coupled to the negative DC terminal 224. A 215 is coupled between the filter node 260 and the positive DC terminal 222. For example, the lower capacitor C A A first end of 255 is coupled to the filter node 260 and a second end is coupled to the positive DC terminal 222 .

[0047] In some examples, the modified converter 210 includes an LCL filter (an LC filter with an additional inductor (L)) in which an additional inductor is coupled between the filter node 260 and the positive interface terminal 227.

[0048] C A The addition of C introduces capacitive coupling between the DC terminal 220 and the interface terminal 225 that is not present in a typical half-bridge topology (e.g., as shown in FIG. 2A). A Including C enables sharing of ripple currents at the input and output nodes of the converter. For example, when converter 210 functions as a DC-DC converter, the inductor current ripple propagates to (input) DC terminal 220, and the ripple current at (input) DC terminal 220 is C A to the (output) interface terminal 227 via the input node. The sharing of the ripple current between the input node and the output node allows for partial cancellation of the differential mode ripple between the input node and the output node. Therefore, the additional upper capacitor (C A ) 215 reduces both the EMI and total ripple current handling requirements of the converter without increasing the total capacitance or volume.

[0049] Support circuit analysis 3A-3F show a step-by-step decomposition of the modified half-bridge topology, starting with FIG. 3A and ending with FIG. 3F, to provide a model for circuit analysis. FIG. 3A shows the modified power converter 210 implemented as a converter that receives a voltage input (Vi) at its DC terminals and provides a voltage output (Vo) at its interface terminals. In FIG. 3B, the transistors M1 and M2 are treated as ideal switches S1 and S2, and the inductor I L is set as an ideal current source. DC , C A , and C BAssume that the capacitance is sufficient such that the voltage ripples present at the input node and the output node can be considered negligible with respect to their DC values. As a result, the current through the inductor is independent of the capacitor value and can be approximated as a current source that is only a function of the average values of V i V o , duty cycle D, switching frequency f sw , and output current I o .

Equation

[0050] This decomposition also assumes trailing-edge modulation. Between 0 < t < DT, S1 is closed and S2 is open. Between DT < t < T, S1 is open and S2 is closed. This is an exemplary operation of a half-bridge converter, where the circuit seen in Figure 3B is split into both Figure 3C and Figure 3D. Figure 3C corresponds to the period 0 < t < DT, and Figure 3D corresponds to DT < t < T.

[0051] I L can be split along this same time division into current sources I S1 and I S2 , and the circuits of Figures 3C - 3D can be recombined to form the circuit shown in Figure 3E.

[0052] Figure 4 shows the waveforms 400, 405, and 410 of the currents I L I S1 and I S2 in Figures 3A - 3F respectively. Since the waveforms 400, 405, and 410 of the currents I L I S1 I S2 in Figure 4 still contain DC components, they do not accurately describe the input-output ripple characteristics of the converter. To remove the DC components of these waveforms, first, V i and V oAssume that the connections across V are ideal constant current sources with currents equal to the average current into those nodes. This assumption causes all current ripple to be absorbed by capacitances internal to the converter, i Or V o The electrical current is not absorbed by any external components connected across the

[0053] Input node V o In order to remove the DC component present in I S1 and I S2 From I o To eliminate the DC current component present at node C, an additional current source can be added to V i A fully resolved circuit with the DC current components removed can be seen in FIG. 3F and its corresponding current source waveforms 415, 420, 425 in FIG.

[0054] The decomposition of the modified half-bridge converter allows the circuit to be analyzed as three separate linear circuits, each corresponding to its respective current source. I C,rip , I S1,rip , and I S2,rip Since all of I and I represent ripple currents with zero average value, the capacitive charging phenomenon can be neglected. The current from each current source is split to all three capacitors according to the circuits of Figures 5A-5D. More specifically, Figure 5A shows the decomposition of the modified converter 210, and Figure 5B shows the decomposition of I C,rip Figure 5C shows the capacitor current due to I S1,rip Figure 5D shows the capacitor current due to I S2,rip The capacitor current due to

[0055] In at least some examples, in order to minimize the total capacitor RMS ripple current, the capacitor C A , C B , and C DC should be selected to have the same or nearly the same capacitance (e.g., within 0.5%, 1%, and / or the capacitor's manufacturing tolerance).

[0056] Upper capacitor C A The modified converter 210 with 215 has been verified by both physical experiments and high-fidelity simulations. The parameters used in both the experimental and simulated setups can be seen in Table 1 (below). [Table 1]

[0057] For each experiment and simulation, the duty cycle D is swept from 0.1 to 0.9 to measure the capacitance of the upper capacitor C across the entire duty cycle range. A The results of using these parameters over a D sweep can be seen in Figures 6-10. The simulation results are consistent with the experimental results. Figure 6 shows the effect of a capacitor C connected to the output terminal Vo (the interface terminal of the modified converter 210). B , C A 7 shows the sum of the currents (if any) of the capacitor C connected to the output terminal Vo (the interface terminal of the modified converter 210). B , C DS , C A Figure 8 shows the output voltage ripple. Figure 9 shows the sum of the currents (if any) of the C DC FIG. 13 is a diagram showing a ripple current passing through

[0058] The Fast Fourier Transform (FFT) was experimentally measured at each point in the duty cycle sweep and then averaged together to produce Figure 10. i Node and V o Both nodes have reduced switching frequency harmonics and V o For V, this reduction exceeds 50%. i and V o There is also a reduction in the high frequencies of both FFTs, and the node V o The strongest reduction occurs at 300 kHz. These reductions in harmonics effectively broaden the spectrum. AThis may be due to current sharing across the

[0059] The RMS value of the sum of the ripple currents in all the capacitors is also reduced, which can be seen in Figure 7. o The total output capacitor current, which is the current through the capacitors connected to A The DC bus capacitor current does not change significantly with the addition of the upper capacitor. However, the DC bus capacitor current decreases over almost the entire D sweep, with a peak reduction in total capacitor current of 20% occurring at D=0.6. Furthermore, the improvement in capacitor current with the optimized capacitance ratio is small, suggesting that the value of the upper capacitor is not as important as its presence.

[0060] The peak-to-peak value of the output voltage ripple does not change significantly, but A The addition of C slightly reduces the A This means that the current ripple is reduced without causing additional voltage ripple at the output node.

[0061] C A The value of is the total output capacitor current and C DC This can be seen in Figures 7 and 9, where the optimal C A value effectively minimizes the sum of all capacitor ripple currents, but increases the output capacitor current while decreasing the DC bus capacitor current. This provides the circuit designer with another option for balancing the DC bus capacitance current ripple and the output capacitance current ripple.

[0062] Upper capacitor (C A The inclusion of V 215 in the modified converter 210 can provide several advantages. The overall capacitor ripple current is reduced, potentially reducing the capacitance and volume required for the converter. Both high and low frequency harmonics are reduced, reducing V oWith a reduction of more than 50% at the switching frequency of 1000V, if a hypothetical design has two parallel capacitors at the output, both are connected to the lower capacitor C B Instead of using one as the upper capacitor (C A ) for better performance.

[0063] III. Example of how it works 11 illustrates a process 1100 for power conversion. Process 1100 is described as being performed by power converter system 100 implemented with modified power converter 210 as power converter 115. However, in some embodiments, process 1100 may be performed by another power converter system or by power converter system 100 using another power converter as power converter 115. Additionally, although the blocks of process 1100 are shown in a particular order, in some embodiments one or more of the blocks may be performed partially or wholly in parallel, may be performed in a different order than that shown in FIG. 11, or may be bypassed.

[0064] In block 1105, a DC voltage terminal (e.g., DC voltage terminal 220) receives an input DC voltage, including a positive DC terminal 222 and a negative DC terminal 224 disposed on the DC side of the power converter. The input DC voltage may be provided by a DC power source, such as a battery, a capacitor, an ultracapacitor, a DC power source from a rectified AC power source (e.g., AC grid power converted to DC power by a diode bridge rectifier).

[0065] In block 1110, a controller (e.g., controller 105) drives a power switching element pair to convert an input DC voltage to an intermediate output voltage at a midpoint node (e.g., midpoint node 242). The power switching element pair includes a high-side power switching element (e.g., upper switch 235) coupled to the positive DC terminal 222 and a low-side power switching element (e.g., lower switch 240) coupled to the negative DC terminal 224. The high-side power switching element 235 and the low-side power switching element 240 are coupled to each other at the midpoint node 242.

[0066] To drive the power switching element pairs, a controller (e.g., controller 105) can generate a respective pulse-width modulated (PWM) control signal for each power switching element (e.g., switches 235, 240) of a power converter (e.g., power converter 210). Generally, switches (M1) 235 and (M2) 240 alternate between an on state (gate terminal enabled, switching conduction from drain to source terminal) and an off state (gate terminal disabled, not conducting from drain to source terminal), so that generally, when the upper switch (M1) 235 is on, the lower switch (M2) 240 is off, and when the upper switch (M1) 235 is off, the lower switch (M2) 240 is on.

[0067] In operation, generally, the upper switch (M1) 235 and the lower switch (M2) are switched by respective control signals at a switching frequency that is much higher than the frequency of the output AC signal (e.g., AC grid signal) on the interface terminals 225. The duty cycle of these control signals can be adjusted up or down to adjust the voltage output to the interface terminals 225. At least in some respects, since the switching frequency is much higher than the AC cycle frequency, at a given point in time, the circuit can be considered a DC / DC converter, where the output "direct current" voltage is the voltage level of the AC signal at a particular point in time.

[0068] In a hard switching implementation, the switches M1 and M2 are driven to switch states (e.g., from off to on and from on to off, respectively) at the same time. Such a control scheme for hard switching can reduce complexity, but can lead to increased power loss (i.e., lower efficiency, lower power density, increased heat, etc.). In a critical soft switching (CSS) implementation, one switch (M1 or M2) can be switched before the other to reduce power loss. FIG. 12 shows a timing diagram for controlling the switches M1 and M2 using critical soft switching, and the resulting inductor current I through the switch-side inductor 250. L In a variable frequency critical soft switching (VFCSS) embodiment, the frequency at which the switches are switched is controlled while the soft switching is controlled to vary based on the operating characteristics to further reduce power losses. Critical soft switching and variable frequency critical soft switching are described in more detail below.

[0069] To generate the PWM control signals for driving the power switching elements (e.g., switches 235, 240), the controller 105 can sense or estimate the operating characteristics of the power converter and increase or decrease the duty cycle (frequency, in the case of VFCSS) of the PWM control signals accordingly. For example, the controller 105 can implement a proportional-integral-derivative (PID) controller that receives the converter's input voltage command (reference voltage) and a measured voltage at the converter's output (e.g., at interface terminal 225). The PID controller can then generate a reference current signal based on the difference between the reference voltage and the measured voltage using standard PID techniques. In general, if the measured voltage is below the reference voltage, the reference current signal is increased and vice versa. The reference current can then be converted to a reference duty cycle value (e.g., a value between 0 and 100%) that indicates the percentage of each switching cycle that the upper switch (M1) 135 should be on and off, and similarly, the percentage of each switching cycle that the lower switch (M2) 140 should be off. In general, the duty cycle of the upper switch (M1) 135 increases as the reference current increases, within certain operating boundaries. The controller 105 (or its gate driver) can then generate the respective PWM control signals according to the reference duty cycle. This PID controller is just one example of a control scheme for generating control signals for driving the power switching elements. In other examples, in block 1110, the controller 105 implements other control schemes, such as cascaded PID control, state-based control, model predictive control (MPC), or another regulated control scheme for driving the power switching elements of the modified converter 210. For example, the controller 105 can implement the VFCSS using another control scheme, as described in more detail below.

[0070] In block 1115, an LC filter (e.g., LC filter 120 of FIG. 1 or LC filter 245 of FIG. 2B) filters the intermediate output voltage to provide a filtered output voltage at an interface terminal (e.g., interface terminal 225). The filtered output voltage may be either an AC voltage or a DC voltage depending on the control or driving of the power switching elements. The interface terminals include a positive interface terminal 227 and a negative interface terminal 229 located on the interface side of the power converter 210. The LC filter includes a switched-side inductor (LF) 250 coupled at a first end to the midpoint node 212, a lower capacitor (CB) coupled between a second end of the switched-side inductor (LF) 250 and the negative DC terminal 224, and an upper capacitor (CA) 215 coupled between the second end of the switched-side inductor (LF) 250 and the positive DC terminal 222.

[0071] As previously mentioned, in some examples, the LC filter 120, 245 includes an additional inductor coupled between the filter node 260 and the positive interface terminal 227, thereby providing an LCL filter.

[0072] In some examples, as part of the filtering of block 1115, the upper capacitor can reduce the ripple current by providing a path for the ripple current to propagate between the DC terminal and the interface terminal and cancel at least a portion of the differential mode current ripple between the DC terminal and the interface terminal. In some examples, the current ripple is at least 200% of the average current, where the average current represents the instantaneous value of the output current through the switch-side inductor 250, such as when the converter 210 is controlled using variable frequency critical soft switching (VFCSS). As an example, when the output current is at its peak, which in this example happens to be 40 amperes (A), the peak-to-peak inductor current ripple should be at least 200% (i.e., 80A). If the instantaneous output current is currently 39A, the peak-to-peak inductor current ripple should be at least 200% of that value (i.e., 200%*39A=78A). Because the output current through the switch-side inductor 250 may vary sinusoidally when the converter is providing an AC output (or because the input current through the switch-side inductor 250 may vary when the converter receives an AC input), the minimum peak-to-peak inductor current ripple also varies with the varying instantaneous current. For example, the converter switching frequency is much greater than the grid AC frequency, so the average current here represents the instantaneous output current. Thus, the average current can be taken at discrete instants or time windows, within which the current does not appear to be a sine wave, but rather a DC current signal, for purposes of determining the minimum peak-to-peak inductor current ripple.

[0073] In some examples of the modified converter 210 operated via the process 1100, the upper and lower switches 235, 240 each include an additional drain-source capacitor (CDS) coupled across the respective source and drain terminals of the switches 235, 240. Such configurations are disclosed in further detail below (e.g., with respect to FIGS. 19-20). As explained, such drain-source capacitors can reduce the rate of drain-source voltage rise between the drain and source terminals of the switches 235 and 240, thereby reducing switching losses of the converter.

[0074] 13 illustrates a process 1300 for power conversion. Process 1300 is described as being performed by power converter system 100 implemented with modified power converter 210 as power converter 115. However, in some embodiments, process 1300 may be performed by another power converter system or by power converter system 100 using another power converter as power converter 115. Additionally, although the blocks of process 1300 are shown in a particular order, in some embodiments one or more of the blocks may be performed partially or wholly in parallel, may be performed in a different order than that shown in FIG. 13, or may be bypassed.

[0075] In block 1305, an AC interface terminal (e.g., interface terminal 225) receives an AC input voltage. Interface terminal 225 includes positive interface terminal 227 and negative interface terminal 229 located on the AC side of power converter 210. The AC input voltage may be provided by an AC power source such as a power grid, an AC generator (e.g., an engine-driven generator), etc.

[0076] In block 1310, an LC filter (e.g., LC filter 120, 245) filters the AC input voltage to provide a filtered voltage at a midpoint node (e.g., midpoint node 242). The LC filter includes a switched-side inductor (LF) 250 coupled at a first end to the midpoint node 212, a lower capacitor (CB) coupled between a second end of the switched-side inductor (LF) 250 and the negative DC terminal 224, and an upper capacitor (CA) 215 coupled between the second end of the switched-side inductor (LF) 250 and the positive DC terminal 222.

[0077] As previously mentioned, in some examples, the LC filter 120, 245 includes an additional inductor coupled between the filter node 260 and the positive interface terminal 227, thereby providing an LCL filter.

[0078] In block 1310, a controller (e.g., controller 105) drives a power switching element pair to convert the filtered voltage to a DC output voltage at a DC terminal (e.g., DC terminal 220). The power switching element pair includes a high-side power switching element (e.g., upper switch 235) coupled to a positive DC terminal 222 of the DC terminals and a low-side power switching element (e.g., lower switch 240) coupled to a negative DC terminal 224 of the DC terminals. Furthermore, the high-side power switching element and the low-side power switching element are coupled to each other at a mid-point node (e.g., mid-point node 242).

[0079] To drive the power switching element pairs, a controller (e.g., controller 105) can generate respective pulse-width modulated (PWM) control signals for each power switching element (e.g., switches 235, 240) of a power converter (e.g., power converter 210). Generally, switches (M1) 235 and (M2) 240 alternate between an on state (gate terminal enabled, switching conduction from drain to source terminal) and an off state (gate terminal disabled, not conducting from drain to source terminal), such that generally, when the upper switch (M1) 235 is on, the lower switch (M2) 240 is off, and when the upper switch (M1) 235 is off, the lower switch (M2) 240 is on. In operation, generally, the upper switch (M1) 235 and the lower switch (M2) are switched by their respective control signals at a switching frequency that is much higher than the frequency of an AC signal (e.g., an AC grid signal) on the interface terminal 225. The duty cycle of these control signals can be adjusted up or down to adjust the DC voltage output at DC terminal 220. Thus, the circuit is controlled to provide active rectification. At least in some respects, the switching frequency of this active rectification is much higher than the AC cycle frequency, so that at a given time, the circuit can be considered a DC / DC converter, with the input "DC" voltage being the voltage level of the AC signal at a particular time. Capacitor 230 can also smooth the output DC voltage.

[0080] As previously described with respect to the driving block 1115 of FIG. 11, the controller may drive the switches 235 and 240 using hard switching, a critical soft switching (CSS) implementation, variable frequency critical soft switching (VFCSS), or other techniques. Additionally, similar to the driving block 1115, to generate PWM control signals for driving the power switching elements (e.g., switches 235, 240), the controller 105 may sense or estimate the operating characteristics of the power converter and increase or decrease the duty cycle (frequency, in the case of VFCSS) accordingly. For example, the controller 105 may implement a proportional-integral-derivative (PID) controller that receives the converter's input voltage command (reference voltage) and a measured voltage at the converter's output (e.g., at DC terminal 220). The PID controller may then generate a reference current signal based on the difference between the reference voltage and the measured voltage using standard PID techniques. In general, if the measured voltage is below the reference voltage, the reference current signal is increased, and vice versa. The reference current can then be converted into a reference duty cycle value (e.g., a value between 0 and 100%) that indicates the percentage of each switching cycle that the upper switch (M1) 135 should be on and off, as well as the percentage of each switching cycle that the lower switch (M2) 140 should be off. In general, the duty cycle of the upper switch (M1) 135 increases as the reference current increases, within certain operating boundaries. This relationship arises because the duty cycle controls the output voltage, which in turn determines the output current. The controller 105 (or its gate driver) can then generate respective PWM control signals according to the reference duty cycle. This PID controller is just one example of a control scheme for generating control signals for driving the power switching elements. In other examples, in block 1315, the controller 105 implements other control schemes, such as cascaded PID control, state-based control, model predictive control (MPC), or another regulated control scheme for driving the power switching elements of the modified converter 210.For example, the controller 105 may implement the VFCSS using another control scheme, as described in more detail below.

[0081] In some examples, as part of the filtering of block 1310, the upper capacitor can reduce ripple current by providing a path for the ripple current to propagate between the AC interface terminal 225 and the DC output terminal 220 and cancel at least a portion of the differential mode current ripple between the AC interface terminal 225 and the DC output terminal 220. In some examples, such as when the converter 210 is controlled using variable frequency critical soft switching (VFCSS), the current ripple in the switched-side inductor (LF) 250 is at least 200% of the average current through the switched-side inductor.

[0082] In some examples of the modified converter 210 operated via the process 1300, the upper and lower switches 235, 240 each have an additional drain-to-source capacitor (C DS ). Such configurations are disclosed in further detail below (e.g., with respect to FIGS. 19-20). As explained, such drain-source capacitors can reduce the rate of drain-source voltage rise between the drain and source terminals of switches 235 and 240, thereby reducing switching losses of the converter.

[0083] The modified power converter 210 has been described above in the context of a single phase of AC power when used to implement a DC / AC inverter or an AC / DC rectifier. However, in some examples, the modified power converter 210 is incorporated into the power converter 115 (see FIG. 1) as a multi-phase power converter. FIG. 14 illustrates the respective upper capacitors (C A14 illustrates a multi-phase power converter 1400 incorporating a synchronous rectifier 1415. In the example illustrated in FIG. 14, converter 1400 has three phases (phases A, B, and C). The waveform (e.g., current or voltage) of each of phases A, B, C may be approximately 120 degrees apart (may lead or lag) from the waveform of each of the other phases A, B, C.

[0084] The topology of the multi-phase power converter 1400 incorporates a modified power converter 210 for each phase of the converter. Components in FIG. 14 that are similar to components in FIG. 2B are identified with similar numbers plus 1200 (e.g., filter 245 in FIG. 2B is similar to filter 1445 in FIG. 14). Thus, the general discussion above for such similar components in FIG. 2B applies to the corresponding components in FIG. 14. For example, phase A is associated with a modified half-bridge power converter (similar to converter 210 in FIG. 2B) that includes DC terminals 1420, a pair of power switching elements 1435 (upper switch M1 and lower switch M2), and an LC filter (part of the overall LC filter 1445) that includes a first upper capacitor 1415, a first switch-side inductor 1450, and a first lower capacitor 1455. In some examples, as shown, the LC filter for phase A includes a grid-side inductor (L F ) the A-phase LC filter is also called an LCL filter.

[0085] Similarly, phase B is associated with a modified half-bridge power converter (similar to converter 210 of FIG. 2B ) that includes a (same) DC terminal 1420, a second pair of power switching elements 1435 (upper switch M3 and lower switch M4), and an LC filter (part of the overall LC filter 1445) that includes a second upper capacitor 1415, a second switch-side inductor 1450, and a second lower capacitor 1455. In some examples, as shown, the LC filter for phase B includes a grid-side inductor (L F) so that the LC filter of phase B is also referred to as an LCL filter. Similarly, phase C is associated with a modified half-bridge power converter (similar to converter 210 of FIG. 2B ) that includes a (same) DC terminal 1420, a third pair of power switching elements 1435 (upper switch M5 and lower switch M6), and an LC filter (part of the overall LC filter 1445) that includes a third upper capacitor 1415, a third switch-side inductor 1450, and a third lower capacitor 1455. In some examples, as shown, the LC filter of phase C includes a grid-side inductor (L F ), the LC filter of phase B may also be called an LCL filter.

[0086] Although multi-phase power converter 1400 is shown as including three phases, in other examples, multi-phase power converter 1400 has fewer or more phases, with each phase associated with an additional modified half-bridge power converter (similar to converter 210 of FIG. 2B).

[0087] The upper capacitor in multi-phase power converter 1400 provides similar advantages as discussed above in connection with modified power converter 210 of FIG. 2B.

[0088] In some examples of process 1100 of FIG. 11 and / or process 1300 of FIG. 13, the power converter providing the power conversion in the process is a multi-phase power converter, such as multi-phase power converter 1400 of FIG. 14. In some examples, a drive block (e.g., block 1110 of FIG. 11 and block 1315 of FIG. 13) includes driving, by a controller, each of the pairs of power switching elements. The driving of each pair of switching elements in multi-phase power converter 1400 may be similar to the driving of the pair of switching elements 235 and 240 of converter 210, but the switching of each pair may be 120 degrees out of phase with respect to adjacent phases. Similarly, in some examples, a filtering block (e.g., block 1115 of FIG. 11 and block 1310 of FIG. 13) includes filtering each phase of multi-phase power converter 1400 by LC filter 1445 (e.g., using a respective portion of LC filter 1445 associated with each phase).

[0089] FIG. 15 illustrates a cascaded half-bridge power converter 1500 incorporating an upper capacitor. The topology of the cascaded converter 1500 incorporates two modified power converters 210. Components of FIG. 15 similar to components of FIG. 2B are identified with similar numbers plus 1300 (e.g., filter 245 of FIG. 2B is similar to filter 1545 of FIG. 15). Thus, the general discussion above for such similar components of FIG. 2B applies to the corresponding components of FIG. 15. In some cases, the cascaded half-bridge is also referred to as a zero-sequence stabilized (e.g., filtered) full-bridge converter.

[0090] The upper capacitors in cascaded converter 1500 provide similar advantages as discussed above in the context of modified power converter 210 of Figure 2B. Cascaded converter 1500 also includes source-drain capacitors 1560 coupled across the source and drain terminals of switches 1535 and 1540, which are described in more detail below with reference to Figures 19-20. In some examples, these source-drain capacitors are not included.

[0091] In some examples of the process 1100 of FIG. 11 and / or the process 1300 of FIG. 13, the power converter providing the power conversion in this process is a cascade converter, such as the cascade converter 1500 of FIG. 14. In some examples, the drive block (e.g., block 1110 of FIG. 11 and block 1315 of FIG. 13) includes driving each of the pairs of power switching elements by a controller. The drive of each respective pair of switching elements in the cascaded converter 1500 may be similar to the drive of the pair of switching elements 235 and 240 of the converter 210, and the two circuits operate similarly to independent converters. In another example, the cascade converter 1500 may operate as a full bridge converter, with the output provided between nodes 1520 and 1525. Here, the first pair of switches 1535 and 1560 may be controlled as a pair, and the second pair of switches 1535 and 1540 may also be controlled as a pair. The pair of switches are controlled to be on / off together. Thus, one duty cycle can control four switches. As with other blocks, in some examples, a filtering block (e.g., block 1115 of FIG. 11 and block 1310 of FIG. 13) includes filtering each half-bridge circuit of the cascade converter 1500 with an LC filter 1545 (e.g., using a respective LC filter 1545 associated with each half-bridge circuit).

[0092] IV. Variable Frequency Critical Soft Switching As mentioned above, in some examples, the modified half-bridge power converter 210, the multi-phase power converter 1400, or the cascaded half-bridge power converter 1500 is driven using a variable frequency critical soft switching (VFCSS) scheme. The VFCSS scheme can provide improved efficiency and reduced filter volume (i.e., improved power density) of the power converter. Soft switching allows for the replacement of turn-on switching losses with turn-off switching losses, which is beneficial because the turn-on losses of at least some FETs (e.g., SiC FETs) are typically much larger than the turn-off losses. This VFCSS technique allows for an increase in switching frequency (e.g., 5 times) and a reduction in inductance (e.g., 20 times) while reducing FET losses, resulting in improved power density and efficiency.

[0093] VFCSS is implemented by varying the switching frequency to achieve a desired inductor ripple current in an LC filter (e.g., in the switch-side inductor 250 of the LC filter 245 of FIG. 2B) to provide a soft switching transition. The desired inductor ripple current is determined by the inductor current valley point being equal to the inductor threshold current I L,thr For a converter such as converter 210 of FIG. 2B, I L、thr is set according to the boundary conditions of the dead time and peak / valley inductor current of inductor 250, which can be derived from the output capacitance of switching elements 235 and 240. d ) and peak-valley inductor current I L,max and I L,minand . The inductor current and dead time values ​​that result in soft switching are identified as the soft turn on switching region or regions, and the inductor current and dead time values ​​that do not result in soft switching are identified as the hard switching region or regions. The soft switching region represents the operating region where there is sufficient time and current to discharge the output capacitance of the power switching element (M1 or M2) before turning on. Analytically, these boundaries are expressed as follows:

number

[0094] For large positive values ​​of the DC inductor current, the threshold current level -I L,thr A large current ripple (e.g., more than 200% of the average current through the inductor) is used or required to keep the valley inductor current point lower than the threshold current I. The negative inductor current discharges the upper switch output capacitance during the turn-off transition of the lower switch. Similarly, for highly negative values ​​of DC inductor current, the peak inductor current point is higher than the threshold current I. L,thrA large current ripple is also required to ensure that the threshold current is greater than 1 V. Zero voltage switching (ZVS) of the lower switch is achieved if the output capacitance of the lower switch is fully discharged by the positive inductor current during the turn-off transition of the upper switch. In general, to achieve full soft switching over the entire cycle (e.g., the entire grid cycle), the current ripple should be large enough to guarantee a bidirectional inductor current path or the dead time should be extended. Since an unnecessarily long dead time can introduce distortion, the VFCSS adjusts the switching frequency to maintain critical soft switching over the entire cycle. The VFCSS scheme is implemented to maintain a positive threshold current during the negative part of the cycle and a negative threshold current during the positive part of the cycle. The switching frequency to achieve this for any threshold can be calculated by the following equation:

number

number

number

number

number

number

[0095] 17 is a control diagram for controlling a pair of switching elements of a power converter. In particular, the control diagram illustrates an example of a controller 105 implementing an exemplary control scheme for VFCSS control of a modified power converter 210 including an upper capacitor 215. The controller 105 determines a reference duty cycle (d*) and a reference switching frequency (f SW The frequency generating controller 1710 includes a duty cycle generating controller 1705 and a frequency generating controller 1710, which may be regulators for generating a reference duty cycle (d*), respectively, based on sensed (or estimated) characteristics of the power converter 210, such as current and / or voltage. For example, the duty cycle generating controller 1705 may implement a PID controller or another type of regulator, as described above with respect to the drive blocks 1110 (of FIG. 11 ) and 1315 (of FIG. 13 ). The frequency generating controller 1710 may generate a reference duty cycle (d*), respectively, based on sensed (or estimated) characteristics of the power converter 210, such as current and / or voltage. SW *Based on the above formula to calculate the reference switching frequency (f SW *) can be generated.

[0096] The gate driver 1715 receives a reference duty ratio (d*) and a reference switching frequency (f SW *) based on the received reference values. The gate driver 1715 generates a first PWM control signal for the upper switch (M1) 235 and a second PWM control signal for the lower switch (M2) 240 based on the received reference values. For example, the gate driver 1715 generates a PWM control signal for the upper switch (M1) 235 and a second PWM control signal for the lower switch (M2) 240 at a frequency (f SW ) and has a duty cycle (d 1 ). Similarly, the gate driver 1715 generates a first PWM control signal with a reference switching frequency (f SW *) equal to the frequency (f SW ) and 1-d 1 -(T d / f SW ) and / or a duty cycle d equal to (1-D)*Tsw-(Td / fsw) 2 and an ON edge of the second PWM control signal occurs at a time T later than an OFF edge of the first PWM control signal. d / 2, and the OFF edge of the second PWM control signal is delayed by a time T d / 2 precedes.

[0097] FIG. 18 is another control diagram for controlling a pair of switching elements of a power converter. In particular, the control diagram shows a more detailed example of a controller 105 implementing VFCSS control (e.g., as provided with respect to FIG. 17). FIG. 18 is merely one example of an implementation of the controller 105 for implementing VFCSS, and in other embodiments, the controller 105 implements VFCSS in other ways. For example, a regulator different from that shown in FIG. 18 can be used to generate the reference duty cycle and reference switching frequency.

[0098] In the example of FIG. 18, the duty cycle generating controller 1705 compares a reference output voltage to a sensed output voltage of the converter (e.g., Vo at interface terminal 225) and generates a reference inductor current (I L The two-stage regulator has a first voltage regulation stage that generates a reference inductor current (I L *) to detect the inductor current (I L ) to generate a reference duty cycle d*.

[0099] In the example of FIG. 18, the frequency generating controller 1710 also calculates the reference switching frequency (f SW In some examples, the frequency generation controller 1710 determines the reference switching frequency (f SW In another example, the input of the frequency generating controller 1710 is dynamically calculated to generate the reference switching frequency (f SW A look-up table is provided to map the reference switching frequency (fsw*) to specific values ​​of fsw*. The frequency generation controller 1710 is also optionally provided with a frequency limiter stage that limits the reference switching frequency (fsw*) to maximum and minimum values.

[0100] As in FIG. 17, the gate driver 1715 is provided with a reference duty ratio (d*) and a reference switching frequency (f SW *) is provided. Gate drivers 1715 then generate PWM control signals to drive the power switching elements of power converter 210 based on these values, as described above.

[0101] V. Additional drain-source capacitor (C DS ) In some examples, in addition to, or instead of, the upper capacitor 215, a drain-source capacitor is provided between the drain terminal and the source terminal of each power switching element of the power converter 210. For example, FIG. 19 shows a power converter 1900 that includes both an upper capacitor 215 and a drain-source capacitor (C DS ) provided between the drain terminal and the source terminal of each power switching element of the power converter. However, in other examples, the power converter 1900 includes a drain-source capacitor (C DS ) but does not include the upper capacitor 215.

[0102] The topology of the power converter 1900 is generally similar to the topology of the power converter 210, except for the addition of the drain-source capacitor (C DS ). Accordingly, components of the power converter 1900 that are similar to those of the power converter 210 in FIG. 2B are given similar numbers, and the descriptions of these components provided herein apply similarly.

[0103] As described above, the power converter 1900 includes the addition of a drain-source capacitor (C DS ). In particular, a first drain-source capacitor 1905a is provided across the source terminal 1910a and the drain terminal 1915a of the upper switch (M1) 235, and a second drain-source capacitor 1905b is provided across the source terminal 1910b and the drain terminal 1915b of the lower switch (M2) 240. The drain-source capacitors (C DS ) 1905a - b can be collectively referred to herein as the drain-source capacitor (C DS ) 1905.

[0104] The addition of the drain-source capacitor 1905 can be particularly beneficial for power converters implementing variable frequency critical soft switching (VFCSS). As previously mentioned, VFCSS is a control scheme that enables soft switching over a wide range of loads without additional circuit components. More specifically, VFCSS involves dynamically varying the switching frequency of the power switching elements to achieve the desired peak and valley inductor current ripple. When the valley of the current ripple is placed at the correct value, the converter operates in the soft switching region, where the turn-on losses of the switches (FETs) are traded for turn-off losses.

[0105] The turn-off losses of a particular switch (FET) (e.g., switch 235 or 240) are calculated by the drain-source capacitor (C DS This can be reduced or optimized by adding a 1905 V DS It reduces turn-off losses by slowing down the transition time, and soft switching can be particularly useful for VFCSSs, since it only incurs turn-off switching losses. DS By slowing down the transition time, the amount of overlap in instantaneous current and voltage during turn-off switching is reduced. Figure 20 shows the instantaneous current and voltage of a FET (e.g., switch 235 or 240) during a turn-off switching event without a drain-source capacitor (plot 2000), with a 150 pF drain-source capacitor (plot 2005), and with a 300 pF drain-source capacitor 1905 (plot 2010). The total power (corresponding to the power loss of the switching transition) for each example is shown in plot 2015, where signal 2020 corresponds to the example of plot 2000, signal 2025 corresponds to the example of plot 2005, and signal 2030 corresponds to the example of plot 2010. As additional capacitance is added between the drain and source terminals of the FET (the additional capacitance reduces V DSThe total power loss (shown in plot 2015) decreases as the capacitance increases from the example plots 2000 to 2010 because the area under the intersection of the current and voltage decreases (as the transition time becomes progressively slower).

[0106] Similar to modified power converter 210, and using similar control principles, power converter 1900 can operate as a DC / AC inverter, as an AC / DC rectifier, or as a DC / DC converter.

[0107] Power converter 1900 is shown in the context of a single phase of AC power when used to implement a DC / AC inverter or an AC / DC rectifier. However, in some examples, power converter 1900 is incorporated into power converter 115 (see FIG. 1) that functions as a multi-phase power converter. Power converter 1900 can be replicated for each phase of a multi-phase power converter, similar to how power converter 1400 of FIG. 14 replicates power converter 210 for each phase. In other words, in some examples, power converter 1400 of FIG. 14 replicates a drain-source capacitor (C DS ) across each of the four power switching elements. Similarly, in some examples, as shown, the cascaded half-bridge power converter 1500 of FIG. 15 may be modified to include a drain-source capacitor (C DS ).

[0108] Additionally, as previously described, the processes 1100 and 1300 can be used to control the power converters 1400 and 1500. Similarly, the processes 1100 and 1300 can be used to control the drain-source capacitor (C DS ) can be used to control modified power converters 1400 and 1500 which further incorporate

[0109] VI. Inverter Design Method FIG. 21 illustrates a process 2100 for inverter design optimization. Process 2100 may be performed by an electronic controller, such as electronic controller 105. However, in some embodiments, process 2100 may be implemented by another electronic controller, such as an electronic controller of a stand-alone desktop computer, laptop computer, table, server, cloud-based distributed processing system, etc., that does not also control power converters. Additionally, although the blocks of process 2100 are shown in a particular order, in some embodiments, one or more of the blocks may be performed partially or wholly in parallel, may be performed in a different order than that shown in FIG. 21, or may be bypassed.

[0110] Additionally, process 2100 may be provided to optimize a multi-phase inverter implementing variable frequency critical soft switching (VFCSS), such as converter 1400 shown in FIG. 14, which may be implemented by reducing the drain-source capacitor (C) across each power switching element M1-M6, as described above with respect to FIGS. 19-20. DS ) (external capacitor or C DS,ext Thus, process 2100 is configured to optimize a multi-phase inverter including a half-bridge converter and an LC filter for each phase, where the half-bridge converter for each phase includes a pair of power switching elements coupled across the positive and negative DC rails of the inverter and having a midpoint node coupled to the LC filter for the phase, and each LC filter includes a switched-side inductor (L SW ), high-side capacitor (C A ), and the low-side capacitor (C B ). In some examples, process 2100 is performed to optimize a single-phase inverter, such as converter 1900 of FIG. 19. In some examples, process 2100 is performed to optimize an inverter of another topology.

[0111] In block 2105, the electronic controller may include a drain-source capacitor (C DS ) to determine the capacitance.

[0112] As mentioned above, the external capacitance connected between the drain and source terminals shown in FIG. 19 is the drain-source capacitor (C DS ), which can be used to reduce turn-off losses in power switching elements (e.g., FETs). This capacitance reduces the V DS Slowing the rise time and widening the overlap will reduce non-zero V DS and I D This effectively reduces the overlap (and therefore the loss).

[0113] Drain-source capacitor (C DS ) to determine the capacitance of DS Turn-off energy E off The trend of C can be defined. DS A maximum allowable value for can be defined.

[0114] Starting with the latter, C DS,ext The maximum allowable value of DS The maximum allowable value of this capacitance can be determined analytically. DS,ext The inductor charges and discharges with a current value at its peaks and valleys equal to the inductor current ripple. This instantaneous current value can be approximated as a constant, with the relationship between capacitor voltage, current, and time calculated by the following equation:

number

[0115] t t The value of is the minimum allowable dead time t that the converter can generate. d and the minimum pulse width t p These timings result in the following analytical expression: t m >0=t d -t t t p >0=DT sw -t d -t t It is. This means that all DTs generated by the converter sw The VFCSS method used in the inverter is based on a switching frequency f that varies over the cycle (e.g. of the connected grid). sw As a result of this change in switching frequency, T sw Both C and D are dynamic, DS,ext This affects the determined value of

[0116] As an example, a converter operating with the parameters listed in Table 2 (below) will have a pulse width DT of 0.205 μs for a projected maximum switching frequency of 1.2 MHz. sw This produces a minimum value of t d with a maximum C in the range of 250pF DS,ext A maximum t of 0.105 μs corresponds to t These values ​​can be seen in FIG. 22A and are the minimum pulse width, maximum t t , and maximum C DS,extThe value of is calculated as a function of the switching frequency. [Table 2]

[0117] Next, C DS,ext An appropriate value for C can be determined from within this range. For example, through simulation by an electronic controller (e.g., by running simulation software such as Simulation Program with IC Emphasis (SPICE)), a constant current may be forced through the FET during the turn-off transient and the switching energy is measured. C DS,ext The value of is swept within a predetermined range to determine the value at which the switching energy is minimized.

[0118] In block 2110, the electronic controller determines the switching energy versus drain current values ​​of the power switching elements of the power switching element pairs. For example, through simulation by the electronic controller (e.g., by running simulation software such as SPICE), DS,ext The value of is held constant at the value determined in block 2105, and the drain-source current (I DS ) is swept. The simulation shows the switching losses versus I D properties, an example of which can be seen in Figure 22B.

[0119] The exemplary characteristic (or plot) of FIG. 22B shows the relationship between the source-drain capacitance (C DS ) shows a significant reduction in turn-off losses due to the inclusion of a MOSFET. Although there is an associated increase in turn-on losses that exceeds the reduction in turn-off losses, the converter is designed to operate in the soft switching region and only incurs turn-off losses. Therefore, the increase in turn-on losses can be neglected as it ultimately does not affect the converter performance.

[0120] In block 2115, the electronic controller adjusts the inductor (LSW ) inductance value and the switching frequency (f SW ) to determine the inductance (L SW ), high-side capacitor (C A ), and the low-side capacitor (C B ) to generate multiple potential combinations of sizes.

[0121] For example, the combination of each potential is L SW The inductance value, associated switching frequency f, that results in the lowest losses SW , and a high-side capacitor (C A ) and low-side capacitor (C B ) capacitance values. The electronic controller can then estimate the size (or volume) of each of these components for each potential combination. Additional details of an example process for performing block 2115 are provided below with respect to FIGS. 24 and 25.

[0122] In block 2120, the electronic controller determines the inductor (L SW ), high-side capacitor (C A ), and the low-side capacitor (C B23. For each potential combination of sizes of inductance and switching frequency, the calculated loss versus LC filter volume data points are plotted. For example, referring to FIG. 23, each plot point of plot 2300 is an optimized combination of inductance and switching frequency determined from block 2115 (in one example). FIG. 23 shows a Pareto frontier 2305 of loss and size. Thus, in some examples, block 2120 includes generating a Pareto frontier using the plotted data points. Furthermore, in some examples, the electronic controller further displays the Pareto front on an electronic display (e.g., I / O interface 142 of FIG. 1). The Pareto frontier 2305 enables selection (e.g., by a user or the electronic controller based on stored design criteria) of an appropriate balance between volume and efficiency, and shows possible performance for a given technology, converter topology, and design requirements. In one example, the circled point 2310 is selected for the inverter.

[0123] As mentioned above, in some examples, block 2115 may be implemented by performing either process 2400 of Figure 24 or process 2500 of Figure 25. Process 2400 is directed to controlling a constant switching frequency converter, while process 2500 of Figure 25 is directed to controlling a static switching frequency f SW The design optimization involves the use of VFCSS and additional capacitors to implement critical soft switching.

[0124] Referring first to FIG. 24, in block 2405, the electronic controller controls the inductor (L SW ) inductance value and the switching frequency (f SW) to generate multiple combinations of inductance and switching frequency. The switching frequency and inductance values ​​of the sweep may include a set of frequency values ​​in a range of switching frequencies between upper and lower limits (e.g., the values ​​may be separated by a predetermined, equal, or variable amount), and a set of inductance values ​​in a range of inductances between upper and lower limits (e.g., the values ​​may be separated by a predetermined, equal, or variable amount). The boundaries and increment amounts between values ​​for the sweep may be predefined (e.g., stored in a memory of the electronic controller).

[0125] At block 2410, (L SW ) inductance and switching frequency (f SW ) the electronic controller calculates the associated losses. The losses in the switching devices and the losses in the output filter are the two important factors that determine the efficiency of a power converter. The losses in the switching devices can be divided into switching losses (the energy lost during each switching event) and resistive losses that occur when the switch is conducting. The losses in the output filter can be largely attributed to inductor losses, which can be similarly divided into resistive losses in the windings and hysteresis losses in the core. There are also losses in the ESR of the filter capacitors. These five sources of loss may be considered simultaneously during the optimization process, since it is possible to trade off losses in one area for losses in another, which is often the case for high switching frequency converters.

[0126] The losses determined in block 2410 (ie, the total losses of the inverter) may be defined by the following equation:

number

[0127] In the following, we first consider the FET loss (P FET ) is first explained, followed by the method for calculating the filter loss (Pinductor +P capacitor ) will be explained.

[0128] The FET losses depend on the instantaneous operating point of the converter. Since the output of the inverter is a sine wave, the output voltage V out , output current I out , and the duty cycle D is dynamic and can be written as:

number

number

[0129] From the above formula, I out As (θ) approaches 0, f sw (θ) approaches (∞). This is not possible in practice, so f sw (θ) is limited by the following formula:

number

number

[0130] I L,p-p The value of (θ) is used to quantify both the conduction losses and the switching losses. The conduction losses can be calculated using the following formula:

number

[0131] As provided herein, to calculate the switching losses, the switching energy is calculated using the drain current I d It is quantified as a function of

[0132] As mentioned before, single-phase output currents and voltages can be considered dynamic, and therefore a distinction between hard and soft switching over one cycle (e.g., of the grid) is considered. This distinction can be made analytically using:

number

[0133] Switching loss P sw can be calculated using the following formula:

number

[0134] Finally, the total FET loss over one cycle (e.g., on the grid), P FET can be found by averaging the sum of both FET loss mechanisms from 0<θ<2π.

number

[0135] Turning now to filter losses, these losses refer to the losses occurring in the output LC filter and can be split into inductor losses and capacitor losses. Inductor losses can be calculated by splitting the total losses into two components: core losses and winding (copper) losses. Copper losses can be calculated by:

number

[0136] The core loss of an inductor can be calculated using the following formula:

number

[0137] Similar to calculating the FET losses, the average inductor losses are found by averaging the losses over one cycle (eg, of the grid) according to:

number

[0138] Capacitor losses can be attributed solely to their ESR losses. Since the filter capacitance can be assumed to absorb the entire inductor ripple current, the capacitor ESR losses can be calculated using:

number

number

[0139] At block 2415, (L SW For each value of inductance, the electronic controller selects the associated switching frequency (f) that produced the lowest losses (as determined, for example, by loss comparison). SW ) to generate an inductance-frequency pair for each value of inductance that was part of the sweep.

[0140] At block 2420, for each inductance-frequency pair, the electronic controller determines the upper capacitor (C A ) and the lower capacitor (C B ) is selected to achieve the desired output voltage ripple.

[0141] For example, the switch-side inductor (L SW For a particular inductance, , the desired current ripple and the desired voltage ripple may be known in advance to the electronic controller. The following equations may define the relationship between inductance, current ripple, and voltage ripple:

number

[0142] In block 2425, the electronic controller adjusts the switch-side inductor (L SW ), upper capacitor (C A ) and the lower capacitor (C B ) in the inductor 100. To determine the size of these LC filter components, the electronic controller can estimate the size based on their associated component values ​​(i.e., inductance or capacitance) by using a scaling law. The volume scale of the inductor is based on the following equation:

number

number

[0143] 25, a process 2500 relates to a design optimization for a power converter implementing variable frequency critical soft switching (VFCSS). The process 2500 optimizes the VFCSS frequency instead of the specific switching frequency used in process 2400. SW2500。 Process 2500 is generally similar to process 2400, except that bounds are used. Thus, aside from the differences, the descriptions of blocks 2405, 2410, 2415, 2420, and 2425 above apply equally to blocks 2505, 2510, 2515, 2520, and 2525, respectively, of process 2500. Furthermore, bounds of variable frequency critical soft switching (e.g., maximum and minimum switching frequencies that define a range of available switching frequencies used in the VFCSS) are determined by performing process 2500, as opposed to determining a particular switching frequency to be used.

[0144] In an exemplary experiment using the values ​​in Table 1, the 2100 and 2400 processes provided a prototype 15 kW three-phase inductor with 99.2% efficiency and a power density of 10.47 kW / L. The prototype 15 kW inductor uses a switching frequency of 1.2 MHz and SiC power switching elements. The prototype uses a VFCSS control scheme, which can be implemented by a controller such as the control diagram shown in FIG. 26.

[0145] The control diagram 2600 of FIG. 26 is similar to that of FIG. 14 and process 2100 (e.g., source-drain capacitor C DS The circuit model 2605 includes a circuit model representing a three-phase converter as described with or without the 0.5V reference and includes a control block 2610. The control block 2610 may be implemented by a controller (e.g., the controller 105 of FIG. 1). The control block 2610 represents a phase-locked loop configured to transfer voltage and current values ​​between the abc and dq reference frames. The active and reactive powers are controlled in the d and q reference frames, respectively. Constant current (CC) and constant voltage (CV) controllers are cascaded with the d and q components of the grid current to regulate the active / reactive power between the battery and the grid. A zero sequence controller is also implemented with a 0.5V reference frame. bus The control block 2610 is utilized to boost the output capacitor voltage with an offset of da , d b , and a switching frequency (f) as described with respect to FIG. 17 and / or FIG. 18 to provide a switching frequency along with dc to the gate drivers. SW ) generation controller. As mentioned above, the gate driver then determines the duty cycle and switching frequency (f SW ) can generate respective PWM control signals for each power switching element based on the

[0146] Although certain embodiments have been disclosed in detail herein, this is done by way of example for illustrative purposes only and is not intended to be limiting with respect to the scope of the following appended claims. Features of the disclosed embodiments can be combined, rearranged, etc., within the scope of the invention to produce many more embodiments. Certain other aspects, advantages, and modifications are believed to be within the scope of the claims provided below. The presented claims represent at least some of the embodiments and features disclosed herein. Other unclaimed embodiments and features are also contemplated.

[0147] (Additional example) Example 1: A method, apparatus, and / or non-transitory converter-readable medium storing processor-executable instructions for a half-bridge power converter comprising: a direct current (DC) voltage terminal, the DC voltage terminal including a positive DC terminal and a negative DC terminal and located on a DC side of the power converter; a DC link capacitor coupled between the positive DC terminal and the negative DC terminal; a power switching element pair including a high side power switching element coupled to the positive DC terminal and a low side power switching element coupled to the negative DC terminal, the high side power switching element and the low side power switching element being coupled to each other at a mid-point node; an interface terminal including a positive interface terminal and a negative interface terminal, the interface terminal located on a second interface side of the power converter; and an LC filter including a switch-side inductor coupled at a first end to the mid-point node, a lower side capacitor coupled between a second end of the switch-side inductor and the negative DC terminal, and an upper side capacitor coupled between the second end of the switch-side inductor and the positive DC terminal.

[0148] Example 2: The method, apparatus, and / or non-transitory converter-readable medium of Example 1, wherein the upper capacitor reduces ripple current in the converter by providing a path for the ripple current to propagate between the DC terminal and the interface terminal and cancel at least a portion of the differential mode current ripple between the DC terminal and the interface terminal.

[0149] Example 3: The method, apparatus, and / or non-transitory converter-readable medium of Examples 1 or 2, further comprising a controller including a processor, the controller configured to drive the pair of power switching elements with variable frequency critical soft switching control signals.

[0150] Example 4: The method, apparatus, and / or non-transitory converter-readable medium of any of Examples 1 to 3, further comprising a controller including a processor, wherein the DC voltage terminal is configured to receive an input DC voltage, the controller is configured to drive a pair of power switching elements to convert the input DC voltage to an intermediate output voltage at a midpoint node, the LC filter is configured to filter the intermediate output voltage and provide the filtered output voltage to the interface terminal, the filtered output voltage being either an AC voltage or a DC voltage, and the current ripple in the switch-side inductor is at least 200% of an average current passing through the inductor.

[0151] Example 5: The method, apparatus, and / or non-transitory converter-readable medium of Example 4, further comprising a half-bridge power converter, wherein the controller is configured to drive the pair of power switching elements with variable frequency critical soft-switching control signals to drive the pair of power switching elements to convert the input DC voltage to the intermediate output voltage.

[0152] Example 6: The method, apparatus, and / or non-transitory converter-readable medium of any of Examples 1 to 5, further comprising a controller including a processor, the interface terminal configured to receive an AC input voltage, the LC filter configured to filter the AC input voltage and provide the filtered voltage to the midpoint node, a current ripple in the switch-side inductor is at least 200% of an average current passing through the inductor, the controller configured to drive the pair of power switching elements to convert the filtered voltage to a DC output voltage, and the DC voltage terminal configured to output the DC output voltage.

[0153] Example 7: The method, apparatus, and / or non-transitory converter-readable medium of any of Examples 1 to 6, further comprising an upper drain-source capacitor coupled across the drain and source terminals of the high side power switching device, and a lower drain-source capacitor coupled across the drain and source terminals of the low side power switching device.

[0154] Example 8: A method for converting an input DC voltage at a direct current (DC) voltage terminal, the DC voltage terminal including a positive DC terminal and a negative DC terminal located on a DC side of a power converter; driving a pair of power switching elements by a controller to convert the input DC voltage to an intermediate output voltage at a mid-point node, the pair of power switching elements including a high-side power switching element coupled to the positive DC terminal and a low-side power switching element coupled to the negative DC terminal, the high-side power switching element and the low-side power switching element being coupled to each other at the mid-point node; filtering the intermediate output voltage with an LC filter to obtain a filtering result. providing a filtered output voltage to an interface terminal, where the filtered output voltage is either an AC voltage or a DC voltage, the interface terminal including a positive interface terminal and a negative interface terminal located on a second interface side of the power converter, and the LC filter includes a switched-side inductor coupled at a first end to a midpoint node, a lower capacitor coupled between a second end of the switched-side inductor and the negative DC terminal, and an upper capacitor connected between the second end of the switched-side inductor and the positive DC terminal.

[0155] Example 9: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 1 to 8, wherein the current ripple in the switched-side inductor is at least 200% of the average current passing through the switched-side inductor.

[0156] Example 10: The method, apparatus, and / or non-transitory converter-readable medium of any of Examples 8 or 9, wherein driving the pair of power switching elements to convert the input DC voltage to the intermediate output voltage includes driving, by the controller, the pair of power switching elements with a variable frequency critical soft switching control signal.

[0157] Example 11: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 8-10, wherein the method of power conversion further includes reducing a drain-source voltage rise rate across the drain and source terminals of the high side power switching device with an upper drain-source capacitor coupled across the drain and source terminals of the high side power switching device, and reducing a drain-source voltage rise rate across the drain and source terminals of the high side power switching device with a lower drain-source capacitor coupled across the drain and source terminals of the low side power switching device.

[0158] Example 12: A non-transitory converter-readable medium storing methods, apparatus, and / or processor-executable instructions for a power conversion method including: receiving an AC input voltage at an interface terminal, the interface terminal including a positive interface terminal and a negative interface terminal located on an interface side of the power converter; filtering the AC input voltage with an LC filter and providing the filtered voltage to a mid-point node, the LC filter including a switch-side inductor coupled at a first end to the mid-point node, a lower side capacitor coupled between a second end of the switch-side inductor and the negative DC terminal, and an upper side capacitor coupled between the second end of the switch-side inductor and the positive DC terminal; and driving, by a controller, a power switching element pair to convert the filtered voltage to a DC output voltage at a DC terminal, the power switching element pair including a high-side power switching element coupled to a positive DC terminal of the DC terminal and a low-side power switching element coupled to the negative DC terminal of the DC terminal, the high-side power switching element and the low-side power switching element being coupled to each other at the mid-point node.

[0159] Example 13: The method, apparatus, and / or non-transitory computer-readable medium of Example 12, further comprising: reducing ripple current in the converter by providing a path for the ripple current to propagate between the DC terminal and the interface terminal and canceling at least a portion of the differential mode current ripple between the DC terminal and the interface terminal with an upper capacitor.

[0160] Example 14: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 12 or 13, wherein the current ripple in the switched-side inductor is at least 200% of the average current passing through the switched-side inductor.

[0161] Example 15: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 12 to 14, wherein driving the pair of power switching elements to convert the filtered voltage to a DC output voltage includes driving, by a controller, the pair of power switching elements with a variable frequency critical soft-switching control signal.

[0162] Example 16: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 12-15, further comprising: reducing a drain-source voltage rise rate across the drain and source terminals of the high-side power switching device by an upper drain-source capacitor coupled across the drain and source terminals of the high-side power switching device; and reducing a drain-source voltage rise rate across the drain and source terminals of the high-side power switching device by a lower drain-source capacitor coupled across the drain and source terminals of the low-side power switching device.

[0163] Example 17: A non-transitory converter-readable medium storing methods, apparatus, and / or processor-executable instructions for a power inverter comprising: a direct current (DC) voltage input including a positive input terminal and a negative input terminal; a DC input capacitor coupled across the positive input terminal and the negative input terminal; a power switching element pair including a high side power switching element coupled to the positive input terminal and a low side power switching element coupled to the negative input terminal, where the high side power switching element and the low side power switching element are coupled at a midpoint node; a high side capacitor coupled across a source and drain of the high side power switching element; a low side capacitor coupled across a source and drain of the low side power switching element; an LC filter including a switch-side inductor and capacitor and coupled to the midpoint node; an AC output terminal coupled to the LC filter; and an electronic controller configured to drive the power switching element pair with a variable frequency critical soft switching control signal.

[0164] Example 18: The method, apparatus, and / or non-transitory computer-readable medium of Example 17, wherein the high-side power switching element and the low-side power switching element are silicon carbide (SiC) field effect transistors (FETs).

[0165] Example 19: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 17 or 18, wherein the LC filter further includes an output inductor to form an LCL filter, the output inductor connecting the switch-side inductor to the AC output terminal.

[0166] Example 20: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 17-19, wherein to drive the pair of power switching elements with a variable frequency critical soft switching control signal, the electronic controller is configured to determine a switching frequency for providing soft switching of the pair of power switching elements based on operating characteristics of the power inverter during operation, and generate the variable frequency critical soft switching control signal as a pulse width modulated (PWM) control signal having the switching frequency.

[0167] Example 21: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 17 to 20, wherein to drive the pair of power switching elements with the variable frequency critical soft switching control signal, the electronic controller is configured to determine a switching frequency based on a duty cycle of the pair of power switching elements, an inductor current, and a boundary threshold current for soft switching, and generate the variable frequency critical soft switching control signal as a pulse width modulated (PWM) control signal having the switching frequency.

[0168] Example 22: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 17 to 21, wherein the capacitor is a lower capacitor of an LC filter, the LC filter further including an upper capacitor, the switched-side inductor is coupled at a first end to the midpoint node, the lower capacitor is coupled between a second end of the switched-side inductor and the negative input terminal, and the upper capacitor is coupled between the second end of the switched-side inductor and the positive input terminal.

[0169] Example 23: The power inverter is a multi-phase power inverter configured to provide a multi-phase AC output, the power switching element pair is a first power switching element pair in a first AC phase of the multi-phase AC output, the LC filter is a first LC filter in the first AC phase, the AC output terminal is a first AC output terminal in the first AC phase, and the power inverter includes an additional power switching element pair including an additional high side power switching element coupled to the positive input terminal and an additional low side power switching element coupled to the negative input terminal for each additional AC phase of the multi-phase AC output, 23. The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 17-22, further comprising: an additional power switching element pair, the additional power switching elements coupled to each other at an additional midpoint node in a respective additional AC phase; an additional high side capacitor coupled across a source and drain of the additional high side power switching element; an additional low side capacitor coupled across a source and drain of the additional low side power switching element; an additional LC filter including an additional switch-side inductor and an additional capacitor, coupled to the additional midpoint node; and an additional AC output terminal coupled to the additional LC filter.

[0170] Example 24: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 17-23, wherein the electronic controller is configured to drive each additional pair of power switching elements with a respective variable frequency critical soft-switching control signal.

[0171] Example 25: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 17-24, wherein the electronic controller is configured to drive the first pair of power switching elements and each additional pair of power switching elements with respective variable frequency critical soft switching control signals to provide independent phase control.

[0172] Example 26: A method for converting an input DC voltage at a direct current (DC) voltage terminal, the DC voltage terminal including a positive DC terminal and a negative DC terminal located on a DC side of a power converter, and driving, by an electronic controller, a pair of power switching elements to convert the input DC voltage to an intermediate output voltage at a midpoint node with a variable frequency critical soft switching control signal, the pair of power switching elements including a high-side power switching element coupled to the positive DC terminal and a low-side power switching element coupled to the negative DC terminal, the high-side power switching element and the low-side power switching element being coupled to each other at the midpoint node, and a high-side capacitor across a source and a drain of the high-side power switching element. a low-side capacitor coupled across a source and drain of a low-side power switching element and a low-side capacitor coupled across a source and drain of a low-side power switching element; filtering the intermediate output voltage with an LC filter to provide a filtered output voltage at an AC output terminal coupled to the LC filter, where the filtered output voltage is either an AC voltage or a DC voltage, and where the interface terminals including a positive interface terminal and a negative interface terminal are located on a second interface side of the power converter, and the LC filter is coupled to a midpoint node and includes a switch-side inductor and capacitor.

[0173] Example 27: The method, apparatus, and / or non-transitory computer-readable medium of Example 26, wherein the high-side capacitor delays the voltage rise across the high-side power switching element during an on-to-off transition and the low-side capacitor delays the voltage rise across the low-side power switching element during an on-to-off transition.

[0174] Example 28: The method, apparatus, and / or non-transitory computer-readable medium of Example 26 or 27, wherein the capacitor is a lower capacitor of an LC filter, the LC filter further includes an upper capacitor, the switched-side inductor is coupled at a first end to the midpoint node, the lower capacitor is coupled between a second end of the switched-side inductor and the negative input terminal, and the upper capacitor is coupled between the second end of the switched-side inductor and the positive input terminal.

[0175] Example 29: The power inverter is a multi-phase power inverter configured to provide a multi-phase AC output, the power switching element pair is a first power switching element pair in a first AC phase of the multi-phase AC output, the LC filter is a first LC filter in the first AC phase, and the AC output terminal is a first AC output terminal in the first AC phase, and the method includes driving, for each additional AC phase of the multi-phase AC output, by an electronic controller, an additional power switching element pair to convert the input DC voltage to an additional intermediate output voltage at an additional mid-point node with a variable frequency critical soft switching control signal, the additional power switching element pair including an additional high side power switching element coupled to the positive DC terminal and an additional low side power switching element coupled to the negative DC terminal. 29. The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 26-28, further comprising: an additional low side power switching element coupled to an additional intermediate node, the additional high side power switching element and the additional low side power switching element being coupled to each other at an additional midpoint node, the additional high side capacitor being coupled across a source and drain of the additional high side power switching element, and the additional low side capacitor being coupled across a source and drain of the additional low side power switching element; and filtering the additional intermediate output voltage with an additional LC filter and providing an additional filtered output voltage to an additional AC output terminal coupled to the additional LC filter.

[0176] Example 30: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 26-29, wherein the electronic controller is configured to drive each additional pair of power switching elements with a respective variable frequency critical soft-switching control signal.

[0177] Example 31: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 26 to 30, wherein the electronic controller is configured to drive the first pair of power switching elements and each additional pair of power switching elements with respective variable frequency critical soft switching control signals to provide independent phase control.

[0178] Example 32: A method of inverter optimization for a multi-phase inverter including a half-bridge and an LC filter for each phase, the half-bridge of each phase including a pair of power switching elements having a midpoint node coupled across a positive DC rail and a negative DC rail of the inverter and coupled to an LC filter for the phase, each LC filter including a switched-side inductor (LSW), a high-side capacitor (CA), and a low-side capacitor (CB), the method including the steps of determining, by an electronic processor, a capacitance of a drain-source capacitor (CDS) coupled across a drain and a source of each power switching element of each pair of power switching elements; 2. A non-transitory converter readable medium storing method, apparatus, and / or processor executable instructions for a method comprising: determining switching energy versus drain current values ​​in a power switching element of a switching element pair; sweeping, by an electronic processor, an inductance value of an inductor (LSW) of an LC filter and a switching frequency in the power switching elements to generate a plurality of potential combinations of sizes of the inductor (LSW), high side capacitor (CA), and low side capacitor (CB) of each LC filter; and plotting data points for the calculated losses versus volume of the LC filter for each potential combination of sizes.

[0179] Example 33: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 32 or 37, further comprising generating a Pareto Frontier using the plotted data points.

[0180] Example 34: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 32-33 or 37, further comprising displaying, by the electronic processor, the Pareto Frontier on an electronic display.

[0181] Example 35: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 32-34 or 37, wherein sweeping inductance values ​​and switching frequencies to generate a plurality of potential combinations of sizes of the inductor (LSW), high-side capacitor (CA), and low-side capacitor (CB) of each LC filter includes calculating losses for each combination of inductance values ​​and switching frequencies of the sweep; for each inductance value of the swept inductance values, identifying an associated frequency that produces the lowest losses from the switching frequencies to generate a plurality of inductance-frequency pairs; associating each inductance-frequency pair with a capacitance size in the high-side capacitor (CA) and a capacitance size in the low-side capacitor (CB) that achieves a desired output voltage ripple, wherein each potential combination of sizes in the LC filter includes an inductance value of one of the inductance-frequency pairs, a capacitance size in the high-side capacitor (CA) associated with the inductance-frequency pair, and a capacitance size in the low-side capacitor (CB) associated with the inductance-frequency pair; and estimating a volume for each potential combination of sizes in the LC filter.

[0182] Example 36: The method, apparatus, and / or non-transitory computer-readable medium of any of Examples 32-35 or 37, wherein the multi-phase inverter is a variable frequency critical soft-switching inverter.

[0183] Example 37: A system for inverter optimization for a multi-phase inverter including a half-bridge and an LC filter for each phase, the half-bridge of each phase including a pair of power switching elements having a midpoint node coupled across a positive DC rail and a negative DC rail of the inverter and coupled to the LC filter of the phase, each LC filter including a switched side inductor (LSW), a high side capacitor (CA), and a low side capacitor (CB), the system comprising an electronic controller including a memory storing instructions and a processor configured to execute the instructions, wherein execution of the instructions causes the electronic controller to optimize the coupling across the drain and source of each power switching element of each pair of power switching elements. and / or a non-transitory converter-readable medium storing a method, apparatus, and / or processor-executable instructions for a system that determines a capacitance of a drain-source capacitor (CDS) combined with a power switching element of a power switching element pair, determines switching energy versus drain current values ​​for a power switching element of a power switching element pair, sweeps inductance values ​​of an LC filter inductor (LSW) and switching frequencies for the power switching elements to generate a plurality of potential combinations of sizes for the inductor (LSW), high-side capacitor (CA), and low-side capacitor (CB) of each LC filter, and plots data points for the calculated losses versus LC filter volume for each potential combination of sizes.

Claims

1. A DC voltage terminal including a positive DC terminal and a negative DC terminal, the DC voltage terminal being located on the DC side of a power converter; A DC link capacitor coupled across the positive DC terminal and the negative DC terminal; A pair of power switching elements including a high-side power switching element coupled to the positive DC terminal and a low-side power switching element coupled to the negative DC terminal, the high-side power switching element and the low-side power switching element being coupled to each other at an intermediate point node; An interface terminal including a positive interface terminal and a negative interface terminal, the interface terminal being located on a second interface side of the power converter; An LC filter, A switch-side inductor coupled to the intermediate point node at a first end; A lower capacitor coupled between a second end of the switch-side inductor and the negative DC terminal; An upper capacitor coupled between the second end of the switch-side inductor and the positive DC terminal; The LC filter including the above; A half-bridge power converter comprising the above.

2. The upper capacitor reduces the ripple current of the converter by providing a path for a ripple current to propagate between the DC terminal and the interface terminal and cancel at least a part of a differential-mode current ripple between the DC terminal and the interface terminal. The half-bridge power converter according to Claim 1.

3. Further comprising a controller including a processor, The controller is configured to drive the pair of power switching elements with a variable-frequency critical soft-switching control signal. The half-bridge power converter according to Claim 1.

4. Further comprising a controller including a processor, The DC voltage terminal is configured to receive an input DC voltage, The controller is configured to drive the pair of power switching elements to convert the input DC voltage into an intermediate output voltage at the intermediate point node, The LC filter is configured to filter the intermediate output voltage and provide a filtered output voltage, which is either an AC voltage or a DC voltage, at the interface terminal. The current ripple in the switch-side inductor is at least 200% of the average current passing through the inductor. The half-bridge power converter according to claim 1.

5. To drive the pair of power switching elements to convert the input DC voltage into the intermediate output voltage, the controller is configured to drive the pair of power switching elements with a variable-frequency critical soft-switching control signal. The half-bridge power converter according to claim 4.

6. Further comprising a controller including a processor, The interface terminal is configured to receive an AC input voltage, The LC filter filters the AC input voltage and is configured to provide the filtered voltage at the intermediate point node. The current ripple in the switch-side inductor is at least 200% of the average current passing through the inductor, The controller is configured to drive the pair of power switching elements to convert the filtered voltage into a DC output voltage. The DC voltage terminal is configured to output the DC output voltage. The half-bridge power converter according to claim 1.

7. An upper drain-source capacitor coupled across the drain and source terminals of the high-side power switching element, and A lower drain-source capacitor coupled across the drain and source terminals of the low-side power switching element, The half-bridge power converter according to claim 1, further comprising.

8. Receiving an input DC voltage at a DC voltage terminal, the DC voltage terminal including a positive DC terminal and a negative DC terminal located on the DC side of the power converter, Driving, by a controller, a pair of power switching elements to convert the input DC voltage into an intermediate output voltage at an intermediate point node, the pair of power switching elements including a high-side power switching element coupled to the positive DC terminal and a low-side power switching element coupled to the negative DC terminal, the high-side power switching element and the low-side power switching element being coupled to each other at the intermediate point node. Filtering the intermediate output voltage by an LC filter to provide a filtered output voltage at an interface terminal, wherein the filtered output voltage is either an AC voltage or a DC voltage, and the interface terminal includes a positive interface terminal and a negative interface terminal located on a second interface side of the power converter, wherein the LC filter includes a switch-side inductor coupled to the intermediate point node at a first end, a lower capacitor coupled between a second end of the switch-side inductor and the negative DC terminal, and an upper capacitor connected between the second end of the switch-side inductor and the positive DC terminal, the step, A power conversion method including.

9. The method according to claim 8, further comprising reducing the ripple current by providing a path for the ripple current to propagate between the DC terminal and the interface terminal by the upper capacitor and canceling at least a part of the differential mode current ripple between the DC terminal and the interface terminal.

10. The method according to claim 8, wherein the current ripple in the switch-side inductor is at least 200% of the average current passing through the switch-side inductor.

11. The method according to claim 8, wherein the step of driving the pair of power switching elements to convert the input DC voltage into an intermediate output voltage at an intermediate point node includes driving the pair of power switching elements with a variable frequency critical soft switching control signal by the controller.

12. Reducing the rate of rise of the drain-source voltage across the drain and source terminals of the high-side power switching element by an upper drain-source capacitor coupled across the drain and source terminals of the high-side power switching element; Reducing the rate of rise of the drain-source voltage across the drain and source terminals of the high-side power switching element by a lower drain-source capacitor coupled across the drain and source terminals of the low-side power switching element; The method according to claim 8, further comprising.

13. A step of receiving an AC input voltage at an interface terminal, wherein the interface terminal includes a positive interface terminal and a negative interface terminal located on the interface side of a power converter, the step; A step of filtering the AC input voltage by an LC filter and providing the filtered voltage at an intermediate point node, wherein the LC filter A switch-side inductor coupled to the intermediate point node at a first end, A lower capacitor coupled between a second end of the switch-side inductor and a negative DC terminal of a DC terminal, An upper capacitor coupled between the second end of the switch-side inductor and a positive DC terminal of the DC terminal, including the step; Step; A step of driving a pair of power switching elements by a controller to convert the filtered voltage into a DC output voltage at the DC terminal, wherein the pair of power switching elements includes a high-side power switching element coupled to the positive DC terminal of the DC terminal and a low-side power switching element coupled to the negative DC terminal of the DC terminal, and the high-side power switching element and the low-side power switching element are coupled to each other at the intermediate point node, the step; A power conversion method including

14. The method according to claim 13, further including a step of reducing the ripple current of the converter by providing a path for a ripple current to propagate between the DC terminal and the interface terminal and canceling at least a part of a differential mode current ripple between the DC terminal and the interface terminal by the upper capacitor.

15. The method according to claim 13, wherein a current ripple in the switch-side inductor is at least 200% of an average current passing through the switch-side inductor.

16. The method according to claim 13, wherein the step of driving the pair of power switching elements to convert the filtered voltage into a DC output voltage at the DC terminal includes a step of driving the pair of power switching elements by the controller with a variable frequency critical soft switching control signal.

17. Reducing a rate of increase in a drain-source voltage across the drain terminal and the source terminal of the high-side power switching element by an upper drain-source capacitor coupled across the drain terminal and the source terminal of the high-side power switching element; Reducing the rate of increase in the drain-source voltage across the drain terminal and the source terminal of the high-side power switching element by a lower drain-source capacitor coupled across the drain terminal and the source terminal of the low-side power switching element; The method of claim 13, further comprising: Reducing the rate of increase in the drain-source voltage across the drain terminal and the source terminal of the high-side power switching element by a lower drain-source capacitor coupled across the drain terminal and the source terminal of the low-side power switching element;

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