A Transformer-Based Architecture for Media Transform Coding

Abstract

Systems and techniques for processing media data using a neural network system are described herein. For example, the process may include obtaining a latent representation of a frame of encoded image data, and generating a frame of decoded image data by a plurality of decoder transformer layers of a decoder sub-network using the latent representation of the frame of encoded image data as an input. At least one of the plurality of decoder transformer layers includes one or more transformer blocks for generating one or more patches of features and determining self-attention locally within one or more window partitions and shift window partitions applied across the one or more patches, and a patch separation engine for reducing a respective size of each of the one or more patches.

Description

[Technical field]

[0001]

[0001] The present disclosure generally relates to image and video coding, including encoding (or compression) and decoding (decompression) of images and / or videos. For example, aspects of the present disclosure relate to techniques for performing transform coding and non-linear transforms using transformer layers with shifted self-attention windows. [Background technology]

[0002]

[0002] Many devices and systems allow video data to be processed and output for consumption. Digital video data comprises a large amount of data to meet the demands of consumers and video providers. For example, consumers of video data desire high quality video, including high fidelity, resolution, frame rate, etc. As a result, the large amount of video data required to meet these demands places a strain on communication networks and devices that process and store the video data.

[0003]

[0003] Video coding techniques may be used to compress video data. The goal of video coding is to compress video data into a format that uses a lower bit rate while avoiding or minimizing degradation to video quality. As ever-evolving video services become available, encoding techniques with better coding efficiency are needed. Summary of the Invention

[0004] In some examples, systems and techniques are described for coding (eg, encoding and / or decoding) media data using a transformer-based neural network architecture. According to at least one illustrative example, there is provided a method for processing media data, the method including obtaining a latent representation of a frame of encoded image data, and generating a frame of decoded image data by a plurality of decoder transformer layers of a decoder sub-network using the latent representation of the frame of encoded image data as an input, wherein at least one decoder transformer layer of the plurality of decoder transformer layers generates one or more patches of features, the method including one or more transformer blocks for determining self-attention locally within one or more window partitions and shifted window partitions applied across the one or more patches, and a patch un-merging engine for reducing a respective size of each patch of the one or more patches.

[0005] In another example, an apparatus for processing media data is provided, the apparatus including at least one memory (configured to store data, such as, for example, virtual content data, one or more images, etc.) and one or more processors (e.g., implemented in a circuit) coupled to the at least one memory, the one or more processors being configured to obtain a latent representation of a frame of encoded image data and generate a frame of decoded image data based on a plurality of decoder transformer layers of a decoder sub-network using the latent representation of the frame of encoded image data as an input, the at least one decoder transformer layer of the plurality of decoder transformer layers including one or more transformer blocks configured to generate one or more patches of features and determine self-attention locally within one or more window partitions and shift window partitions applied across the one or more patches, and a patch separation engine configured to reduce a respective size of each of the one or more patches.

[0006]

[0006] In another example, a non-transitory computer-readable medium is provided that stores instructions that, when executed by one or more processors, cause the one or more processors to obtain a latent representation of a frame of encoded image data and generate a frame of decoded image data based on multiple decoder transformer layers of a decoder sub-network using the latent representation of the frame of encoded image data as input, wherein at least one decoder transformer layer of the multiple decoder transformer layers includes one or more transformer blocks configured to generate one or more patches of features and determine self-attention locally within one or more window partitions and shift window partitions applied across the one or more patches, and a patch separation engine configured to reduce a respective size of each patch of the one or more patches.

[0007]

[0007] An apparatus for processing media data is provided, the apparatus including: means for obtaining a latent representation of a frame of encoded image data; and means for generating a frame of decoded image data based on a plurality of decoder transformer layers of a decoder sub-network using the latent representation of the frame of encoded image data as an input, wherein at least one of the plurality of decoder transformer layers includes one or more transformer blocks configured to generate one or more patches of features and determine self-attention locally within one or more window partitions and shift window partitions applied across the one or more patches; and a patch separation engine configured to reduce a respective size of each patch of the one or more patches.

[0008]

[0008] In some aspects, to generate a frame of decoded image data, the methods, apparatus, and computer-readable media described above may include determining self-attention locally within one or more first window partitions applied across the one or more patches by a first transformer block of a first decoder transformer layer of the multiple decoder transformer layers, determining self-attention locally within one or more second window partitions applied across the one or more patches by a second transformer block of the first decoder transformer layer, the one or more second window partitions being shifted to overlap one or more boundaries between adjacent ones of the one or more first window partitions, and segmenting, by a patch separation engine, each patch of the one or more patches into a plurality of non-overlapping un-merged patches.

[0009]

[0009] In some aspects, the above-described methods, apparatus, and computer-readable media may include providing a plurality of separation patches to a first transformer block of a second decoder transformer layer of the plurality of decoder transformer layers.

[0010]

[0010] In some aspects, the above-described methods, apparatus, and computer-readable media may include segmenting a plurality of separated patches by a patch separation engine of a second decoder transformer layer, and providing an output of the patch separation engine to a third decoder transformer layer of the plurality of decoder transformer layers.

[0011] In some aspects, each separation patch of the plurality of separation patches has a uniform patch size, and the patch separation engine applies a patch size reduction factor of two.

[0012]

[0012] In some aspects, to segment each patch of one or more patches into a plurality of separate patches, the above-described methods, apparatus, and computer-readable media may include reducing a feature dimension of the plurality of separate patches.

[0013]

[0013] In some aspects, the above-described methods, apparatus, and computer-readable media may include multiple decoder transformer layers receiving as input a latent representation of a frame of encoded image data, applying a nonlinear transformation, and generating a frame of decoded image data.

[0014]

[0014] In some aspects, the nonlinear transform is a synthesis transform and the frame of decoded image data is a reconstruction of an input image associated with the frame of encoded image data.

[0015] In some aspects, the methods, apparatus, and computer-readable media described above may include training one or more of the decoder transformer layers using a loss function based at least in part on a rate-distortion. In some cases, the loss function includes a Lagrangian multiplier for the rate-distortion.

[0016] In some aspects, at least a portion of one or more transformer blocks included in at least one decoder transformer layer have the same architecture.

[0017] In some aspects, each of the one or more transformer blocks included in at least one decoder transformer layer has the same architecture.

[0018] In some aspects, the frame of encoded image data includes an encoded still image.

[0019] In some aspects, the frame of encoded image data comprises an encoded video frame.

[0020]

[0020] In some aspects, the methods, apparatus, and computer-readable media described above may include training multiple decoder transformer layers with at least a first training data set and a second training data set, where the data of the second training data set has a reversed temporal order compared to the data of the first training data set.

[0021]

[0021] In some aspects, the multiple decoder transformer layers include a series of consecutive decoder transformer layers.

[0022] According to another illustrative example, there is provided a method for processing media data, the method including segmenting a frame into a plurality of patches and generating a frame of encoded image data by a plurality of encoder transformer layers of an encoder sub-network using the plurality of patches as inputs.

[0023] In another example, an apparatus is provided for processing media data, the apparatus including at least one memory (configured to store data, e.g., virtual content data, one or more images, etc.) and one or more processors (e.g., implemented in a circuit) coupled to the at least one memory, the one or more processors configured to segment a frame into a plurality of patches and generate a frame of encoded image data based on a plurality of encoder transformer layers of an encoder sub-network using the plurality of patches as inputs.

[0024]

[0024] In another example, a non-transitory computer-readable medium is provided that stores instructions that, when executed by one or more processors, cause the one or more processors to segment a frame into a plurality of patches and use the plurality of patches as inputs to generate a frame of encoded image data based on a plurality of encoder transformer layers of an encoder sub-network.

[0025]

[0025] An apparatus for processing media data is provided, the apparatus including: means for segmenting a frame into a plurality of patches; and means for generating a frame of encoded image data based on a plurality of encoder transformer layers of an encoder sub-network using the plurality of patches as input.

[0026]

[0026] In some aspects, to generate a frame of encoded image data, the methods, apparatus, and computer-readable media described above may include determining self-attention locally within one or more window partitions by a first transformer block of a first encoder transformer layer of the multiple encoder transformer layers, determining self-attention locally within one or more shift window partitions overlapping the one or more window partitions by a second transformer block of the first encoder transformer layer, determining one or more patches of features for applying a nonlinear transformation to the segmented frame by one or more of the first transformer block and the second transformer block, and increasing a patch size between the first encoder transformer layer and the second encoder transformer layer by a patch merging engine.

[0027]

[0027] In some aspects, the patch merging engine is configured to combine multiple adjacent patches from a first encoder transformer layer into a merged patch that is provided to a second encoder transformer layer.

[0028] In some aspects, an output of the second transformer block of the first encoder transformer layer is coupled to an input of the second encoder transformer layer.

[0029]

[0029] In some aspects, the methods, apparatus, and computer-readable media described above may include generating a hierarchical feature map for the segmented frame by multiple encoder transformer layers of an encoder sub-network using multiple patches as input, and generating a frame of encoded image data from the hierarchical feature map.

[0030] In some aspects, each patch of the multiple patches is of uniform size and includes one or more pixels of the segmented frame.

[0031]

[0031] In some aspects, the above-described methods, apparatus, and computer-readable media may include using a patch merging engine to increase a patch size by concatenating features obtained from one or more subsets of adjacent patches, each subset of adjacent patches being merged into a merged patch output by the patch merging engine.

[0032] In some aspects, the first transformer block and the second transformer block have the same architecture.

[0033]

[0033] In some aspects, the above-described methods, apparatus, and computer-readable media may include providing a plurality of patches to a linear embedding layer of the encoder sub-network before the first encoder transformer layer.

[0034]

[0034] In some aspects, the frame of encoded image data is a latent representation of the image data.

[0035]

[0035] In some aspects, the latent representation is a hierarchical feature map generated by multiple encoder transformer layers of the encoder sub-network.

[0036] In some aspects, the methods, apparatus, and computer-readable media described above may include training one or more of the encoder transformer layers using a loss function based on a rate-distortion loss. In some cases, the loss function includes a Lagrangian multiplier for the rate-distortion loss.

[0037] In some aspects, the multiple patches are segmented from an input that includes a still image frame or a video frame.

[0038] In some aspects, the methods, apparatus, and computer-readable media described above may include entropy coding the encoded image data with a factorized prior.

[0039] In some aspects, the apparatus includes a mobile device (e.g., a mobile phone or so-called “smartphone”, tablet computer, or other type of mobile device), a wearable device, an extended reality device (e.g., a virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device), a personal computer, a laptop computer, a video server, a television, a vehicle (or a computing device of the vehicle), or other device. In some aspects, the apparatus includes at least one camera for capturing one or more images or video frames. For example, the apparatus may include a camera (e.g., an RGB camera) or multiple cameras for capturing one or more videos including one or more images and / or video frames. In some aspects, the apparatus includes a display for displaying one or more images, videos, notifications, or other displayable data. In some aspects, the apparatus includes a transmitter configured to transmit one or more video frames and / or syntax data to the at least one device via a transmission medium. In some aspects, the processor may include a neural processing unit (NPU), a central processing unit (CPU), a graphics processing unit (GPU), or other processing device or component.

[0040]

[0040] This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used independently to determine the scope of the claimed subject matter, which should be understood by reference to the entire specification of this patent, any or all drawings, and appropriate portions of each claim.

[0041]

[0041] The above, together with other features and embodiments, will become more apparent with reference to the following specification, claims, and accompanying drawings. [Brief description of the drawings]

[0042]

[0042] Exemplary embodiments of the present application are described in detail below with reference to the following figures. [Figure 1]

[0043] FIG. 1 illustrates an example implementation of a system on a chip (SOC). [Figure 2A]

[0044] FIG. 1 is a diagram illustrating an example of a fully connected neural network. [Figure 2B]

[0045] FIG. 1 is a diagram illustrating an example of a locally connected neural network. [Diagram 3]

[0046] FIG. 1 illustrates an example of a system including a device operable to perform image and / or video coding (encoding and decoding) using a neural network-based system, according to some examples. [Figure 4]

[0047] FIG. 1 illustrates an example of an end-to-end neural network-based image and video coding system for input having a Red-Green-Blue (RGB) format, in accordance with some examples. [Figure 5A]

[0048] FIG. 1 illustrates an example of a transformer-based neural network architecture for an encoder of a neural network-based image and video coding system, in accordance with some examples. [Figure 5B]

[0049] FIG. 1 illustrates an example of a transformer-based neural network architecture for a decoder of a neural network-based image and video coding system, in accordance with some examples. [Figure 5C]

[0050] FIG. 1 illustrates an example of a transformer-based end-to-end neural network architecture for neural network-based image and video coding systems, in accordance with some examples. [Figure 6A]

[0051] FIG. 2 illustrates an example architecture of a pair of shift window transformer blocks, in accordance with some examples. [Figure 6B]

[0052] FIG. 1 illustrates an example of a video coding system that uses one or more transformer-based neural network architectures, in accordance with some examples. [Figure 7A]

[0053] FIG. 2 illustrates an example of a patch merging or patch separation process that can be applied between transformer layers of an encoder or decoder neural network-based image and video coding system, in accordance with some examples. [Figure 7B]

[0054] FIG. 1 illustrates an example of shifting window self-attention calculation between two self-attention layers of an encoder or decoder neural network-based image and video coding system, according to some examples. [Figure 8]

[0055] 1 is a flowchart illustrating an example of a process for processing image and / or video data, according to some examples. [Figure 9]

[0056] 11 is a flowchart illustrating another example of a process for processing image and / or video data, in accordance with some examples. [Figure 10]

[0057] FIG. 2 illustrates an example computing device architecture for an example computing device capable of implementing various techniques described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043]

[0058] Specific aspects and embodiments of the present disclosure are provided below. As will be apparent to those skilled in the art, some of these aspects and embodiments may be applied independently, and some of them may be applied in combination. In the following description, for the purpose of explanation, specific details are set forth to provide a thorough understanding of the embodiments of the present application. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and descriptions are not intended to be limiting.

[0044]

[0059] The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Instead, the following description of exemplary embodiments provides those skilled in the art with an enabling description for implementing the exemplary embodiments. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the present application as set forth in the appended claims.

[0045]

[0060] Digital video data can contain large amounts of data, especially as the demand for high quality video data continues to grow. For example, video data consumers typically desire increasingly higher quality video, having high fidelity, resolution, frame rates, etc. However, the large amounts of video data required to meet the high demands often translate into large bandwidth and storage needs, placing a heavy burden on communication networks and devices that process and store the video data.

[0046]

[0061] Various techniques may be used to code the video data. For example, the video coding may be performed according to a particular video coding standard. Exemplary video coding standards include high-efficiency video coding (HEVC), advanced video coding (AVC), and versatile video coding (VVC) developed by the moving picture experts group (MPEG), as well as AOMedia Video 1 (AV1) developed by the Alliance for Open Media (AOM). Video coding often uses prediction methods, such as inter-prediction or intra-prediction, that exploit redundancy that exists within a video image or sequence. A common goal of video coding techniques is, for example, to compress video data into a format that uses a lower bitrate while avoiding or minimizing degradation of video quality when the compressed video data is decompressed. As the demand for video services increases and new video services become available, coding techniques with better coding efficiency, performance, and rate control are needed.

[0047]

[0062] Described herein are systems, apparatus, processes (also referred to as methods), and computer-readable media (collectively "systems and techniques") for performing image and / or video coding using one or more machine learning (ML) systems. In general, ML may be considered a subset of artificial intelligence (AI). ML systems may include algorithms and statistical models that computer systems can use to perform various tasks by relying on patterns and inferences without explicit instructions. One example of an ML system is a neural network (also referred to as an artificial neural network), which may include an interconnected group of artificial neurons (e.g., neuron models). Neural networks may be used in a variety of applications and / or devices, such as image and / or video coding, image analysis and / or computer vision applications, Internet Protocol (IP) cameras, Internet of Things (IoT) devices, autonomous vehicles, service robots, among others.

[0048]

[0063] Individual nodes in a neural network can emulate biological neurons by taking input data and performing simple operations on the data. The results of the simple operations performed on the input data may be selectively passed to other neurons. Each vector and node in the network is associated with a weight value, which constrains how the input data relates to the output data. For example, the input data of each node may be multiplied by the corresponding weight value and the products may be summed. The summed products may be adjusted by an optional bias, and an activation function may be applied to the result to obtain the output signal or "output activation" of the node (sometimes called a feature map or activation map). The weight values ​​may initially be determined by an iterative flow of training data through the network (e.g., the weight values ​​are established during a training phase in which the network learns how to identify particular classes by their typical input data characteristics).

[0049]

[0064] There are different types of neural networks, such as convolutional neural networks (CNNs), recurrent neural networks (RNNs), generative adversarial networks (GANs), multilayer perceptron (MLP) neural networks, and transformer neural networks, among others. For example, convolutional neural networks (CNNs) are a type of feed-forward artificial neural network. Convolutional neural networks may include a collection of artificial neurons, each with a receptive field (e.g., a spatially localized region of the input space) and tiling the input space together. RNNs work in a way that they save the output of a layer and feed this output back to the input to help predict the outcome of the layer. GANs are a form of generative neural network that can learn patterns in the input data so that the neural network model can generate new synthetic outputs that can reasonably be from the original dataset. A GAN can include two neural networks working together, including a generative neural network that generates a synthesized output and a discriminative neural network that evaluates the output for reliability. In an MLP neural network, data can be fed into an input layer, and one or more hidden layers provide a level of abstraction to the data. Predictions can then be made in the output layer based on the abstracted data.

[0050]

[0065] Deep learning (DL) is an example of a machine learning technique and can be considered a subset of ML. Many DL approaches are based on neural networks, such as RNNs or CNNs, and utilize multiple layers. The use of multiple layers in a deep neural network can allow increasingly higher levels of features to be extracted from a given input of raw data. For example, the output of a first layer of artificial neurons becomes the input to a second layer of artificial neurons, the output of the second layer of artificial neurons becomes the input to a third layer of artificial neurons, and so on. The layers located between the input and output of the entire deep neural network are often referred to as hidden layers. Hidden layers learn (e.g., are trained) to transform intermediate inputs from previous layers into slightly more abstract and synthetic representations that can be provided to subsequent layers until a final or desired representation is obtained as the final output of the deep neural network.

[0051]

[0066] CNNs (and in some cases RNNs) are commonly used in the context of image-based inputs, e.g., to implement computer vision or perform image / video coding. For example, in the context of image / video coding, existing approaches utilize autoregressive CNNs to implement a priori models that are used to perform entropy encoding and decoding. Although some existing approaches have been shown to achieve rate-distortion performance comparable to or superior to that of traditional codecs, low-latency (e.g., real-time or near real-time) coding cannot be achieved due to the complexity and latency of the autoregressive decoding performed by autoregressive CNNs.

[0052]

[0067] Systems and techniques are needed to perform image and video coding accurately and more efficiently with low latency. Although ML and DL based approaches have shown theoretical improvements over existing codecs in terms of rate-distortion performance, these existing approaches are often limited by their lack of ability to perform with low latency (e.g., based on autoregressive decoding performed by autoregressive CNNs, as described above). Furthermore, as the resolution of image and video data continues to increase, the computational execution times of these existing approaches will likely only continue to increase.

[0053]

[0068] In some aspects, the systems and techniques described herein include transformer-based image and video coding systems that can perform low-latency image and / or video coding using faster coding (e.g., decoding) than other neural network-based image and / or video coding systems, such as CNN-based transforms. For example, using transformer-based transforms, the systems and techniques described herein can achieve coding efficiency improvements of at least 7% using the Kodak image compression dataset and 12% using the Ultra Video Group (UVG) video compression dataset (low latency mode).

[0054]

[0069] A Transformer is a type of deep learning model that utilizes an attention mechanism to weight the significance of each portion of input data differently and model long-term dependencies. Transformers are often used to handle sequential input data, but the Transformer does not necessarily process data in the same order in which the data was originally received or arranged. Furthermore, because the Transformer can use attention to determine contextual relationships between portions of the input data, the Transformer can process some or all of the portions in parallel, such as when calculating attention or self-attention. This parallelization can provide greater computational flexibility, for example, compared to RNNs, CNNs, or other neural networks trained to perform the same task.

[0055]

[0070] In some cases, the transformer-based image and video coding systems described herein include an encoder sub-network and a decoder sub-network, each including a plurality of successive shift-window transformer layers. The encoder sub-network applies a transformation to convert an input image into a latent representation, while the decoder sub-network applies a transformation to convert the latent representation into a reconstructed image, which is a reconstructed version of the input image. The input images can include still images (e.g., photographs and other types of still images) and video images (e.g., frames of video). In some examples, the encoder and decoder sub-networks can apply nonlinear transformations that are used in conjunction with factorized priors (e.g., as opposed to the computationally more complex autoregressive priors used in CNN-based approaches) to enable low-latency encoding and decoding of image data. Moreover, the transformer-based image and video coding systems described herein can achieve this low-latency encoding and decoding with rate-distortion losses that are comparable to or improve upon those associated with existing neural network image and video coding systems (e.g., CNN-based image and video coding systems).

[0056]

[0071] In some examples, the decoder sub-network is symmetrical to the encoder sub-network, except for a patch separation engine that replaces and reverses the functionality of the patch merging engine contained within the encoder sub-network. The encoder and decoder sub-networks operate over a series of patches (also referred to herein as "patch tokens"). In some cases, the series of patches is first formed in the encoder sub-network as a non-overlapping segmentation of the input image.

[0057]

[0072] In some aspects, the encoder sub-network and the decoder sub-network utilize a modified self-attention calculation using a shifting window approach. The shifting window approach is based on a pair of self-attention layers (also referred to as a self-attention layer pair) that restricts the self-attention calculation to non-overlapping local windows while also allowing cross-window combination. In some examples, cross-window combination can be utilized in a deeper self-attention layer to determine an attention vector that each spans (e.g., based on elements from) multiple separate attention windows of a lower self-attention layer. In an illustrative example, a first layer of the self-attention layer pair can apply a first partitioning configuration to partition a set of patches into non-overlapping windows that each encompass multiple patches, and then self-attention is calculated locally within each window. In a second self-attention layer of the self-attention layer pair, the window partitioning is shifted, resulting in a new window that overlaps a window from the first self-attention layer. The self-attention computation within the shifted window of the second self-attention layer crosses the boundary of the previous window in the first self-attention layer, thereby resulting in a connection between them.

[0058]

[0073] By confining the self-attention calculation to non-overlapping local windows of the first self-attention layer, the transformer-based image and video coding system described herein can achieve higher efficiency and computational performance that supports low-latency image and video encoding and decoding (and in some cases, real-time or near real-time encoding and decoding, such as when a fast entropy model is used). For example, in some aspects, the transformer-based image and video coding system has linear computational complexity with respect to image size. By introducing cross-window coupling determined by the shift window partition of the second self-attention layer, the transformer-based image and video coding system described herein can achieve rate-distortion loss that is comparable to or improves on the rate-distortion loss associated with CNN-based approaches and other existing image and video coding approaches.

[0059]

[0074] Various aspects of the present disclosure are described with reference to the figures. Figure 1 illustrates an example implementation of a system on chip (SOC) 100 that may include a central processing unit (CPU) 102 or a multi-core CPU configured to perform one or more of the functions described herein. Among other information, parameters or variables (e.g., neural signals and synaptic weights), system parameters associated with a computing device (e.g., neural networks with weights), delays, frequency bin information, task information, may be stored in a memory block associated with a neural processing unit (NPU) 108, a memory block associated with the CPU 102, a memory block associated with a graphics processing unit (GPU) 104, a memory block associated with a digital signal processor (DSP) 106, a memory block 118, and / or may be distributed across multiple blocks. Instructions executed in the CPU 102 may be loaded from a program memory associated with the CPU 102 or from the memory block 118.

[0060]

[0075] The SOC 100 may also include a GPU 104, a DSP 106, a connectivity block 110 that may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc., as well as additional processing blocks adapted to specific functions, such as a multimedia processor 112 that may detect and recognize gestures. In one implementation, the NPU is implemented within the CPU 102, the DSP 106, and / or the GPU 104. The SOC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120 that may include a global positioning system.

[0061]

[0076] The SOC 100 may be based on an ARM instruction set. In one aspect of the disclosure, the instructions loaded into the CPU 102 may comprise code for searching a stored multiplication result in a look-up table (LUT) corresponding to the multiplication product of the input value and the filter weight. The instructions loaded into the CPU 102 may also comprise code for disabling a multiplier during a multiplication operation of the multiplication product when a look-up table hit of the multiplication product is detected. Additionally, the instructions loaded into the CPU 102 may comprise code for storing the calculated multiplication product of the input value and the filter weight when a look-up table miss of the multiplication product is detected.

[0062]

[0077] SOC 100 and / or its components may be configured to perform video compression and / or decompression (also referred to as video encoding and / or decoding, collectively referred to as video coding) using machine learning techniques in accordance with aspects of the disclosure described herein. By using a deep learning architecture to perform video compression and / or decompression, aspects of the disclosure can increase the efficiency of video compression and / or decompression on a device. For example, a device using the described video coding techniques can more efficiently compress video using machine learning based techniques and transmit the compressed video to another device that can more efficiently decompress the compressed video using the machine learning based techniques described herein.

[0063]

[0078] As mentioned above, a neural network is an example of a machine learning system, and may include an input layer, one or more hidden layers, and an output layer. Data is provided from input nodes in the input layer, processing is performed by hidden nodes in one or more hidden layers, and output is generated through output nodes in the output layer. A deep learning network typically includes multiple hidden layers. Each layer of a neural network may include a feature map or activation map, which may include artificial neurons (or nodes). The feature map may include filters, kernels, etc. The nodes may include one or more weights that are used to indicate the importance of one or more nodes of the layer. In some cases, a deep learning network may have a series of many hidden layers, with early layers being used to determine simple, low-level characteristics of the input, and later layers building a hierarchy of more complex and abstract characteristics.

[0064]

[0079] A deep learning architecture may learn a hierarchy of features. When presented with visual data, for example, a first layer may learn to recognize relatively simple features such as edges in the input stream. In another example, when presented with auditory data, the first layer may learn to recognize spectral power at specific frequencies. A second layer, taking as input the output of the first layer, may learn to recognize combinations of features such as simple shapes in the case of visual data, or combinations of sounds in the case of auditory data. For example, higher layers may learn to represent complex shapes in visual data or words in auditory data. Even higher layers may learn to recognize common visual objects or spoken phrases.

[0065]

[0080] Deep learning architectures may work particularly well when applied to problems that have a natural hierarchical structure. For example, classification of electric vehicles may benefit from first learning to recognize wheels, windshields, and other features. These features may be combined in different ways at higher layers to recognize cars, trucks, and planes.

[0066]

[0081] Neural networks may be designed with various connectivity patterns. In feedforward networks, each neuron in a given layer communicates with neurons in a higher layer, so that information is passed from lower layers to higher layers. As described above, hierarchical representations may be constructed in successive layers of a feedforward network. Neural networks may also have recurrent or feedback (also called top-down) connections. In recurrent connections, the output from a neuron in a given layer may be transmitted to another neuron in the same layer. Recurrent architectures may be useful in recognizing patterns across two or more of the input data chunks delivered in a sequence to the neural network. Connections from neurons in a given layer to neurons in a lower layer are called feedback (or top-down) connections. Networks with many feedback connections may be useful when recognition of high-level concepts can help distinguish certain low-level features of the input.

[0067]

[0082] The connections between layers of a neural network may be fully connected or locally connected. FIG. 2A shows an example of a fully connected neural network 202. In the fully connected neural network 202, a neuron in a first layer may transmit its output to every neuron in a second layer, so that each neuron in the second layer receives input from every neuron in the first layer. FIG. 2B shows an example of a locally connected neural network 204. In the locally connected neural network 204, a neuron in a first layer may be connected to a limited number of neurons in the second layer. More generally, the locally connected layers of the locally connected neural network 204 may be configured such that each neuron in a layer has the same or similar connectivity pattern, but with connection strengths that may have different values ​​(e.g., 210, 212, 214, and 216). Because higher layer neurons in a given region may receive inputs that are tuned through training to the properties of a limited subset of all inputs to the network, the connectivity patterns of local connections may give rise to spatially distinct receptive fields within the higher layers.

[0068]

[0083] As mentioned above, digital video data can contain large amounts of data that can place a significant burden on communication networks as well as devices that process and store the video data. For example, recording uncompressed video content generally results in large file sizes that increase significantly as the resolution of the recorded video content increases. In one illustrative example, uncompressed video with 16 bits per channel recorded at 1080p / 24 (e.g., a resolution of 1920 pixels wide and 1080 pixels high captured at 24 frames per second) can occupy 12.4 megabytes per frame, or 297.6 megabytes per second. Uncompressed video with 16 bits per channel recorded at 4K resolution at 24 frames per second can occupy 49.8 megabytes per frame, or 1195.2 megabytes per second.

[0069]

[0084] Network bandwidth is another constraint that can be problematic for large video files. For example, video content is often delivered over wireless networks (e.g., over LTE, LTE Advanced, New Radio (NR), WiFi™, Bluetooth™, or other wireless networks) and can constitute a large portion of consumer Internet traffic. Despite advances in the amount of available bandwidth in wireless networks, it may still be desirable to reduce the amount of bandwidth used to deliver video content in these networks.

[0070]

[0085] Because uncompressed video content can result in large files that may require significant memory for physical storage and significant bandwidth for transmission, video coding techniques may be utilized to compress and then decompress such video content.

[0071]

[0086] In order to reduce the size of video content and therefore the amount of storage required to store the video content and the amount of bandwidth required to deliver the video content, various video coding techniques may be implemented according to specific video coding standards such as HEVC, AVC, MPEG, VVC, among others. Video coding often uses prediction methods such as inter-prediction or intra-prediction that exploit redundancy present in a video image or sequence. A common goal of video coding techniques is to compress video data into a format that uses a lower bit rate while avoiding or minimizing degradation of video quality. As the demand for video services increases and new video services become available, coding techniques with better coding efficiency, performance, and rate control are needed.

[0072]

[0087] In general, an encoding device encodes video data according to a video coding standard to generate an encoded video bitstream. In some examples, an encoded video bitstream (or "video bitstream" or "bitstream") is a sequence of one or more coded video sequences. An encoding device may generate a coded representation of a picture by partitioning each picture into multiple slices. A slice is independent of other slices such that information in the slice is coded without dependency on data from other slices in the same picture. A slice includes one or more slice segments, including an independent slice segment and, if present, one or more dependent slice segments that depend on previous slice segments. In HEVC, a slice is partitioned into coding tree blocks (CTBs) of luma samples and chroma samples. The CTB of luma samples and one or more CTBs of chroma samples, together with syntax for the samples, are referred to as a coding tree unit (CTU). A CTU may also be referred to as a "treeblock" or a "largest coding unit" (LCU). A CTU is the basic processing unit for HEVC encoding. A CTU may be split into multiple coding units (CUs) of various sizes, each of which contains a luma sample array and a chroma sample array, each of which is called a coding block (CB).

[0073]

[0088] The luma CB and the chroma CB may be further split into prediction blocks (PBs). A PB is a block of luma or chroma component samples that uses the same motion parameters for inter prediction or intra block copy (IBC) prediction (when available or enabled for use). The luma PB and one or more chroma PBs, together with associated syntax, form a prediction unit (PU). In the case of inter prediction, a set of motion parameters (e.g., one or more motion vectors, reference indexes, etc.) is signaled in the bitstream for each PU and is used for inter prediction of the luma PB and one or more chroma PBs. The motion parameters are sometimes referred to as motion information. The CB may also be partitioned into one or more transform blocks (TBs). A TB represents a square block of samples of a color component to which a residual transform (e.g., possibly the same two-dimensional transform) is applied to code the prediction residual signal. A transform unit (TU) represents a TB of luma and chroma samples, as well as the corresponding syntax elements. Transform coding is described in more detail below.

[0074]

[0089] According to the HEVC standard, the transform may be performed using TUs. The TUs may be sized based on the size of the PUs in a given CU. The TUs may be the same size or smaller than the PUs. In some examples, the residual samples corresponding to the CU may be subdivided into smaller units using a quadtree structure called a residual quadtree (RQT). Leaf nodes of the RQT may correspond to TUs. Pixel difference values ​​associated with the TUs may be transformed to generate transform coefficients. The transform coefficients may then be quantized by the encoding device.

[0075]

[0090] Once a picture of video data is partitioned into CUs, the encoding device predicts each PU using a prediction mode. The prediction unit or prediction block is then subtracted from the original video data to obtain a residual (described below). For each CU, a prediction mode may be signaled inside the bitstream using syntax data. The prediction mode may include intra prediction (or intra-picture prediction) or inter prediction (or inter-picture prediction). Intra prediction exploits the correlation between spatially neighboring samples within a picture. For example, with intra prediction, each PU is predicted from neighboring image data in the same picture, for example, using DC prediction to find the mean value for the PU, planar prediction to fit a flat surface to the PU, directional prediction to extrapolate from neighboring data, or any other suitable type of prediction. Inter prediction uses temporal correlation between pictures to derive a motion compensated prediction for a block of image samples. For example, with inter prediction, each PU is predicted using motion compensated prediction from image data in one or more reference pictures (before or after the current picture in output order). The decision as to whether a picture area should be coded using inter-picture prediction or intra-picture prediction may be made, for example, at the CU level.

[0076]

[0091] After performing prediction using intra prediction and / or inter prediction, the encoding device may perform transformation and quantization. For example, following prediction, the encoding device may calculate a residual value corresponding to the PU. The residual value may include pixel difference values ​​between a current block of pixels being coded (PU) and a predictive block (e.g., a predicted version of the current block) used to predict the current block. For example, after generating a predictive block (e.g., issuing an inter prediction or intra prediction), the encoding device may generate a residual block by subtracting the predictive block generated by the prediction unit from the current block. The residual block includes a set of pixel difference values ​​that quantify differences between pixel values ​​of the current block and pixel values ​​of the predictive block. In some examples, the residual block may be represented in a two-dimensional block format (e.g., a two-dimensional matrix or array of pixel values). In such examples, the residual block is a two-dimensional representation of pixel values.

[0077]

[0092] Any residual data that may remain after prediction is performed is transformed using a block transform, which may be based on a discrete cosine transform, a discrete sine transform, an integer transform, a wavelet transform, other suitable transform functions, or any combination thereof. In some cases, one or more block transforms (e.g., size 32x32, 16x16, 8x8, 4x4, or other suitable sizes) may be applied to the residual data in each CU. In some embodiments, TUs may be used for the transform and quantization processes performed by the encoding device. A given CU having one or more PUs may also include one or more TUs. As described in more detail below, the residual values ​​may be transformed into transform coefficients using a block transform, and then quantized and scanned using the TUs to generate serialized transform coefficients for entropy coding.

[0078]

[0093] The encoding device may perform quantization of the transform coefficients. Quantization provides further compression by quantizing the transform coefficients to reduce the amount of data used to represent the coefficients. For example, quantization may reduce the bit depth associated with some or all of the coefficients. In one example, a coefficient having an n-bit value may be truncated to an m-bit value during quantization, where n is greater than m.

[0079]

[0094] Once quantization is performed, the coded video bitstream includes the quantized transform coefficients, prediction information (e.g., prediction modes, motion vectors, block vectors, etc.), partition information, and any other suitable data, such as other syntax data. Various elements of the coded video bitstream may then be entropy coded by an encoding device. In some examples, the encoding device may scan the quantized transform coefficients utilizing a predefined scan order to generate serialized vectors that may be entropy coded. In some examples, the encoding device may perform an adaptive scan. After scanning the quantized transform coefficients to form vectors (e.g., one-dimensional vectors), the encoding device may entropy code the vectors. For example, the encoding device may use context-adaptive variable length coding, context-adaptive binary arithmetic coding, syntax-based context-adaptive binary arithmetic coding, probability interval partition entropy coding, or another suitable entropy coding technique.

[0080]

[0095] The encoding device may store the encoded video bitstream and / or send the encoded video bitstream data via a communication link to a receiving device, which may include a decoding device. The decoding device may decode the encoded video bitstream data by entropy decoding and extracting (e.g., using an entropy decoder) elements of one or more coded video sequences that make up the encoded video data. The decoding device may then rescale the encoded video bitstream data and perform an inverse transform on the encoded video bitstream data. The residual data is then passed to a prediction stage of the decoding device. The decoding device then predicts blocks of pixels (e.g., PUs) using intra prediction, inter prediction, IBC, and / or other types of prediction. In some examples, the prediction is added to the output of the inverse transform (the residual data). The decoding device may output the decoded video to a video destination device, which may include a display or other output device for displaying the decoded video data to a consumer of the content.

[0081]

[0096] Video coding systems and techniques defined by various video coding standards (e.g., the HEVC video coding techniques described above) may be able to preserve most of the information in the raw video content and may be defined a priori based on concepts of signal processing and information theory. However, in some cases, machine learning (ML)-based image and / or video systems may provide benefits over non-ML-based image and video coding systems, such as end-to-end neural network-based image and video coding (E2E-NNVC) systems. As described above, many E2E-NNVC systems are designed as a combination of an autoencoder sub-network (encoder sub-network) and a second sub-network responsible for learning a probability model on the quantization latent used for entropy coding. Such an architecture can be seen as a combination of a transform plus quantization module (encoder sub-network) and an entropy modeling sub-network module.

[0082]

[0097] FIG. 3 illustrates a system 300 including a device 302 configured to perform image and / or video encoding and decoding using an E2E-NNVC system 310. The device 302 is coupled to a camera 307 and a storage medium 314 (e.g., a data storage device). In some implementations, the camera 307 is configured to provide image data 308 (e.g., a video data stream) to a processor 304 for encoding by the E2E-NNVC system 310. In some implementations, the device 302 can be coupled to and / or include multiple cameras (e.g., a dual camera system, three cameras, or other number of cameras). In some cases, the device 302 can be coupled to a microphone and / or other input devices (e.g., a keyboard, a mouse, a touch input device such as a touch screen and / or a touch pad, and / or other input devices). In some examples, the camera 307, the storage medium 314, the microphone, and / or other input devices can be part of the device 302.

[0083]

[0098] The device 302 is also coupled to a second device 390 via a transmission medium 318, such as one or more wireless networks, one or more wired networks, or a combination thereof. For example, the transmission medium 318 may include a channel provided by a wireless network, a wired network, or a combination of a wired network and a wireless network. The transmission medium 318 may form part of a packet-based network, such as a local area network, a wide area network, or a global network such as the Internet. The transmission medium 318 may include routers, switches, base stations, or any other equipment that may be useful for facilitating communication from a source device to a receiving device. The wireless network may include any wireless interface or combination of wireless interfaces, and may include any suitable wireless network (e.g., the Internet or other wide area network, a packet-based network, WiFi™, Radio Frequency (RF), UWB, WiFi-Direct, cellular, Long Term Evolution (LTE), WiMax™, etc.). The wired network may include any wired interface (e.g., fiber, Ethernet, powerline Ethernet, Ethernet over coaxial cable, digital signal line (DSL), etc.). Wired and / or wireless networks may be implemented using a variety of equipment, such as base stations, routers, access points, bridges, gateways, switches, etc. The encoded video bitstream data may be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to a receiving device.

[0084]

[0099] The device 302 includes one or more processors 304 (referred to herein as “processors”) coupled to a memory 306, a first interface (“I / F1”) 312, and a second interface (“I / F2”) 316. The processor 304 is configured to receive image data 308 from a camera 307, from the memory 306, and / or from a storage medium 314. The processor 304 is coupled to the storage medium 314 via the first interface 312 (e.g., via a memory bus) and to a transmission medium 318 via a second interface 316 (e.g., a network interface device, a wireless transceiver and antenna, one or more other network interface devices, or a combination thereof).

[0085]

[0100] The processor 304 includes an E2E-NNVC system 310. The E2E-NNVC system 310 includes an encoder portion 362 and a decoder portion 366. In some implementations, the E2E-NNVC system 310 may include one or more autoencoders. The encoder portion 362 is configured to receive input data 370 and process the input data 370 to generate output data 374 based at least in part on the input data 370.

[0086]

[0101] In some implementations, the encoder portion 362 of the E2E-NNVC system 310 is configured to perform lossy compression of the input data 370 to generate the output data 374, such that the output data 374 has fewer bits than the input data 370. The encoder portion 362 may be trained to compress the input data 370 (e.g., an image or video frame) without using motion compensation based on any prior representation (e.g., one or more previously reconstructed frames). For example, the encoder portion 362 may compress a video frame using only video data from that video frame and without using any data from previously reconstructed frames. The video frames processed by the encoder portion 362 may be referred to herein as intra-predicted frames (I-frames). In some examples, the I-frames may be generated using conventional video coding techniques (e.g., in accordance with HEVC, VVC, MPEG-4, or other video coding standards). In such examples, the processor 304 may include or be coupled to a video coding device (e.g., an encoding device) configured to perform block-based intra prediction, such as that described above with respect to the HEVC standard. In such examples, the E2E-NNVC system 310 may be excluded from the processor 304.

[0087]

[0102] In some implementations, the encoder portion 362 of the E2E-NNVC system 310 may be trained to compress input data 370 (e.g., a video frame) using motion compensation based on a previous representation (e.g., one or more previously reconstructed frames). For example, the encoder portion 362 may compress a video frame using video data from that video frame and using data from a previously reconstructed frame. The video frames processed by the encoder portion 362 may be referred to herein as intra-predicted frames (P-frames). Motion compensation may be used to determine data for a current frame by describing how pixels from a previously reconstructed frame move to new positions within the current frame along with residual information.

[0088]

[0103] As shown, the encoder portion 362 of the E2E-NNVC system 310 may include a neural network 363 and a quantizer 364. The neural network 363 may include one or more transformers, one or more convolutional neural networks (CNNs), one or more fully connected neural networks, one or more gated recurrent units (GRUs), one or more Long Short-Term Memory (LSTM) networks, one or more ConvRNNs, one or more ConvGRUs, one or more ConvLSTMs, one or more GANs, any combination thereof, and / or other types of neural network architectures that generate intermediate data 372. The intermediate data 372 is input to the quantizer 364. Examples of components that may be included in the encoder portion 362 are shown in FIGS. 5A and 6A.

[0089]

[0104] The quantizer 364 is configured to perform quantization and possibly entropy coding of the intermediate data 372 to generate the output data 374. The output data 374 may include the quantized (and possibly entropy coded) data. The quantization operation performed by the quantizer 364 may result in the generation of a quantization code (or data representing the quantization code generated by the E2E-NNVC system 310) from the intermediate data 372. The quantization code (or data representing the quantization code) may also be referred to as a latent code (denoted as z) or a latent. The entropy model applied to the latent may be referred to herein as a "prior." In some examples, the quantization and / or entropy coding operation may be performed using existing quantization and entropy coding operations performed when encoding and / or decoding video data according to existing video coding standards. In some examples, the quantization and / or entropy coding operation may be performed by the E2E-NNVC system 310. In one illustrative example, the E2E-NNVC system 310 can be trained using supervised training, where residual data is used as input during training and quantization codes and entropy codes are used as known outputs (labels).

[0090]

[0105] The decoder portion 366 of the E2E-NNVC system 310 is configured to receive output data 374 (e.g., directly from the quantizer 364 and / or from the storage medium 314). The decoder portion 366 can process the output data 374 to generate a representation 376 of the input data 370 based at least in part on the output data 374. In some examples, the decoder portion 366 of the E2E-NNVC system 310 includes a neural network 368, which may include one or more transformers, one or more CNNs, one or more fully connected neural networks, one or more GRUs, one or more LSTM networks, one or more ConvRNNs, one or more ConvGRUs, one or more ConvLSTMs, one or more GANs, any combination thereof, and / or other types of neural network architectures. Examples of components that may be included in the decoder portion 366 are illustrated in FIG. 5B and FIG. 6A.

[0091]

[0106] The processor 304 is configured to send the output data 374 to at least one of the transmission medium 318 or the storage medium 314. For example, the output data 374 may be stored in the storage medium 314 for later retrieval and decoding (or decompression) by the decoder portion 366 to generate a representation 376 of the input data 370 as reconstructed data. The reconstructed data may be used for various purposes, such as for playback of the video data that was encoded / compressed to generate the output data 374. In some implementations, the output data 374 may be decoded in another decoder device that matches the decoder portion 366 (e.g., in the device 302, in the second device 390, or in another device) to generate the representation 376 of the input data 370 as reconstructed data. For example, the second device 390 may include a decoder that matches (or substantially matches) the decoder portion 366, and the output data 374 may be transmitted to the second device 390 via the transmission medium 318. The second device 390 can process the output data 374 to generate a representation 376 of the input data 370 as reconstructed data.

[0092]

[0107] The components of system 300 may include and / or be implemented using electronic circuitry or other electronic hardware, which may include one or more programmable electronic circuitry (e.g., a microprocessor, a graphics processing unit (GPU), a digital signal processor (DSP), a central processing unit (CPU), and / or other suitable electronic circuitry), and / or may include and / or be implemented using computer software, firmware, or any combination thereof, to perform various operations described herein.

[0093]

[0108] Although system 300 is shown as including several components, one skilled in the art will appreciate that system 300 can include more or fewer components than those shown in Figure 3. For example, system 300 can also include or be part of a computing device including input and output devices (not shown). In some implementations, system 300 may also include, or be a part of, a computing device that includes one or more memory devices (e.g., one or more random access memory (RAM) components, read-only memory (ROM) components, cache memory components, buffer components, database components, and / or other memory devices), one or more processing devices (e.g., one or more CPUs, GPUs, and / or other processing devices) in communication with and / or electrically connected to the one or more memory devices, one or more wireless interfaces (e.g., including one or more transceivers and a baseband processor for each wireless interface) for performing wireless communications, one or more wired interfaces (e.g., serial interfaces, such as universal serial bus (USB) inputs, lightening connectors, and / or other wired interfaces) for performing communications over one or more hardwired connections, and / or other components not shown in FIG. 3 .

[0094]

[0109] In some implementations, system 300 may be implemented locally by and / or included in a computing device, such as a mobile device, a personal computer, a tablet computer, a virtual reality (VR) device (e.g., a head mounted display (HMD) or other VR device), an augmented reality (AR) device (e.g., an HMD, AR glasses, or other AR device), a wearable device, a server (e.g., in a Software as a Service (SaaS) system or other server-based system), a television, and / or any other computing device having resource capabilities to perform the techniques described herein.

[0095]

[0110] In one example, the E2E-NNVC system 310 may be incorporated into a portable electronic device including a memory 306 coupled to a processor 304 and configured to store instructions executable by the processor 304, and a wireless transceiver coupled to an antenna and the processor 304 and operable to transmit output data 374 to a remote device.

[0096]

[0111] FIG. 4 illustrates an example of an E2E-NNVC system that uses convolutional neural network layers to implement a hyperprior model for image and / or video coding. a Sub-network and g s The sub-networks correspond to the encoder sub-network (e.g., encoder portion 362) and the decoder sub-network (e.g., decoder portion 366), respectively. a Sub-network and g sThe sub-network is designed for a three-channel RGB input, and all three R, G, and B input channels pass through and are processed by the same neural network layers (convolutional layers and generalized divisive normalization (GDN) layers). The E2E-NNVC system (such as that shown in FIG. 4) can target input channels with similar statistical properties, such as RGB data (where the statistical properties of the different R, G, and B channels are similar) and / or YUV data. However, as described above, CNNs trained to perform image coding still cannot achieve low-latency performance of either the encoding or decoding operations, such as based on the use of autoregressive priors (which results in slow decoding times).

[0097]

[0112] As mentioned above, systems and techniques are described herein for performing image and / or video coding (e.g., low latency encoding and decoding) using one or more transformer neural networks. The transformer neural network may include transformer blocks and / or layers organized, for example, according to the hyperprior architecture of FIG. 4 and / or the scale-space flow (SSF) architecture of FIG. 6B described below. For example, the four convolutional networks g shown in FIG. a , g s , h a , and h s can alternatively be implemented as corresponding four Transformer Neural Networks, as will be explained in more depth below.

[0098]

[0113] In some examples, one or more transformer-based neural networks described herein may be trained using a loss function based at least in part on rate-distortion. The distortion may be determined as the mean square error (MSE) between an original image (e.g., an image that would be provided as an input to an encoder sub-network) and a decompressed / decoded image (e.g., an image restored by a decoder sub-network). In some examples, the loss function used in training a transformer-based media coding neural network may be based on a trade-off between distortion and rate using Lagrangian multipliers. One example of such a rate-distortion loss function is L=D+β * R, where D represents distortion, R represents rate, and different β values ​​represent models trained for different bit rates and / or peak-signal-to-noise ratios (PSNR).

[0099]

[0114] In one illustrative example, unsupervised learning techniques (without supervision) can be used to train one or more of the transformer-based neural networks described herein. The unsupervised training process may eliminate the need to label or classify portions of the training data or elements thereof. For example, a backpropagation training process can be used to adjust the weights (and in some cases other parameters such as biases) of nodes of a neural network, e.g., the encoder and / or decoder sub-networks such as those shown in Figures 5A and 5B, respectively. Backpropagation includes a forward pass, a loss function, a backward pass, and a weight update. In some examples, the loss function can include the rate-distortion-based loss function described above. The forward pass, loss function, backward pass, and parameter update can be performed during one training iteration. The process is repeated for a certain number of iterations for each set of training data until the weights of the parameters of the encoder or decoder sub-network are precisely adjusted.

[0100]

[0115] Since the actual output values ​​may differ significantly from the training data outputs, the loss (or error) may be high for the initial training data inputs. The goal of training is to find the loss (e.g., loss function L=D+β * The goal of the neural network is to minimize the amount of loss (rate-distortion loss, e.g., using R). The neural network performs a backward pass by determining which inputs (weights) contributed most to the neural network's loss, and then adjusts the weights so that the loss is reduced and ultimately minimized. To determine which weights contributed most to the neural network's loss, the derivative of the loss with respect to the weights (denoted as dL / dW, where W is the weight in a particular layer) is calculated. For example, the weights are updated so that they change in the opposite direction of the gradient. The weight update is

[0101]

number

[0102] where w denotes the weight and w i denotes initial weights and η denotes a learning rate. The learning rate may be set to any suitable value, with a higher learning rate inducing larger weight updates and a lower value indicating smaller weight updates. The shift window transformer layers or blocks of the encoder or decoder sub-network, or components of one such sub-network, continue to be trained in this manner until a desired output is achieved. In some cases, each of the components of the encoder and / or decoder sub-network are trained in a similar manner.

[0103]

[0116] 5A and 5B are briefly introduced below before proceeding with the description of FIGS. 6-7B, which provide an example architecture of a shifting window transformer block (FIG. 6A), an example of patch merging between shifting window transformer layers (FIG. 7A), and an example of shifting window self-attention performed by a pair of transformer blocks within a given transformer layer (FIG. 7B). After the above examples, the description returns to FIGS. 5A and 5B and is given in more detail.

[0104]

[0117] FIG. 5A illustrates an example architecture of an encoder sub-network 500a having a series of transformer layers 520, 530, 540, 550. In some examples, the encoder sub-network 500a may be trained to perform a nonlinear transformation that converts an input image 502 into a latent representation 555a. In some cases, the nonlinear transformation is also an analytical transformation. As illustrated, each encoder transformer layer may include a set of consecutively arranged shift-window transformer blocks 524, 534, 544, and 554 (also referred to herein as an "encoder transformer block set" or "transformer block set"). In some examples, the encoder transformer block sets 524-554 may include one or more pairs of shift-window transformer blocks, such as the example pair of shift-window transformer blocks illustrated in FIG. 6A. For example, the total number of shift window transformer blocks provided in the encoder transformer block set from encoder block set 524-554 can be a multiple of two (e.g., two shift window transformer blocks in transformer block set 524, two shift window transformer blocks in transformer block set 534, six shift window transformer blocks in transformer block set 544, and two shift window transformer blocks in transformer block set 554, as indicated by "x2", "x6", and similar notations in FIG. 5A). An example of a transformer block set having two shift window transformer blocks is shown in FIG. 6A and described below. In some cases, a pair of shift window transformer blocks can correspond to a two-step self-attention calculation process that alternates between using two partition configurations to calculate self-attention over consecutive shift window transformer blocks (e.g., as described with respect to FIG. 6A and FIG. 7B).

[0105]

[0118] 5B illustrates an example architecture of a decoder sub-network 500b having a patch partition engine 510b and a series of transformer layers 560, 570, 580, 590. The patch partition engine 510b can operate similarly to the patch partition engine 510a of the encoder sub-network 500a. In some examples, the decoder sub-network 500b can be trained to perform a nonlinear transformation that transforms the latent representation 555b into the reconstructed image 504. In some cases, the nonlinear transformation is also a synthesis transformation. The latent representation 555b can be the same as the latent representation 555a output by the encoder sub-network 500a, such as in the absence of information loss or corruption in the quantization, entropy coding, and / or data transmission process that communicates the latent representation 555a from the encoder sub-network 500a to the decoder sub-network 500b. As shown, each decoder transformer layer may include a set of consecutively arranged shift window transformer blocks 564, 574, 584, and 594 (also referred to herein as a "decoder transformer block set" or a "transformer block set"). In some examples, the decoder transformer block sets 564-594 may include one or more pairs of shift window transformer blocks, such as the example pair of shift window transformer blocks shown in FIG. 6A. For example, the total number of shift window transformer blocks provided in a decoder transformer block set from transformer decoder block sets 564-594 can be a multiple of two (e.g., two shift window transformer blocks in transformer block set 564, six shift window transformer blocks in transformer block set 574, two shift window transformer blocks in transformer block set 584, and two shift window transformer blocks in transformer block set 594, as indicated by "x2", "x6", and similar notations in FIG. 5B).In some cases, a pair of shifting window transformer blocks may correspond to a two-step self-attention calculation process that alternates between using two partitioning configurations to calculate self-attention across consecutive shifting window transformer blocks (e.g., as with respect to Figures 6A and 7B).

[0106]

[0119] It is noted that in some examples, some or all of the descriptions made herein with reference to the encoder sub-network 500a may also apply to the decoder sub-network 500b. For example, in some cases, one or more of the decoder transformer layers 560-590 may utilize shift window transformer blocks that are identical to or otherwise share a common architecture with the shift window transformer blocks of the encoder transformer layers 520-550. Furthermore, in some examples, the architecture of the decoder sub-network 500b may be symmetrical to the architecture of the encoder sub-network 500a, with the decoder sub-network 500b using patch separation engines 563, 573, 583 instead of the patch merging engines 532, 542, 552 of the encoder sub-network 500a. The symmetry between the architectures of the decoder sub-network 500b and the encoder sub-network 500a may include the use of the same architectural arrangement or configuration of the component shift window transformer blocks provided in the decoder and encoder sub-networks.

[0107]

[0120] FIG. 5C illustrates an example of a transformer-based end-to-end neural network architecture for a neural network-based image and video coding system. In some cases, the transformer-based end-to-end neural network architecture of FIG. 5C can include the encoder sub-network 500a of FIG. 5A and the decoder sub-network 500b of FIG. 5B. The patch split engine (shown as "patch split" in FIG. 5C) is similar to the patch separation engine shown in FIG. 5B and can perform the same operations.

[0108]

[0121] Before returning to Figures 5A and 5B, the discussion now proceeds to the examples shown in Figures 6-7B. As mentioned above, Figures 6-7B provide an example architecture of a shifting window transformer block (Figure 6A), an example of patch merging between shifting window transformer layers (Figure 7A), and an example of shifting window self-attention performed by a pair of transformer blocks within a given transformer layer.

[0109]

[0122] 6A illustrates an example architecture 600 of a first shifting window transformer block 601 and a second shifting window transformer block 603, collectively referred to as a transformer block pair. As illustrated, the first shifting window transformer block 601 includes a layer norm 610a, a self-attention component 622 (also referred to as a "first self-attention layer"), a layer norm 612a, and a feed-forward neural network component 630a, shown as a multi-layer perceptron (MLP). The second shifting window transformer block 603 includes a layer norm 610b, a self-attention component 624 (also referred to as a "second self-attention layer"), a layer norm 612b, and a feed-forward neural network component 630b, again shown as a MLP.

[0110]

[0123] In some examples, the first shifting window transformer block 601 can be the same as the second shifting window transformer block 603, except for their respective self-attention layers 622 and 624, which apply different window partitioning configurations. In some cases, the first self-attention layer 622 can include windowed multi-head self-attention (W-MSA) and the second self-attention layer 624 can include shifted window multi-head self-attention (SW-MSA).

[0111]

[0124] In some examples, the first self-attention layer 622 of the first shift window transformer block 601 can use a shift window with a shift size=0 (corresponding to no shift). For example, when the window size is 8, the first attention layer (e.g., the first self-attention layer 622) can use a shift size=0, the second attention layer (following the first attention layer, such as the second self-attention layer 624) can use a shift size=4, the third attention layer (following the second attention layer) can again use a shift size=0, the fourth attention layer (following the third attention layer) can use a shift size=4, and so on for the number of shift window transformer blocks in a given transformer block set (e.g., as indicated by “x2”, “x6”, and similar notations in FIG. 5A and FIG. 5B). Alternating shift size values ​​(e.g., alternating shift=0 and shift=4) has the effect of propagating the signal between windows. In some cases, the shift size can be variable, so it is not necessary to have a shift=0 followed by a shift=4.

[0112]

[0125] In some examples, the first self-attention layer 622 can apply a non-overlapping window partitioning configuration (such as configuration 720 of FIG. 7B ) to divide the set of patches into non-overlapping windows, each containing multiple patches. The first self-attention layer 622 can then compute self-attention locally within each window. The first self-attention layer 622 can provide self-attention information to a layer norm 612a (e.g., a softmax layer). For example, the first self-attention layer 622 can compute the self-attention value by computing a matrix of outputs as follows:

[0113]

number

[0114]

[0126] Here, the matrix Q=W q X, matrix K=W k X and matrix V=W v The inputs to X, Q, K, and V are the same X (and therefore the "self"). W q , W k , and W v The term d is a linear layer that projects or maps the input vector X to a query (Q), key (K), and value (V) matrix. k refers to the dimension of key k,

[0115]

number

[0116] serves as a scaling factor. softmax refers to the softmax function used to obtain weights for the self-attention values. The layer norm 612a may output weights to a feedforward neural network component 630a (e.g., a multi-layer perceptron (MLP) layer). The output of the first shifting window transformer block 601 may then be provided as an input to the second shifting window transformer block 603.

[0117]

[0127] In the second self-attention layer 624, the window partition is shifted, resulting in a new window that overlaps with that of the first self-attention layer 622. For example, a shifted window partition configuration (such as configuration 730 of FIG. 7B) may be applied by the second self-attention layer 624. The self-attention calculation within the shifted window of the second self-attention layer 624 crosses the boundary of the previous window in the first self-attention layer 622, resulting in a cross-window combination that may be provided to the layer norm 612b. The layer norm 612b may provide an output to a feedforward neural network component 630b.

[0118]

[0128] By determining self-attention locally, the transformer-based image and video coding system described herein can achieve higher efficiency and computational performance that supports low-latency encoding and decoding. For example, in some aspects, the transformer-based image and video coding system has linear computational complexity with respect to image size. By obtaining cross-window combination via a second self-attention layer, the transformer-based image and video coding system can achieve rate-distortion loss that is comparable to or improves on the rate-distortion loss associated with CNN-based and other existing approaches.

[0119]

[0129] FIG. 7A illustrates an example process of merging image patches (e.g., from bottom to top) within a deeper encoder transformer layer in the context of the encoder sub-network 500a, and will be described in more detail below. FIG. 7B illustrates an example of two different window partition configurations, including a window partition configuration 720 and a window partition configuration 730. The window partition configuration 720 illustrates non-overlapping window partitions applied across a set of patch tokens, and in some examples may be utilized by the first self-attention layer 622 of FIG. 6A. An example of a non-overlapping window partition is indicated at 722, and an example of one of its component patch tokens is indicated at 711. In some examples, the first shift window transformer block 601 of FIG. 6A may apply the non-overlapping window partition configuration 720 using the self-attention component 622.

[0120]

[0130] Window partition configuration 730 illustrates a shifting window partition applied across a set of patch tokens, and in some examples may be utilized by the second self-attention layer 624 of Figure 6A. In some cases, the two window partition configurations 720 and 730 may be applied across the same set of patch tokens.

[0121]

[0131] In some examples, the non-overlapping window partitioning configuration 720 divides the set of input patch tokens into equal sized windows, shown here as 4x4 windows encompassing 16 patch tokens. However, other window geometries and / or sizes may be utilized. The shifting window partitioning configuration 730 may utilize displaced windows relative to those of the non-overlapping partitioning configuration 720. For example, the shifting windows 732 and 734 have been displaced such that they each encompass a set of tokens that were previously encompassed in different ones of the non-overlapping windows of the partitioning configuration 720. This may introduce the cross-window coupling discussed above, since a single shifting window encompasses patch tokens from multiple non-overlapping windows of a previous self-attention layer. As shown, the shifting window partitioning configuration 730 uses the same 4x4 window size as the non-overlapping window partitioning configuration, with clipping or truncation of the window size where it extends beyond the boundaries of the patch token set. However, in some examples, the shifting window subdivision configuration 730 and the non-overlapping window partitioning configuration 720 may use different window sizes.

[0122]

[0132] Returning now to the encoder and decoder sub-networks shown in Figures 5A and 5B, as shown in Figure 5A, the first transformer layer 520 of the encoder sub-network 500a includes two shift window transformer blocks (e.g., as indicated by the "x2" label below the shift window transformer block 524), the transformer layer 530 includes two shift window transformer blocks, the transformer layer 540 includes six shift window transformer blocks, and the transformer layer 550 includes two shift window transformer blocks. It is noted that in some examples, one or more of the transformer layers described herein may each include more or fewer shift window transformer blocks than shown in the example of Figure 5A.

[0123]

[0133] The transformer layers 520-550 (and their component shift window transformer blocks) can be based on a Vision Transformer in some examples. A Vision Transformer is a type of transformer architecture that is configured to operate with image-based inputs. Image-based inputs can include still images (e.g., photographs or other types of still images) as well as video images (e.g., frames of a video). Under the Vision Transformer architecture, an input image is first partitioned into multiple non-overlapping patches, which are then projected into a linear space to obtain vectors on which the Vision Transformer(s) can operate.

[0124]

[0134] The encoder sub-network 500a includes a patch partitioning engine 510a that divides an input image 502 into non-overlapping patches (two example patch partitioning operations are shown in FIG. 7A). The input image 502 is designated as having dimensions HxWx3, where H designates height in pixels, W designates width in pixels, and the number 3 designates the number of dimensions of the input image (one dimension for each color channel of the input image, e.g., R, G, and B). Each patch may have the same or similar size, e.g., given by the number of pixels in the height and width dimensions. In some examples, the size of the patches generated by the patch partitioning engine 510a may be predetermined. As shown, the predetermined patch size is 4×4, such that the patches generated by the patch partitioning engine 510a include 16 pixels arranged in a square of 4 pixels per side. However, other sizes and / or height-to-width ratios may be utilized. Additionally, it is noted that the patch partitioning engine 510 may partition the input image 502 into patches as part of the process flow of the encoder sub-network 500a, or may partition the input image 502 into patches beforehand. In some examples, the patches generated by the patch partitioning engine 510a are treated as tokens (also referred to as "patch tokens"), and the features for each token are set as the concatenation of the raw pixel RGB values ​​of the patch's constituent elements. In the illustrated example, the feature dimensions of each 4x4 patch are represented by labels detailing the set of input patches provided to the transformer layer 520.

[0125]

number

[0126] As indicated by, the sum is 48 (e.g., 4 x 4 x 3 = 48).

[0127]

[0135] From the patch partitioning model 510a, a set of non-overlapping patches generated from the input image 502 are provided to a first transformer layer 520. As shown, the first transformer layer 520 includes a linear embedding layer 521 that is applied to the raw features of each patch to project them into an arbitrary dimension C, such as by applying a linear transformation. In some examples, the linear embedding layer 521 may be external to the first transformer layer 520 or otherwise separate from it, e.g., provided in combination with the patch partitioning engine 510a. In addition, it is noted that the linear embedding layer 521 appears only in the first transformer layer 520, while the subsequent transformer layers 530, 540, 550 lack a linear embedding layer but include patch merging engines 532, 542, 552, respectively.

[0128]

[0136] Next, a shifting window transformer block 524 is applied across the patch tokens. As mentioned above, the series of shifting window transformer blocks 524 is shown to include two consecutive shifting window transformer blocks, such as the two seen in FIG. 6A. The shifting window transformer block 524 performs a modified self-attention calculation (described in more detail with respect to FIGS. 6 and 7A-7B) to generate one or more attention vectors that are then used for feature transformation. The output of the shifting window transformer block 524 is then provided as input to a second transformer layer 530, where the patch tokens (e.g.,

[0129]

number

[0130] ) and the number of linear embeddings are both preserved.

[0131]

[0137] To generate a hierarchical representation or feature map from the input image 502, the transformer layers 530, 540, and 550 each include a respective patch merging engine 532, 542, 552. The patch merging engines 532, 542, 552 may be applied to reduce the number of patch tokens that the transformer layers must operate on. As shown, the patch merging engines 532-552 are provided before the shift window transformer blocks 534-554 in each transformer layer. In some examples, one or more of the transformer layers 530-550 may be configured such that the output of its patch merging engine is directly coupled to the input of its set of shift window transform blocks.

[0132]

[0138] In some examples, the patch merging engine 532 is configured to split a set of patches from the previous transformer layer 520 into non-overlapping groups of adjacent patches or blocks. The patch merging engine 532 can concatenate patch features within each group and generate a single new patch for each concatenated group. In one illustrative example, the patch merging operation performed by the patch merging engines 532, 542, 552 can include reordering blocks of spatial data to depth. Specifically, the patch merging operation can include outputting a copy of an input tensor where values ​​from the height and width dimensions are shifted to the depth dimension. Non-overlapping patches or blocks of size block_size x block_size (where block_size represents the spatial size of the input block or patch to be reordered to the depth / channel dimension) are reordered to depth at each location of the block or patch (as each input patch of size block_size x block_size will be collapsed to one pixel in the output). The depth of the output tensor is determined by the block_size x block_size tensor. * block_size *The input_depth is the vertical (Y) and horizontal (X) coordinates within each block of the input become the higher order components of the output channel index. The height and width of the input tensor are divisible by the block_size. In some examples, the encoder sub-network 500a can apply a linear layer after the patch merging operation to change the number of channels of the feature. Similar operations can be performed by the patch merging engine 542 and the patch merging engine 552. Thus, the patch merging engines 532-552 can reduce the number of patch tokens provided to each successive transformer layer 530-550 by a factor equal to the number of patches per merged group. As mentioned above, FIG. 7A illustrates an example process of merging image patches within deeper encoder transformer layers (e.g., from bottom to top) in the context of the encoder sub-network 500a.

[0133]

[0139] Referring to FIG. 5B, the transformer layers 560, 570, and 580 of the decoder sub-network 500b each include a respective patch separation engine 563, 573, and 583 (also referred to as patch splitting engines). The patch separation engines 563, 573, and 583 may perform a patch separation process to upsample (increase their size) the feature maps. The patch separation process is the inverse process of the patch merging process performed by the patch merging engines 532-552. In some examples, the patch separation engine 563 is configured to split non-overlapping groups of adjacent patches from a previous block or layer (e.g., a shift window transformer block in the same transformer layer) from one pixel with four channels to four pixels with one channel (when the upscale factor is 2). For example, in one illustrative example, the patch separation operation performed by the patch separation engines 563, 573, and 583 may be of the form ( * , C×r 2 ,H,W) tensor elements of shape ( *, C, H×r, W×r) tensors, where r is an upscaling factor. In some examples, the decoder sub-network 500b can apply a linear layer after the patch separation operation to change the number of feature channels. FIG. 7A can also be viewed in the context of the decoder sub-network 500b as illustrating an example process of separating image patches within a deeper decoder transformer layer (e.g., from top to bottom).

[0134]

[0140] In the first layer 702, the image data is represented as partitioned into a 16x16 grid of patches, each patch containing some number of distinct pixels from the original input image 502. Patch merging is applied between the first layer 702 and the second layer 704, and between the second layer 704 and the third layer 706. In some examples, the layers 702, 704, 706 can be the same as the transformer layers 520, 530, 540, respectively, and the patch merging process described above can be performed by patch merging engines 532 and 542.

[0135]

[0141] Between the first layer 702 and the second layer 704, patch merging is performed by concatenating features from 2x2 groups of adjacent patches (e.g., in the first layer 702) into a single patch (e.g., in the second layer 704) and applying a linear layer on the concatenated features. Thus, a single merged patch in the second layer 704 contains concatenated features from four separate patches in the first layer 702. The total number of patches is reduced by a factor of four, the resolution is downsampled by a factor of two, and the output dimension of the patch merging process is 2C.

[0136]

[0142] Between the second layer 704 and the third layer 706, the same patch merging process may be applied (e.g., a group of 2x2 adjacent patches is merged into a single patch). The obtained merged patch in the third layer 706 can be considered to contain connected features from four separate patches in the second layer 704, or alternatively, to contain connected features from 16 separate patches in the first layer 702. As between the first layer 702 and the second layer 704, the patch merging process between the second layer 704 and the third layer 706 again reduces the total number of patches by a factor of four and downsamples the resolution by a factor of two. Thus, the output dimension of this patch merging process is 4C.

[0137]

[0143] Thus, when repeated patch merging logic is utilized, each patch merging engine may have different input and output resolutions (e.g., patch merging engine 532 may have different input and output resolutions).

[0138]

number

[0139] Input patch token resolution and

[0140]

number

[0141] and the patch merging engine 542 has an output resolution of

[0142]

number

[0143] Input resolution and

[0144]

number

[0145] and the patch merging engine 552 has an output resolution of

[0146]

number

[0147] Input resolution and

[0148]

number

[0149] 3, the patch merging engines 532-552 may be identical to each other.

[0150]

[0144] Figure 6B is a diagram illustrating an example of a video coding architecture in which one or more transformer-based neural network architectures described herein may be utilized. Using a transformer-based neural network allows the video coding architecture to operate with low latency (e.g., a low-delay video coding architecture). The architecture of the video coding system of Figure 6B is based, at least in part, on a scale-space flow (SSF), which extends or generalizes optical flow by adding a scale parameter to better enable the system to model uncertainty. In the context of Figure 6B, the scale parameter is associated with a scale-space warping component. As shown, the SSF video coding architecture uses an SSF encoder and an SSF decoder, collectively labeled "Flow AE" or flow autoencoder, to perform motion compensation. Both the SSF encoder and the SSF decoder may be based on one or more convolutional transforms. Similarly, both the residual encoder and the residual decoder may be based on one or more convolutional transforms. In some cases, the SSF encoder and the decoder, and the residual encoder and the decoder may each be implemented as a CNN. In some examples, all four of the encoder and decoder components may be implemented as a four-layer CNN.

[0151]

[0145] As shown in Figure 6B, one or more shifting window transformer neural networks described herein can be used to replace the CNN and / or convolutional transform in an SSF architecture in some examples. For example, one or more shifting window transformer neural networks can be provided to replace the SSF encoder, SSF decoder, residual encoder, and / or residual decoder. In some examples, four shifting window transformer neural networks can replace four convolutional components in an SSF video coding architecture, as described in more detail below.

[0152] 8 is a flow chart illustrating an example of a process 800 for processing image and / or video data. At block 802, the process 800 includes obtaining a latent representation of a frame of encoded image data. In some examples, the frame of encoded image data includes an encoded still image. In some examples, the frame of encoded image data includes an encoded video frame.

[0153]

[0147] At block 804, the process 800 includes generating a frame of decoded image data by a plurality of decoder transformer layers of a decoder sub-network using the latent representation of the frame of encoded image data as an input. In some cases, the plurality of decoder transformer layers includes a series of consecutive decoder transformer layers (e.g., a series of decoder transformer layers 560, 570, 580, and 590 shown in FIG. 5B). At least one of the plurality of decoder transformer layers includes one or more transformer blocks for generating one or more patches of features and determining self-attention locally within one or more window partitions and shift window partitions applied across the one or more patches. At least one of the plurality of decoder transformer layers further includes a patch separation engine for reducing a respective size of each patch of the one or more patches. For example, referring to FIG. 5B as an illustrative example, the decoder transformer layer 560 includes a shift window transformer block 564 and a patch separation engine 563. In some aspects, at least a portion of one or more transformer blocks included in at least one decoder transformer layer have the same architecture, hi some aspects, each (e.g., all) of one or more transformer blocks included in at least one decoder transformer layer have the same architecture.

[0154]

[0148] In some examples, to generate a frame of decoded image data, the process 800 may include determining self-attention locally within one or more first window partitions applied across the one or more patches by a first transformer block of a first decoder transformer layer of the multiple decoder transformer layers. The process 800 may further include determining self-attention locally within one or more second window partitions applied across the one or more patches by a second transformer block of the first decoder transformer layer. For example, the one or more second window partitions may be shifted to overlap one or more boundaries between adjacent ones of the one or more first window partitions (e.g., as shown in Figures 7A and 7B). The process 800 may include segmenting, by a patch separation engine, each patch of the one or more patches into multiple separated patches. The multiple separated patches do not overlap. In some examples, each separated patch of the multiple separated patches has a uniform patch size. In some cases, the patch separation engine applies a patch size reduction factor of 2 or other value. In some aspects, to segment each patch of the one or more patches into multiple separate patches, the process 800 can include reducing a feature dimension of the multiple separate patches.

[0155]

[0149] In some cases, the process 800 may include providing the plurality of separation patches to a first transformer block of a second decoder transformer layer of the plurality of decoder transformer layers. For example, the patch separation engine 563 of the decoder transformer layer 560 may provide the separation patches to a transformer block 574 of the decoder transformer layer 570. In some examples, the process 800 may include segmenting the plurality of separation patches by the patch separation engine of the second decoder transformer layer. The process 800 may further include providing an output of the patch separation engine to a third decoder transformer layer of the plurality of decoder transformer layers. For example, the patch separation engine 573 of the decoder transformer layer 570 may provide the separation patches to a decoder transformer layer 580 (e.g., a transformer block 584 of the decoder transformer layer 580). In another example, the linear embedding engine 591 of the decoder transformer layer 590 can apply a linear transformation to the features output from the transformer block 594 and output the linearly transformed features to the patch partitioning engine 510b.

[0156]

[0150] In some aspects, the process 800 can include receiving as input a latent representation of a frame of encoded image data by multiple decoder transformer layers. The process 800 can include applying a nonlinear transform to generate a frame of decoded image data. In some cases, the nonlinear transform is a synthesis transform, and the frame of decoded image data is a reconstruction of an input image associated with the frame of encoded image data.

[0157] In some examples, the process 800 may include training one or more of the decoder transformer layers using a loss function based at least in part on rate-distortion. In some cases, the loss function includes a Lagrangian multiplier for rate-distortion. For example, as described herein, the rate-distortion loss function may be L=D+β * R, where D represents distortion and R represents rate, and different β values ​​represent models trained for different bit rates and / or peak signal-to-noise ratios (PSNR).

[0158] In some examples, the process 800 may include training a plurality of decoder transformer layers (e.g., using unsupervised training or learning) with at least a first training data set and a second training data set. In such examples, the data of the second training data set has a reversed time order compared to the data of the first training data set. In some cases, all layer norm layers in the transformer block may be removed. In some examples, a window size used in the transformer block may be reduced from 8 to 4. Using a reversed time order for the second training set compared to the data of the first training set, removing the layer norm layers in the transformer block, and / or reducing the window size from 8 to 4 may result in stable training.

[0159]

[0153] Figure 9 is a flow chart illustrating an example of a process 900 for processing image and / or video data. At block 902, the process 900 includes segmenting a frame into a number of patches. In some examples, the frame includes a still image. In some examples, the frame includes a video frame (e.g., an unencoded video frame). In some cases, each patch of the number of patches is of uniform size and includes one or more pixels of the segmented frame. For example, the number of patches may be segmented from an input including a still image frame or a video frame.

[0160]

[0154] At block 904, the process 900 includes generating a frame of encoded image data by a plurality of encoder transformer layers of an encoder sub-network using the plurality of patches as input. In some examples, the frame of encoded image data is a latent representation of the image data. In some cases, the latent representation is a hierarchical feature map generated by a plurality of encoder transformer layers of the encoder sub-network. In some examples, the process 900 can include generating a hierarchical feature map for the segmented frame by a plurality of encoder transformer layers of the encoder sub-network using the plurality of patches as input. The process 900 can include generating the frame of encoded image data from the hierarchical feature map.

[0161] In one illustrative example, to generate a frame of encoded image data, the process 900 may include determining self-attention locally within one or more window partitions by a first transformer block of a first encoder transformer layer of the multiple encoder transformer layers. The process 900 may include determining self-attention locally within one or more shift window partitions by a second transformer block of the first encoder transformer layer. In some aspects, the first transformer block and the second transformer block have the same architecture. The one or more shift window partitions overlap the one or more window partitions. The process 900 may further include determining, by one or more of the first transformer block and the second transformer block, one or more patches of features for applying a nonlinear transformation to the segmented frame. The process 900 may include increasing a patch size between the first encoder transformer layer and the second encoder transformer layer by a patch merging engine. As described herein, the patch merging engine is configured to combine multiple adjacent patches from a first encoder Transformer layer into a merged patch that is provided to a second encoder Transformer layer. In some cases, an output of a second Transformer block of the first encoder Transformer layer is coupled to an input of the second encoder Transformer layer.

[0162] In some cases, the process 900 may include increasing the patch size by concatenating features obtained from one or more subsets of adjacent patches using a patch merging engine. The patch merging engine may merge each subset of adjacent patches into a merged patch output.

[0163] In some examples, the process 900 may include providing the multiple patches to a linear embedding layer of the encoder sub-network (e.g., the linear embedding layer 521 of FIG. 5A) prior to the first encoder transformer layer. The linear embedding layer may apply a linear transformation to the multiple patches.

[0164] In some aspects, the process 900 can include training one or more of the encoder transformer layers using a loss function based on a rate-distortion loss. In some cases, the loss function includes a Lagrangian multiplier for the rate-distortion loss. As described above, the rate-distortion loss is expressed as L=D+β * It can be represented as R.

[0165]

[0159] In some aspects, the process 900 may include entropy coding the encoded image data with a factorized prior.

[0166] In some examples, the processes described herein (e.g., process 800, process 900, and / or any other processes described herein) may be performed by a computing device, apparatus, or system. In one example, process 800 and / or process 900 may be performed by a computing device or system having the computing device architecture 1000 of FIG. 10. The computing device, apparatus, or system may include any suitable device, such as a mobile device (e.g., a mobile phone), a desktop computing device, a tablet computing device, a wearable device (e.g., a VR headset, an AR headset, an AR glasses, a network-connected watch or smart watch, or other wearable device), a server computer, an autonomous vehicle or autonomous vehicle computing device, a robotic device, a laptop computer, a smart television, a camera, and / or any other computing device having resource capabilities to perform the processes described herein, including process 800 and / or process 900 and / or any other processes described herein. In some cases, a computing device or apparatus may include various components, such as one or more input devices, one or more output devices, one or more processors, one or more microprocessors, one or more microcomputers, one or more cameras, one or more sensors, and / or other component(s) configured to perform steps of processes described herein. In some examples, a computing device may include a display, a network interface configured to communicate and / or receive data, any combination thereof, and / or other component(s). The network interface may be configured to communicate and / or receive Internet Protocol (IP)-based data or other types of data.

[0167]

[0161] Components of a computing device may be implemented in circuits. For example, components may include and / or be implemented using electronic circuitry or other electronic hardware, which may include one or more programmable electronic circuits (e.g., a microprocessor, a graphics processing unit (GPU), a digital signal processor (DSP), a central processing unit (CPU), and / or other suitable electronic circuits), and / or may include and / or be implemented using computer software, firmware, or any combination thereof to perform various operations described herein.

[0168]

[0162] Processes 800 and 900 are illustrated as logic flow diagrams, whose operations represent sequences of operations that may be implemented in hardware, computer instructions, or a combination thereof. In the context of computer instructions, the operations represent computer-executable instructions stored on one or more computer-readable storage media that, when executed by one or more processors, perform the described operations. Generally, computer-executable instructions include routines, programs, objects, components, data structures, etc. that perform a particular function or implement a particular data type. The order in which the operations are described is not intended to be construed as a limitation, and any number of the described operations can be combined in any order and / or in parallel to implement a process.

[0169]

[0163] Additionally, process 800, process 900, and / or any other process described herein may be executed under the control of one or more computer systems configured with executable instructions and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that collectively execute on one or more processors, by hardware, or a combination thereof. As mentioned above, the code may be stored on a computer-readable or machine-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. The computer-readable or machine-readable storage medium may be non-transitory.

[0170]

[0164] Figure 10 illustrates an exemplary computing device architecture 1000 of an exemplary computing device capable of implementing various techniques described herein. In some examples, the computing device may include a mobile device, a wearable device, an extended reality device (e.g., a virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device), a personal computer, a laptop computer, a video server, a vehicle (or a computing device in a vehicle), or other devices. For example, the computing device architecture 1000 may implement the system of Figure 6A. The components of the computing device architecture 1000 are shown in electrical communication with each other using a connection 1005 such as a bus. The exemplary computing device architecture 1000 includes a processing unit (CPU or processor) 1010 and a computing device connection 1005 that couples various computing device components, including a computing device memory 1015 such as a read only memory (ROM) 1020 and a random access memory (RAM) 1025, to the processor 1010.

[0171]

[0165] The computing device architecture 1000 may include a cache of high-speed memory directly connected to, in close proximity to, or integrated as part of the processor 1010. The computing device architecture 1000 may copy data from the memory 1015 and / or storage device 1030 to the cache 1012 for fast access by the processor 1010. In this manner, the cache may provide performance improvements that avoid delays to the processor 1010 while waiting for data. These and other engines may control or be configured to control the processor 1010 to perform various actions. Other computer device memories 1015 may be available for use as well. The memory 1015 may include multiple different types of memories with different performance characteristics. The processor 1010 may include any general-purpose processor and hardware, or software services such as service 1 1032, service 2 1034, and service 3 1036 stored in the storage device 1030 configured to control the processor 1010, as well as dedicated processors where software instructions are built into the processor design. The processor 1010 may be a self-contained system that includes multiple cores or processors, buses, memory controllers, caches, etc. Multi-core processors may be symmetric or asymmetric.

[0172]

[0166] To enable user interaction with the computing device architecture 1000, the input device 1045 can represent any number of input mechanisms, such as a microphone for voice, a touch-sensitive screen for gesture or graphic input, a keyboard, a mouse, motion input, voice, etc. The output device 1035 can also be one of many output mechanisms known to those skilled in the art, such as a display, projector, television, speaker device or devices. In some cases, a multimodal computing device can enable a user to provide multiple types of input to communicate with the computing device architecture 1000. The communication interface 1040 can generally govern and manage user input and computing device output. There is no constraint to operate on any particular hardware configuration, and therefore the basic functions herein can be easily replaced with improved hardware or firmware configurations as they are developed.

[0173]

[0167] The storage device 1030 is a non-volatile memory and may be a hard disk or other type of computer-readable medium capable of storing data accessible by a computer, such as a magnetic cassette, a flash memory card, a solid-state memory device, a digital versatile disk, a cartridge, a random access memory (RAM) 1025, a read-only memory (ROM) 1020, and hybrids thereof. The storage device 1030 may include services 1032, 1034, 1036 for controlling the processor 1010. Other hardware or software modules or engines are also contemplated. The storage device 1030 may be connected to a computing device connection 1005. In one aspect, a hardware module that performs a particular function may include software components stored in a computer-readable medium connected with the necessary hardware components, such as the processor 1010, the connection 1005, the output device 1035, etc., to perform the function.

[0174] Aspects of the present disclosure are applicable to any suitable electronic device (such as a security system, a smartphone, a tablet, a laptop computer, a vehicle, a drone, or other device) that includes or is coupled to one or more active depth sensing systems. Although described below with respect to a device having or coupled to one light projector, aspects of the present disclosure are applicable to devices having any number of light projectors and are therefore not limited to any particular device.

[0175]

[0169] The term "device" is not limited to one or a specific number of physical objects (such as one smartphone, one controller, one processing system, etc.). A device as used herein may be any electronic device having one or more parts that can implement at least some parts of the present disclosure. The following description and examples use the term "device" to describe various aspects of the present disclosure, but the term "device" is not limited to a specific configuration, type, or number of objects. Additionally, the term "system" is not limited to multiple components or a specific embodiment. For example, a system may be implemented on one or more printed circuit boards or other substrates and may have movable or static components. The following description and examples use the term "system" to describe various aspects of the present disclosure, but the term "system" is not limited to a specific configuration, type, or number of objects.

[0176]

[0170] Specific details are provided in the above description to provide a thorough understanding of the embodiments and examples provided herein. However, it will be understood by those skilled in the art that the embodiments may be practiced without these specific details. For ease of explanation, in some cases, the present technology may be presented as including individual functional blocks, including devices, device components, steps or routines in a method embodied in software, or functional blocks comprising a combination of hardware and software. Additional components other than those shown in the figures and / or described herein may be used. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form so as not to obscure the embodiments in unnecessary detail. In other cases, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as to avoid obscuring the embodiments.

[0177]

[0171] Each embodiment may be described above as a process or method that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. In addition, the order of steps may be rearranged. A process terminates when its operations are completed, but may have additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to the function returning to a calling function or a main function.

[0178]

[0172] The processes and methods according to the examples described above may be implemented using computer-executable instructions stored in or otherwise available from a computer-readable medium. Such instructions may include, for example, instructions and data that cause or otherwise configure a general-purpose computer, a special-purpose computer, or a processing device to perform a particular function or group of functions. Portions of the computer resources used may be accessible via a network. The computer-executable instructions may be, for example, binary or intermediate format instructions such as assembly language, firmware, source code, etc.

[0179]

[0173] The term "computer-readable medium" includes, but is not limited to, portable or non-portable storage devices, optical storage devices, and various other media that can store, store, or convey instruction(s) and / or data. Computer-readable media may include non-transitory media on which data is stored and does not include carrier waves and / or transitory electronic signals propagating wirelessly or over wired connections. Examples of non-transitory media may include, but are not limited to, magnetic disks or magnetic tapes, optical storage media such as flash memory, memories or memory devices, magnetic or optical disks, flash memories, USB devices provided with non-volatile memory, networked storage devices, compact discs (CDs) or digital versatile discs (DVDs), among others, and any suitable combination thereof. Computer-readable media may have code and / or machine-executable instructions stored thereon, which may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, an engine, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0180] In some embodiments, computer-readable storage devices, media, and memories may include cables or wireless signals containing bit streams, etc. However, when mentioned, non-transitory computer-readable storage media specifically excludes media such as energy, carrier signals, electromagnetic waves, and the signals themselves.

[0181]

[0175] A device implementing the processes and methods according to these disclosures may include hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof, and may take any of a variety of form factors. When implemented in software, firmware, middleware, or microcode, the program code or code segments (e.g., computer program product) for performing the necessary tasks may be stored in a computer-readable medium or machine-readable medium. A processor(s) may perform the necessary tasks. Typical examples of form factors include laptops, smartphones, mobile phones, tablet devices or other small-footprint personal computers, personal digital assistants, rack-mounted devices, standalone devices, and the like. The functions described herein may also be embodied in peripheral devices or add-in cards. Such functions may also be implemented on a circuit board among different chips, or on different processes executing in a single device, as further examples.

[0182]

[0176] The instructions, media for conveying such instructions, computing resources for executing such instructions, and other structures for supporting such computing resources are exemplary means for providing functionality described in this disclosure.

[0183]

[0177] In the above description, aspects of the present application are described with reference to specific embodiments thereof, but those skilled in the art will recognize that the present application is not limited thereto. Thus, while exemplary embodiments of the present application are described in detail herein, it should be understood that the inventive concepts may be embodied and employed in various other ways, and that the appended claims are intended to be construed to include such variations, except as limited by the prior art. The various features and aspects of the present application described above may be used individually or jointly. Moreover, the embodiments may be utilized in any number of environments and applications other than those described herein without departing from the broader spirit and scope of the present specification. Thus, the present specification and drawings should be regarded as illustrative and not restrictive. For purposes of illustration, the methods have been described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in an order different from that described.

[0184]

[0178] Those skilled in the art will understand that the symbols or terms less than ("<") and greater than (">") used in this specification may be replaced with the symbols less than or equal to ("≦") and greater than or equal to ("≧"), respectively, without departing from the scope of this description.

[0185]

[0179] When a component is described as being "configured to" perform a particular operation, such configuration may be achieved, for example, by designing electronic circuitry or other hardware to perform the operation, by programming a programmable electronic circuitry (e.g., a microprocessor or other suitable electronic circuitry) to perform the operation, or any combination thereof.

[0186]

[0180] The phrase "coupled to" refers to any component that is physically connected to another component, either directly or indirectly, and / or any component that is in communication with another component, either directly or indirectly (e.g., connected to the other component via a wired or wireless connection and / or other suitable communication interface).

[0187]

[0181] Claim language or other language reciting "at least one of" a set and / or "one or more" of a set indicates that one member of the set or multiple members of the set (in any combination) satisfy the claim. For example, a claim language reciting "at least one of A and B" or "at least one of A or B" means A, B, or A and B. In another example, a claim language reciting "at least one of A, B, and C" or "at least one of A, B, or C" means A, B, C, or A and B, or A and C, or B and C, or A and B and C. The language "at least one of" a set and / or "one or more" of a set does not limit the set to the items listed in the set. For example, claim language reciting "at least one of A and B" or "at least one of A or B" can mean A, B, or A and B, and can additionally include unrecited items in the set of A and B.

[0188]

[0182] The various exemplary logic blocks, modules, engines, circuits, and algorithm steps described with respect to the embodiments disclosed herein may be implemented as electronic hardware, computer software, firmware, or a combination thereof. To clearly illustrate this interchangeability of hardware and software, the various exemplary components, blocks, modules, engines, circuits, and steps are described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as a cause for departure from the scope of this application.

[0189]

[0183] The techniques described herein may also be implemented in electronic hardware, computer software, firmware, or any combination thereof. Such techniques may be implemented in any of a variety of devices, such as a general purpose computer, a wireless communication device handset, or an integrated circuit device having multiple uses, including applications in wireless communication device handsets and other devices. Any features described as modules or components may be implemented together in an integrated logic device, or separately as separate but interoperable logic devices. If implemented in software, the techniques may be realized at least in part by a computer-readable data storage medium comprising program code including instructions that, when executed, perform one or more of the methods described above. The computer-readable data storage medium may form part of a computer program product, which may include packaging materials. The computer-readable medium may include memory or data storage media, such as random access memory (RAM), such as synchronous dynamic random-access memory (SDRAM), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic or optical data storage media, and the like. The techniques may additionally or alternatively be realized at least in part by a computer-readable communications medium, such as a propagated signal or wave, which may carry or communicate program code in the form of instructions or data structures and which may be accessed, read, and / or executed by a computer.

[0190]

[0184] The program code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such a processor may be configured to perform any of the techniques described in this disclosure. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Thus, the term "processor" as used herein may refer to any of the above structures, any combination of the above structures, or any other structure or apparatus suitable for implementing the techniques described herein.

[0191]

[0185] Exemplary aspects of the present disclosure include the following.

[0186] Aspect 1: An apparatus for processing media data, comprising at least one memory and at least one processor coupled to the at least one memory, wherein the at least one processor is configured to obtain a latent representation of a frame of encoded image data and generate a frame of decoded image data based on multiple decoder transformer layers of a decoder sub-network using the latent representation of the frame of encoded image data as an input, wherein at least one of the multiple decoder transformer layers includes one or more transformer blocks configured to generate one or more patches of features and determine self-attention locally within one or more window partitions and shift window partitions applied across the one or more patches, and a patch separation engine configured to reduce a respective size of each patch of the one or more patches.

[0192]

[0187] Aspect 2: The apparatus of aspect 1, wherein to generate a frame of decoded image data, at least one processor is configured to use a first transformer block of a first decoder transformer layer of a plurality of decoder transformer layers to determine self-attention locally within one or more first window partitions applied across the one or more patches, using a second transformer block of the first decoder transformer layer to determine self-attention locally within one or more second window partitions applied across the one or more patches, the second window partitions being shifted to overlap one or more boundaries between adjacent ones of the one or more first window partitions, and using a patch separation engine to segment each patch of the one or more patches into a plurality of non-overlapping separated patches.

[0193]

[0188] Aspect 3: The apparatus of aspect 2, wherein at least one processor is configured to provide a plurality of separation patches to a first transformer block of a second decoder transformer layer among a plurality of decoder transformer layers.

[0194]

[0189] Aspect 4: The apparatus of aspect 3, wherein at least one processor is configured to segment a plurality of separated patches using a patch separation engine of a second decoder transformer layer and provide an output of the patch separation engine to a third decoder transformer layer of the plurality of decoder transformer layers.

[0195]

[0190] Aspect 5: An apparatus described in any of aspects 2 to 4, wherein each separation patch of the multiple separation patches has a uniform patch size and the patch separation engine applies a patch size reduction factor of 2.

[0196]

[0191] Aspect 6: An apparatus described in any of aspects 2 to 5, wherein at least one processor is configured to reduce a feature dimension of the multiple separated patches in order to segment each patch of the one or more patches into multiple separated patches.

[0197]

[0192] Aspect 7: An apparatus described in any of aspects 1 to 6, wherein a plurality of decoder transformer layers are configured to receive as input a latent representation of a frame of encoded image data, apply a nonlinear transformation, and generate a frame of decoded image data.

[0198]

[0193] Aspect 8: The apparatus of aspect 7, wherein the nonlinear transform is a synthesis transform and the frame of decoded image data is a reconstruction of an input image associated with the frame of encoded image data.

[0199]

[0194] Aspect 9: An apparatus described in any of aspects 1 to 8, wherein at least one processor is configured to train one or more of the multiple decoder transformer layers using a loss function based at least in part on rate-distortion.

[0200]

[0195] Aspect 10: The apparatus of aspect 9, wherein the loss function includes a Lagrangian multiplier for rate distortion.

[0201]

[0196] Aspect 11: An apparatus as described in any of aspects 1 to 10, wherein at least a portion of one or more transformer blocks included in at least one decoder transformer layer have the same architecture.

[0202]

[0197] Aspect 12: The apparatus of any one of aspects 1 to 11, wherein each of the one or more transformer blocks included in at least one decoder transformer layer has the same architecture.

[0203]

[0198] Aspect 13: An apparatus described in any of aspects 1 to 12, wherein the frame of encoded image data includes an encoded still image.

[0204]

[0199] Aspect 14: An apparatus described in any of aspects 1 to 13, wherein the frame of encoded image data includes an encoded video frame.

[0205]

[0200] Aspect 15: An apparatus described in any of aspects 1 to 14, wherein at least one processor is configured to train multiple decoder transformer layers with at least a first training data set and a second training data set, and the data of the second training data set has a reverse temporal order compared to the data of the first training data set.

[0206]

[0201] Aspect 16: An apparatus described in any of aspects 1 to 15, wherein the multiple decoder transformer layers include a series of consecutive decoder transformer layers.

[0207]

[0202] Aspect 17: An apparatus for processing media data, comprising at least one memory and at least one processor coupled to the at least one memory, wherein the at least one processor is configured to segment a frame into a plurality of patches and use the plurality of patches as inputs to generate a frame of encoded image data based on a plurality of encoder transformer layers of an encoder sub-network.

[0208]

[0203] Aspect 18: The apparatus described in aspect 17, wherein to generate a frame of encoded image data, at least one processor is configured to use a first transformer block of a first encoder transformer layer of a plurality of encoder transformer layers to determine self-attention locally within one or more window partitions, use a second transformer block of the first encoder transformer layer to determine self-attention locally within one or more shift window partitions overlapping the one or more window partitions, use one or more of the first transformer block and the second transformer block to determine one or more patches of features for applying a nonlinear transformation to the segmented frame, and use a patch merging engine to increase patch size between the first encoder transformer layer and the second encoder transformer layer.

[0209]

[0204] Aspect 19: The apparatus described in aspect 18, wherein the patch merging engine is configured to combine multiple adjacent patches from a first encoder transformer layer into a merged patch provided to a second encoder transformer layer.

[0210]

[0205] Aspect 20: The apparatus of any of aspects 18 or 19, wherein an output of the second transformer block of the first encoder transformer layer is coupled to an input of the second encoder transformer layer.

[0211]

[0206] Aspect 21: An apparatus described in any of aspects 18 to 20, wherein at least one processor is configured to use multiple patches as input to generate a hierarchical feature map for the segmented frame using multiple encoder transformer layers of an encoder sub-network, and to generate a frame of encoded image data from the hierarchical feature map.

[0212]

[0207] Aspect 22: An apparatus described in any of aspects 18 to 21, wherein each patch of the multiple patches is of uniform size and includes one or more pixels of the segmented frame.

[0213]

[0208] Aspect 23: An apparatus described in any of aspects 18 to 22, wherein the patch merging engine is configured to increase the patch size by concatenating features obtained from one or more subsets of adjacent patches, and each subset of adjacent patches is merged into a merged patch output by the patch merging engine.

[0214]

[0209] Aspect 24: The apparatus of any of aspects 18 to 23, wherein the first transformer block and the second transformer block have the same architecture.

[0215]

[0210] Aspect 25: An apparatus described in any of aspects 18 to 24, wherein at least one processor is configured to provide a plurality of patches to a linear embedding layer of the encoder sub-network before the first encoder transformer layer.

[0216]

[0211] Aspect 26: An apparatus described in any of aspects 17 to 25, wherein the frame of encoded image data is a latent representation of the image data.

[0217]

[0212] Aspect 27: The apparatus described in aspect 26, wherein the latent representation is a hierarchical feature map generated by multiple encoder transformer layers of the encoder sub-network.

[0218]

[0213] Aspect 28: An apparatus described in any of aspects 17 to 27, wherein at least one processor is configured to train one or more of the multiple encoder transformer layers using a loss function based on rate-distortion loss.

[0219]

[0214] Aspect 29: The apparatus described in aspect 28, wherein the loss function includes a Lagrangian multiplier for rate distortion.

[0220]

[0215] Aspect 30: An apparatus described in any of aspects 17 to 29, wherein a plurality of patches are segmented from an input including a still image frame or a video frame.

[0221]

[0216] Aspect 31: An apparatus described in any of aspects 17 to 30, wherein at least one processor is configured to entropy code the encoded image data using a factorization prior.

[0222]

[0217] Aspect 32: A method for processing media data, the method comprising: obtaining a latent representation of a frame of encoded image data; and generating a frame of decoded image data by multiple decoder transformer layers of a decoder sub-network using the latent representation of the frame of encoded image data as input, wherein at least one decoder transformer layer of the multiple decoder transformer layers comprises one or more transformer blocks for generating one or more patches of features and determining self-attention locally within one or more window partitions and shift window partitions applied across the one or more patches; and a patch separation engine for reducing a respective size of each patch of the one or more patches.

[0223]

[0218] Aspect 33: A method as described in aspect 32, wherein generating a frame of decoded image data by a plurality of decoder transformer layers includes determining self-attention locally within one or more first window partitions applied across the one or more patches by a first transformer block of a first decoder transformer layer of the plurality of decoder transformer layers, determining self-attention locally within one or more second window partitions applied across the one or more patches by a second transformer block of the first decoder transformer layer, the one or more second window partitions being shifted to overlap one or more boundaries between adjacent ones of the one or more first window partitions, and segmenting each of the one or more patches into a plurality of non-overlapping separated patches by a patch separation engine.

[0224]

[0219] Aspect 34: The method of aspect 33, further comprising providing a plurality of separation patches to a first transformer block of a second decoder transformer layer of the plurality of decoder transformer layers.

[0225]

[0220] Aspect 35: The method described in aspect 34, further comprising segmenting the multiple separated patches by a patch separation engine of a second decoder transformer layer, and providing an output of the patch separation engine to a third decoder transformer layer of the multiple decoder transformer layers.

[0226]

[0221] Aspect 36: A method described in any of aspects 33 to 35, wherein each separation patch of the multiple separation patches has a uniform patch size and the patch separation engine applies a patch size reduction factor of 2.

[0227]

[0222] Aspect 37: A method described in any of aspects 33 to 36, wherein segmenting each patch of the one or more patches into a plurality of separate patches further comprises reducing a feature dimension of the plurality of separate patches.

[0228]

[0223] Aspect 38: A method described in any of aspects 32 to 37, further comprising receiving as input a latent representation of a frame of encoded image data by multiple decoder transformer layers, applying a nonlinear transformation, and generating a frame of decoded image data.

[0229]

[0224] Aspect 39: The method of aspect 38, wherein the nonlinear transform is a synthesis transform and the frame of decoded image data is a reconstruction of an input image associated with the frame of encoded image data.

[0230]

[0225] Aspect 40: A method as described in any of aspects 32 to 39, further comprising training one or more decoder transformer layers of the plurality of decoder transformer layers using a loss function based at least in part on rate-distortion.

[0231]

[0226] Aspect 41: The method described in aspect 40, wherein the loss function includes a Lagrangian multiplier for rate distortion.

[0232]

[0227] Aspect 42: The method of any of aspects 32 to 41, wherein at least a portion of one or more transformer blocks included in at least one decoder transformer layer have the same architecture.

[0233]

[0228] Aspect 43: The method of any of aspects 32 to 42, wherein each of the one or more transformer blocks included in at least one decoder transformer layer has the same architecture.

[0234]

[0229] Aspect 44: A method according to any one of aspects 32 to 43, wherein the frame of encoded image data includes an encoded still image.

[0235]

[0230] Aspect 45: A method according to any one of aspects 32 to 44, wherein the frame of encoded image data comprises an encoded video frame.

[0236]

[0231] Aspect 46: A method described in any of aspects 32 to 45, further comprising training a plurality of decoder transformer layers with at least a first training data set and a second training data set, wherein the data of the second training data set has a reversed temporal order compared to the data of the first training data set.

[0237]

[0232] Aspect 47: The method of any of aspects 32 to 46, wherein the multiple decoder transformer layers include a series of consecutive decoder transformer layers.

[0238]

[0233] Aspect 48: A method for processing media data, comprising segmenting a frame into a plurality of patches, and generating a frame of encoded image data by a plurality of encoder transformer layers of an encoder sub-network using the plurality of patches as input.

[0239]

[0234] Aspect 49: The method of aspect 48, wherein generating a frame of encoded image data includes determining self-attention locally within one or more window partitions by a first transformer block of a first encoder transformer layer of a plurality of encoder transformer layers, determining self-attention locally within one or more shift window partitions overlapping the one or more window partitions by a second transformer block of the first encoder transformer layer, determining one or more patches of features for applying a nonlinear transformation to the segmented frame by one or more of the first transformer block and the second transformer block, and increasing a patch size between the first encoder transformer layer and the second encoder transformer layer by a patch merging engine.

[0240]

[0235] Aspect 50: A non-transitory computer-readable storage medium storing instructions that, when executed by one or more processors, cause the one or more processors to perform any of the operations of aspects 1 to 16 and aspects 32 to 47.

[0241]

[0236] Aspect 51: An apparatus comprising means for performing any of the operations of aspects 1 to 16 and aspects 32 to 47.

[0242]

[0237] Aspect 52: A method of performing any of the operations of aspects 17 to 31.

[0243]

[0238] Aspect 53: A non-transitory computer-readable storage medium storing instructions that, when executed by one or more processors, cause the one or more processors to perform any of the operations of aspects 17 to 31.

[0244]

[0239] Example 54: An apparatus comprising means for performing any of the operations of examples 17 to 31.

Claims

1. 1. An apparatus for processing media data, comprising: at least one memory; at least one processor coupled to the at least one memory, the at least one processor: Obtain a latent representation of a frame of encoded image data; and configured to generate a frame of decoded image data based on a plurality of decoder transformer layers of a decoder sub-network using the latent representation of the frame of encoded image data as an input, wherein at least one decoder transformer layer of the plurality of decoder transformer layers: one or more transformer blocks configured to generate one or more patches of features and determine self-attention locally within one or more windowing and shifting windowing applied across the one or more patches; a patch separation engine configured to reduce a respective size of each patch of the one or more patches; To generate the frames of decoded image data, the at least one processor: determining self-attention locally within one or more first windowing segments applied across the one or more patches using a first transformer block of a first decoder transformer layer of the plurality of decoder transformer layers; using a second transformer block of the first decoder transformer layer to determine self-attention locally within one or more second windowing segments applied across the one or more patches, the second windowing segments being shifted to overlap one or more boundaries between adjacent ones of the one or more first windowing segments; configured to segment each patch of the one or more patches into a plurality of non-overlapping separated patches using the patch separation engine; the plurality of decoder transformer layers are configured to receive as input the latent representation of the frame of encoded image data and apply a nonlinear transform to generate the frame of decoded image data, the nonlinear transform being a synthesis transform, and the frame of decoded image data being a reconstruction of an input image associated with the frame of encoded image data.

2. the at least one processor is configured to provide the plurality of separation patches to a first transformer block of a second decoder transformer layer of the plurality of decoder transformer layers, and optionally the at least one processor is configured to: segmenting the plurality of separated patches using a patch separation engine of the second decoder transformer layer; The apparatus of claim 1 , configured to provide an output of the patch separation engine to a third decoder transform layer of the plurality of decoder transform layers.

3. The apparatus of claim 1 , wherein each separation patch of the plurality of separation patches has a uniform patch size, and the patch separation engine applies a patch size reduction factor of two.

4. 2. The apparatus of claim 1, wherein the at least one processor is configured to reduce a feature dimension of the plurality of separated patches to segment each patch of the one or more patches into the plurality of separated patches.

5. 2. The apparatus of claim 1 , wherein the at least one processor is configured to train one or more decoder transformer layers of the plurality of decoder transformer layers using a loss function based at least in part on rate-distortion, and optionally the loss function includes a Lagrangian multiplier for rate-distortion.

6. 2. The apparatus of claim 1 , wherein at least a portion of the one or more transformer blocks included in the at least one decoder transformer layer have the same architecture and / or each of the one or more transformer blocks included in the at least one decoder transformer layer have the same architecture.

7. The apparatus of claim 1 , wherein the frames of encoded image data comprise encoded still images or encoded video frames.

8. 2. The apparatus of claim 1, wherein the at least one processor is configured to train the plurality of decoder transformer layers with at least a first training data set and a second training data set, wherein data in the second training data set has a reverse temporal order compared to data in the first training data set.

9. The apparatus of claim 1 , wherein the plurality of decoder transformer layers comprises a series of consecutive decoder transformer layers.

10. 1. An apparatus for processing media data, comprising: at least one memory; at least one processor coupled to the at least one memory, the at least one processor: Segmenting the frame into a plurality of patches; generating a frame of encoded image data based on a plurality of encoder transformer layers of an encoder sub-network using the plurality of patches as input; and To generate the frames of encoded image data, the at least one processor: determining self-attention locally within one or more windowing partitions applied across the plurality of patches using a first transformer block of a first encoder transformer layer of the plurality of encoder transformer layers; determining self-attention locally within one or more shifted window segments that overlap the one or more window segments using a second transformer block of the first encoder transformer layer; determining one or more patches of features for applying a nonlinear transformation to the segmented frame using one or more of the first transformer block and the second transformer block, wherein the nonlinear transformation is a synthesis transform; increasing a patch size between the first encoder transformer layer and the second encoder transformer layer using a patch merging engine; and The frame of encoded image data is a latent representation of image data.

11. the at least one processor: generating a hierarchical feature map for the segmented frame using the plurality of patches as inputs and the plurality of encoder transformer layers of the encoder sub-network; The apparatus of claim 10 , configured to generate the frames of encoded image data from the hierarchical feature maps.

12. The apparatus of claim 10 , wherein each patch of the plurality of patches is of uniform size and comprises one or more pixels of the segmented frame.

13. 11. The apparatus of claim 10, wherein the patch merging engine is configured to increase the patch size by concatenating features obtained from one or more subsets of adjacent patches, each subset of adjacent patches being merged into a merged patch output by the patch merging engine.

14. 11. The apparatus of claim 10, wherein the at least one processor is configured to provide the plurality of patches to a linear embedding layer of the encoder sub-network before the first encoder transformer layer.

15. The apparatus of claim 10 , wherein the latent representation is a hierarchical feature map produced by the multiple encoder transformer layers of the encoder sub-network.

16. The apparatus of claim 10 , wherein the at least one processor is configured to entropy code the encoded image data using a factorization prior.

17. 1. A method for processing media data, said method comprising: obtaining a latent representation of a frame of encoded image data; generating a frame of decoded image data by a plurality of decoder transformer layers of a decoder sub-network using the latent representation of the frame of encoded image data as an input, wherein at least one decoder transformer layer of the plurality of decoder transformer layers: one or more transformer blocks for generating one or more patches of features and determining self-attention locally within one or more windowing and shifting windowing applied across the one or more patches; a patch separation engine for reducing a respective size of each patch of the one or more patches; generating the frames of decoded image data by the plurality of decoder transformer layers; determining self-attention locally within one or more first windowing partitions applied across the one or more patches by a first transformer block of a first decoder transformer layer of the plurality of decoder transformer layers; determining self-attention locally within one or more second windowing segments applied across the one or more patches by a second transformer block of the first decoder transformer layer, the second windowing segments being shifted to overlap one or more boundaries between adjacent ones of the one or more first windowing segments; segmenting each patch of the one or more patches into a plurality of non-overlapping separate patches with the patch separation engine; Including, the plurality of decoder transformer layers are configured to receive as input the latent representation of the frame of encoded image data and apply a nonlinear transform to generate the frame of decoded image data, the nonlinear transform being a synthesis transform, and the frame of decoded image data being a reconstruction of an input image associated with the frame of encoded image data.

18. 1. A method for processing media data, comprising: Segmenting the frame into a plurality of patches; generating frames of encoded image data by a plurality of encoder transformer layers of an encoder sub-network using the plurality of patches as inputs; Including, generating the frames of encoded image data, determining self-attention locally within one or more windowing partitions applied across the plurality of patches by a first transformer block of a first encoder transformer layer of the plurality of encoder transformer layers; determining, by a second transformer block of the first encoder transformer layer, local self-attention within one or more shifted window segments that overlap the one or more window segments; determining, by one or more of the first transformer block and the second transformer block, one or more patches of features for applying a nonlinear transformation to the segmented frame, wherein the nonlinear transformation is a synthesis transformation; increasing a patch size between the first encoder transformer layer and the second encoder transformer layer by a patch merging engine; Including, A method wherein the frames of encoded image data are a latent representation of image data.

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