Suppression of laser annealing patterns

Abstract

A location of grid lines within an image of a laser annealed semiconductor wafer is determined. The area covered by the grid lines is filled with a new grayscale value. The new grayscale value may be based on a second grayscale value of a neighboring area around the area, the neighboring area being outside the area covered by the grid lines.

Description

[Technical field]

[0001] The present disclosure relates to processing semiconductor wafer images. [Background technology]

[0002] Advances in the semiconductor manufacturing industry are driving demand for yield management, particularly metrology and inspection systems. As critical dimensions continue to shrink, the industry must reduce the time to achieve high yield, high value production. Reducing the overall time between detecting a yield issue and correcting it maximizes the return on investment for semiconductor producers.

[0003] The fabrication of semiconductor devices, such as logic and memory devices, typically involves processing a semiconductor wafer through a number of manufacturing steps to form various functions and multiple stages of the semiconductor device. For example, lithography is one of the semiconductor manufacturing steps that involves transferring a pattern from a reticle to a resist on the semiconductor wafer. Further examples of semiconductor manufacturing steps include, but are not limited to, CMP (chemical mechanical polishing), etching, deposition, and ion implantation. The array of semiconductor devices formed on a single semiconductor wafer can be separated into individual semiconductor devices.

[0004] Inspection procedures are performed at various stages during semiconductor manufacturing to detect defects on the wafers and facilitate high yields and therefore high profits in the manufacturing process. Inspection has always been an important part in the manufacture of semiconductor devices such as ICs (integrated circuits). However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of semiconductor devices of sufficient quality, since even smaller defects can cause the devices to fail. For example, as the dimensions of semiconductor devices decrease, the detection of smaller sized defects becomes necessary, since even very small defects can cause undesirable aberrations in the semiconductor device.

[0005] However, shrinking design rules force semiconductor manufacturing processes to operate closer to the limits of each process's operating capacity. Furthermore, shrinking design rules result in smaller defects affecting the electrical parameters of the device, which in turn requires more sensitive inspection. As design rules shrink, the number of potential yield-relevant defects detected by inspection increases dramatically, as does the number of false defects detected by inspection. This results in more defects being detected on the wafer, and modifying the process to eliminate all defects is difficult and expensive. Determining the defects that actually affect the electrical parameters and yield of the device allows process control methods to focus on those defects and ignore many others. Furthermore, with smaller design rules, process induced defects can sometimes be regular; that is, process induced defects tend to occur in a predefined pattern of features that are often repeated within the feature. Eliminating spatially regular, electrically related defects also has a significant impact on yield.

[0006] Laser annealing creates a distinct grid pattern on the backside of the wafer, which appears as a discoloration in the areas irradiated and heated by the laser. The grid pattern can be lighter or darker than the rest of the wafer. Because backside-illuminated tools inspect exposed areas, such grid patterns can be erroneously labeled and classified as defects. To avoid such errors, the inspection algorithms can be reduced in accuracy or the grid pattern can be omitted. Such a technique eliminates the problem of false defects.

[0007] Detuning the defect detection algorithm reduces its sensitivity, which may allow damaged chips to slip through the quality control process. Omitting the grating lines will miss defects on or around the laser annealed grating lines. Figure 1 shows the backside of the wafer after the laser annealing process. Regular grating lines are visible. Defects may occur on or around these grating lines. Such defects may even overlap the grating pattern. The brightness of some of these defects may be the same as the grating lines, in which case they are difficult to detect. Omitting the grating lines will cause subsequent defect detection algorithms to miss defects on or near the grating lines. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] US Patent Application Publication No. 2011 / 0280470 Summary of the Invention [Problem to be solved by the invention]

[0009] Thus, improved systems and techniques are needed. [Means for solving the problem]

[0010] In a first embodiment, a system is defined that includes a light source generating light, a stage configured to hold a laser annealed semiconductor wafer in a path of the light, a detector configured to receive light reflected from the laser annealed semiconductor wafer, and a processor in electronic communication with the detector. The processor generates an image of the laser annealed semiconductor wafer using data from the detector, determines locations of grid lines in the image, and fills an area covered by the grid lines with a new grayscale value based on a second grayscale value of a neighborhood near the area, the neighborhood being outside the area covered by the grid lines.

[0011] The processor may be further configured to compare a first grayscale value of the region covered by the grid lines with second grayscale values ​​of a neighborhood around the region and divide the first grayscale value of the region by a correction factor to obtain a new grayscale value. The correction factor is an average graylevel of the region divided by an average graylevel of the neighborhood. The second grayscale value may be obtained from a location that is more than a width of the grid lines away from the first grayscale value. The steps of comparing, dividing and filling may be repeated for all pixels within the grid lines of the image.

[0012] The light source and detector can be configured so that the image can be a bright field image or a dark field image.

[0013] The processor may be further configured to perform defect inspection on the image after the regions have been filled with the new greyscale values.

[0014] The determining step may utilize Sobel edge detection.

[0015] The filling step may include histogram remapping.

[0016] In a second embodiment, a method is defined, using a processor to determine the location of grid lines in an image of a laser annealed semiconductor wafer, and using a processor to fill an area covered by the grid lines with a new grayscale value based on a second grayscale value of a neighborhood near the area, the neighborhood being outside the area covered by the grid lines.

[0017] The method may further include the steps of: using a processor to compare a first grayscale value of the area covered by the grid lines with a second grayscale value of a neighborhood around the area; and using a processor to divide the first grayscale value of the area by a correction factor to obtain a new grayscale value, the correction factor being the average graylevel of the area divided by the average graylevel of the neighborhood. The second grayscale value may be obtained from a location that is more than the width of the grid lines away from the first grayscale value. The steps of comparing, dividing and filling may be repeated for all pixels within the grid lines of the image.

[0018] The image may be a bright field image or a dark field image.

[0019] The method may further include performing a defect inspection on the image after the filling step.

[0020] The determining step may utilize Sobel edge detection.

[0021] The filling step may include histogram remapping.

[0022] A non-transitory computer readable medium storing a program configured to instruct a processor to perform the method of the second embodiment. [Brief description of the drawings]

[0023] For a more complete understanding of the nature and objects of the present disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings. [Figure 1] FIG. 13 is an image of the backside of the wafer showing the grating pattern due to laser annealing. [Diagram 2] FIG. 2 is the image of FIG. 1 where the grid pattern has been suppressed using an embodiment of the present disclosure. [Diagram 3] FIG. 2 illustrates a flow chart of an embodiment according to the present disclosure. [Figure 4]FIG. 4 shows an example of a defect map image before using the method shown in FIG. 3. [Diagram 5] FIG. 4 is a diagram showing an example of a defect situation image after using the method shown in FIG. 3. [Figure 6] FIG. 1 illustrates an embodiment of a system according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Although the subject matter of the present disclosure will be described with respect to certain embodiments, other embodiments are within the scope of the present disclosure, including embodiments that do not fulfil all of the advantages and features set forth herein. Various structural, logical, process and electronic changes may be made without departing from the scope of the present disclosure. Accordingly, the scope of the present disclosure is defined solely by the claims that follow.

[0025] The presently disclosed embodiments correct and suppress brightness changes in discolored areas of laser annealed semiconductor wafers. Subsequent defect detection algorithms will not detect false defects due to the grid pattern, meaning the defect detection algorithms can maintain maximum sensitivity. For example, Figure 2 shows the image of Figure 1 after the grid pattern has been suppressed using the presently disclosed embodiments. In Figure 2, the grid pattern is no longer visible.

[0026] One embodiment of method 100 is shown in Figure 3 with corresponding diagrams to the right of each step. Some or all of the steps shown in Figure 3 can be performed using a processor. Although shown for a single image, method 100 can be performed for a semiconductor wafer or multiple images across multiple semiconductor wafers.

[0027] In step 101, the location of grid lines 105 in an image of a laser annealed semiconductor wafer is determined. In the example image, the grid lines 105 are shaded darker (e.g., gray) than non-grid areas, but may also be shaded lighter than non-grid areas.

[0028] The image can be a bright field or a dark field image. Depending on whether the image is a bright field or a dark field image, the grid lines can be brighter or darker.

[0029] The position of the grating lines will vary from wafer to wafer. Furthermore, the grating lines may not be aligned with the orientation of the wafer, i.e., the grating lines may appear at an angle. By measuring and correcting for such relative angles, the position of the grating can be determined more accurately. For example, the exact position of the grating lines may be determined by utilizing the regular distance between the grating lines.

[0030] Other techniques can be used to determine the location of the grid lines, for example using Sobel edge detection or a Canny filter to determine the location of the grid lines.

[0031] In another example, a Fourier transform may be used to determine the location of the grid lines in frequency space. Fourier analysis analyzes an image in terms of frequency. Regularly spaced patterns show up as strong peaks in the frequency spectrum.

[0032] In other examples, the location of grid lines can be determined by utilizing the regular repetition of the grid pattern, the assumed location of the grid lines relative to the starting point in the pattern, etc. Techniques other than those listed here may also be used to determine the location of grid lines.

[0033] After determining the location of the grid lines in step 101, the area covered by the grid lines 105 is filled with a new grayscale based on the second grayscale values ​​of a nearby area 107 around the area 106. The nearby area 107 is the area outside the area 106 covered by the grid lines 105.

[0034] In step 102, a first grayscale value of an area 106 covered by grid lines 105 is compared to a second grayscale value of a neighboring area 107 around the area 106. The neighboring area may be only on one side of the grid lines 105, or may be an average value on both sides of the grid lines 105. The second grayscale value is preferably taken from a position that is a distance away from the grid lines that is greater than the width of a grid line. This prevents the second grayscale value from being too close to the first grayscale value. For example, the second grayscale value may be within 64 pixels of the first grayscale value.

[0035] By selecting the neighborhood 107 as close as practical to the grid lines 105, a more accurate measurement of the correction value can be obtained than if the neighborhood 107 were selected farther away. The exact distance will vary from implementation to implementation and can be selected by the user to optimize the results.

[0036] The amount of correction is determined in step 103. For example, the first grayscale value in region 106 is divided by a correction factor. By dividing the first grayscale value, a new grayscale value can be determined. The correction factor is the average gray level in region 106 divided by the average gray level in the neighborhood 107.

[0037] The average gray level may be determined as the average of the gray levels within the box or horizontal or vertical lines. The area depends on whether the correction is within a horizontal or vertical line or another area. The dimensions of the box or line can be selected by the user to optimize the results.

[0038] In other embodiments, the amount of correction is determined using additive terms: the amount of correction for the gray levels may be added to or subtracted from the original values ​​instead of using a correction factor.

[0039] In step 104, new grayscale values ​​fill the regions 106, i.e., the pixels on the grid lines are corrected to look the same as their non-grid neighbors. Figure 2 shows an image of the same wafer of Figure 1 after such gray level correction. The grid lines are now nearly invisible to the naked eye. The signal-to-noise ratio is increased, and defects on or around the grid lines become visible.

[0040] Region 106 may be filled on a pixel-by-pixel or region-by-region basis. Region 106 can be filled within the boundaries determined in step 101. That is, it is applicable for region 106 to include multiple pixels, a single pixel, or a single line.

[0041] Because the grayscale varies significantly across a wafer due to processing performed on the backside of the wafer, the grayscale variations can be measured locally and corrected. Measurement of the grayscale on and off the grid lines may be achieved using several techniques, measuring the average gray level in one dimension (linear projection) or two dimensions.

[0042] For example, histogram remapping may be performed to fill region 106. The gray level distributions of region 106 and the neighboring region 107 may be compared and the endpoints of the histograms may be matched to each other to determine a correction to the distribution. Other methods of color correction may also be applied.

[0043] The comparison step 102, correction determination step 103, and filling step 104 may be repeated for every pixel in a grid line of the image, which may be performed pixel by pixel or using multiple local areas within a grid line.

[0044] The image may be inspected for defects after method 100 has been performed on a portion of the pixels within the grid lines of the image, or after method 100 has been performed on all pixels.

[0045] The method 100 performs a one-dimensional measurement of the average grayscale value along a column or row of pixels depending on their proximity to a vertical or horizontal grid line. Areas where grid lines meet or intersect may be corrected by measuring the average brightness value in two dimensions. For example, a box may be used for the region 106. The size of this box may be the size of the area where the vertical and horizontal lines intersect. The box used at this intersection may be sized so that it does not overlap other portions of the grid lines 105 outside the intersection.

[0046] FIGS. 4 and 5 show example defect maps. The defect map of FIG. 4 contains both defects and grid lines. This can affect inspection or defect analysis. The grid lines may hide defects or result in false positives. FIG. 5 shows a defect map of the same area after applying method 100. The grid lines have been suppressed and real defects can be identified and classified. The defect analysis of FIG. 5 has fewer errors than the defect analysis of FIG. 4.

[0047] One example of system 200 is shown in Figure 6. System 200 includes an optical subsystem 201. In general, optical subsystem 201 is configured to generate an optical output related to the inspected object 202 by illuminating (or scanning) light onto (or detecting) the inspected object 202 and detecting light from (or detecting) the inspected object 202. In some embodiments, inspected object 202 includes a wafer. The wafer may include any wafer known in the art, such as a laser annealed wafer, or other inspected object.

[0048] In the embodiment of the system 200 shown in FIG. 6, the optical system subsystem 201 includes an illumination subsystem configured to illuminate the inspected object 202 with light. The illumination subsystem includes at least one light source. For example, as shown in FIG. 6, the illumination subsystem includes a light source 203. In some embodiments, the illumination subsystem is configured to illuminate the inspected object 202 with light at one or more angles of incidence, including one or more oblique angles and one or more normal angles. For example, as shown in FIG. 6, light from the light source 203 passes through an optical element 204, passes through a lens 205, and is illuminated at an oblique angle of incidence on the inspected object 202. The oblique angle of incidence may be any suitable angle of incidence and may vary depending on, for example, the characteristics of the inspected object 202.

[0049] The optical subsystem 201 may optionally irradiate the inspected object 202 with different angles of incidence. For example, the optical subsystem 201 may change one or more characteristics of one or more elements of the illumination subsystem to irradiate the inspected object 202 with light at angles of incidence different from the angles of incidence shown in Figure 6. As such an example, the optical subsystem 201 may be configured to move the light source 203, the optical element 204, and the lens 205 to irradiate the inspected object 202 with light at different oblique angles of incidence or normal (or near normal) angles of incidence.

[0050] For example, the optical subsystem 201 may be configured to simultaneously illuminate the inspected object 202 with light at multiple angles of incidence. For example, the illumination subsystem may include multiple illumination paths, one of which includes a light source 203, optical elements 204, and a lens 205 as shown in FIG. 6, and another illumination path (not shown) may include similar components, which may be configured differently or the same, or may include at least one light source and one or more other components as further described herein. When such lights are simultaneously illuminated on the inspected object with other lights, it is also possible to vary one or more characteristics (e.g., wavelength, polarization, etc.) of each light illuminated on the inspected object 202 at different angles of incidence so that the light resulting from illumination on the inspected object 202 at different angles of incidence can be distinguished by the detector(s).

[0051] In another example, the illumination subsystem may include only one light source (e.g., light source 203 in FIG. 6 ), and the light from the light source may be split into different optical paths (e.g., based on wavelength, polarization, etc.) by one or more optical elements (not shown) of the illumination subsystem. The light from each different optical path may then be irradiated onto the inspected object 202. The illumination paths may be configured to irradiate the inspected object 202 with light simultaneously or at different times (e.g., when used to sequentially irradiate the inspected object from different illumination paths). In another example, the same illumination path may be configured to irradiate the inspected object 202 with light having different characteristics at different times. For example, in some cases, the optical element 204 may be configured as a spectral filter, and the spectral filter may have different functions (e.g., by changing the spectral filter) so that the inspected object 202 may be irradiated with light of different wavelengths at different times. The illumination subsystem may have other suitable configurations known in the art for illuminating the inspected object 202 with light having different or the same characteristics, sequentially or simultaneously, and at different or the same angles of incidence.

[0052] In some embodiments, the light source 203 may include a broadband plasma (BBP) light source, which allows the light generated by the light source 203 and irradiated onto the inspected object 202 to include broadband light. However, the light source may include other suitable light sources, such as, for example, a laser. The laser may include any suitable laser known in the art and may be configured to generate light at any suitable wavelength or wavelengths known in the art. Additionally, the laser may be configured to generate monochromatic or near monochromatic light, in which case the laser may be a narrowband laser. The light source 203 may include a polychromatic light source that generates light at multiple discrete wavelengths or discrete bands.

[0053] The lens 205 can focus the light from the optical element 204 onto the inspected object 202. Although the lens 205 is shown in FIG. 6 as a single refractive optical element, it is understood that in practice the lens 205 can include multiple refractive optical elements and / or multiple reflective optical elements that combine to focus the light from the optical element onto the inspected object. The illumination subsystem shown in FIG. 6 and described herein can include other suitable optical elements (not shown). Such optical elements can include, but are not limited to, one or more of a polarizing element, a spectral filter, a spatial filter, a reflective optical element, an apodizer, a beam splitter (e.g., beam splitter 213), an aperture, and others, including any such suitable optical element known in the art. Additionally, the optical subsystem 201 can be configured to allow one or more elements of the illumination subsystem to be altered depending on the type of illumination used to generate the optical output.

[0054] The optical subsystem 201 may also include a scanning subsystem configured to scan the light onto the inspected object 202. For example, the optical subsystem 201 may include a stage 206 on which the inspected object 202 is positioned during optical output generation. The scanning subsystem may include any suitable mechanical and / or robotic parts (including the stage 206) configured to move the inspected object 202 so that the light is scanned onto the inspected object 202. Additionally or alternatively, the optical subsystem 201 may be configured such that one or more optical elements of the optical subsystem 201 perform the scanning of the light onto the inspected object 202. The light may be scanned onto the inspected object 202 in any suitable manner, such as a zigzag path or a spiral path.

[0055] The optical subsystem 201 includes one or more detection paths. At least one detection path includes a detector configured to detect light from the inspected object 202 by illuminating the inspected object 202 by the subsystem and generate an output according to the detected light. For example, the optical subsystem 201 shown in FIG. 6 includes two detection paths, one configured by a collector 207, an element 208, and a detector 209, and the other configured by a collector 210, an element 211, and a detector 212. As shown in FIG. 6, the two detection paths are configured to collect and detect light by different collection angles. In some cases, both detection paths are configured to detect scattered light. Both detection paths are configured to detect light scattered at different angles from the inspected object 202. However, one or more detection paths may be configured to detect other types of light (e.g., reflected light) from the inspected object 202.

[0056] As further shown in FIG. 6, both detection paths lie in the plane of the paper, and the illumination subsystem also lies in the plane of the paper. That is, in this embodiment, both detection paths lie in the plane of incidence (e.g., at its center). However, one or more detection paths may be located outside the plane of incidence. For example, a detection path formed by collector 210, element 211, and detector 212 may collect and detect scattered light that is out of the plane of incidence. Such detection paths are commonly referred to as "side" paths. Such side paths may be located in the center of a plane that is substantially perpendicular to the plane of incidence.

[0057] Although FIG. 6 shows the optical subsystem 201 including two detection paths, the optical subsystem 201 may include other numbers of detection paths (e.g., only one detection path or more than one detection path). For example, the detector including the collector 210, the element 211, and the detector 212 may have one side path as described above, and the optical subsystem 201 may further include a detection path (not shown) as another side path, located on the opposite side of the incidence plane. Thus, the optical subsystem 201 may include a detection path including the collector 207, the element 208, and the detector 209, which may be located in the center of the incidence plane to collect and detect light at a scattering angle that is normal or nearly normal to the surface of the inspected object 202. This detection path is commonly referred to as the "upper" path, and the optical subsystem 201 may further include two or more of the above-mentioned side paths. That is, the optical subsystem 201 may have at least three paths (one top path and two side paths), each of which includes a collector, each of which collects light at a different scattering angle than the other collectors.

[0058] As described above, each detection path included in the optical subsystem 201 can be configured to detect scattered light. Thus, the optical subsystem 201 shown in FIG. 6 may be configured to generate a dark field (DF) output for the inspected object 202. However, the optical subsystem 201 may also or alternatively include a detection path configured to generate a bright field (BF) output for the inspected object 202. In other words, the optical subsystem 201 may include at least one detection path configured to detect light specularly reflected from the inspected object 202. Thus, the optical subsystem 201 described herein can be configured for only DF imaging, only BF imaging, or both DF and BF imaging. Although each collector is shown in FIG. 6 as a refractive optical element, each collector may include one or both of one or more refractive optical dies and one or more reflective optical elements.

[0059] The detection path or paths may include any suitable detectors known in the art. For example, the detectors may include photomultiplier tubes (PMTs), charge-coupled devices (CCDs), time-delay integration (TDI) cameras, or any other suitable detectors known in the art. The detectors may include non-imaging or imaging detectors. In such methods, when the detectors are non-imaging detectors, each detector may be configured to detect a particular characteristic of the scattered light, such as brightness, and not a characteristic such as positional correlation in the imaging plane. That is, the output generated by each detector in each detection path of the optical subsystem is a signal or data, and not an image signal or image data. In such cases, a processor, such as processor 214, may be configured to generate an image of the inspected object 202 from the non-imaging output of the detector. However, in other examples, the detectors are configured as imaging detectors configured to generate image signals or image data. Thus, the optical subsystem may be configured to detect the optical images shown herein or other optical output in a variety of ways.

[0060] It should be noted that FIG. 6 generally illustrates an optical subsystem 201 configuration that may be configured to generate an optical output included in or used by the system embodiments described herein. The optical subsystem 201 configuration illustrated herein may be modified to optimize the performance of the optical subsystem 201, as is typically done when designing a product system that obtains the output. Additionally, the systems illustrated herein may be built using existing systems (e.g., the functionality illustrated herein may be added to an existing system). Some such systems may include the methods illustrated herein as an option to the system's functionality (an additional functionality to other system functionality). Alternatively, the systems illustrated herein may be designed as entirely new systems.

[0061] The processor 214 may be coupled to the components of the system 200 in any suitable manner capable of receiving the output (e.g., via one or more transmission media, including wired or wireless or both transmission media). The processor 214 may be configured to use the output to perform various functions. The system 200 may obtain instructions and other information from the processor 214. The processor 214 and / or the electronic data storage 215 may optionally be in electronic communication with a wafer inspection tool, a wafer metrology tool, or a wafer analysis tool (not shown) for receiving further information or sending instructions. For example, the processor 214 and / or the electronic data storage 215 may be in electronic communication with a scanning electron microscope.

[0062] The processor 214, other system(s) or other subsystem(s) shown herein may be part of a variety of systems including, for example, PC systems, image computers, mainframe computers, workstations, network appliances, Internet appliances, etc. The subsystem(s) or system(s) may include any suitable processor known in the art, such as a parallel processor. Additionally, the subsystem(s) or system(s) may comprise a platform with high speed processing and software as a stand-alone or networked tool.

[0063] The processor 214 and electronic data storage 215 may be provided internally to the system 200 or other equipment, or externally as part of the system 200 or other equipment. For example, the processor 214 and electronic data storage 215 may be part of a stand-alone control unit or within a central quality control unit. Multiple processors 214 or multiple electronic data storage units 215 may be used.

[0064] The processor 214 may actually be implemented using any combination of hardware, software, and firmware. Furthermore, the functions described herein may be performed by a single component or may be shared among several different components, each of which may in turn be implemented using any combination of hardware, software, and firmware. Programs and instructions for the processor 214 to execute the various methods and functions may be stored in a readable storage medium, such as memory in the electronic data storage unit 215 or other memory.

[0065] Where system 200 includes more than one processor 214, the multiple subsystems may be interconnected to allow images, data, instructions, etc. to be transmitted between the subsystems. For example, a subsystem may be connected to additional subsystem(s) by a suitable transmission medium, which may include suitable wired or wireless, or both, transmission media known in the art. Two or more such subsystems may also be efficiently connected by a common computer-readable storage medium (not shown).

[0066] The processor 214 may be configured to perform various functions using the output of the system 200 or other outputs. For example, the processor 214 may be configured to transmit the output to an electronic data storage 215 or other storage medium. The processor 214 may be configured according to any of the embodiments described herein. The processor 214 may be configured to perform other functions or additional steps using the output of the system 200 or images or data from other sources.

[0067] The various steps, functions, operations of system 200, and methods illustrated herein may be performed by one or more of electronic circuits, logic gates, multiplexers, programmable logic devices, ASICs, analog or digital adjustment means or switches, microcontrollers, or computer systems. Program instructions for performing methods as illustrated herein may be transmitted over or stored on a carrier medium. The carrier medium may include storage media such as read-only memory, random access memory, magnetic or optical disks, non-volatile memory, solid-state memory, magnetic tape, and the like. The carrier medium may include transmission media such as wire, cable, or wireless transmission paths. For example, the various steps illustrated throughout this disclosure may be performed by one or more processors 214. Furthermore, each subsystem of system 200 may include one or more computer or logic systems. Thus, the above description should not be construed as a limitation on the present disclosure, but is merely exemplary.

[0068] For example, processor 214 can be in communication with system 200. Processor 214 is configured to generate an image of inspected object 202 (e.g., a laser annealed semiconductor wafer) using data from detector 209 or detector 212, or both, determine the location of grid lines within the image, and fill areas covered by the grid lines with new grayscale values ​​based on second grayscale values ​​of neighboring areas around the area, the neighboring areas being outside the area covered by the grid lines, which can be performed using embodiments disclosed herein.

[0069] Further embodiments relate to a non-transitory computer readable medium storing program instructions executable by a controller that performs a computer implemented method for adjusting grayscale values ​​on grating lines of a laser annealed semiconductor wafer as described herein. As particularly shown in FIG. 6, electronic data storage 215 or other storage medium may comprise a non-transitory computer readable medium that includes program instructions executable by processor 214. The computer implemented method may include any of the steps of the methods described herein, including method 100.

[0070] The program instructions may be implemented in a variety of ways, including, but not limited to, procedure-based, component-based, or object-oriented techniques, or any combination thereof, such as, for example, the program instructions may be implemented as ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (MFC), Streaming SIMD Extensions (SSE), or any other suitable technology or approach.

[0071] Illumination using system 200 may be performed on either the front or back side of inspected object 202 .

[0072] Although the present disclosure describes particular embodiments, it should be understood that other embodiments of the present disclosure may be made without departing from the scope of the present disclosure, that is, the present disclosure is limited only by the appended claims and their proper interpretation.

Claims

1. 1. A system comprising: A light source that generates light; a stage configured to hold a laser annealed semiconductor wafer in an optical path of the light; a detector configured to receive the light reflected from the laser annealed semiconductor wafer; a processor in electronic communication with the detector; The processor, generating an image of the laser annealed semiconductor wafer using data from the detector; determining a location of grid lines within the image; comparing a first greyscale value of an area in the image covered by the grid lines with a second greyscale value of a neighbouring area around the area, the neighbouring area being outside the area covered by the grid lines; dividing the first grayscale values ​​in the region by a correction factor to determine new grayscale values, the correction factor being the average graylevel of the region divided by the average graylevel of the neighborhood; configured to fill the areas in the image covered by the grid lines using the new greyscale values. A system characterized by:

2. 2. The system of claim 1, The system, wherein the second grayscale value is obtained from a location that is more than a width of a grid line away from the first grayscale value.

3. 2. The system of claim 1, the steps of comparing, dividing, and filling are repeated for every pixel within the grid lines of the image.

4. 2. The system of claim 1, The system, wherein the light source and the detector are configured such that the image is a bright field image.

5. 2. The system of claim 1, The system, wherein the light source and the detector are configured such that the image is a dark field image.

6. 2. The system of claim 1, The system, wherein the processor is further configured to perform defect inspection on the image after the regions are filled with the new grayscale values.

7. 2. The system of claim 1, The determining step utilizes Sobel edge detection.

8. 2. The system of claim 1, The system wherein the step of filling includes histogram remapping.

9. 1. A method comprising: generating light using a light source; holding a laser annealed semiconductor wafer in a path of the light; receiving the light reflected from the laser annealed semiconductor wafer using a detector; determining, using a processor, a location of grid lines in an image of the laser annealed semiconductor wafer, the image using data from the detector; using the processor to compare a first greyscale value of an area covered by the grid lines with a second greyscale value of a neighboring area about the area, the neighboring area being outside the area covered by the grid lines; using the processor to divide the first grayscale value of the region by a correction factor, the correction factor being the average gray level of the region divided by the average gray level of the neighborhood, to determine a new grayscale value; using said processor to fill the areas in said image covered by said grid lines with said new greyscale values; Includes A method comprising:

10. 10. The method of claim 9, The method of claim 1, wherein the second grayscale value is obtained from a location that is more than a width of a grid line away from the first grayscale value.

11. 10. The method of claim 9, The method of claim 1, wherein the steps of comparing, dividing, and filling are performed repeatedly for every pixel within the grid lines of the image.

12. 10. The method of claim 9, The method, wherein the image is a bright field image.

13. 10. The method of claim 9, The method, wherein the image is a dark field image.

14. 10. The method of claim 9, The method further comprising the step of performing a defect inspection on the image after the filling step.

15. 10. The method of claim 9, The method, wherein the determining step utilizes Sobel edge detection.

16. 10. The method of claim 9, The method according to claim 1, wherein said filling step comprises histogram remapping.

Images