Transconductor with improved slew performance and low quiescent current - Patents.com

Abstract

A semiconductor device (200) includes a low-power, high-speed differential transconductor (202) that provides an output current as a function of the difference between a reference potential input (206) and a feedback potential input (210). The transconductance increases as the absolute value of the difference between the reference potential and the feedback potential increases. The transconductor includes a reference input stage (204) for receiving a reference potential and a reference load (220) coupled in series to the reference input stage. The transconductor includes a feedback input stage (208) for receiving a feedback potential and a feedback load (224) coupled in series to the feedback input stage. The transconductor also includes a current limiting component (212) configured to control a total current through the reference input stage and the feedback input stage. The transconductor includes a negative feedback path (236) from the reference load to the current limiting component that compensates for a change in the total current due to the difference between the reference potential and the feedback potential.

Description

[Technical field]

[0001] The present description relates to the field of semiconductor devices. More specifically, but not by way of limitation, the present description relates to transconductors in semiconductor devices. [Background technology]

[0002] A differential transconductor provides an output current that is an approximately linear function of the difference between the two voltage inputs. Differential transconductors are used, for example, in voltage regulators, filters, and amplifiers. Two important performance parameters of a differential transconductor are the slew rate and the quiescent current. The slew rate is a measure of the output current when the two voltage inputs are different. The quiescent current is a measure of the current consumed by the differential transconductor when the two voltage inputs are equal. Summary of the Invention

[0003] This description describes a semiconductor device including a low-power high-speed differential transconductor, referred to herein as a transconductor. The transconductor includes a reference input stage configured to receive a reference potential and a reference load coupled in series to the reference input stage. The transconductor includes a feedback input stage configured to receive a feedback potential and a feedback load coupled in series to the feedback input stage. The transconductor further includes a current limiting component configured to control a total current through the reference input stage and the feedback input stage. The transconductor includes an output current terminal configured to provide an output current that is a function of the difference between the reference potential and the feedback potential. The transconductor includes a negative feedback path from the reference load to the current limiting component configured to compensate for the change in the total current when the reference potential differs from the feedback potential. Transconductance is the ratio of the change in output current at the output current terminal to the change in the difference between the reference potential and the feedback potential, and increases as the absolute value of the difference between the reference potential and the feedback potential increases. [Brief description of the drawings]

[0004] [Figure 1] 1 is a graph illustrating the difference between a reference potential and a feedback potential for an example transconductor versus transconductance and output current;

[0005] [Diagram 2] 1 is a conceptual schematic diagram of a semiconductor device including an example transconductor;

[0006] [Diagram 3] FIG. 2 is a circuit schematic diagram illustrating an example transconductor.

[0007] [Figure 4] FIG. 2 is a circuit schematic diagram illustrating another example transconductor.

[0008] [Diagram 5] FIG. 2 is a circuit schematic diagram illustrating another example transconductor.

[0009] [Figure 6] FIG. 2 is a circuit schematic diagram illustrating another example transconductor.

[0010] [Figure 7] FIG. 2 is a circuit schematic diagram illustrating another example transconductor.

[0011] [Figure 8] FIG. 2 is a circuit schematic diagram illustrating another example transconductor.

[0012] [Figure 9] FIG. 2 is a circuit schematic diagram illustrating another example transconductor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The drawings are not necessarily drawn to scale. This description is not limited to the illustrated order of acts or events, and some acts or events may occur in different orders and / or contemporaneously with other acts or events. Also, some illustrated acts or events are optional.

[0014] Although some examples illustrated herein are shown in two-dimensional views with various regions having depth and width, the regions may in fact depict portions of devices that are three-dimensional structures, and thus, when fabricated on an actual device, the regions will have three dimensions, including length, width, and depth.

[0015] The transconductor includes a reference input stage configured to receive a reference potential and a feedback input stage configured to receive a feedback potential. A current limiting component controls the total current through the reference input stage and the feedback input stage. A reference load is coupled in series to the reference input stage and a feedback load is coupled in series to the feedback input stage. An output current node is configured to provide an output current. Increasing the transconductance is achieved by a negative feedback path from the reference load to the current limiting component configured to compensate for changes in the total current when the reference potential is different from the feedback potential. As a result of having a current limiting component in series with the reference input stage and the feedback input stage, the transconductor draws less power when the feedback potential is equal to the reference potential, which may advantageously reduce the quiescent current of the semiconductor device compared to a semiconductor device having a transconductor with a positive feedback loop. A further advantage of the transconductor is that the through current, which is the output current when the feedback potential is different from the reference potential, is not present when the feedback potential is equal to the reference potential, which may further reduce the quiescent current.

[0016] In some examples, the transconductor may provide a sunk output functionality, where the output current is controlled by controlling an output driver connected between an output node and a ground terminal of the semiconductor device. In some examples, the transconductor may provide a sourced output functionality, where the output current is controlled by controlling an output driver connected between an output node and a power terminal of the semiconductor device. In some examples, the transconductor may provide a bidirectional output functionality, where the output current is controlled by controlling an output driver connected between an output node and a power terminal of the semiconductor device and by controlling another output driver connected between an output node and a ground terminal of the semiconductor device. In some examples, the transconductor may provide a complementary polarity of output current, where when the difference between the reference potential and the feedback potential increases, the output current decreases and vice versa. The difference between the reference potential and the feedback potential is defined for purposes of this description as the reference potential minus the feedback potential. In some examples, the transconductors may provide non-complementary polarities of the output current, where when the difference between the reference potential and the feedback potential increases, the output current increases, and vice versa.

[0017] For purposes of this description, when a component is described as being "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or there may be intervening components. In either case, components that are coupled or connected together may have direct current (DC) conductivity between the coupled or connected components. When a component is referred to as being "directly coupled" or "directly connected" to another component, there are no other intentionally placed intervening components, with the possible exception of electrical conductors such as metal interconnects in semiconductor devices. Components that are not capable of DC conductivity between the components may be affected by mutual inductive or capacitive effects and are not considered to be coupled or connected unless specifically stated to that effect.

[0018] In this description, operational characteristics of various components of the transconductor, such as current flow, are described. The described component operational characteristics arise during operation of the semiconductor device and are not expected to be present when the semiconductor device is not operating.

[0019] FIG. 1 is a graph showing the difference between a reference potential and a feedback potential for an example transconductor versus transconductance and output current. In graph 100, the horizontal axis is the difference between the reference potential and the feedback potential. The difference between the reference potential and the feedback potential may be expressed, for example, in millivolts. The left vertical axis 102 is transconductance. The transconductance may be expressed, for example, in siemens, which is amperes per volt. In some cases, the transconductance may be expressed in millisiemens, or the transconductance may be expressed in microsiemens. The transconductance curve 104 has a minimum value of approximately 0 millivolts within 5 millivolts of the difference between the reference potential and the feedback potential. The transconductance curve 104 is upwardly concave for both positive and negative values ​​of the difference between the reference potential and the feedback potential, which advantageously provides more current to reduce recovery time for circuits coupled to the transconductor compared to transconductors having flat or downwardly curving transconductance curves. In this example, all transconductance values ​​are positive.

[0020] The right vertical axis 106 is the output current. The output current may be expressed, by way of example, in some cases in units of microamps, or in other cases in milliamps. In this example, the output current curve 108 is upwardly concave for positive values ​​of the difference between the reference potential and the feedback potential, and downwardly concave for negative values ​​of the difference, consistent with the transconductance values ​​being all positive.

[0021] 2 is a conceptual schematic diagram of a semiconductor device including an example transconductor. The semiconductor device 200 may be implemented as a voltage regulator, a high-speed amplifier, or a filter, by way of example. The transconductor 202 includes a reference input stage 204 configured to receive a reference potential, labeled "VREF" in FIG. 2, at a reference input port 206. The transconductor 202 includes a feedback input stage 208 configured to receive a feedback potential, labeled "VFB" in FIG. 2, at a feedback input port 210. In this example, the reference input stage 204 has a negative transconductance, such that an increase in the reference potential VREF decreases the current through the reference input stage 204, and vice versa. Similarly, the feedback input stage 208 has a negative transconductance, such that an increase in the feedback potential VFB decreases the current through the feedback input stage 208, and vice versa.

[0022] The transconductor 202 includes a current limiting component 212 coupled in series to the reference input stage 204 and the feedback input stage 208 at a branch node 214. The reference input stage 204 and the feedback input stage 208 are in parallel current paths as shown in FIG. 2. The current limiting component 212 has a current control node 216. The current through the current limiting component 212 is regulated by a first control potential, labeled "VCTL1" in FIG. 2 on the current control node 216 during operation of the semiconductor device 200. The current limiting component 212 in this example has a positive transconductance, such that an increase in the first control potential VCTL1 on the current control node 216 increases the current through the current limiting component 212 and vice versa. The current limiting component 212 is connected to a power terminal 218 opposite its connection to the reference input stage 204 and the feedback input stage 208. 2. Power terminal 218 is configured to provide current to transconductor 202 at a positive power potential, labeled "VDD" in FIG. 2, such that current from power terminal 218 flows through current limiting component 212 to reference input stage 204 and feedback input stage 208. The current through current limiting component 212 is split into a reference current through reference input stage 204, labeled "IREF" in FIG. 2, and a feedback current through feedback input stage 208, labeled "IFB" in FIG. 2.

[0023] Transconductor 202 includes a reference load 220, which is connected to reference input stage 204 via a control signal node 222. A reference current I flows through reference input stage 204, control signal node 222, and reference load 220. Reference load 220 may have an impedance that varies as a function of reference current I through reference load 220, as shown diagrammatically in Figure 2, such that a second control potential at control signal node 222, labeled "VCTL2" in Figure 2, is a function of reference current I.

[0024] The transconductor 202 includes a feedback load 224 that is connected to the feedback input stage 208 via an output signal node 226. A feedback current IFB through the feedback input stage 208 flows through the output signal node 226 and the feedback load 224. The feedback load 224 may have an impedance that varies as a function of the feedback current IFB through the feedback load 224, as shown diagrammatically in Figure 2, such that the output signal potential at the control signal node 222, labeled "VSIG" in Figure 2, is a function of the feedback current IFB.

[0025] Reference load 220 and feedback load 224 are connected to a ground terminal 228 opposite the connections to reference input stage 204 and feedback input stage 208, respectively. Ground terminal 228 is configured to receive a current at a ground potential, labeled "VSS" in Figure 2. Reference current IREF and feedback current IFB flow to ground terminal 228.

[0026] Transconductor 202 includes an output current terminal 230 that is coupled to output signal node 226 through an output buffer 232. Output buffer 232 converts the output signal potential VSIG at output signal node 226 into an output current, labeled "IOUT" in FIG.

[0027] The control signal node 222 is coupled to the current control node 216 of the current limiting component 212 through an inverting control buffer 234, as shown in FIG. 2, such that the first control potential VCTL1 has a negative correlation with the second control potential VCTL2. Coupling the control signal node 222 to the current control node 216 through the inverting control buffer 234 provides a negative feedback path 236 that compensates for variations in the head potential, labeled "VHEAD" in FIG. 2, at the branch node 214 when the feedback current IFB changes due to variations in the feedback potential VFB. During operation of the semiconductor device 200, when the feedback potential VFB decreases, the impedance of the feedback input stage 208 decreases and the feedback current IFB increases due to the negative transconductance of the feedback input stage 208, causing the output signal potential VSIG to increase and the output current IOUT to increase. The head potential VHEAD decreases as the impedance of the feedback input stage 208 decreases, decreasing the reference current VREF and decreasing the second control potential VCTL2. The inverting control buffer 234 increases the first control potential VCTL1, which decreases the impedance of the current limiting component 212, thereby further increasing the feedback current IFB and further increasing the output current IOUT, which increases the transconductance of the transconductor 202. Conversely, when the feedback potential VFB increases, the impedance of the feedback input stage 208 increases and the feedback current IFB decreases, decreasing the output signal potential VSIG and decreasing the output current IOUT. The second control potential VCTL2 increases and the inverting control buffer 234 decreases the first control potential VCTL1, which increases the impedance of the current limiting component 212, thereby further decreasing the feedback current IFB and further decreasing the output current IOUT, which increases the transconductance of the transconductor 202. Thus, the negative feedback path 236 provides an increased transconductance of the transconductor 202 when the feedback potential VFB differs from the reference potential VREF.

[0028] 3 is a circuit schematic of an example transconductor. Transconductor 302 includes a reference input stage 304 configured to receive a reference potential, labeled "VREF" in FIG. 3, at a reference input port 306. Transconductor 302 includes a feedback input stage 308 configured to receive a feedback potential, labeled "VFB" in FIG. 3, at a feedback input port 310. In this example, reference input stage 304 and feedback input stage 308 may be implemented as p-channel field effect transistors (PFETs) having negative transconductance.

[0029] The transconductor 302 includes a current limiting component 312 coupled in series to the reference input stage 304 and to the feedback input stage 308 in parallel current paths at a branch node 314, as shown in FIG. 3. In this example, the current limiting component 312 may be implemented as an n-channel field effect transistor (NFET) with a positive transconductance. The current limiting component 312 has a current control node 316 that has a first control potential, labeled "VCTL1" in FIG. 3, during operation of the transconductor 302. The current limiting component 312 is coupled to a power terminal 318 configured to provide a current to the transconductor 302 at a positive power potential, labeled "VDD" in FIG. 3. Current flows from the power terminal 318 through the current limiting component 312 and splits into a reference current through the reference input stage 304, labeled "IREF" in FIG. 3, and a feedback current through the feedback input stage 308, labeled "IFB" in FIG. 3.

[0030] The transconductor 302 includes a feedback load 324 that is connected to the feedback input stage 308 via an output signal node 326. In this example, the feedback load 324 may be implemented as an NFET configured as an NMOS diode, with the gate of the NMOS diode connected directly to the drain of the NMOS diode, as shown in Figure 3. The output signal potential at the output signal node 326, labeled "VSIG" in Figure 3, is equal to the voltage drop across the feedback load 324 due to the feedback current IFB.

[0031] The transconductor 302 includes a reference load 320 connected to the reference input stage 304 via a control signal node 322. In this example, the reference load 320 may be implemented as an NFET. A gate of the reference load 320 may be connected to an NMOS bias terminal 338, which is configured to provide an NMOS bias potential, labeled "NBIAS" in FIG. 3, to the gate of the reference load 320. The NMOS bias potential NBIAS may be above the threshold potential of the reference load 320 but significantly below the saturation potential, such that the reference load 320 is operating in a linear mode. A second control potential at the control signal node 322, labeled "VCTL2" in FIG. 3, is equal to the voltage drop across the reference load 320 due to the reference current IREF.

[0032] The reference load 320 and the feedback load 324 are connected to a ground terminal 328 that is configured to receive a current at a ground potential, labeled "VSS" in Figure 3. The reference current IREF and the feedback current IFB flow to the ground terminal 328.

[0033] The transconductor 302 includes an output current terminal 330 that is coupled to an output signal node 326 via an output buffer 332. The output buffer 332 converts the output signal potential VSIG at the output signal node 326 into an output current, labeled "IOUT" in FIG. 3 and flowing via the output current terminal 330. In this example, the output buffer 332 includes an output load 340, implemented in this example as a PFET, and an output driver 342, implemented in this example as an NFET, coupled in series to the output signal node 326, with the output signal node 326 connected to a drain of the output load 340 and a drain of the output driver 342. A gate of the output load 340 is connected to a PMOS bias terminal 344 that is configured to provide a PMOS bias potential, labeled "PBIAS" in FIG. 3, to the gate of the output load 340. The PMOS bias potential PBIAS may be below the threshold potential of the output load 340 but significantly above the saturation potential, so that the output load 340 is operating in a linear mode. The gate of the output driver 342 is connected to the output signal node 326. The source of the output load 340 is connected to the power terminal 318. The source of the output driver 342 is connected to the ground terminal 328. The output buffer 332 in this example provides a sinking output functionality with complementary polarity for the output current IOUT.

[0034] 3, the control signal node 322 is coupled to the current control node 316 of the current limiting component 312 via an inverting control buffer 334, so that the first control potential VCTL1 has a negative correlation to the second control potential VCTL2. In this example, the inverting control buffer 334 includes a controlled load 346, implemented in this example as a PFET, and a controlled driver 348, implemented in this example as an NFET, coupled in series to the control signal node 322, and the control signal node 322 is connected to the drain of the controlled load 346 and the drain of the controlled driver 348. A gate of the controlled load 346 is connected to the PMOS bias terminal 344. A gate of the controlled driver 348 is connected to the control signal node 322. A source of the controlled load 346 is connected to the power terminal 318. A source of the controlled driver 348 is connected to the ground terminal 328. Coupling the control signal node 322 to the current control node 316 through an inverting control buffer 334 provides a negative feedback path 336 that reduces fluctuations in the head potential, labeled “VHEAD” in FIG. 3, at the branch node 314 when the feedback current IFB changes due to variations in the feedback potential VFB.

[0035] The operation of the transconductor 302 proceeds as described for the transconductor 202 of Fig. 2. The transconductor 302 may provide a desired increase in transconductance as the absolute value of the difference between the feedback potential VFB and the reference potential VREF increases. Also, the transconductor 302 of this example may be smaller in area than more complex transconductors due to the implementation of the negative feedback path 336, advantageously allowing for a smaller area for the semiconductor device 300 including the transconductor 302.

[0036] 4 is a circuit schematic diagram of another example transconductor. The transconductor 402 includes a reference input stage 404 configured to receive a reference potential, labeled "VREF" in FIG. 4, at a reference input port 406. The transconductor 402 includes a feedback input stage 408 configured to receive a feedback potential, labeled "VFB" in FIG. 4, at a feedback input port 410. In this example, the reference input stage 404 and the feedback input stage 408 may be implemented as PFETs as shown in FIG. 4.

[0037] The transconductor 402 includes a current limiting component 412, implemented in this example as an NFET, coupled in series with the reference input stage 404 and the feedback input stage 408 at a branch node 414, as shown in Figure 4. The current limiting component 412 has a current control node 416 that has a first control potential, labeled "VCTL1" in Figure 4, during operation of the transconductor 402. The current limiting component 412 is coupled to a power terminal 418, which is configured to provide a current to the transconductor 402 at a positive power potential, labeled "VDD" in Figure 4.

[0038] The transconductor 402 includes a feedback load 424, implemented in this example as an NMOS diode, which is connected to the feedback input stage 408 via an output signal node 426. An output signal potential at the output signal node 426, labeled "VSIG" in FIG. 4, is equal to the voltage drop across the feedback load 424 due to the feedback current IFB.

[0039] The transconductor 402 includes a reference load 420, implemented in this example as an NFET, connected to the reference input stage 404 via a control signal node 422. A gate of the reference load 420 may be connected to an NMOS bias terminal 438. At the control signal node 422, a second control potential, labeled "VCTL2" in FIG. 4, is equal to the voltage drop across the reference load 420 due to the reference current IREF. The reference load 420 and the feedback load 424 are connected to a ground terminal 428 configured to receive a current at a ground potential, labeled "VSS" in FIG. 4.

[0040] During operation of the semiconductor device 400 including the transconductor 402, current flows from the power terminal 418 through the current limiting component 412 and splits at the branch node 414 into a reference current through the reference input stage 404, labeled "IREF" in FIG. 4, and a feedback current through the feedback input stage 408, labeled "IFB" in FIG. 4. The reference current IREF flows through the control signal node 422 and the reference load 420 to the ground terminal 428. The feedback current IFB flows through the output signal node 426 and the feedback load 424 to the ground terminal 428.

[0041] 4, the control signal node 422 is coupled to the current control node 416 of the current limiting component 412 via an inverting control buffer 434, so that the first control potential VCTL1 has a negative correlation to the second control potential VCTL2. In this example, the inverting control buffer 434 includes a controlled load 446, implemented in this example as a PFET, and a controlled driver 448, implemented in this example as an NFET, coupled in series to the control signal node 422, and the control signal node 422 is connected to the drain of the controlled load 446 and the drain of the controlled driver 448. The gate of the controlled load 446 is connected to the PMOS bias terminal 444. The gate of the controlled driver 448 is connected to the control signal node 422. The source of the controlled load 446 is connected to the power terminal 418. The source of the controlled driver 448 is connected to the ground terminal 428. Coupling the control signal node 422 to the current control node 416 through an inverting control buffer 434 provides a negative feedback path 436 that reduces fluctuations in the head potential, labeled “VHEAD” in FIG. 4, at the branch node 414 when the feedback current IFB changes due to variations in the feedback potential VFB.

[0042] The transconductor 402 includes an output current terminal 430 that is coupled to an output signal node 426 through an output buffer 432. The output buffer 432 converts the output signal potential VSIG at the output signal node 426 into an output current, labeled "IOUT" in Figure 4, that flows through the output current terminal 430. In this example, the output buffer 432 includes two parallel current paths to provide an amplified transconductance.

[0043] 4, a first output load 440a, implemented in this example as a PFET, and a first output driver 442a, implemented in this example as an NFET. A first terminal of the first resistor 450a is connected to the power terminal 418. A source of the first output load 440a is connected to a second terminal of the first resistor R1 450a. A source of the first output driver 442a is connected to the ground terminal 428.

[0044] 4, a second output load 440b, implemented in this example as a PFET, and a second output driver 442b, implemented in this example as an NFET. A first terminal of the second resistor 450b is connected to the power terminal 418. A source of the second output load 440b is connected to a second terminal of the second resistor R2 450b. A source of the second output driver 442b is connected to the ground terminal 428.

[0045] The gates of the first output load 440a and the second output load 440b are connected to the drain of the first output load 440a so that the first output load 440a acts as a PMOS diode. The gates of the first output driver 442a and the second output driver 442b are connected to the output signal node 426. The first resistor R1 450a, the second resistor R2 450b, the first output load 440a, the second output load 440b, the first output driver 442a, and the second output driver 442b provide an amplifier of the output buffer 432 configured to provide an amplified transconductance.

[0046] The output buffer 432 includes an output stage 452, implemented in this example as a PMOS source follower. The source of the output stage 452 is connected to the source of the first output load 440a. The gate of the output stage 452 is connected to the drain of the second output driver 442b. The drain of the output stage 452 is connected to the output current terminal 430.

[0047] The operation of the transconductor 402 is similar to that of the transconductor 302 of Figure 3 up to the generation of the output signal potential VSIG at the output signal node 326 of Figure 3. The output buffer 432 amplifies the output signal potential VSIG at the output signal node 426 by a factor approximately equal to the ratio of the resistance of the second resistor 450b to the resistance of the first resistor 450a. Thus, the intrinsic transconductance of the reference input stage 404, the feedback input stage 408, the reference load 420, and the feedback load 424 is amplified by a factor approximately equal to the ratio of the resistance of the second resistor 450b to the resistance of the first resistor 450a, allowing the transconductor 402 to drive a larger load at the output signal node 426. When the feedback potential VFB is equal to the reference potential VREF, the quiescent current of the transconductor 402 is lower than a similar transconductor having an equivalent transconductance value because the transconductor 402 does not draw a through current.

[0048] The output buffer 432 in this example provides a source output functionality with a complementary polarity to the output current IOUT. The source output functionality may be advantageous for a grounded load connected to the output signal node 326. The transconductor 402 with an amplified transconductance may be particularly advantageous for driving a capacitor external to the semiconductor device 400 that contains the transconductor 402.

[0049] 5 is a circuit schematic diagram of another exemplary transconductor. Transconductor 502 includes a reference input stage 504 configured to receive a reference potential, labeled "VREF" in FIG. 5, at a reference input port 506. Transconductor 502 includes a feedback input stage 508 configured to receive a feedback potential, labeled "VFB" in FIG. 5, at a feedback input port 510. In this example, reference input stage 504 and feedback input stage 508 may be implemented as PFETs as shown in FIG. 5.

[0050] 5, is coupled in series with the reference input stage 504 and the feedback input stage 508 at a branch node 514. The current limiting component 512 has a current control node 516 that has a first control potential, labeled “VCTL1” in FIG.

[0051] The transconductor 502 in this example includes a current sensor 554 coupled in series with the current limiting component 512. In this example, the current sensor 554 is implemented as a PFET. The drain of the current sensor 554 is connected to the gate of the current sensor 554 and to the drain of the current limiting component 512. The source of the current sensor 554 is connected to a power terminal 518, which is configured to provide a current to the transconductor 502 at a positive power potential, labeled "VDD" in FIG. 5. Thus, the current sensor 554 in this example is configured as a PMOS diode. In this example, the gate of the current sensor 554 provides an output signal node 526 having an output signal potential, labeled "VSIG" in FIG. 5, during operation of the transconductor 502.

[0052] The transconductor 502 includes a reference load 520, implemented in this example as an NFET, that is connected to a reference input stage 504 via a control signal node 522. The gate of the reference load 520 may be connected to an NMOS bias terminal 538.

[0053] The transconductor 502 includes a feedback load 524, implemented in this example as an NMOS diode. A drain of the feedback load 524 is connected to the feedback input stage 508. The reference load 520 and the feedback load 524 are connected to a ground terminal 528 that is configured to receive a current at a ground potential, labeled "VSS" in FIG.

[0054] Current flows from power terminal 518, through current sensor 554, through current limiting component 512, and splits at branch node 514 into a reference current through reference input stage 504, labeled "IREF" in FIG. 5, and a feedback current through feedback input stage 508, labeled "IFB" in FIG. 5. The reference current IREF flows through control signal node 522 and reference load 520 to ground terminal 528. At control signal node 522, a second control potential, labeled "VCTL2" in FIG. 5, is equal to the voltage drop across reference load 520 due to reference current IREF. The feedback current IFB flows through feedback load 524 to ground terminal 528.

[0055] 5, the control signal node 522 is coupled to the current control node 516 of the current limiting component 512 via an inverting control buffer 534, so that the first control potential VCTL1 has a negative correlation to the second control potential VCTL2. In this example, the inverting control buffer 534 includes a controlled load 546, implemented in this example as a PFET, and a controlled driver 548, implemented in this example as an NFET, coupled in series to the control signal node 522, and the control signal node 522 is connected to the drain of the controlled load 546 and the drain of the controlled driver 548. The gate of the controlled load 546 is connected to the PMOS bias terminal 544. The gate of the controlled driver 548 is connected to the control signal node 522. The source of the controlled load 546 is connected to the power terminal 518. The source of the controlled driver 548 is connected to the ground terminal 528. Coupling the control signal node 522 to the current control node 516 through an inverting control buffer 534 provides a negative feedback path 536 that reduces fluctuations in the head potential, labeled "VHEAD" in FIG. 5, at the branch node 514 when the feedback current IFB changes due to variations in the feedback potential VFB.

[0056] The transconductor 502 includes an output current terminal 530 coupled to an output signal node 526 through an output buffer 532. The output buffer 532 converts the output signal potential VSIG at the output signal node 526 to an output current, labeled "IOUT" in FIG. 5, flowing through the output current terminal 530. In this example, the output buffer 532 includes an output load 540, implemented in this example as an NFET, and an output driver 542, implemented in this example as a PFET, coupled in series to the output signal node 526, with the output signal node 526 connected to the drain of the output load 540 and the drain of the output driver 542. A gate of the output load 540 is connected to an NMOS bias terminal 538. A gate of the output driver 542 is connected to the output signal node 526. A source of the output load 540 is connected to a ground terminal 528. A source of the output driver 542 is connected to a power terminal 518. The output buffer 532 in this example provides a source output functionality with a complementary polarity to the output current IOUT. The operation of the transconductor 502 is similar to that of the transconductor 302 of Figure 3, with the current sensor 554 providing an output signal potential VSIG to enable source output functionality. Complementary polarity may be appropriate for networks external to the semiconductor device 500 that includes the transconductor 502.

[0057] 6 is a circuit schematic diagram of another example transconductor. Transconductor 602 includes a reference input stage 604 configured to receive a reference potential, labeled "VREF" in FIG. 6, at a reference input port 606, and a feedback input stage 608 configured to receive a feedback potential, labeled "VFB" in FIG. 6, at a feedback input port 610. In this example, reference input stage 604 and feedback input stage 608 may be implemented as PFETs with negative transconductance.

[0058] The transconductor 602 includes a current limiting component 612 coupled in series to the reference input stage 604 and the feedback input stage 608 in parallel current paths at a branch node 614, as shown in FIG. 6. In this example, the current limiting component 612 may be implemented as an NFET having a positive transconductance. The current limiting component 612 has a current control node 616 having a first control potential, labeled "VCTL1" in FIG. 6, during operation of the transconductor 602. The current limiting component 612 is coupled to a power terminal 618 configured to provide a current to the transconductor 602 at a positive power potential, labeled "VDD" in FIG. 6. The current flows from the power terminal 618 through the current limiting component 612 and splits into a reference current through the reference input stage 604, labeled "IREF" in FIG. 6, and a feedback input stage 608, labeled "IFB" in FIG. 6.

[0059] The transconductor 602 includes a feedback load 624, which is connected to the feedback input stage 608 via an output signal node 626. In this example, the feedback load 624 may be implemented as an NMOS diode, with the gate of the NMOS diode directly connected to the drain of the NMOS diode, as shown in Figure 6. The output signal potential at the output signal node 626, labeled "VSIG" in Figure 6, is equal to the voltage drop across the feedback load 624 due to the feedback current IFB.

[0060] The transconductor 602 includes a reference load 620 that is connected to the reference input stage 604 via a control signal node 622. In this example, the reference load 620 may be implemented as an NFET. A gate of the reference load 620 may be connected to an NMOS bias terminal 638. At the control signal node 622, a second control potential, labeled "VCTL2" in FIG. 6, is equal to the voltage drop across the reference load 620 due to the reference current IREF.

[0061] The reference load 620 and the feedback load 624 are connected to a ground terminal 628 that is configured to receive a current at a ground potential, labeled "VSS" in Figure 6. The reference current IREF and the feedback current IFB flow to the ground terminal 628.

[0062] 6, the control signal node 622 is coupled to the current control node 616 of the current limiting component 612 via an inverting control buffer 634, so that the first control potential VCTL1 has a negative correlation to the second control potential VCTL2. In this example, the inverting control buffer 634 includes a controlled load 646, implemented in this example as a PFET, and a controlled driver 648, implemented in this example as an NFET, coupled in series to the control signal node 622, and the control signal node 622 is connected to the drain of the controlled load 646 and the drain of the controlled driver 648. The gate of the controlled load 646 is connected to the PMOS bias terminal 644. The gate of the controlled driver 648 is connected to the control signal node 622. The source of the controlled load 646 is connected to the power terminal 618. The source of the controlled driver 648 is connected to the ground terminal 628. Coupling the control signal node 622 to the current control node 616 through an inverting control buffer 634 provides a negative feedback path 636 that reduces fluctuations in the head potential, labeled "VHEAD" in FIG. 6, at the branch node 614 when the feedback current IFB changes due to variations in the feedback potential VFB.

[0063] The transconductor 602 includes an output current terminal 630 coupled to an output signal node 626 via an output buffer 632. The output buffer 632 converts the output signal potential VSIG at the output signal node 626 to an output current, labeled "IOUT" in FIG. 6, flowing through the output current terminal 630. In this example, the output buffer 632 includes an output driver 642, implemented in this example as an NFET, in series with an output current sensor 640 of an output current mirror 656. The output current mirror 656 includes an output stage 652 connected to the output signal node 626. In this example, the output current sensor 640 and the output stage 652 may be implemented as a PFET. A source of the output driver 642 is connected to a ground terminal 628. A source of the output current sensor 640 and a source of the output stage 652 are connected to a power terminal 618.

[0064] Operation of the transconductor 602 proceeds as described for the transconductor 302 of Figure 3 up to the output buffer 632. The output current mirror 656 provides more current than the output buffer 332 of Figure 3, allowing the transconductor 602 to operate at a lower value of the positive power potential VDD than the transconductor 302. The output buffer 632 in this example provides source output functionality with non-complementary polarities for the output current IOUT. The non-complementary polarities may be appropriate for networks external to the semiconductor device 600 that includes the transconductor 602.

[0065] 7 is a circuit schematic diagram of another example transconductor. Transconductor 702 includes a reference input stage 704 configured to receive a reference potential, labeled "VREF" in FIG. 7, at a reference input port 706, and a feedback input stage 708 configured to receive a feedback potential, labeled "VFB" in FIG. 7, at a feedback input port 710. In this example, reference input stage 704 and feedback input stage 708 may be implemented as PFETs, as shown in FIG. 7.

[0066] The transconductor 702 in this example includes a current sensor 754 coupled in series with a current limiting component 712. In this example, the current sensor 754 is implemented as a PFET and the current limiting component 712 is implemented as an NFET, as shown in FIG. 7. The drain of the current sensor 754 is connected to the gate of the current sensor 754 and to the drain of the current limiting component 712. The source of the current sensor 754 is connected to a power terminal 718 configured to provide a current to the transconductor 702 at a positive power potential, labeled "VDD" in FIG. 7. Thus, the current sensor 754 in this example is configured as a PMOS diode. In this example, the gate of the current sensor 754 provides an output signal node 726 having an output signal potential, labeled "VSIG" in FIG. 7, during operation of the transconductor 702. The current limiting component 712 has a current control node 716 having a first control potential, labeled "VCTL1" in FIG. 7, during operation of the transconductor 702. A current limiting component 712 is coupled in series with the reference input stage 704 and the feedback input stage 708 at a branch node 714 .

[0067] The transconductor 702 includes a reference load 720, implemented in this example as an NFET, connected to a reference input stage 704 via a control signal node 722. A gate of the reference load 720 may be connected to an NMOS bias terminal 738. At the control signal node 722, a second control potential, labeled "VCTL2" in FIG. 7, is equal to the voltage drop across the reference load 720 due to the reference current IREF.

[0068] The transconductor 702 includes a feedback load 724, implemented in this example as an NMOS diode. A drain of the feedback load 724 is connected to the feedback input stage 708. The reference load 720 and the feedback load 724 are connected to a ground terminal 728 that is configured to receive a current at a ground potential, labeled "VSS" in FIG.

[0069] Current flows from power terminal 718, through current sensor 754, through current limiting component 712, and splits into a reference current, labeled "IREF" in FIG. 7, through reference input stage 704, and a feedback current, labeled "IFB" in FIG. 7, through feedback input stage 708. The reference current IREF flows through control signal node 722 and reference load 720 to ground terminal 728. The feedback current IFB flows through feedback load 724 to ground terminal 728.

[0070] 7, the control signal node 722 is coupled to the current control node 716 of the current limiting component 712 via an inverting control buffer 734, so that the first control potential VCTL1 has a negative correlation to the second control potential VCTL2. In this example, the inverting control buffer 734 includes a controlled load 746, implemented in this example as a PFET, and a controlled driver 748, implemented in this example as an NFET, coupled in series to the control signal node 722, and the control signal node 722 is connected to the drain of the controlled load 746 and the drain of the controlled driver 748. The gate of the controlled load 746 is connected to the PMOS bias terminal 744. The gate of the controlled driver 748 is connected to the control signal node 722. The source of the controlled load 746 is connected to the power terminal 718. The source of the controlled driver 748 is connected to the ground terminal 728. Coupling the control signal node 722 to the current control node 716 through an inverting control buffer 734 provides a negative feedback path 736 that reduces fluctuations in the head potential, labeled "VHEAD" in FIG. 7, at the branch node 714 when the feedback current IFB changes due to variations in the feedback potential VFB.

[0071] The transconductor 702 includes an output current terminal 730 coupled to an output signal node 726 via an output buffer 732. The output buffer 732 converts the output signal potential VSIG at the output signal node 726 to an output current, labeled "IOUT" in FIG. 7, flowing via the output current terminal 730. In this example, the output buffer 732 includes an output stage 752, implemented in this example as a PMOS source follower. A source of the output stage 752 is connected to the power terminal 718. A gate of the output stage 752 is connected to the output signal node 726. A drain of the output stage 752 is connected to the output current terminal 730. The output buffer 732 in this example provides source output functionality with a non-complementary polarity to the output current IOUT. The operation of the transconductor 702 is similar to that of the transconductor of FIG. 3, with a current sensor 754 providing the output signal potential VSIG to enable the source output functionality. The output stage 752 may advantageously provide more current than a driver / load buffer and occupy less area in the semiconductor device 700 that includes the transconductor 702 .

[0072] 8 is a circuit schematic diagram of another example transconductor. The transconductor 802 includes a first reference input stage 804a configured to receive a reference potential, labeled "VREF" in FIG. 8, at a reference input port 806, which is paired with a first feedback input stage 808a configured to receive a feedback potential, labeled "VFB" in FIG. 8, at a feedback input port 810. In this example, the first reference input stage 804a and the first feedback input stage 808a may be implemented as PFETs, as shown in FIG.

[0073] The transconductor 802 includes a first current limiting component 812a, implemented as an NFET in this example, as shown in FIG. 8. A source of the first current limiting component 812 is connected to a first branch node 814a. The first current limiting component has a first current control node 816a, which has a first control potential, labeled "VCTL1a" in FIG. 8, during operation of the transconductor 802. The transconductor 802 in this example includes a current sensor 854 coupled in series with the first current limiting component 812a. In this example, the current sensor 854 is implemented as a PFET. A drain of the current sensor 854 is connected to a gate of the current sensor 854 and to a drain of the first current limiting component 812a. A source of the current sensor 854 is connected to a power terminal 818 configured to provide a current to the transconductor 802 at a positive power potential, labeled "VDD" in FIG. 8. As such, current sensor 854 in this example is configured as a PMOS diode. In this example, the gate of current sensor 854 provides a first output signal node 826a having a first output signal potential labeled "VSIGa" in FIG. 8 during operation of transconductor 802.

[0074] In this example, the first reference input stage 804a is connected to the first current limiting component 812a through a first resistor 858, labeled "R1" in Figure 8. The first feedback input stage 808a is connected to the first current limiting component 812a through a second resistor 860, labeled "R2" in Figure 8.

[0075] The transconductor 802 includes a first reference load 820a, implemented in this example as an NFET, connected to the first reference input stage 804a via a first control signal node 822a. A gate of the first reference load 820a may be connected to an NMOS bias terminal 838.

[0076] The transconductor 802 includes a first feedback load 824a, implemented in this example as an NMOS diode. A drain of the first feedback load 824a is connected to the first feedback input stage 808a. A gate of the first feedback load 824a may be connected to a drain of the first feedback load 824a, such that the first feedback load 824a is implemented as an NMOS diode in this example. The first reference load 820a and the source of the first feedback load 824a are connected to a ground terminal 828 configured to receive a current at a ground potential, labeled "VSS" in FIG. 8.

[0077] A current flows from the power terminal 818 through the current sensor 854, through the first current limiting component 812a, and splits into a first reference current, labeled "IREFa" in FIG. 8, through the first resistor R1 858 and the first reference input stage 804a, and a first feedback current, labeled "IFBa" in FIG. 8, through the second resistor R2 860 and the first feedback input stage 808a. The reference current IREFa flows through the first control signal node 822a and the first reference load 820a to the ground terminal 828. At the first control signal node 822a, a second control potential, labeled "VCTL2a" in FIG. 8, is equal to the voltage drop across the first reference load 820a due to the reference current IREFa. The feedback current IFBa flows through the first feedback load 824a to the ground terminal 828.

[0078] The first control signal node 822a is coupled to the first current control node 816a of the first current limiting component 812a through a first inverting control buffer 834a, as shown in FIG. 8, so that the first control potential VCTL1a has a negative correlation to the second control potential VCTL2a. In this example, the first inverting control buffer 834a includes a first controlled load 846a, implemented as a PFET in this example, and a first controlled driver 848a, implemented as an NFET in this example, coupled in series to the first control signal node 822a, and the first control signal node 822a is connected to the drain of the first controlled load 846a and the drain of the first controlled driver 848a. The gate of the first controlled load 846a is connected to the PMOS bias terminal 844. The gate of the first controlled driver 848a is connected to the first control signal node 822a. The source of the first controlled load 846a is connected to the power terminal 818. A source of the first control driver 848a is connected to the ground terminal 828. Coupling the first control signal node 822a to the first current control node 816a through the first inverting control buffer 834a provides a first negative feedback path 836a that reduces fluctuations in the first head potential, labeled "VHEADa" in FIG. 8, at the first branch node 814a when the first feedback current IFBa changes due to variations in the feedback potential VFB.

[0079] The transconductor 802 of this example includes a second reference input stage 804b configured to receive a reference potential VREF from a reference input port 806, which is paired with a second feedback input stage 808b configured to receive a feedback potential VFB from a feedback input port 810. The second reference input stage 804b is connected to a second branch node 814b via a third resistor 862, labeled "R3" in FIG. 8. The second feedback input stage 808b is connected to the second branch node 814b via a fourth resistor 864, labeled "R4" in FIG. 8.

[0080] The transconductor 802 includes a second current limiting component 812b, which is coupled in series to the second reference input stage 804b and the second feedback input stage 808b in parallel current paths via a third resistor R3 862 and a fourth resistor R4 864, respectively, at a second branch node 814b, as shown in FIG. 8. In this example, the second current limiting component 812b may be implemented as an NFET with positive transconductance. The second current limiting component 812b has a second current control node 816b with a third control potential, labeled "VCTL1b" in FIG. 8, during operation of the transconductor 802. The second current limiting component 812b is coupled to a power terminal 818. Current flows from the power terminal 818 through the second current limiting component 812b and splits into a second reference current, labeled "IREFb" in FIG. 8, through the second reference input stage 804b, and a second feedback current, labeled "IFBb" in FIG. 8, through the second feedback input stage 808b.

[0081] The transconductor 802 includes a second feedback load 824b, which is connected to the second feedback input stage 808b via a second output signal node 826b. In this example, the second feedback load 824b may be implemented as an NMOS diode, as shown in Figure 8. At the second output signal node 826b, a second output signal potential, labeled "VSIGb" in Figure 8, is equal to the voltage drop across the second feedback load 824b due to the second feedback current IFBb.

[0082] The transconductor 802 includes a second reference load 820b, which is connected to the second reference input stage 804b via a second control signal node 822b. In this example, the second reference load 820b may be implemented as an NFET. The gate of the second reference load 820b may be connected to an NMOS bias terminal 838. At the second control signal node 822b, a fourth control potential, labeled "VCTL2b" in FIG. 8, is equal to the voltage drop across the second reference load 820b due to the second reference current IREFb.

[0083] The sources of the second reference load 820b and the second feedback load 824b are connected to the ground terminal 828. The second reference current IREFb and the second feedback current IFBb flow to the ground terminal 828.

[0084] The second control signal node 822b is coupled to the second current control node 816b of the second current limiting component 812b through a second inverting control buffer 834b as shown in FIG. 8, so that the third control potential VCTL1b has a negative correlation with the fourth control potential VCTL2b. In this example, the second inverting control buffer 834b includes a second controlled load 846b, implemented as a PFET in this example, and a second controlled driver 848b, implemented as an NFET in this example, coupled in series to the second control signal node 822b, and the second control signal node 822b is connected to the drain of the second controlled load 846b and the drain of the second controlled driver 848b. The gate of the second controlled load 846b is connected to the PMOS bias terminal 844. The gate of the second controlled driver 848b is connected to the second control signal node 822b. The source of the second controlled load 846b is connected to the power terminal 818. A source of the second control driver 848b is connected to the ground terminal 828. Coupling the second control signal node 822b to the second current control node 816b through a second inverting control buffer 834b provides a second negative feedback path 836b that reduces fluctuations in the second head potential, labeled "VHEADb" in FIG. 8, at the second branch node 814b when the second feedback current IFBb changes due to variations in the feedback potential VFB.

[0085] The transconductor 802 includes an output current terminal 830 that is coupled to a first output signal node 826a and a second output signal node 826b via an output buffer 832. The output buffer 832 converts a first output signal potential VSIGa at the first output signal node 826a and a second output signal potential VSIGb at the second output signal node 826b into an output current, labeled "IOUT" in FIG. 3, that flows through the output current terminal 830. In this example, the output buffer 832 includes a first output driver 842a, implemented in this example as a PFET, and a second output driver 842b, implemented in this example as an NFET, coupled in series between their drains. A source of the first output driver 842a is connected to the power terminal 818, and a source of the second output driver 842b is connected to the ground terminal 828. The first output signal node 826a is connected to the gate of the first output driver 842a, and the second output signal node 826b is connected to the second output driver 842b. The output current terminal 830 is connected to the drain of the first output driver 842a and the drain of the second output driver 842b. The output buffer 832 in this example provides bidirectional output functionality with non-complementary polarity for the output current IOUT. Resistors R1 858, R2 860, R3 862, and R4 864 may advantageously provide further linearity in the output current IOUT as a function of the difference between the feedback potential VFB and the reference potential VREF. The bidirectional output functionality may be appropriate for a network external to the semiconductor device 800 including the transconductor 802.

[0086] 9 is a circuit schematic diagram of another exemplary transconductor. The transconductor 902 includes a first reference input stage 904a configured to receive a reference potential, labeled "VREF" in FIG. 9, at a reference input port 906, and paired with a first feedback input stage 908a configured to receive a feedback potential, labeled "VFB" in FIG. 9, at a feedback input port 910. In this example, the first reference input stage 904a and the first feedback input stage 908a may be implemented as NFETs, as shown in FIG. 9. During operation of the transconductor 902, a first reference current, labeled "IREFa" in FIG. 9, flows through the first reference input stage 904a, and a first feedback current, labeled "IFBa" in FIG. 9, flows through the first feedback input stage 908a.

[0087] The transconductor 902 includes a first current limiting component 912a coupled in series at a first branch node 914a to a first reference input stage 904a and a first feedback input stage 908a in parallel current paths as shown in FIG. 9. In this example, the first current limiting component 912a may be implemented as a PFET having a negative transconductance. The first current limiting component 912a has a first current control node 916a having a first control potential, labeled "VCTL1a" in FIG. 9, during operation of the transconductor 902. A drain of the first current limiting component 912a is coupled to a ground terminal 928 configured to receive a current at a ground potential, labeled "VSS" in FIG. 9. The first reference current IREFa and the first feedback current IFBa are combined at the first branch node 914a and flow to the ground terminal 928 through the first current limiting component 912a.

[0088] The transconductor 902 includes a first reference load 920a, implemented in this example as a PFET, connected to the first reference input stage 904a via a first control signal node 922a. A gate of the first reference load 920a may be connected to a PMOS bias terminal 944.

[0089] The transconductor 902 includes a first feedback load 924a, implemented in this example as a PMOS diode. A drain of the first feedback load 924a is connected to the first feedback input stage 908a. A gate of the first feedback load 924a may be connected to a drain of the first feedback load 924a, such that the first feedback load 924a is implemented as a PMOS diode in this example. The first reference load 920a and a source of the first feedback load 924a are connected to a power terminal 918, which is configured to provide a current to the transconductor 902 at a positive power potential, labeled "VDD" in FIG. 9.

[0090] A current flows from the ground terminal 928 through the first current limiting component 912a and splits into a first reference current IREFa and a first feedback current IFBa at a first branch node 914a. The reference current IREFa flows through a first control signal node 922a and a first reference load 920a to a power terminal 918. At the first control signal node 922a, a second control potential, labeled "VCTL2a" in FIG. 9, is equal to the voltage drop across the first reference load 920a with respect to VDD due to the reference current IREFa. The feedback current IFBa flows through a first feedback load 924a to the power terminal 918.

[0091] The first control signal node 922a is coupled to the first current control node 916a of the first current limiting component 912a through a first inverting control buffer 934a as shown in FIG. 9, so that the first control potential VCTL1a has a negative correlation with the second control potential VCTL2a. In this example, the first inverting control buffer 934a includes a first controlled load 946a, implemented in this example as an NFET, and a first controlled driver 948a, implemented in this example as a PFET, coupled in series between the first current control node 916a and the drain, and the first current control node 916a is connected to the drain of the first controlled load 946a and the drain of the first controlled driver 948a. The gate of the first controlled load 946a is connected to the NMOS bias terminal 938. The gate of the first controlled driver 948a is connected to the first control signal node 922a. The source of the first controlled load 946a is connected to the ground terminal 928. A source of the first control driver 948a is connected to the power terminal 918. Coupling the first control signal node 922a to the first current control node 916a through the first inverting control buffer 934a provides a first negative feedback path 936a that reduces fluctuations in the first head potential, labeled "VHEADa" in FIG. 9, at the first branch node 914a when the first feedback current IFBa changes due to variations in the feedback potential VFB.

[0092] The transconductor 902 of this example includes a second reference input stage 904b configured to receive a reference potential VREF from a reference input port 906 and paired with a second feedback input stage 908b configured to receive a feedback potential VFB from a feedback input port 910. The second reference input stage 904b and the second feedback input stage 908b are connected to a second branch node 914b. The transconductor 902 includes a second current limiting component 912b coupled in series to the second reference input stage 904b and to the second feedback input stage 908b at the second branch node 914b. In this example, the second current limiting component 912b may be implemented as a PFET. The second current limiting component 912b has a second current control node 916b that has a third control potential, labeled "VCTL1b" in FIG.

[0093] The transconductor 902 of this example includes a current sensor 954 coupled in series with the first current limiting component 912a. In this example, the current sensor 954 is implemented as an NFET. The drain of the current sensor 954 is connected to the gate of the current sensor 954 and the drain of the first current limiting component 912a. The source of the current sensor 954 is connected to the ground terminal 928. Thus, the current sensor 954 of this example is configured as an NMOS diode. In this example, the gate of the current sensor 954 provides a second output signal node 926b having a second output signal potential, labeled "VSIGb" in FIG. 9, during operation of the transconductor 902. Also during operation of the transconductor 902, the second reference current IREFb and the second feedback current IFBb are combined at the second branch node 914b and flow through the first current limiting component 912a and the current sensor 954 to the ground terminal 928.

[0094] The transconductor 902 includes a second feedback load 924b, which is connected to the second feedback input stage 908b via a second control signal node 922b. In this example, the second feedback load 924b may be implemented as a PFET. The second feedback load 924b may be connected to the power terminal 918. The gate of the second feedback load 924b may be connected to the PMOS bias terminal 944. At the second control signal node 922b, a fourth control potential, labeled "VCTL2b" in FIG. 9, is equal to the voltage drop across the second feedback load 924b with respect to VDD due to the second reference current IREFb.

[0095] The transconductor 902 includes a second reference load 920b connected to the second reference input stage 904b. In this example, the second reference load 920b may be implemented as a PMOS diode. The sources of the second reference load 920b and the second feedback load 924b are connected to the power terminal 918.

[0096] The second control signal node 922b is coupled to the second current control node 916b of the second current limiting component 912b through a second inverting control buffer 934b as shown in FIG. 9, so that the third control potential VCTL1b has a negative correlation with the fourth control potential VCTL2b. In this example, the second inverting control buffer 934b includes a second controlled load 946b, implemented as an NFET in this example, and a second controlled driver 948b, implemented as a PFET in this example, coupled in series to the second current control node 916b, and the second current control node 916b is connected to the drain of the second controlled load 946b and the drain of the second controlled driver 948b. The gate of the second controlled load 946b is connected to the NMOS bias terminal 938. The gate of the second controlled driver 948b is connected to the second control signal node 922b. The source of the second controlled load 946b is connected to the ground terminal 928. A source of a second control driver 948b is connected to the power terminal 918. Coupling the second control signal node 922b to the second current control node 916b via a second inverting control buffer 934b provides a second negative feedback path 936b that reduces fluctuations in the second head potential, labeled "VHEADb" in FIG. 9, at the second branch node 914b when the second feedback current IFBb changes due to variations in the feedback potential VFB.

[0097] The transconductor 902 includes an output current terminal 930 that is coupled to a first output signal node 926a via a first output buffer 932a and to a second output signal node 926b via a second output buffer 932b. The first output buffer 932a and the second output buffer 932b in this example have the inverted configuration relative to each other.

[0098] The first output buffer 932a converts the first output signal potential VSIGa at the first output signal node 926a into a source output current portion flowing through the output current terminal 930. In this example, the first output buffer 932a includes two parallel current paths to provide an amplified transconductance. The first current path of the first output buffer 932a includes a first resistor 950a, labeled "R1" in FIG. 9, a first output load 940a, implemented in this example as an NFET, and a first output driver 942a, implemented in this example as a PFET, coupled in series. A first terminal of the first resistor 950a is connected to the ground terminal 928. A source of the first output load 940a is connected to the second terminal of the first resistor 950a. A source of the first output driver 942a is connected to the power terminal 918. A second current path of the first output buffer 932a includes a second resistor 950b, labeled "R2" in FIG. 9, a second output load 940b, implemented in this example as an NFET, and a second output driver 942b, implemented in this example as a PFET, coupled in series. A first terminal of the second resistor 950b is connected to the ground terminal 928. A source of the second output load 940b is connected to a second terminal of the second resistor 950b. A source of the second output driver 942b is connected to the power terminal 918. The gates of the first output load 940a and the second output load 940b are connected to the drain of the first output load 940a, such that the first output load 940a operates as an NMOS diode. The gates of the first output driver 942a and the second output driver 942b are connected to the first output signal node 926a. The first output buffer 932a includes a first output stage 952a, implemented in this example as an NFET. The source of the first output stage 952a is connected to the source of the first output load 940a. The gate of the first output stage 952a is connected to the drain of the second output driver 942b. The drain of the first output stage 952a is connected to the output current terminal 930. The first output buffer 932a amplifies the first output signal potential VSIGa at the first output signal node 926a by a factor approximately equal to the ratio of the resistance of the second resistor 950b to the resistance of the first resistor 950a.

[0099] The second output buffer 932b converts the second output signal potential VSIGb at the second output signal node 926b into a sinking output current portion flowing through the output current terminal 930. In this example, the second output buffer 932b includes two parallel current paths to provide an amplified transconductance. A first current path of the second output buffer 932b includes a third resistor 950c, labeled "R3" in FIG. 9, a third output load 940c, implemented in this example as a PFET, and a third output driver 942c, implemented in this example as an NFET, coupled in series. A first terminal of the third resistor 950c is connected to the power terminal 918. A source of the third output load 940c is connected to a second terminal of the third resistor 950c. A source of the third output driver 942c is connected to the ground terminal 928. A second current path of the second output buffer 932b includes a fourth resistor 950d, labeled "R4" in FIG. 9, a fourth output load 940d, implemented in this example as a PFET, and a fourth output driver 942d, implemented in this example as an NFET, coupled in series. A first terminal of the fourth resistor 950d is connected to the power terminal 918. A source of the fourth output load 940d is connected to a second terminal of the fourth resistor 950d. A source of the fourth output driver 942d is connected to the ground terminal 928. The gates of the third output load 940c and the fourth output load 940d are connected to the drain of the third output load 940c, such that the third output load 940c operates as a PMOS diode. The gates of the third output driver 942c and the fourth output driver 942d are connected to the second output signal node 926b. The second output buffer 932b includes a second output stage 952b, implemented in this example as a PFET. The source of the second output stage 952b is connected to the source of the third output load 940c. The gate of the second output stage 952b is connected to the drain of the fourth output driver 942d. The drain of the second output stage 952b is connected to the output current terminal 930. The second output buffer 932b amplifies the second output signal potential VSIGb at the second output signal node 926b by a factor approximately equal to the ratio of the resistance of the fourth resistor 950d to the resistance of the third resistor 950c.The first output buffer 932a and the second output buffer 932b in this example provide bidirectional output functionality with complementary polarities for the output current I. The bidirectional output functionality and complementary polarities may be appropriate for networks external to the semiconductor device 900 that includes the transconductor 902. Modifications in the described examples are possible and other examples are possible within the scope of the claims.

Claims

1. A transconductor comprising: a reference input stage configured to receive a reference potential, the reference input stage including a first transistor having a first current terminal, a second current terminal, and a control terminal; a feedback input stage configured to receive a feedback potential; a current limiting component configured to control a total current through the reference input stage and the feedback input stage, the current limiting component having a first current terminal, a second current terminal coupled to the second current terminal of the first transistor, and a control terminal; a reference load coupled in series with the reference input stage, the reference load including a second transistor having a first current terminal coupled to the first current terminal of the first transistor, a second current terminal, and a control terminal configured to be coupled to an external bias; a feedback load coupled in series with the feedback input stage, the feedback load including a third transistor having a first current terminal and a control terminal coupled to the feedback input stage and a second current terminal coupled to the second current terminal of the second transistor; an output buffer coupled to the feedback load and to an output current terminal, the output buffer configured to provide an output current to the output current terminal that is a function of a difference between the reference potential and the feedback potential; a negative feedback loop having a first terminal coupled to a first current terminal of the first transistor and a second terminal coupled to a control terminal of the current limiting component, the negative feedback loop being configured to compensate for a change in the total current due to a difference between the reference potential and the feedback potential, the difference between the reference potential and the feedback potential being the reference potential minus the feedback potential; a transconductor,

2. 2. The transconductor of claim 1, A transconductor, the transconductance of which increases as the absolute value of the difference between the reference potential and the feedback potential increases.

3. 2. The transconductor of claim 1, The transconductor, wherein the output buffer is further configured to provide an output current with a sink output functionality.

4. 2. The transconductor of claim 1, The transconductor, wherein the output buffer is further configured to provide an output current with sourced output functionality.

5. 2. The transconductor of claim 1, The transconductor, wherein the output buffer is further configured to provide an output current with bidirectional output functionality.

6. 2. The transconductor of claim 1, The transconductor is configured to provide complementary polarities of the output current, such that the output current decreases when the difference between the reference potential and the feedback potential increases and increases when the difference between the reference potential and the feedback potential decreases.

7. 2. The transconductor of claim 1, The transconductor is configured to provide non-complementary polarities of the output current, such that the output current increases when the difference between the reference potential and the feedback potential increases and increases when the difference between the reference potential and the feedback potential decreases.

8. 2. The transconductor of claim 1, The transconductor, wherein the current limiting component comprises an n-channel field effect transistor (NFET).

9. 2. The transconductor of claim 1, The current-limiting component includes a p-channel field-effect transistor (PFET).

10. 2. The transconductor of claim 1, The reference load comprises an NFET.

11. 2. The transconductor of claim 1, The transconductor, wherein the feedback load comprises an NFET.

12. 2. The transconductor of claim 1, The transconductor, wherein the negative feedback loop includes an inverting buffer.

13. 13. A transconductor according to claim 12, comprising: The transconductor, wherein the inverting buffer includes a controlled load and a controlled driver coupled in series to the controlled load.

14. 14. A transconductor according to claim 13, The control driver is connected to the reference load and the reference input stage.

15. 14. A transconductor according to claim 13, The current limiting component is coupled to the controlled load and the controlled driver.

16. 14. A transconductor according to claim 13, A transconductor wherein the control load is implemented as a PFET and the control driver is implemented as an NFET.

17. 2. The transconductor of claim 1, The transconductor further includes a current sensor coupled in series with the current limiting component.

18. 2. The transconductor of claim 1, a first resistor coupled in series between the current limiting component and the reference input stage; a second resistor coupled in series between the current limiting component and the feedback input stage; The transconductor further comprises:

19. 2. The transconductor of claim 1, The transconductor, wherein the output buffer includes an amplifier configured to provide an amplified transconductance.

20. 2. The transconductor of claim 1, the reference input stage is a first reference input stage, the feedback input stage is a first feedback input stage, the current limiting component is a first current limiting component, the reference load is a first reference load, the feedback load is a first feedback load, the output buffer is a first output buffer, the negative feedback loop is a first negative feedback loop, and the total current is a first total current; The transconductor a second reference input stage configured to receive the reference potential; a second feedback input stage configured to receive the feedback potential; a second current limiting component configured to control the total current through the second reference input stage and the second feedback input stage; a second reference load coupled in series with the second reference input stage; a second feedback load coupled in series with the second feedback input stage; a second output buffer coupled between the second feedback load and the current output current terminal; a second negative feedback loop from the second reference load to the second current limiting component, the second negative feedback loop configured to compensate for changes in total current through the second reference input stage and the second feedback input stage due to a difference between the reference potential and the feedback potential; The transconductor further comprises:

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