Ripple cancellation for switched-capacitor circuits.

Abstract

The system (105) includes a voltage rail (115), a switched capacitor circuit (110) coupled to the voltage rail, and a ripple cancellation circuit (310). The ripple cancellation circuit includes a current mirror (420) having a first branch (422, 430, 424) and a second branch (426, 435, 228), where the second branch of the current mirror is coupled to the voltage rail (314, 428), a switching circuit (414) having a first terminal (414), a second terminal (416), and a third terminal (418), where the first terminal (414) of the switching circuit is coupled to the first branch (424) of the current mirror and the third terminal (418) is coupled to ground or a reference voltage, and a first capacitor (440) coupled to the second terminal (416) of the switching circuit.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of nonprovisional patent application Ser. No. 17 / 457,840, filed with the U.S. Patent and Trademark Office on December 6, 2021, the entire contents of which are incorporated herein by reference as if set forth in their entirety below and for all applicable purposes. [Background technology]

[0002] Field Aspects of the present disclosure relate generally to switched capacitor circuits, and more specifically to ripple cancellation for switched capacitor circuits.

[0003] background Various types of circuits can be implemented using switched-capacitor circuits, including charge pumps, filters, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), discrete-time signal processors, etc. A switched-capacitor circuit includes one or more capacitors and switches configured to transfer charge to and from the one or more capacitors. The switches can be driven by one or more switching signals (e.g., clock signals). Summary of the Invention

[0004] SUMMARY OF THE DISCLOSURE The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This Summary is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005] A first aspect relates to a system including a voltage rail, a switched capacitor circuit coupled to the voltage rail, and a ripple cancellation circuit including a current mirror having a first branch and a second branch, the second branch of the current mirror being coupled to the voltage rail, a switching circuit having a first terminal, a second terminal, and a third terminal, the first terminal of the switching circuit being coupled to the first branch of the current mirror and the third terminal being coupled to ground or a reference voltage, and a first capacitor coupled to the second terminal of the switching circuit.

[0006] A second aspect relates to a method for reducing ripple on a voltage line coupled to a switched-capacitor circuit, the method including receiving a switching signal that drives one or more switches in the switched-capacitor circuit, generating current pulses in response to edges of the switching signal, and injecting the current pulses onto the voltage line. [Brief description of the drawings]

[0007] [Figure 1] 1 illustrates an example of a system including a switched-capacitor circuit in accordance with some aspects of the present disclosure. [Diagram 2] 1 illustrates an example of a low-dropout regulator in accordance with some aspects of the present disclosure. [Diagram 3]1 illustrates an example of a system including a ripple cancellation circuit in accordance with some aspects of the present disclosure. [Figure 4] 1 illustrates an example implementation of a ripple cancellation circuit in accordance with some aspects of the present disclosure. [Diagram 5] FIG. 2 is a timing diagram illustrating an example of ripple cancellation in accordance with some aspects of the present disclosure. [Figure 6] 1 illustrates an example implementation of a switching circuit according to some aspects of the present disclosure. [Figure 7] 1 illustrates an example implementation of a switch in a switching circuit according to some aspects of the present disclosure. [Figure 8] 1 illustrates an example of an inverter coupled to a switching circuit in accordance with some aspects of the present disclosure. [Figure 9] 1 illustrates an example implementation of a current mirror in accordance with some aspects of the present disclosure. [Figure 10] 1 illustrates an example of a system including a charge pump in accordance with some aspects of the present disclosure. [Figure 11] 1 illustrates an example implementation of a charge pump in accordance with some aspects of the present disclosure. [Figure 12] 1 illustrates an example of a feedback circuit for a charge pump in accordance with some aspects of the present disclosure. [Figure 13] 1 is a flowchart illustrating a method for reducing ripple in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The detailed description of the present invention, described below in connection with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0009] 1 illustrates one embodiment of a system 105 that includes a switched-capacitor circuit 110 and a voltage regulator 120. The switched-capacitor circuit 110 may implement any one of a variety of circuits including a charge pump, a switched-capacitor filter, a digital-to-analog converter (DAC) (e.g., a capacitive DAC), an analog-to-digital converter (ADC), a phase-locked loop (PLL), a discrete-time signal processor, a sample-and-hold circuit, a voltage converter, etc.

[0010] The switched capacitor circuit 110 includes one or more capacitors (not shown) and switches (not shown) configured to transfer charge to and from the one or more capacitors. The switches may be driven by one or more switching signals including a first switching signal (labeled "sw1") and a second switching signal (labeled "sw2"). The first switching signal sw1 may drive one or more of the switches in the switched capacitor circuit 110, and the second switching signal sw2 may drive another one or more of the switches in the switched capacitor circuit 110. It should be understood that additional switching signals may be used.

[0011] In some aspects, each of the switching signals sw1 and sw2 may include an oscillating signal (e.g., a clock signal) that oscillates between high (i.e., logic 1) and low (logic 0) at an oscillating frequency. In these aspects, the switching signals sw1 and sw2 may be out of phase with each other (e.g., based on a desired switching sequence for the switches in the switched capacitor circuit 110). For example, the switching signals sw1 and sw2 may be approximately 180° out of phase with each other. However, it should be appreciated that the present disclosure is not limited to this example. The switching signals sw1 and sw2 may have the same duty cycle or different duty cycles.

[0012] The voltage regulator 120 has an input 122 and an output 124. The input 122 is connected to a supply voltage V DD The output 124 is coupled to a supply rail 125 that provides a supply voltage V. The output 124 is coupled to the switched capacitor circuit 110 via a voltage line 115 (i.e., the voltage line 115 is coupled between the output 124 and the switched capacitor circuit 110). The voltage regulator 120 provides a supply voltage V DD to the regulated voltage V Reg and generates a regulated voltage V at output 124. Reg The voltage line 115 is configured to output a regulated voltage V Reg to the switched-capacitor circuit 110. The voltage regulator 120 may be implemented using a low-dropout (LDO) regulator or another type of voltage regulator. One example of an LDO regulator is described below with respect to FIG. 2. As used herein, a "voltage line" is a line (e.g., a metal line) used to supply a voltage to one or more circuits coupled to the voltage line, and may also be referred to as a voltage rail, a voltage path, a voltage supply rail, or other terminology.

[0013] A challenge with the switched capacitor circuit 110 is that it draws current pulses from the voltage line 115, thereby causing ripples on the voltage line 115. The ripples can couple to the supply rail 125 through the voltage regulator 120 (e.g., due to the limited bandwidth of the voltage regulator 120) and can degrade the performance of other circuits (e.g., analog and radio frequency circuits) coupled to the supply rail 125.

[0014] A current pulse (represented in FIG. 1 by current pulse 150) is caused by a charge transfer from the voltage line 115 to one or more capacitors in the switched capacitor circuit 110, triggered by switching in the switched capacitor circuit 110. For example, a current pulse may be triggered when a switch between the voltage line 115 and a capacitor in the switched capacitor circuit 110 is switched on, allowing charge to flow through the switch from the voltage line 115 to the capacitor. Because the switches in the switched capacitor circuit 110 are switched on and off by switching signals sw1 and sw2, each current pulse is triggered by one edge of the switching signals sw1 and sw2.

[0015] One approach to reduce the ripple on the voltage line 115 caused by the current pulse is to use a large load capacitor coupled to the voltage line 115. One example of this approach is shown in FIG. 2, which illustrates an exemplary implementation of the voltage regulator 120. In this example, the voltage regulator 120 is implemented using an LDO regulator including a pass transistor 230, an error amplifier 240, and a voltage divider 210. The pass transistor 230 is coupled between the input 122 and the output 124, and the voltage divider 210 is coupled between the output 124 and ground. In the example of FIG. 2, the pass transistor 230 is implemented using a p-type field effect transistor (PFET). However, it should be understood that the pass transistor 230 can also be implemented using an n-type field effect transistor (NFET).

[0016] 2, the voltage divider 210 includes a first resistor 220 and a second resistor 225 coupled in series between the output 124 and ground. The voltage divider 210 generates a feedback voltage V at a node 222 between the first resistor 220 and the second resistor 225. fb Generates a feedback voltage V fb has a voltage given by:

[0017]

number

[0018] The error amplifier 240 has a first input 242, a second input 244, and an output 246. The first input 242 is connected to a reference voltage V Ref The second input 244 is configured to receive a feedback voltage V fb , and output 246 is coupled to the gate of pass transistor 230 .

[0019] In operation, the error amplifier 240 receives a reference voltage V Ref and the feedback voltage V fb The gate voltage of the pass transistor 230 is adjusted in a direction to reduce the difference between the feedback voltage V fb is the reference voltage V Ref , resulting in a regulated voltage V Reg is approximately equal to

[0020]

number

[0021] In the embodiment of FIG. 2, voltage regulator 120 also includes a compensation capacitor C C and a load capacitor C coupled to the output 124 (and thus to the voltage line 115). L In this embodiment, the ripple on the voltage line 115 caused by a current pulse in the switched-capacitor circuit 110 is L However, the load capacitance C L Increasing the capacitance of the pass transistor 230 at the output 124 pushes the second pole of the voltage regulator 120 to a lower frequency, which adversely affects the stability of the voltage regulator 120. In this case, to stabilize the voltage regulator 120, the impedance of the pass transistor 230 at the output 124 can be reduced by increasing the quiescent current of the voltage regulator 120. The reduced impedance pushes the second pole back to a higher frequency. However, increasing the quiescent current of the voltage regulator 120 increases power consumption.

[0022] To address this, aspects of the disclosure provide a ripple cancellation circuit configured to inject a current pulse into the voltage line 115 to cancel the current pulse of the switched capacitor circuit 110, thereby reducing the ripple on the voltage line 115, as described further below.

[0023] 3 illustrates an example of a system 305 including a ripple cancellation circuit 310 in accordance with some aspects of the present disclosure. The system 305 also includes the switched capacitor circuit 110 and the voltage regulator 120 described above with reference to FIG.

[0024] The ripple cancellation circuit 310 has a control input 312, a supply input 316, and an output 314. The supply input 316 may be coupled to the supply rail 125 as shown in the embodiment of FIG. 3. The control input 312 is configured to receive one of the switching signals sw1 and sw2 or both of the switching signals sw1 and sw2. The output 314 is coupled to the voltage rail 115.

[0025] In some aspects, the ripple cancellation circuit 310 is configured to generate a current pulse and inject the generated current pulse (represented in FIG. 3 by current pulse 320) into the voltage line 115 via the output 314 to cancel the current pulse (represented in FIG. 3 by current pulse 150) of the switched capacitor circuit 110. The current pulse of the ripple cancellation circuit 310 can cancel all or a portion of the current pulse of the switched capacitor circuit 110 to reduce ripple on the voltage line 115.

[0026] As described above, the switching signals sw1 and sw2 control the switches in the switched capacitor circuit 110, so that the current pulses of the switched capacitor circuit 110 are triggered on one or more edges of the switching signals sw1 and sw2. In some aspects, the ripple cancellation circuit 310 is configured to time the injection of the current pulses into the voltage line 115 on one or more edges of the switching signals sw1 and sw2. This helps to ensure that the current pulses of the ripple cancellation circuit 310 are approximately time-aligned (i.e., synchronized) with the current pulses of the switched capacitor circuit 110 to cancel the current pulses of the switched capacitor circuit 110.

[0027] 4 illustrates an example implementation of a ripple cancellation circuit 310 according to some embodiments. In this example, the ripple cancellation circuit 310 includes a first capacitor 440, a switching circuit 410, a current mirror 420, a second capacitor 450, and a resistor 455.

[0028] The current mirror 420 has a first branch 430 and a second branch 435. The first branch 430 is between a first terminal 422 and a second terminal 424 of the current mirror 420. The second branch 435 is between a third terminal 426 and a fourth terminal 428 of the current mirror 420. The current mirror 420 is configured to mirror the current flowing through the first branch 430 to the second branch 435. In some aspects, the current mirror 420 can also scale the current flowing through the first branch by a scaling factor of N, as described further below.

[0029] The second capacitor 450 has a first terminal 452 coupled to the supply rail 125 via a resistor 455 and a second terminal 454 coupled to ground. The second capacitor 450 can receive charge from the supply rail 125 via the resistor 455 and store the charge. The stored charge can be used to provide charge for the current pulses generated by the ripple cancellation circuit 310, as described further below. The resistor 455 can be used to attenuate the ripple. In the embodiment of FIG. 4, the first terminal 422 and the third terminal 426 of the current mirror 420 are coupled to the first terminal 452 of the second capacitor 450, and the fourth terminal 428 of the current mirror 420 is coupled to the output 314 of the ripple cancellation circuit 310.

[0030] The switching circuit 410 has a control input 412 coupled to the control input 312 of the ripple cancellation circuit 310. The switching circuit 410 also has a first terminal 414, a second terminal 416, and a third terminal 418. The first terminal 414 is coupled to the second terminal 424 of the current mirror 420, and the third terminal 418 is coupled to ground. The first capacitor 440 can be coupled between the second terminal 416 and ground. More specifically, the first capacitor 440 has a first terminal 442 coupled to the second terminal 416 of the switching circuit 410 and a second terminal 444 coupled to ground. However, it should be understood that in some implementations, the second terminal 444 of the first capacitor 440 and the third terminal 418 of the switching circuit 410 can be coupled to a DC reference voltage.

[0031] In some aspects, the switching circuit 410 is configured to receive a switching signal (e.g., one of the switching signals sw1 and sw2) via a control input 412. The switching circuit 410 is configured to couple the second terminal 416 to the third terminal 418 when the switching signal has a first logic state, and to couple the second terminal 416 to the first terminal 414 when the switching signal has a second logic state. The first logic state may be 1 and the second logic state may be 0, or vice versa. In some aspects, a logic state of 1 is approximately equal to or lower than V DD or another voltage, and a logic state of 0 may correspond to approximately ground.

[0032] In this embodiment, the switching circuit 410 couples the first terminal 442 of the first capacitor 440 to ground when the switching signal has a first logic state. As a result, the first capacitor 440 is discharged through the switching circuit 410.

[0033] When the switching signal transitions from a first logic state to a second logic state on an edge of the switching signal, the switching circuit 410 couples the first terminal 442 of the first capacitor 440 to the first terminal 414 of the switching circuit 410. This allows charge to flow from the second capacitor 450 to the first capacitor 440 through the current mirror 420 and the switching circuit 410 to charge the first capacitor 440. Thus, the switching circuit 410 triggers the charging of the first capacitor 440 on an edge of the switching signal. The edge may be a falling edge for embodiments where the first logic state is 1 and the second logic state is 0, or a rising edge for embodiments where the first logic state is 0 and the second logic state is 1.

[0034] The charging of the first capacitor 440 produces a current pulse having a similar shape (i.e., profile) as the current pulse of the switched-capacitor circuit 110 corresponding to the same edge of the switching signal because the current pulse of the switched-capacitor circuit 110 is also produced by charging a capacitor.

[0035] The current pulse resulting from the charging of the first capacitor 440 flows through the first branch 430 of the current mirror 420, which mirrors (i.e., copies) the current pulse to the second branch 435 of the current mirror 420. The current mirror 420 may also scale the current pulse by a scaling factor N (i.e., the current pulse in the second branch 435 may be N times the current pulse in the first branch 430). The scaling factor may be greater than one.

[0036] The current pulse in the second branch 435 of the current mirror 420 is injected via the output 314 into the voltage line 115 (not shown in FIG. 4 ) and cancels the corresponding current pulse in the switched capacitor circuit 110. Because both current pulses are triggered by the same edge of the switch signal, the current pulse from the ripple cancellation circuit 310 is approximately time-aligned (i.e., synchronized) with the current pulse in the switched capacitor circuit 110.

[0037] Figure 5 illustrates an example of a current pulse 510 from the switched capacitor circuit 110 and a current pulse 520 from the ripple cancellation circuit 310. The current pulses 510 and 520 have opposite polarity in Figure 5 because the switched capacitor circuit 110 sinks the current pulse 510 from the voltage line 115 and the ripple cancellation circuit 310 injects the current pulse 520 into the voltage line 115. Also, because the current pulses 510 and 520 are triggered by the same edge of the switching signal, the current pulses 510 and 520 are approximately time aligned.

[0038] Figure 5 also shows a net current pulse 530 on the voltage line 115. In the embodiment of Figure 5, the current pulse 520 from the ripple cancellation circuit 310 cancels most of the current pulse 510 from the switched capacitor circuit 110, causing the net current pulse 530 on the voltage line 115 to be substantially smaller than the current pulse 510 from the switched capacitor circuit 110. As a result, the ripple on the voltage line 115 is substantially reduced.

[0039] In some aspects, the switching signal (e.g., one of the switching signals sw1 and sw2) input to the ripple cancellation circuit 310 is a clock signal. As used herein, a clock signal is a signal that oscillates between high (i.e., logic 1) and low (logic 0) at a clock frequency. In one embodiment, the ripple cancellation circuit 310 can generate a current pulse during each cycle (i.e., period) of the clock signal to inject the current pulse into the voltage line 115.

[0040] In some aspects, the system 305 may include multiple instances of the ripple cancellation circuit 310 coupled to the voltage line 115. In one embodiment, a different switching signal (e.g., a different one of the switching signals sw1 and sw2) may be input to each instance of the ripple cancellation circuit 310. In this embodiment, each instance of the ripple cancellation circuit 310 may be used to cancel a current pulse in the switched capacitor circuit 110 triggered by an edge of the respective switching signal.

[0041] 6 illustrates an example implementation of a switching circuit 410 according to some aspects of the disclosure. In this example, the switching circuit 410 includes a first switch 610 and a second switch 620. The first switch 610 is coupled between the first terminal 414 and the second terminal 416, and the second switch 620 is coupled between the second terminal 416 and the third terminal 418.

[0042] The first switch 610 has a control input 615 coupled to the control input 412 of the switching circuit 410, and the second switch 620 has a control input 625 coupled to the control input 412 of the switching circuit 410. As used herein, the "control input" of a switch controls the on / off state of the switch based on a signal (e.g., a voltage or logic state) at the control input.

[0043] In some aspects, the second switch 620 is configured to be on when the switching signal at the control input 625 has a first logic state and to be off when the switching signal at the control input 625 has a second logic state. As mentioned above, the first logic state may be 1 and the second logic state may be 0, or vice versa. Thus, in this example, the second switch 620 couples the first terminal 442 of the first capacitor 440 to ground to discharge the first capacitor 440 when the switching signal has the first logic state.

[0044] The first switch 610 is configured to be on when the switching signal at the control input 615 has a second logic state and to be off when the switching signal at the control input 615 has a first logic state. Thus, in this example, the first switch 610 couples the first terminal 442 of the first capacitor 440 to the first terminal 414 of the switching circuit 410 when the switching signal has the second logic state.

[0045] When the switching signal transitions from a first logic state to a second logic state on an edge of the switching signal, the first switch 610 is switched on. This allows charge to flow from the second capacitor 450 through the current mirror 420 and the first switch 610 to the first capacitor 440, charging the first capacitor 440. The charging of the first capacitor 440 generates a current pulse, which flows through the first branch 430 of the current mirror 420. The current mirror 420 mirrors (i.e., copies) the current pulse to the second branch 435, which outputs the current pulse at the output 314.

[0046] Thus, in this embodiment, a current pulse of the ripple cancellation circuit 310 is triggered by switching of the first switch 610 at an edge of a switching signal (e.g., one of the switching signals sw1 and sw2). The edge of the switching signal may be a falling edge for embodiments where the first logic state is 1 and the second logic state is 0, or a rising edge for embodiments where the first logic state is 0 and the second logic state is 1.

[0047] 7 illustrates an example implementation of a first switch 610 and a second switch 620 according to some embodiments. In this example, the first switch 610 includes a p-type field effect transistor (PFET) 710 coupled between the first terminal 414 and the second terminal 416. A control input 615 of the first switch 610 is located at a gate of the PFET 710. The second switch 620 includes an n-type field effect transistor (NFET) 720 coupled between the second terminal 416 and the third terminal 418. A control input 625 of the second switch 620 is located at a gate of the NFET 720.

[0048] In this embodiment, the second switch 620 is turned on when the switching signal at the control input 625 is 1 (e.g., approximately V DD) and off when the switching signal at the control input 625 is 0. The first switch 610 is configured to be on when the switching signal at the control input 615 is 0 and off when the switching signal at the control input 615 is 1 (e.g., approximately V DD ) when the power is turned off.

[0049] Thus, in this example, the first switch 610 is switched on when the switching signal (e.g., one of the switching signals sw1 and sw2) transitions from 1 to 0 on a falling edge of the switching signal. This allows charge to flow from the second capacitor 450 through the current mirror 420 and the first switch 610 to the first capacitor 440 to charge the first capacitor 440. The charging of the first capacitor 440 generates a current pulse, which flows through the first branch 430 of the current mirror 420. The current mirror 420 mirrors (i.e., copies) the current pulse to the second branch 435, which outputs the current pulse at the output 314.

[0050] Thus, in this embodiment, the current pulse of the ripple cancellation circuit 310 is triggered by the switching of the first switch 610 at the falling edge of the switching signal (e.g., one of the switching signals sw1 and sw2). To trigger the current pulse at the rising edge of the switching signal, an inverter 810 can be coupled between the control input 312 of the ripple cancellation circuit 310 and the control input 412 of the switching circuit 410, one embodiment of which is shown in FIG. 8. In this embodiment, the input 812 of the inverter is coupled to the control input 312 of the ripple cancellation circuit 310, and the output 814 of the inverter 810 is coupled to the control input 412 of the switching circuit 410. The inverter 810 is configured to invert the switching signal and output the inverted switching signal to the control input 412 of the switching circuit 410. This causes the first switch 610 in the embodiment shown in FIG. 8 to switch on and trigger the current pulse at the rising edge of the switching signal.

[0051] 9 illustrates an example implementation of a current mirror 420 according to some embodiments. In this example, the current mirror 420 includes a first transistor 910 and a second transistor 915. A source of the first transistor 910 is coupled to the first terminal 422, a drain of the first transistor 910 is coupled to the second terminal 424, and a gate of the first transistor 910 is coupled to the drain of the first transistor 910. The current of the first branch 430 flows through the channel of the first transistor 910. A source of the second transistor 915 is coupled to the third terminal 426, a drain of the second transistor 915 is coupled to the fourth terminal 428, and a gate of the second transistor 915 is coupled to the gate of the first transistor 910. The current of the second branch 435 flows through the channel of the second transistor 915. 9, each of the first transistor 910 and the second transistor 915 is implemented with a respective PFET, however, it should be understood that other types of transistors may be used.

[0052] In this embodiment, the gate of the second transistor 915 is coupled to the gate of the first transistor 910 so that the source-to-gate voltage of the second transistor 915 is approximately equal to the source-to-gate voltage of the first transistor 910. This causes the second transistor 915 to mirror the current flowing through the first transistor 910.

[0053] In some aspects, the current mirror 420 has a scaling factor N, and the current flowing through the first transistor 910 is scaled by the scaling factor N (i.e., the current flowing through the second transistor 915 is N times the current flowing through the first transistor 910). In these aspects, the second transistor 915 can be sized relative to the first transistor 910 to achieve the scaling factor N.

[0054] In this embodiment, the amount of charge that the ripple cancellation circuit 310 injects into the voltage line 115 during one current pulse is approximately given by:

[0055]

number

[0056] 10 illustrates an example embodiment in which a switched-capacitor circuit 110 includes a charge pump 1010, according to some aspects. The charge pump 1010 has an input 1012 coupled to a voltage line 115 and an output 1014. The charge pump 1010 converts the voltage at the input 1012 (e.g., V Reg ) to the lower or higher voltage V out For example, the charge pump 1010 can double or triple the voltage at the input 1012. In other words, the output voltage V out may be two or three times the voltage at the input 1012. In another embodiment, the charge pump 1010 can invert the voltage at the input 1012. In other words, the output voltage V out may be the negative of the voltage at the input 1012. In another embodiment, the charge pump 1010 can both double or triple the voltage at the input 1012 and invert the voltage at the input 1012 (e.g., V out =-2V Reg Or V out =-3V Reg It should be understood that the charge pump 1010 is not limited to the above embodiment.

[0057] 11 illustrates an example implementation of a charge pump 1010 in accordance with some aspects of the disclosure. In this example, the charge pump 1010 is configured to invert the voltage at the input 1012.

[0058] The charge pump 1010 includes a first switch 1110, a second switch 1115, a third switch 1120, a fourth switch 1125, a first capacitor 1150, and a second capacitor 1160. The first switch 1110 is coupled between the input 1012 and a first terminal 1152 of the first capacitor 1150. The second switch 1115 is coupled between ground and a second terminal 1154 of the first capacitor 1150.

[0059] The third switch 1120 is coupled between a first terminal 1152 of the first capacitor 1150 and ground. The fourth switch 1125 is coupled between a second terminal 1154 of the first capacitor 1150 and the output 1014. A first terminal 1162 of the second capacitor 1160 is coupled to the output 1014 and a second terminal 1164 of the second capacitor 1160 is coupled to ground.

[0060] The control input 1112 of the first switch 1110 and the control input 1118 of the second switch 1115 may be driven by a first switching signal sw1, and the control input 1122 of the third switch 1120 and the control input 1127 of the fourth switch 1125 may be driven by a second switching signal sw2. In this embodiment, the switching signals sw1 and sw2 can turn on the first switch 1110 and the second switch 1115 and turn off the third switch 1120 and the fourth switch 1125 during a first phase of the charge pump 1010. The switching signals sw1 and sw2 can turn off the first switch 1110 and the second switch 1115 and turn on the third switch 1120 and the fourth switch 1125 during a second phase of the charge pump 1010.

[0061] During the first phase, the first switch 1110 couples the first terminal 1152 of the first capacitor 1150 to the input 1012, and the second switch 1115 couples the second terminal 1154 of the first capacitor 1150 to ground. This couples the first capacitor 1150 to the voltage at the input 1012 (e.g., V Reg ) until the battery voltage is equal to

[0062] During the second phase, the third switch 1120 couples the first terminal 1152 of the first capacitor 1150 to ground, and the fourth switch 1125 couples the second terminal 1154 of the first capacitor 1150 to the output 1014. This inverts the voltage of the first capacitor 1150 at the output 1014. The first capacitor 1150 is coupled to the input voltage (e.g., V Reg), by reversing the voltage on the first capacitor 1150 during the second phase, a voltage approximately equal to the negative of the input voltage (e.g., −V Reg ) at the output 1014. The second capacitor 1160 helps to hold the negative voltage at the output 1014.

[0063] In this embodiment, the switching signals sw1 and sw2 may be periodic signals that cause the charge pump 1010 to cycle between the first and second phases.

[0064] In this embodiment, the charge pump 1010 draws a current pulse from the voltage line 115 when the first switch 1110 is switched on. This is because switching on the first switch 1110 allows charge to move from the voltage line 115 to the first capacitor 1150 to charge the first capacitor 1150. In this embodiment, the first switch 1110 is controlled by the first switching signal sw1, so that the current pulse is triggered on an edge of the first switching signal sw1. In this embodiment, the first switching signal sw1 can be input to a control input 312 of the ripple cancellation circuit 310, and the ripple cancellation circuit 310 can be configured to inject a current pulse into the voltage line 115 on an edge of the first switching signal sw1 to cancel the current pulse of the charge pump 1010. The edge of the first switch signal sw1 can be a rising edge or a falling edge (e.g., depending on whether the first switch signal sw1 is implemented with an NFET or a PFET).

[0065] It should be understood that the charge pump 1010 is not limited to the exemplary implementation shown in Figure 11. In one embodiment, the charge pump 1010 can be configured to double or triple the negative voltage at the output 1014 by adding one or more additional stages to the implementation shown in Figure 11, each stage including a switch and a capacitor. For example, the charge pump 1010 can be configured to provide a -2V Reg Output voltage V is approximately equal to out Or Vout =-3V Reg The method may be configured to generate:

[0066] In some embodiments, the output voltage V of the charge pump 1010 out can be adjusted using a feedback circuit. In this regard, FIG. 12 illustrates an embodiment of a feedback circuit 1208 including a first resistor R1, a second resistor R2, an amplifier 1220, and an oscillator 1210, according to some embodiments. The first resistor R1 is coupled between a node 1230 and a reference voltage Ref_cp, and the second resistor R2 is coupled between the node 1230 and an output 1014 of the charge pump 1010. The amplifier 1220 has a first input 1222 coupled to ground, a second input 1224 coupled to the node 1230, and an output 1226.

[0067] The oscillator 1210 has a control input 1212 coupled to an output 1226 of the amplifier 1220, a first output 1214, and a second output 1216. The oscillator 1210 is configured to generate a first switching signal sw1 and a second switching signal sw2 and to output the first switching signal sw1 at the first output 1214 and the second switching signal sw2 at the second output 1216. The first output 1214 and the second output 1216 are coupled to the charge pump 1010 to provide the switching signals sw1 and sw2 to the charge pump 1010. The first output 1214 and / or the second output 1216 may also be coupled to a control input 312 of the ripple cancellation circuit 310 to provide one or both of the switching signals sw1 and sw2 to the ripple cancellation circuit 310. The oscillator 1210 is also configured to adjust the frequency of the first switching signal sw1 and the second switching signal sw2 based on the signal at the output 1226 of the amplifier 1220.

[0068] In operation, the amplifier 1220 receives the voltage at node 1230 via the second input 1224 and adjusts the frequency of the first switching signal sw1 and the second switching signal sw2 in a direction that reduces the difference between the voltage at node 1230 and ground. In other words, the feedback loop of the feedback circuit 1208 forces the voltage at node 1230 to be approximately equal to 0 volts. This feedback causes the output voltage V out Let be approximately equal to

[0069]

number

[0070] FIG. 13 illustrates one example of a method 1300 for reducing ripple on a voltage line (eg, voltage line 115) coupled to a switched capacitor circuit (eg, switched capacitor circuit 110) in accordance with some aspects.

[0071] In block 1310, a switching signal is received, the switching signal driving one or more switches in the switched capacitor circuit. The switching signal may correspond to one of the switching signals sw1 and sw2. The switching signal may be received at the ripple cancellation circuit 310.

[0072] In block 1320, a current pulse is generated in response to an edge of the switching signal. For example, the current pulse may be generated by charging the first capacitor 440. The switching circuit 410 may charge the first capacitor 440 in response to an edge of the switching signal by coupling the second terminal 416 of the switching circuit 410 to the first terminal 414 of the switching circuit 410 on the edge of the switching signal. The edge may be a falling edge or a rising edge.

[0073] At block 1330, a current pulse is injected into the voltage line. For example, the current mirror 420 can inject the current pulse into the voltage line.

[0074] In some aspects, injecting the current pulse into the voltage rail can include passing the current pulse through a current mirror (e.g., current mirror 420) configured to mirror the current pulse into a second branch of the current mirror (e.g., first branch 430) and injecting the current pulse from the second branch of the current mirror (e.g., second branch 435) into the voltage rail. In some aspects, the current mirror is configured to scale the current pulse by a scaling factor of N, where N is greater than 1.

[0075] In some aspects, generating a current pulse includes opening a first switch (e.g., first switch 610), coupled between a first branch of the current mirror and a capacitor (e.g., first capacitor 440), when the switching signal has a first logic state, and closing the first switch when the switching signal has a second logic state, where the edge includes a transition from the first logic state to the second logic state. In an embodiment where the first logic state is 1 and the second logic state is 0, the edge is a falling edge. In an embodiment where the first logic state is 0 and the second logic state is 1, the edge is a rising edge.

[0076] In some aspects, the method 1300 may also include closing a second switch (e.g., the second switch 620), the second switch being coupled between the capacitor and ground or between the capacitor and a reference voltage, when the switching signal has a first logic state, and opening the second switch when the switching signal has a second logic state.

[0077] The following numbered clauses describe example implementations. 1. A system comprising: Voltage lines, a switched capacitor circuit coupled to the voltage line; A ripple cancellation circuit, a current mirror having a first branch and a second branch, the second branch of the current mirror being coupled to a voltage rail; a switching circuit having a first terminal, a second terminal, and a third terminal, the first terminal of the switching circuit being coupled to the first branch of the current mirror and the third terminal being coupled to ground or a reference voltage; a first capacitor coupled to the second terminal of the switching circuit; A ripple cancellation circuit comprising: Prepare the system. 2. One or more switches in the switched capacitor circuit are driven by a switching signal; the switching circuit having a control input configured to receive a switching signal; 2. A system as described in clause 1. 3. The switching circuit is coupling the second terminal of the switching circuit to the third terminal of the switching circuit when the switching signal has a first logic state; coupling the second terminal of the switching circuit to the first terminal of the switching circuit when the switching signal has a second logic state; It is configured as follows: 2. A system as described in clause 2. 4. The switching circuit is a first switch coupled between the second terminal of the switching circuit and the first terminal of the switching circuit, the first switch having a control input coupled to the control input of the switching circuit; a second switch coupled between the second terminal of the switching circuit and a third terminal of the switching circuit, the second switch having a control input coupled to the control input of the switching circuit; Equipped with 4. A system according to claim 2 or 3. 5. The system of claim 4, wherein the first switch comprises a p-type field effect transistor (PFET) and the second switch comprises an n-type field effect transistor (NFET). 6. The system of any one of clauses 1 to 5, wherein the first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor is coupled to the second terminal of the switching circuit, and the second terminal of the first capacitor is coupled to ground or a reference voltage. 7. The system of any one of clauses 1 to 6, wherein the ripple cancellation circuit further comprises a resistor coupled between the current mirror and the supply rail. 8. The system described in clause 7, wherein the ripple cancellation circuit further comprises a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor being coupled between the current mirror and the resistor, and the second terminal of the second capacitor being coupled to ground. 9. Current mirror is a first transistor having a source, a drain, and a gate, the source of the first transistor coupled to the resistor, the gate of the first transistor coupled to the drain of the first transistor, and the drain of the first transistor coupled to a first terminal of the switching circuit; a second transistor having a source, a drain, and a gate, the source of the second transistor being coupled to the resistor, the gate of the second transistor being coupled to the gate of the first transistor, and the drain of the second transistor being coupled to a voltage line; Equipped with 9. A system according to clause 7 or 8. 10. The system of any one of clauses 1 to 9, further comprising a voltage regulator having an input coupled to the supply rail and an output coupled to the voltage rail. 11. The system of claim 10, wherein the voltage regulator comprises a low dropout (LDO) regulator. 12. The system of any one of clauses 1 to 11, wherein the switched capacitor circuit comprises a charge pump. 13. The system of any one of clauses 1 to 11, wherein the switched capacitor circuit comprises at least one of a switched capacitor filter, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a phase-locked loop (PLL), a discrete time signal processor, a sample-and-hold circuit, or a voltage converter. 14. A method for reducing ripple on a voltage line coupled to a switched capacitor circuit, comprising: Receiving a switching signal to drive one or more switches in a switched capacitor circuit; generating current pulses in response to edges of a switching signal; injecting a current pulse into the voltage line; A method comprising: 15. The method of claim 14, wherein generating a current pulse includes charging a capacitor. 16. Injecting a current pulse into a voltage line passing the current pulse through a first branch of a current mirror configured to mirror the current pulse into a second branch of the current mirror; injecting a current pulse from a second branch of the current mirror into the voltage rail; Including, 16. The method according to clause 14 or 15. 17. The method of claim 16, wherein the current mirror is configured to scale the current pulse by a scaling factor of N, where N is greater than 1. 18. Generating a current pulse opening a first switch coupled between the first branch of the current mirror and the capacitor when the switching signal has a first logic state; closing the first switch when the switching signal has a second logic state; wherein the edge comprises a transition from a first logic state to a second logic state. 18. The method according to clause 16 or 17. 19. closing a second switch, the second switch being coupled between the capacitor and ground or between the capacitor and a reference voltage, when the switching signal has a first logic state; opening a second switch when the switching signal has a second logic state; 19. The method of claim 18, further comprising: 20. The method of any one of clauses 14 to 19, wherein the edge of the switching signal is a rising edge. 21. The method of any one of clauses 14 to 19, wherein the edge of the switching signal is a falling edge. 22. The method of any one of clauses 14 to 21, wherein the switched capacitor circuit comprises a charge pump. 23. The method of any one of clauses 14 to 21, wherein the switched capacitor circuit comprises at least one of a switched capacitor filter, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a phase-locked loop (PLL), a discrete time signal processor, a sample-and-hold circuit, or a voltage converter.

[0078] It should be understood that the transistors described herein may be physically implemented on a chip having multiple transistors coupled in parallel.

[0079] Any reference herein to an element using a designation such as "first," "second," etc. generally does not limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements, or instances of an element. Thus, a reference to a first and a second element does not imply that only two elements may be employed, or that the first element must precede the second element.

[0080] Within the scope of this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. When used herein with respect to a stated value or characteristic, the term "approximately" is intended to indicate within 10% of the stated value or characteristic (i.e., within 90%-110% of the stated value or characteristic).

[0081] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. 1. A system comprising: Voltage lines and a switched capacitor circuit coupled to the voltage line; A ripple cancellation circuit, a current mirror having a first branch and a second branch, the second branch of the current mirror being coupled to the voltage rail; a switching circuit having a first terminal, a second terminal, and a third terminal, the first terminal of the switching circuit being coupled to the first branch of the current mirror and the third terminal being coupled to ground or a reference voltage; a first capacitor coupled to the second terminal of the switching circuit, the first capacitor having a first terminal and a second terminal, the first terminal of the first capacitor coupled to the second terminal of the switching circuit, and the second terminal of the first capacitor coupled to the ground or the reference voltage; a ripple cancellation circuit comprising: A system comprising:

2. one or more switches in the switched capacitor circuit are driven by a switching signal; the switching circuit having a control input configured to receive the switching signal; The system of claim 1 .

3. The switching circuit coupling the second terminal of the switching circuit to the third terminal of the switching circuit when the switching signal has a first logic state; coupling the second terminal of the switching circuit to the first terminal of the switching circuit when the switching signal has a second logic state; It is configured as follows: The system of claim 2 .

4. The switching circuit a first switch coupled between the second terminal of the switching circuit and the first terminal of the switching circuit, the first switch having a control input coupled to the control input of the switching circuit; a second switch coupled between the second terminal of the switching circuit and the third terminal of the switching circuit, the second switch having a control input coupled to the control input of the switching circuit; Equipped with The system of claim 2 .

5. 5. The system of claim 4, wherein the first switch comprises a p-type field effect transistor (PFET) and the second switch comprises an n-type field effect transistor (NFET).

6. The system of claim 1 , wherein the ripple cancellation circuit further comprises a resistor coupled between the current mirror and a supply rail.

7. 7. The system of claim 6, wherein the ripple cancellation circuit further comprises a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor coupled between the current mirror and the resistor, and the second terminal of the second capacitor coupled to the ground.

8. The current mirror a first transistor having a source, a drain, and a gate, the source of the first transistor coupled to the resistor, the gate of the first transistor coupled to the drain of the first transistor, and the drain of the first transistor coupled to the first terminal of the switching circuit; a second transistor having a source, a drain, and a gate, the source of the second transistor coupled to the resistor, the gate of the second transistor coupled to the gate of the first transistor, and the drain of the second transistor coupled to the voltage line; Equipped with The system of claim 6.

9. 10. The system of claim 1, further comprising a voltage regulator having an input coupled to a supply rail and an output coupled to the voltage rail.

10. 10. The system of claim 9, wherein the voltage regulator comprises a low dropout (LDO) regulator.

11. The system of claim 1 , wherein the switched capacitor circuit comprises a charge pump.

12. 10. The system of claim 1, wherein the switched capacitor circuit comprises at least one of a switched capacitor filter, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a phase-locked loop (PLL), a discrete-time signal processor, a sample-and-hold circuit, or a voltage converter.

13. A method for reducing ripple on the voltage line coupled to the switched capacitor circuit, performed by the system of claim 1, comprising: receiving a switching signal, the switching signal driving one or more switches in the switched capacitor circuit; the ripple cancellation circuit generates a current pulse in response to an edge of the switching signal; the ripple cancellation circuit injecting the current pulse into the voltage line; A method comprising:

14. The method of claim 13 , wherein generating the current pulse comprises charging the first capacitor.

15. injecting the current pulse into the voltage line; passing the current pulse through the first branch of the current mirror, the current mirror configured to mirror the current pulse through a second branch of the current mirror; injecting the current pulse from the second branch of the current mirror into the voltage rail; Including, The method of claim 13.

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