Hierarchical asymmetric core attribute detection

Abstract

Within a processing system, thread count asymmetry manifests when one or more cores of a processing device are disabled. To determine such thread count asymmetry, a discovery operation is performed to determine thread count asymmetry for one or more hierarchical levels of a processing device based on a number of threads per enumerated instance within the hierarchical level. In response to determining the thread count asymmetry, one thread identifier per enumerated instance within the asymmetry hierarchical level is defined to determine a representation of the asymmetry. Software tasks associated with one or more applications within the processing system are performed using the representation of the asymmetry.

Description

[Background technology]

[0001] Within a processing system, an operating system uses processor topology information of one or more processors to implement software tasks associated with an application. For example, the operating system uses the processor topology information to implement certain processor resource management operations, such as scheduling tasks and threads of software tasks associated with an application. The processor topology information of a processor identifies a hierarchical arrangement of hardware and software resources within the processing system that are used to implement the software tasks of an application. However, core attribute asymmetries within a processing system may cause the operating system to inefficiently or inaccurately manage the hardware and software resources of the processors, which may adversely affect the processing efficiency and processing time of the application. In addition, such asymmetries may cause the operating system to use additional memory and processing resources when compensating for the asymmetry.

[0002] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief description of the drawings]

[0003] [Figure 1] FIG. 1 illustrates a block diagram of a processing system for hierarchical asymmetric core attribute detection, according to some embodiments. [Diagram 2] 1 is a block diagram of a processing device configured to determine one or more core attribute asymmetries at one or more hierarchical levels, according to some embodiments. [Diagram 3] FIG. 1 is a flow diagram illustrating a method for determining thread count asymmetry at one or more hierarchical levels, according to some embodiments. [Figure 4] 1 is a flow diagram illustrating a method for determining power efficiency asymmetry at one or more hierarchical levels according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] The techniques and systems described herein address determining thread count asymmetries within a topology of a processing device and reporting the asymmetries identified by a relatively small number of thread identifiers (e.g., by a single thread identifier for a given enumerated instance of a processing device), thereby facilitating efficient reporting of the asymmetries and enabling more efficient asymmetry management, such as more efficient scheduling of threads executing on the processing devices.

[0005] For purposes of explanation, as used herein, the "topology" of a processing device includes the arrangement of the hardware and software resources of the processing device into one or more hierarchical levels. As used herein, a "hierarchical level" includes one or more portions of a processing device that include similar hardware or software resources (also referred to herein as "enumerated instances") of the processing device. For example, a processing device includes a die hierarchical level that includes one or more dies. As another example, a processing device includes a core complex hierarchical level that includes one or more core complexes. Each level is "hierarchical" in that a hierarchical level that includes a larger portion of the processing device (e.g., die level) is a "higher" level than a hierarchical level that includes a smaller portion of the processing device (e.g., core complex level, core level). An enumerated instance of a hierarchical level includes one or more hardware or software resources from other (e.g., lower) hierarchical levels. For example, a die at the die level includes one or more core complexes from the core complex level.

[0006] In some embodiments, the processing device is configured to determine thread count asymmetries for one or more hierarchical levels of the processor based on the number of threads per enumerated instance of the hierarchical level (i.e., how many threads each enumerated instance has in the hierarchical level). If one or more cores of a processing device in a processing system are downcored (e.g., disabled), thread count asymmetries may appear in one or more hierarchical levels of the processing device between the enumerated instances of the hierarchical level. That is, the number of threads per enumerated instance in the hierarchical level is different as a result of the downcored core. To provide a representation of these thread count asymmetries to an operating system that manages one or more applications running or about to run on the processing device, an operating system of the processing system performs discovery operations to determine whether there are thread count asymmetries at any hierarchical level of the processing device. Based on the discovery operations, the operating system determines whether there are one or more thread count asymmetries for each hierarchical level of the processing device. That is, the operating system determines whether each hierarchical level is symmetric or asymmetric with respect to thread count.

[0007] In response to determining the thread count asymmetry for a hierarchical level, the operating system defines one thread identifier for each enumeration instance of the hierarchical level to determine the expression of the asymmetry. To define the thread identifier, the operating system only reads one thread identifier from a register for each enumeration instance. Because each thread identifier includes several threads for that enumeration instance, only one thread identifier needs to be read from each enumeration instance to determine the expression of the thread count asymmetry. In this manner, the operating system does not need to read all thread identifiers for a hierarchical level, reducing the processing time and resources required to determine the expression of the asymmetry.

[0008] The techniques and systems described herein address determining power efficiency asymmetry for one or more hierarchical levels of a processing device based on the number of cores per enumeration instance operating in respective operating modes, e.g., power efficiency mode and performance mode. Power efficiency asymmetry may manifest itself at one or more hierarchical levels of a processing device between enumeration instances of the hierarchical levels when the number of cores of the processing device operating in a power efficiency mode differs from the number of cores operating in a performance mode. The processing device determines such power efficiency asymmetry at one or more hierarchical levels of a processing device by, for example, comparing the number of cores operating in a first or second operating mode per enumeration instance of the hierarchical level. To provide a representation of these power efficiency asymmetries to applications running or about to run on the processing device, an operating system of the processing system performs discovery operations to determine whether there is a power efficiency asymmetry at any hierarchical level of the processing device. For example, the operating system provides instructions to the processing device that cause the processing device to store data indicative of the power efficiency asymmetry at the respective hierarchical levels in one or more registers. The operating system then reads the data in the registers to determine whether there is a power efficiency asymmetry for one or more hierarchical levels.

[0009] FIG. 1 is a block diagram of a processing system 100 for asymmetric core attribute detection, according to some embodiments. The processing system 100 includes or has access to a memory 106 or other storage components implemented using a non-transitory computer-readable storage medium, for example, dynamic random-access memory (DRAM). However, in embodiments, the memory 106 is implemented using other types of memory, including static random-access memory (SRAM), non-volatile RAM, and the like. According to embodiments, the memory 106 includes an external memory to be implemented outside of a processing unit implemented in the processing system 100. The processing system 100 also includes a bus 112 to support communication between entities implemented in the processing system 100, such as the memory 106. Some embodiments of the processing system 100 include other buses, bridges, switches, routers, and the like, which are not shown in FIG. 1 for clarity.

[0010] The techniques described herein may be utilized in various embodiments with any of a variety of parallel processors (e.g., vector processors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), non-scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multi-threaded processing units, etc.), scalar processors, serial processors, or any combination thereof. FIG. 1 illustrates an example of a parallel processor, specifically a graphics processing unit (GPU) 114, according to some embodiments. GPU 114 renders images for presentation on display 120. For example, GPU 114 renders objects to generate pixel values ​​that are provided to display 120, which uses the pixel values ​​to display images representing the rendered objects. GPU 114 implements multiple processor cores 116-1 to 116-N that execute instructions simultaneously or in parallel. According to embodiments, one or more processor cores 116 operate as SIMD units that perform the same operations on different data sets. 1, three cores (116-1, 116-2, 116-N) are presented representing N cores, however, the number of processor cores 116 implemented within the GPU 114 is a matter of design choice. Thus, in other embodiments, the GPU 114 may include any number of cores 116. Some embodiments of the GPU 114 are used for general purpose computing. The GPU 114 executes instructions, such as program code 108, stored in the memory 106, and the GPU 114 stores information, such as results of executed instructions, in the memory 106.

[0011] Processing system 100 also includes a central processing unit (CPU) 102 connected to bus 112 and thus in communication with GPU 114 and memory 106 via bus 112. CPU 102 implements multiple processor cores 104-1 to 104-N that execute instructions simultaneously or in parallel. In an embodiment, one or more of processor cores 104 operate as SIMD units that perform the same operation on different data sets. In the exemplary embodiment shown in FIG. 1, three cores (104-1, 104-2, 104-M) are presented that represent M cores, however, the number of processor cores 104 implemented within CPU 102 is a matter of design choice. Thus, in other embodiments, CPU 102 can include any number of cores 104. In some embodiments, CPU 102 and GPU 114 have equal numbers of cores 104, 116, while in other embodiments, CPU 102 and GPU 114 have different numbers of cores 104, 116. Processor core 104 executes instructions, such as program code 110, stored in memory 106, and CPU 102 stores information, such as results of executed instructions, in memory 106. CPU 102 may also initiate graphics operations by issuing draw calls to GPU 114. In an embodiment, CPU 102 implements multiple processor cores (not shown in FIG. 1 for clarity) that independently execute instructions simultaneously or in parallel.

[0012] An input / output (I / O) engine 118 includes hardware and software that handles input or output operations associated with the display 120 and other elements of the processing system 100, such as a keyboard, a mouse, a printer, an external disk, etc. The I / O engine 118 is coupled to the bus 112 such that the I / O engine 118 is in communication with the memory 106, the GPU 114, or the CPU 102. In the illustrated embodiment, the I / O engine 118 reads information stored on an external storage component 122, which is implemented using a non-transitory computer-readable storage medium, such as a compact disk (CD), a digital video disc (DVD), or the like. The I / O engine 118 can also write information, such as results of processing by the GPU 114 or the CPU 102, to the external storage component 122.

[0013] In an embodiment, memory 106 includes one or more operating systems 124, each including software configured to manage hardware and software resources of system 100. Operating systems 124 interact with hardware and software resources of system 100 to allow one or more applications (not shown for clarity) to access the hardware and software resources of system 100. For example, operating systems 124 may execute one or more system calls on behalf of one or more applications, interrupt one or more applications, perform one or more hardware functions (e.g., memory allocation, input, output) for one or more applications, or any combination thereof, to name a few. In an embodiment, operating systems 124 are configured to perform one or more discovery operations to determine one or more hardware and software resources of system 100. Such hardware and software resources may include, for example, processing devices (e.g., CPU 102, GPU 114), device hierarchies, processing cores (e.g., cores 104, 116), threads, sockets, dies, complexes, or any combination thereof, to name a few. According to an embodiment, operating system 124 is further configured to perform one or more discovery operations to determine one or more hardware and software resource attributes of hardware and software resources of system 100. Such attributes may include, for example, the amount of a resource (e.g., thread count), the operating mode of the resource (e.g., active, inactive, power efficient mode, performance mode), the power efficiency of the resource, or any combination thereof, to name a few. In an embodiment, one or more hardware and software resources of system 100 include one or more hierarchical levels. For example, one or more portions of a processing device may be arranged in one or more hierarchical levels.In an embodiment, a hierarchical level includes one or more similar enumerated instances (i.e., similar portions) of a device, such as a core, a core complex, a die, and a socket, to name a few. As an example, a processing device (e.g., CPU 102, GPU 114) includes four or more hierarchical levels, including a core level, a core complex level, a die level, and a socket level, to name a few. In an embodiment, each enumerated instance of a hierarchical level includes any or portions of a device from a different hierarchical level, such as a lower hierarchical level. As an example, a die level includes one or more core complexes, each including one or more cores. According to an embodiment, the discovery operation includes instructions for the processing device to store data in one or more memory registers representing one or more hardware and software resources, hardware and software resource attributes, hierarchical levels, or any combination thereof.

[0014] According to an embodiment, the operating system 124 performs one or more discovery operations to determine one or more asymmetries for one or more hierarchical levels of hardware resources of the system 100. "Asymmetry," as used herein, includes one or more enumerated instances (e.g., cores, core complexes, dies) within a hierarchical level having one or more different hardware attributes (e.g., operating mode, thread count). For example, at a core complex level including two core complexes, the asymmetry includes a different thread count (i.e., amount of threads) between the two core complexes. As another example, at a die level including two dies, the asymmetry includes a first number of cores operating in a power-efficient mode in the first die and a second, different number of cores operating in a power-efficient mode in the second die. In an embodiment, the discovery operation includes instructions that cause the processing device to load data representing the one or more asymmetries and the one or more hierarchical levels into one or more registers. The operating system then determines the one or more asymmetries for the one or more hierarchical levels by reading at least a portion of the data stored in the registers.

[0015] In response to determining one or more asymmetries, operating system 124 is configured to define a thread identifier for each enumerated instance (e.g., each discrete portion) of a hierarchical level. For example, in response to determining one or more asymmetries at a core complex level, operating system 124 is configured to send instructions to a processing device to store data representing a thread identifier for each thread in a hierarchical level. A "thread identifier," as used herein, includes data indicative of, for example, a unique key that identifies a thread, an enumerated instance at each level of the hierarchy that includes the thread, the number of threads in each enumerated instance that includes the thread, or any combination thereof. For example, each thread identifier indicates the number of other threads in the enumerated instance. In an embodiment, operating system 124 sends instructions to a processing device to generate and store a thread identifier for each thread in a hierarchical level based on one or more shift values ​​stored in one or more registers. For example, the operating system 124 sends instructions to the processing device to store in a first register data representing a unique key (e.g., an APIC ID) identifying each thread and to store in a second register a value indicating a bit shift that, when applied to the unique key identifying the thread, returns a unique key identifying a higher level topology, e.g., a core, a core complex, a die, a socket, or any combination thereof. According to an embodiment, the operating system 124 is configured to read only one thread identifier per enumerated instance of a hierarchical level to determine a representation of asymmetry at the hierarchical level. For example, based on the shift value, the operating system determines one thread identifier per enumerated instance in the register to read. In this manner, the operating system 124 determines a representation of asymmetry (e.g., how the asymmetry affects the threads) without having to read thread attributes for each thread at the hierarchical level, reducing the processing time required to determine the representation of asymmetry.That is, because each thread identifier indicates the number of threads per enumeration instance, operating system 124 need only retrieve one thread identifier per enumeration instance, reducing the processing time required to determine the representation of the asymmetry. According to an embodiment, operating system 124 then enables one or more applications to access at least a portion of the hardware of system 100 based on the representation of the asymmetry. For example, operating system 124 enables access to one or more threads of system 100 based on the representation of the asymmetry. As an example, operating system 124 schedules software tasks for the applications based on the thread count indicated in the representation of the asymmetry.

[0016] 2, a block diagram of a processing device 200 having one or more hardware hierarchical levels and one or more asymmetries is shown. In an embodiment, the processing device 200 implements aspects of the processing system 100 as described in FIG. 1. For example, the processing device 200 may be similar to or the same as the CPU 102, the GPU 114, or both as described in FIG. 1. In an embodiment, the processing device 200 includes a first hierarchical level including one or more cores 234, e.g., each similar to or the same as the cores 104, 116. For example, in the exemplary embodiment shown in FIG. 2, the processing device 200 includes a first hierarchical level (e.g., a core level) including cores 0 234-1 through cores 15 234-16. In the illustrative embodiment of FIG. 2, the first hierarchical level of processing device 200 is presented as having 16 cores (234-1, 234-2, 234-3, 234-4, 234-5, 234-6, 234-7, 234-8, 234-9, 234-10, 234-11, 234-12, 234-13, 234-14, and 234-15), although in other embodiments, the first hierarchical level of processing device 200 may have any number of cores, such as, for example, 4, 8, 32, 64, 128 or 256 cores, to name a few.

[0017] According to an embodiment, the processing device 200 includes a second hierarchical level (e.g., a core complex level) including, for example, one or more core complexes (CCX). A "core complex," as used herein, includes one or more pairs of cores 234 and one or more caches (not shown for clarity). In an embodiment, the cores 234 in a CCX are connected to each other by one or more caches. That is, the cores 234 in a CCX share one or more caches of the CCX. For example, in the exemplary embodiment of FIG. 2, the processing device 200 includes a second hierarchical level (e.g., a CCX level) including CCX0 232-1 (including cores 234-1 through 234-4), CCX1 232-2 (including cores 234-5 through 234-8), CCX2 (including cores 234-9 through 234-12), and CCX3 232-4 (including cores 234-13 through 234-16). In the illustrative embodiment of FIG. 2, the second hierarchical level of processing device 200 is presented as having four CCXs, each having four cores, although in other embodiments, the second hierarchical level of processing device 200 may include any number of CCXs, each having any respective number of cores.

[0018] According to an embodiment, the processing device 200 includes a third hierarchical level (e.g., die level) including, for example, one or more dies (e.g., core complex die (CCD)). Each die or CCD 230 includes circuitry including one or more CCXs 232, each including one or more cores 234. For example, in the exemplary embodiment of FIG. 2, the processing device 200 includes a third hierarchical level (e.g., CCD level or die level) including CCD0 230-1 (including CCX0 232-1 and CCX1 232-2) and CCD1 230-2 (including CCX2 232-3 and CCX3 232-4). Although in the exemplary embodiment of FIG. 2, the third hierarchical level of the processing device 200 is presented as having two CCDs, each having two CCXs, in other embodiments, the third hierarchical level of the processing device 200 can include any number of CCDs, each having any respective number of CCXs. In an embodiment, one or more CCXs 232 in a CCD 230 are connected to each other by one or more caches, a data fabric, or any combination thereof. For example, in CCD0 23-1, CCX0 232-1 and CCX1 232-2 are connected by a data fabric.

[0019] In an embodiment, the processing device 200 includes a fourth hierarchical level (e.g., socket level) including, for example, one or more sockets. A "socket," as used herein, includes an interface, for example, one or more pins, between the processing device 200 and one or more other circuits (e.g., a motherboard). According to an embodiment, a socket includes one or more CCDs 230 connected to each other by one or more caches, a data fabric, or any combination thereof. For example, in the exemplary embodiment of FIG. 2, the processing device 200 includes a fourth hierarchical level (e.g., socket level) including a socket (not shown for clarity) including CCD0 230-1 and CCD1 230-2 connected by a data fabric (not shown for clarity). Although in the exemplary embodiment of FIG. 2, the fourth hierarchical level of the processing device 200 is presented as having one socket including two CCDs, in other embodiments, the fourth hierarchical level of the processing device 200 can include any number of sockets, each including any number of CCDs.

[0020] According to an embodiment, the processing device 200 is configured to downcore one or more cores 234 of the processing device 200. “Downcore,” as used herein, includes disabling one or more cores 234, e.g., by fuse disabling, software disabling, or both, to generate a disabled core. According to an embodiment, in response to downcore of one or more cores 234, thread count asymmetries (i.e., different thread counts between enumeration instances of a hierarchical level) in one or more hierarchies of the processing device 200 may appear. For example, by downcore of one or more cores 234, one or more enumeration instances (e.g., core, CCX, CCD) of one or more hierarchical levels (e.g., core level, CCX level, CDD level, socket level) may have a different thread count than another enumeration instance at the same hierarchical level. One skilled in the art will appreciate that as the number of cores in an enumeration instance being downcored increases, the number of threads in that enumeration instance decreases. As an example, in the exemplary embodiment of FIG. 2, in response to down-coring core 2 234-3 and core 3 234-4, CCX0 232-1 will have a different number of threads than CCX1 232-2. In other words, there is a thread count asymmetry at the CCX hierarchy level because there are different numbers of threads per CCX. As another example, in the exemplary embodiment of FIG. 2, in response to down-coring core 4 234-5, core 12 234-13, core 13 234-14, and core 14 234-15, there is a thread count asymmetry at the CCD level because there are different numbers of threads per CCD, and there is a thread count asymmetry at the CCX level because there are different numbers of threads per CCX.

[0021] In an embodiment, the processing device 200 is configured to change the operating mode of one or more cores 234, for example, between a power efficiency mode and a performance mode. A "power efficiency mode," as used herein, includes one or more instructions for a core 234 to operate such that power consumption is minimized by the core (i.e., power efficiency is maximized), and a "performance mode," as used herein, includes one or more instructions for a core 234 to operate such that computing performance is maximized for the core. In some embodiments, one or more cores are designed to operate only in a power efficiency mode or a performance mode. In response to changing one or more cores from a power efficiency mode to a performance mode, from a performance mode to a power efficiency mode, or both, power efficiency asymmetries at one or more hierarchical levels may appear. Additionally, in response to a processing device including a first number of cores designed to operate only in a power efficiency mode and a second number of cores designed to operate only in a performance mode, power efficiency asymmetries at one or more hierarchical levels may appear. For example, a power efficiency asymmetry for a hierarchical level may manifest in response to the number of cores in a performance mode in an enumeration instance (e.g., Core, CCX, CCD) differing from the number of cores in a performance mode in another enumeration instance at the same hierarchical level. Similarly, a power efficiency asymmetry for a hierarchical level may manifest in response to the number of cores in a power efficiency mode in an enumeration instance (e.g., Core, CCX, CCD) differing from the number of cores in a power efficiency mode in another enumeration instance at the same hierarchical level. As an example, a power efficiency asymmetry may manifest for the CCX hierarchical level because CCX0 and CCX1 have asymmetric power efficiency in response to CCX0 232-1 having four cores (234-1 to 234-4) in power efficiency mode and CCX1 232-2 having four cores (234-5 to 234-8) in performance mode.

[0022] In an embodiment, the processing device 200 is configured to determine one or more hardware and software resources, hardware and software resource attributes, asymmetries (e.g., thread count asymmetries, power efficiency asymmetries), or any combination thereof, for one or more hierarchical levels of the processing device 200. For example, the processing device 200 uses microcode to determine one or more thread counts, thread count asymmetries, power efficiency asymmetries, or any combination thereof. According to an embodiment, the processing device 200 is configured to determine one or more hardware and software resources, hardware and software resource attributes, asymmetries, or any combination thereof, during boot-up of the processing device 200. As an example, at boot-up, the processing device 200 is configured to determine the number of threads for each enumerated instance (e.g., core, CCX, CCD) in the processing device 200. As another example, processing device 200 is configured to execute one or more instructions, microcode, or any combination thereof to determine one or more thread count asymmetries at a hierarchical level by comparing the number of threads per enumeration instance (e.g., core, CCX, CCD, socket) to determine whether the number of threads per enumeration instance differs within the hierarchical level, i.e., whether one or more enumeration instances at a hierarchical level have a different number of threads than one or more other enumeration instances at that hierarchical level. In another example, processing device 200 is configured to use microcode to determine one or more power efficiency asymmetries at one or more hierarchical levels at startup.According to an embodiment, the processing device 200 is configured to store one or more of the determined hardware and software resources, hardware and software resource attributes, asymmetries, or any combination thereof, in memory including, for example, CMOS memory, flash memory, programmable read-only memory (PROM), electronically erasable PROM (EEPROM), RAM, cache, or any combination thereof, to name a few.

[0023] According to an embodiment, the processing device 200 includes or is connected to a memory 206 similar or identical to the memory 106. In an embodiment, the memory 206 includes one or more operating systems 224 similar or identical to the operating system 124 and one or more registers 226-1 to 226-N. In the embodiment shown in FIG. 2, three registers (226-1, 226-2, 226-N) representing N registers are presented, but in other embodiments, the memory 206 may include any number of registers. According to an embodiment, the one or more operating systems 224 each include one or more kernels 236 configured to interface or interact with the processing device 200. For example, the operating system 224 includes a kernel 236 configured to interact with the processing device 200 on behalf of one or more applications.

[0024] In an embodiment, the operating system 224 is configured to perform one or more discovery operations 228, e.g., a CPUID operation, a read model-specific register (RDMSR) operation, a read operation of a table stored in the memory 206, or any combination thereof, to determine one or more hardware resources, hardware attributes, asymmetries, or any combination thereof, of the processing device 200. In an embodiment, the one or more discovery operations 228 include one or more leaves of the discovery operation, e.g., one or more CPUID leaves. According to an embodiment, the one or more discovery operations 228 include instructions for the processing device 200 to store data indicative of the requested hardware and software resources, hardware and software resource attributes, asymmetries (e.g., thread count asymmetries, power efficiency asymmetries), or any combination thereof, in one or more bits of the register 226. For example, the discovery operation 228 includes instructions for the processing device 200 to generate, store, or both, data indicative of thread count asymmetries for a hierarchical level. In an embodiment, the hardware and software resources, hardware and software resource attributes, asymmetries, or any combination thereof, required in the discovery operation 228 are determined by data stored in one or more bits of the register 226. That is, the data stored in one or more bits of the register 226 causes the processing device 200 to determine which hardware and software resources, hardware and software resource attributes, asymmetries, or any combination thereof, to identify by storing the data in the register 226. For example, based on one or more bits in the first register 226-2, the discovery operation 228 includes instructions for the processing device 200 to store data in the second register 226-1 representing the power efficiency asymmetry of the hierarchical level. According to an embodiment, the one or more registers 226 store one or more shift values, e.g., one or more bit shift values.Based on the shift value stored in the register 226, the discovery operation 228 includes one or more instructions for the processing device 200 to store one or more thread identifiers 238 for each enumerated instance of the hierarchical level in one or more bits of the register 226 based on the shift value. For example, the shift value indicates the bits of the register 226 in which the processing device 200 stores the thread identifiers 238. As an example, based on a shift value indicating a bit shift value of 4 stored in the first register 226-1, the discovery operation 228 includes one or more instructions for the processing device to store one or more thread identifiers 238 (e.g., APIC IDs) in the second register 226-2. The stored thread identifiers 238 can be shifted by 16 bits to provide a unique key for a higher level topology, such as a core, a core complex, a die, or a socket.

[0025] In an embodiment, operating system 224 is configured to determine one or more hardware resources, hardware attributes, asymmetries, or any combination thereof, of processing device 200 by reading data from one or more bits stored in register 226. For example, operating system 224 determines one or more hardware and software resource attributes of processing device 200 by reading data in one or more bits of register 226-1 stored by processing device 200 during discovery operation 228. According to an embodiment, operating system 224 provides one or more determined hardware and software resources, hardware and software resource attributes, asymmetries, or any combination thereof, to one or more applications as the applications execute on at least a portion of processing device 200. For example, operating system 224 schedules software tasks for the applications using one or more hardware and software resources of processing device 200.

[0026] According to an embodiment, the operating system 224 is configured to determine a representation of the thread count asymmetry at each hierarchical level of the processing device 200 in response to determining one or more thread count asymmetries at one or more hierarchical levels of the processing device 200. The representation of the thread count asymmetry includes, for example, a number of threads per enumerated instance at the hierarchical level. Determining the representation of the thread count asymmetry for each hierarchical level includes, for example, reading data from one or more registers 226 indicative of a thread identifier 238 identifying a number of threads per enumerated instance at each hierarchical level. As an example, thread identifiers 238 indicative of a number of threads per CCX at the CCX hierarchical level and a number of threads per CCD at the CCD hierarchical level are read from the one or more registers 226. To determine the representation of the asymmetry, the operating system 224 is configured to read only data indicative of one thread identifier 238 per enumerated instance at the hierarchical level from the registers 226. For example, for the CCX hierarchical level, the operating system 224 only reads data indicative of one thread identifier 238 per CCX from the registers 226. According to an embodiment, the operating system 224 is configured to read data representing one thread identifier 238 for each enumeration instance in a hierarchical level from the registers 226 based on a shift value stored in one or more registers 226. For example, based on a shift value indicating a bit shift of four (e.g., a logical bit right shift operation having a value of four resulting in a thread identifier that is an even multiple of 16), the operating system 224 determines that the first thread identifier 238 for each enumeration instance is stored in a shifted location within each thread's unique key (e.g., a shifted location within the APICID). That is, the first thread identifier 238 for each enumeration instance is found in the thread's unique key (e.g., APICID) 0, 16, 32, 48, etc. in the registers 226.In this manner, operating system 224 reads from register 226 only data representative of one thread identifier 238 for each enumerated instance in a hierarchy level, rather than all thread identifiers 238 for that hierarchy level. Thus, the processing time and memory resources required to determine the asymmetry representation are reduced. In an embodiment, operating system 224 uses the asymmetry representation to provide one or more applications with access to hardware and software resources of processing device 200, whereby the applications perform one or more operations, calculations, or instructions using one or more hardware resources of processing device 200. For example, operating system 224 schedules software tasks for the applications based on the thread counts indicated in the asymmetry representation.

[0027] 3, a flow diagram of an exemplary method 300 for determining thread count asymmetry at one or more hierarchical levels is shown. At step 305, the processing device downcores one or more cores of the processing device similar or the same as the processing device 200 to generate disabled cores. For example, the one or more cores of the processing device are fuse disabled, software disabled, or both. At step 310, the processing device determines one or more thread count asymmetries at one or more hierarchical levels of the processing device. For example, at startup, the processing device determines that the thread count of each of one or more of the enumerated instances (e.g., core, CCX, CCD) at the device at the hierarchical level (e.g., core level, CCX level, CCD level, socket level) is different from the thread count of each of one or more of the other enumerated instances at the hierarchical level. That is, the processing device determines that one or more of the enumerated instances at the hierarchical level have a different number of threads than one or more other enumerated instances at the hierarchical level. In an embodiment, the processing device uses microcode to determine the number of threads per enumerated instance at the hierarchical level and compare the number of threads per enumerated instance to determine one or more thread count asymmetries. Additionally, at step 310, the processing device determines, for each thread at each hierarchical level, a thread identifier similar or the same as thread identifier 238. According to an embodiment, the processing device stores the determined asymmetry and thread count in memory including, for example, CMOS memory, flash memory, PROM, EEPROM, RAM, cache, or any combination thereof, to name a few.

[0028] At step 315, one or more operating systems similar to or the same as operating system 224 perform one or more discovery operations similar to or the same as discovery operation 228. In an embodiment, the discovery operations each include instructions for the processing device to generate, store, or both requested data in one or more registers similar to or the same as register 226. For example, the discovery operations include instructions for the processing device to load (i.e., report) data representing any determined asymmetry, thread count, and thread identifier into one or more bits of a register. For example, the discovery operations include instructions for the processing device to load a respective bit of each hierarchical level indicating the presence or absence of thread count asymmetry at the respective hierarchical level (i.e., a bit indicating whether the respective hierarchical level is symmetric or asymmetric with respect to thread count). In an embodiment, the discovery operations include instructions for storing data in one or more registers according to one or more values ​​stored in the registers, such as a shift value stored in the registers. As an example, the discovery operation includes instructions for the processing device to store thread identifiers (e.g., APICIDs) for each hierarchical level in a first register based on a shift value stored in a second register indicating a bit shift of four (e.g., a logical bit right shift operation having a value of four resulting in a thread identifier that is an even multiple of 16). Based on the bit shift of four, the processing device indicates that the first thread identifier for each enumerated instance of the hierarchical level is in the thread identifier of the first register (e.g., APICIDs 0, 16, 32, 48, etc.). At step 320, the operating system determines whether one or more thread count asymmetries for one or more hierarchical levels of the processing device have been reported (i.e., loaded) by the processing device into the register. That is, it determines whether each hierarchical level is symmetric or asymmetric with respect to thread count. For example, the operating system reads one or more bits in the operating system to determine whether one or more asymmetries have been reported by the processing device.In response to determining that no asymmetries exist at any hierarchical levels of the processing device (i.e., the hierarchical levels are symmetric with respect to thread count), the system proceeds to step 325 and ends the discovery operation. In response to determining that one or more asymmetries have been reported for one or more hierarchical levels, the system proceeds to step 330.

[0029] In response to determining one or more asymmetries for one or more hierarchical levels at step 330, the operating system defines one thread identifier for each enumeration instance (e.g., core, CCX, CCD) at the hierarchical level for which the asymmetry was reported. For example, in response to determining the asymmetry at the CCD hierarchical level, the operating system determines one thread identifier for all CCXs at the CCD hierarchical level. In an embodiment, the operating system is configured to determine the thread identifier by reading one or more bits indicative of the thread identifier stored in the register. According to an embodiment, the operating system is configured to define the thread identifier by reading only the bits indicative of the first thread identifier for each enumeration instance of the hierarchical level stored in the register. The operating system determines the location of the first thread identifier for each enumeration instance based on one or more shift values ​​stored in the register. As an example, based on a bit shift of 4 (e.g., a logical bit right shift operation having a value of 4 resulting in a thread identifier that is an even multiple of 16), the operating system determines that the first thread identifier for each enumeration instance of the hierarchical level is at thread identifier (e.g., APICID) 0, 16, 32, 48, etc. in the register. After determining the location of the first thread identifier for each enumeration instance in the register, the operating system reads only the first thread identifier for each enumeration instance to determine a representation of the asymmetry (e.g., a thread count per enumeration instance). Because the first thread identifier for each enumeration indicates the number of threads in the respective enumeration instance, the operating system determines the thread count for each enumeration instance of a hierarchical level without reading all thread identifiers of the hierarchical level. Thus, the processing time and memory resources for determining the thread count for each enumeration instance are reduced.

[0030] In step 335, the operating system determines an expression of the asymmetry (e.g., the number of threads per hierarchical level or the number of threads per enumeration instance) and provides the one or more applications with access to one or more hardware and software resources of the processing device based on the expression of the asymmetry. For example, the operating system schedules one or more tasks for the one or more applications based on the thread count indicated in the expression of the asymmetry. The applications are configured to execute or perform one or more operations using the hardware and software resources of the processing device based on the expression of the asymmetry. For example, the applications perform one or more operations using one or more threads of the processing device as scheduled by the operating system.

[0031] 4, a flow diagram of an example method 400 for determining power efficiency asymmetries at one or more hierarchical levels is shown. At step 405, a processing device similar or identical to processing device 200 powers up, waits a period of time after powering up, changes the operating mode of one or more cores of the processing device, or any combination thereof. For example, the processing device changes one or more cores operating in a power efficiency mode to a performance mode, or changes one or more cores operating in a performance mode to a power efficiency mode, or does both. As another example, the processing device powers up with a first number of cores operating in a power efficiency mode and a second, different number of cores operating in a performance mode. At step 410, the processing device determines one or more power efficiency asymmetries at one or more hierarchical levels of the processing device. For example, at power up, the processing device determines that the number of cores having a first operating mode (e.g., performance mode, power efficiency mode, density mode) in an enumerated instance (e.g., core, CCX, CCD) of a hierarchical level is different from the number of cores having the same operating mode in a different enumerated instance of the hierarchical level. That is, the processing device determines that one or more enumerated instances of a hierarchical level have a different number of cores in a first operating mode (e.g., a performance mode, a power efficiency mode, a density mode) than one or more other enumerated instances of that hierarchical level.

[0032] At step 415, one or more operating systems similar to or the same as operating system 224 perform one or more discovery operations similar to or the same as discovery operation 228. In an embodiment, the discovery operations each include instructions for the processing device to generate, store, or both requested data in one or more registers similar to or the same as register 226. For example, the discovery operations include instructions for the processing device to load (i.e., report) data representative of any determined power efficiency asymmetry into one or more bits of a register. For example, the discovery operations include instructions for the processing device to load a respective bit of each hierarchical level indicating the presence or absence of power efficiency asymmetry at the respective hierarchical level (i.e., whether the respective hierarchical level is symmetric or asymmetric with respect to power efficiency). At step 420, the operating system determines whether one or more power efficiency asymmetries for one or more hierarchical levels of the processing device have been reported (i.e., loaded) into a register by the processing device. For example, the operating system reads one or more bits in the operating system to determine whether one or more power efficiency asymmetries have been reported by the processing device. In response to determining that no power efficiency asymmetry exists at any hierarchical level of the processing device (i.e., all hierarchical levels are symmetric with respect to power efficiency), the system proceeds to step 425 and terminates the discovery operation. In response to determining that one or more power efficiency asymmetries have been reported for one or more hierarchical levels, the system proceeds to step 430.

[0033] In response to determining one or more power efficiency asymmetries for one or more hierarchical levels at step 430, the operating system determines a representation of the asymmetry. For example, the operating system determines an operating mode of one or more cores in the asymmetric hierarchical level. According to an embodiment, the operating system provides access to one or more hardware and software resources of the processing device based on the one or more determined representations of the power efficiency asymmetry. For example, the operating system schedules one or more software tasks of one or more applications based on the one or more operating modes for each core indicated in the representation of the power efficiency asymmetry. In an embodiment, the application is configured to execute or perform one or more operations using the hardware of the processing device based on the representation of the power efficiency asymmetry. For example, the application performs one or more operations using one or more cores of the processing device in a first mode (e.g., a power efficiency mode) and one or more cores of the processing device in a second mode (a performance mode) based on the needs of the application.

[0034] As disclosed herein, in some embodiments, a method includes, in response to determining a thread count asymmetry at a hierarchical level of a processing device, defining a thread identifier for each enumerated instance at the hierarchical level to generate a representation of the asymmetry at the hierarchical level, and scheduling one or more tasks based on the representation of the asymmetry at the hierarchical level. In one aspect, the method includes determining a second thread count asymmetry at a second hierarchical level of the processing device, the second hierarchical level including one or more dies that include the enumerated instance at the hierarchical level, and defining only one thread identifier for each die in the second hierarchical level of the processing device. In another aspect, only one thread identifier for each enumerated instance in the hierarchical level of the processing device is defined to generate a representation of the asymmetry at the hierarchical level.

[0035] In one aspect, the method includes determining thread count symmetry at a second hierarchical level of the processing device. In another aspect, the method includes accessing a first portion of a register configured to store a thread identifier associated with a first enumerated instance of the hierarchical level and a second portion of a register configured to store a thread identifier associated with a second enumerated instance of the hierarchical level. In yet another aspect, the thread identifier for each enumerated instance is based on a shift value stored in the register. In yet another aspect, the method includes disabling a first core of the processing device to generate a disabled core, the thread count asymmetry being based on the disabled core. In another aspect, the disabled core is fuse disabled. In yet another aspect, the disabled core is software disabled.

[0036] In some embodiments, a system includes a memory and a processing device including one or more processing cores, the processing cores configured to determine a thread count asymmetry at a hierarchical level of the processing device and to perform a task of the application based on the thread count asymmetry. In one aspect, the one or more processing cores are further configured to determine a thread count for each enumerated instance of the hierarchical level. In another aspect, the one or more processing cores are further configured to determine a thread count symmetry at a second hierarchical level of the processing device. In yet another aspect, the one or more processing cores are further configured to determine a thread identifier for each enumerated instance of the hierarchical level based on bits stored in a register.

[0037] In one aspect, the one or more processing cores are further configured to disable processing cores of the processing device to generate disabled cores, and the thread count asymmetry is based on the disabled cores. In another aspect, the hierarchical level comprises a die level of the processing device. In yet another aspect, the hierarchical level comprises a core complex level of the processing device.

[0038] In some embodiments, the system includes a memory and a processing device including one or more processing cores configured to determine a power efficiency asymmetry at a hierarchical level of the processing device based on a number of cores operating in an operational mode at the hierarchical level, and to perform a task of the application based on the power efficiency asymmetry at the hierarchical level of the processing device. In another aspect, the one or more processing cores are further configured to change the processing cores of the processing device from their operational mode to a second operational mode. In yet another aspect, the one or more processing cores are further configured to determine the power efficiency asymmetry at a hierarchical level of the processing device based on a number of cores operating in a second operational mode at the hierarchical level. In another aspect, the operational mode includes a power efficiency mode, and the second operational mode includes a performance mode.

[0039] In some embodiments, the apparatus and techniques described above are implemented in a system including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the systems described above with reference to FIGS. 1-4. Electronic design automation (EDA) and computer aided design (CAD) software tools can be used in the design and manufacture of these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs include code executable by a computer system for operating the computer system to operate on code representing the circuits of one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system for manufacturing the circuits. This code may include instructions, data, or a combination of instructions and data. The software instructions representing the design tool or manufacturing tool are typically stored in a computer readable storage medium accessible to the computing system. Similarly, code representing one or more stages of the design or manufacture of the IC device is stored in and accessed from the same computer readable storage medium or a different computer readable storage medium.

[0040] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS) based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0041] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied in a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by the one or more processors, operate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as a flash memory, a cache, a random access memory (RAM), or other non-volatile memory device(s), etc. The executable instructions stored in the non-transitory computer-readable storage medium may be implemented as source code, assembly language code, object code, or other form of instructions that can be interpreted or otherwise executed by one or more processors.

[0042] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, some of the specific activities or devices may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Thus, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0043] The preposition "or" used in the context of "at least one of A, B, or C" is used herein to mean "inclusive or." That is, in the above and similar contexts, "or" is used to mean "at least one of, or any combination thereof." For example, "at least one of A, B, and C" is used to mean "at least one of A, B, C, or any combination thereof."

[0044] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and features by which any benefit, advantage, or solution may occur or be manifested are not to be construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, as the disclosed invention may be modified and practiced in different but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as set forth in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. 1. A method comprising: In response to determining asymmetry in thread counts at a hierarchical level of a processing device, defining a thread identifier for each enumerated instance at the hierarchical level to generate a representation of the asymmetry at the hierarchical level; scheduling one or more tasks based on a representation of asymmetry at said hierarchical level; method.

2. determining a second thread count asymmetry at a second hierarchical level of the processing device, the second hierarchical level including one or more dies including enumerated instances at the hierarchical level; defining only one thread identifier for each die in a second hierarchical level of the processing device; 10. The method of claim 1.

3. only one thread identifier per enumerated instance within a hierarchical level of the processing device is defined to generate a representation of asymmetry at that hierarchical level; 10. The method of claim 1.

4. The method of claim 1 , further comprising determining thread count symmetry at a second hierarchical level of the processing device.

5. accessing a first portion of a register configured to store a thread identifier associated with a first enumerated instance of the hierarchical level and a second portion of the register configured to store a thread identifier associated with a second enumerated instance of the hierarchical level; 10. The method of claim 1.

6. the thread identifier for each enumeration instance is based on a shift value stored in a register; 10. The method of claim 1.

7. disabling a first core of the processing device to create a disabled core; the thread count asymmetry is based on the disabled cores.

10. The method of claim 1.

8. the disabled core is fuse disabled; The method of claim 7.

9. the disabled core is software disabled; The method of claim 7.

10. 1. A system comprising: Memory and a processing device including one or more processing cores; The processing core determining thread count asymmetry at a hierarchical level of the processing device; performing a task of the application based on the thread count asymmetry; and configured to: system.

11. the one or more processing cores configured to determine a thread count for each enumerated instance of the hierarchical level. The system of claim 10.

12. the one or more processing cores and configured to determine thread count symmetry at a second hierarchical level of the processing device. The system of claim 10.

13. the one or more processing cores configured to determine a thread identifier for each enumerated instance of the hierarchical level based on the bits stored in the register; The system of claim 10.

14. the one or more processing cores configured to disable processing cores of the processing device to generate disabled cores; the thread count asymmetry is based on the disabled cores. The system of claim 10.

15. the hierarchical level includes a die level of the processing device; The system of claim 10.

16. The hierarchical level includes a core complex level of the processing device. The system of claim 10.

17. A system comprising: Memory and a processing device including one or more processing cores; The processing core determining a power efficiency asymmetry at a hierarchical level of the processing device based on the number of cores operating in an operating mode at the hierarchical level; Implementing a task of the application based on the asymmetry of power efficiency at the hierarchical level of the processing device; configured to: system.

18. The one or more processing cores: configured to change a processing core of the processing device from the operating mode to a second operating mode.

18. The system of claim 17.

19. The one or more processing cores: configured to determine a power efficiency asymmetry at a hierarchical level of the processing device based on the number of cores operating in the second operating mode at the hierarchical level; 20. The system of claim 18.

20. The method of claim 1, wherein the operating mode comprises a power efficiency mode and the second operating mode comprises a performance mode.

20. The system of claim 18.

Images