HYBRID MEMORY SYSTEM HAVING INCREASED BANDWIDTH - Patent application

Abstract

A hybrid memory system having improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth over the JEDEC Low Power Double Data Rate Version 5 (LPDDR5) standard. The improvement is made possible by increasing the number of data conductors from 16 to 24. Optionally, the bandwidth can be further improved by increasing the clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complexity of simply doubling the pin count or doubling the clock speed. Additionally, coding techniques are provided for pin count and pin layout.

Description

[Technical field]

[0001] Priority claim This application claims priority to U.S. Provisional Patent Application No. 63 / 284,439, entitled "HYBRID MEMORY SYSTEM WITH INCREASED BANDWIDTH," filed November 30, 2021, the entire contents of which are incorporated herein by reference.

[0002] This application also claims priority to U.S. patent application Ser. No. 17 / 658,846, entitled "HYBRID MEMORY SYSTEM WITH INCREASED BANDWIDTH," filed April 12, 2022, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] I. Field of Disclosure The technology of this disclosure relates generally to memory systems, and more particularly to memory systems operating in the Joint Electron Device Engineering Council (JEDEC) Low Power Double Data Rate (LPDDR) specification space.

[0004] II. Background Computing devices are abundant in modern society, and more particularly, mobile communication devices are becoming more and more common. The proliferation of these mobile communication devices is driven in part by the many functions now enabled on such devices. Increased processing power within such devices means that mobile communication devices have evolved from pure communication tools to advanced mobile entertainment centers, thereby enabling an enhanced user experience. Applications and data for these myriad functions are typically stored in memory within the mobile communication device. With the advent of the myriad functions available to such devices, there has been increasing pressure to find ways to reduce power consumption. Memory elements within mobile communication devices are under pressure to reduce power consumption, but also face the requirement to be competitively priced and have reasonably low latency through sufficient bandwidth. Finding a good balance between these competing factors, particularly bandwidth demands, provides an opportunity for innovation. Summary of the Invention

[0005] Aspects disclosed in the detailed description include a hybrid memory system having improved bandwidth. In particular, a memory system is provided that increases bandwidth over the JEDEC Low Power Double Data Rate Version 5 (LPDDR5) standard. The improvement is made possible by increasing the number of data conductors from 16 to 24. Optionally, the bandwidth can be further improved by increasing the clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complexity of simply doubling the pin count or doubling the clock speed. Additionally, coding techniques are provided for pin count and pin layout.

[0006] In this regard, in one aspect, an integrated circuit (IC) is disclosed. The IC comprises a memory bus interface including 32 pins. 24 pins correspond to data conductors, 4 pins correspond to clock conductors, and 4 pins correspond to read strobe clock (RDQS) conductors. The IC also comprises routing and encoding logic associated with the memory bus interface and configured to route signals to pins within the memory bus interface.

[0007] In another aspect, a computing device is disclosed. The computing device includes a host. The host includes a physical layer (PHY) including 32 pins. 24 pins correspond to data conductors, 4 pins correspond to clock conductors, and 4 pins correspond to RDQS conductors. The host also includes routing and encoding logic associated with the PHY and configured to route signals to pins in a memory bus interface. The computing device also includes a memory bus. The memory bus includes 24 data conductors, two differential clock channels, and two differential RDQS channels. The computing device also includes a memory module. The memory module includes an input / output (IO) block including 32 pins that correspond to the conductors of the memory bus.

[0008] In another aspect, an IC is disclosed. The IC comprises a memory bus interface. The memory bus interface includes a plurality of data pins corresponding to the data conductors. The memory bus interface also includes a plurality of clock pins corresponding to the clock conductors. The IC also comprises routing and encoding logic associated with the memory bus interface and configured to encode bytes onto a plurality of data conductors associated with the plurality of data pins. [Brief description of the drawings]

[0009] [Figure 1A] 1 is a block diagram of an exemplary memory system using a memory bus in accordance with an exemplary aspect of the present disclosure. [Figure 1B] FIG. 2 is a block diagram of an exemplary memory system having a first array of banks in two pseudo channels. [Figure 1C] FIG. 13 is a block diagram of an exemplary memory system having a second array of banks in two pseudo channels. [Figure 2A] 1 is a signaling chart illustrating an encoding scheme for two data conductors per byte, according to an exemplary embodiment of the present disclosure. [Figure 2B] 1 is a signaling chart illustrating an encoding scheme for three data conductors per byte, according to an exemplary embodiment of the present disclosure. [Figure 2C] 1 is a signaling chart illustrating an encoding scheme for four data conductors per byte, according to an exemplary embodiment of the present disclosure. [Figure 3A] 2B is an exemplary data receiver structure for use in the encoding scheme of FIG. 2A. [Figure 3B] 2C is an exemplary data receiver structure for use in the encoding scheme of FIG. 2B. [Figure 4] FIG. 3B is a block diagram showing details of the receiver structure of FIG. 3A. [Diagram 5] 2 is a block diagram of an example processor-based system that can include the memory system of FIG. 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0011] Aspects disclosed in the detailed description include a hybrid memory system having improved bandwidth. In particular, a memory system is provided that increases bandwidth over the JEDEC Low Power Double Data Rate Version 5 (LPDDR5) standard. The improvement is made possible by increasing the number of data conductors from 16 to 24. Optionally, the bandwidth can be further improved by increasing the clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complexity of simply doubling the number of pins or doubling the clock speed. That is, although some burden is imposed on finding additional pins and space for routing, this burden is less than the burden imposed by simply doubling the number of pins. Similarly, increasing the clock frequency may result in some electromagnetic compatibility (EMC) type burdens and power burdens, but this burden is less than would be present from simply doubling the clock frequency. Additionally, coding techniques are provided for pin count and pin layout.

[0012] As a first piece of terminology, it should be understood that Double Data Rate (DDR) is a term of art within the JEDEC specifications and memory world in general. As used herein, DDR is defined as a signaling technique that uses both the falling and rising edges of a clock signal. This use of both edges is independent of frequency, and no change in frequency (e.g., doubling) is included within DDR unless both edges are used. DDR, as defined herein, is specifically contrasted with Single Data Rate (SDR), which means transferring data on either the rising or falling edge, but not both, as defined herein.

[0013] Before addressing exemplary aspects of the present disclosure, an overview of conventional memory systems is provided along with an examination of some of the challenges they face. One common memory system is one that complies with the JEDEC LPDDR5 standard. A typical one-channel LPDDR5 system interface consists of 16 data conductors (DQs), two data mask inversion (DMI) conductors that contain data mask and data bus inversion information, two differential clock channels (i.e., four conductors), two differential read strobe clock (RDQS) channels (i.e., four conductors), a command and address (CA) channel, a command clock channel, a chip select channel, and a reset channel. To provide higher bandwidth in such conventional memory systems, typically four or eight memory devices were linked together. A transition to newer memory standards is likely imminent, likely to offer a balance of high performance (e.g., typically considering twice the bandwidth than LPDDR5), low power, competitive cost, and a variety of package types.

[0014] One way to double the bandwidth is to double the clock frequency of the existing standard. However, faster clocks lead to larger circuit size and more technical challenges to achieve stable operation. Such an approach increases system cost and overhead to provide the increased bandwidth.

[0015] A second way that bandwidth can be doubled is to double the number of data conductors in existing standards. This approach avoids the power penalty and stability issues associated with faster clocks, but it consumes substantially more space to accommodate the pins for the additional conductors. Similarly, routing conductors within a memory bus becomes increasingly difficult with that many conductors.

[0016] Exemplary aspects of the present disclosure compromise by increasing the number of conductors but not doubling the number of conductors, and by increasing the clock frequency but not doubling the clock frequency. The extra conductors impose some additional burden on routing, but it is not insurmountable. Similarly, the increased frequency adds some burden, but it is not insurmountable.

[0017] In this regard, FIG. 1A is a block diagram of a memory system 100 including a host 102 and multiple memory devices 104(1)-104(N) coupled by one or more memory buses 106 (only one shown). In an exemplary embodiment, the host 102 may be an integrated circuit (IC) implementing as a system on chip (SoC), an application processor, a main modem, or other control circuitry designed to access the memory devices 104(1)-104(N). The host 102 may include a neural processing unit 108, a graphics processing unit (GPU) and multimedia engine 110, and / or a multicore central processing unit (CPU) 112. The neural processing unit 108, the GPU and multimedia engine 110, and / or the multicore CPU 112 may communicate with a memory controller 114 through a system bus 116. The memory controller 114 may transmit data to a physical layer (PHY) 118 via data lines 120. PHY 118 is a memory bus interface and includes routing and encoding logic 122 (or equivalent circuitry that performs the same function) that routes data from data lines 120 to appropriate pins (e.g., data pins) coupled to memory bus 106.

[0018] Memory devices 104(1)-104(N) may be identical, and therefore a general discussion of memory device 104 is provided. Memory device 104 may include an input / output (I / O) block 124. I / O block 124 is a memory bus interface that communicates with banks 126 of data cell array 128 using read and write commands, as is well understood. I / O block 124 also includes routing and encoding logic 130 that routes data from the data lines to appropriate pins coupled to memory bus 106. Memory bus 106 includes 24 data conductors, 4 clock conductors, and 4 RDQS conductors. Thus, memory bus interface 118, 124 may include 24 pins (e.g., data pins) corresponding to data conductors, 4 pins (e.g., clock pins) corresponding to clock conductors, and 4 pins corresponding to RDQS conductors. Additional conductors may be provided for command and address signals, additional clock signals, chip select signals, and / or reset signals.

[0019] In an exemplary embodiment, the conductors of memory bus 106 are arranged in a particular layout that helps minimize crosstalk and generally simplify routing. That is, moving inward from the first edge, there are six data conductors (DQ0[0:5]), a differential clock channel having two conductors (WCK0_t, WCK0_c), a differential RDQS channel having two conductors (RDQS0_t, RDQS0_c), and six data conductors (DQ0[6:11]) generally shown as a first group 132. In the center of memory bus 106, command and address (CA[0:k]) channel conductors, a differential command clock channel having two conductors (CK_t, CK_c), a chip select channel conductor, and a reset channel conductor may be arranged generally shown as a middle group 134. Then, moving outward toward the second edge of the memory bus, there are six data conductors (DQ1[6:11]), a differential clock channel having two conductors (WCK1_t, WCK1_c), and a differential RDQS channel having two conductors (RDQS1_t, RDQS1_c) and six data conductors (DQ1[0:5]), generally shown as a second group 136. There are reasons for this arrangement for ease of routing, electromagnetic interference (EMI), and / or electromagnetic compatibility (EMC) (e.g., crosstalk), although it should be understood that other arrangements may be used without departing from the scope of this disclosure.

[0020] As an additional feature, the memory controller 114 may include an error correction code (ECC) circuit 140 capable of encoding and decoding ECC signals. Additionally, the data cell array 128 may include ECC cells 142 that store parity bits and cooperate with the ECC circuit 140 for error correction. In an exemplary embodiment, the ECC parity bits (data 2 *The ECC parity bits (p as opposed to n) may be transmitted from the host 102 to the memory device 104 via the RDQS pins (e.g., RDQS_t, RDQS_c, or both), such as during a write operation. In the opposite direction, the ECC parity bits may be transmitted via the data mask slots (e.g., M[0:31], described in more detail below) during a read operation. Alternatively, instead of using the RDQS signal, the host 102 may use the data mask slots (e.g., M[0:31]) for write operations.

[0021] The data cell array 128 can be arranged in banks in a variety of configurations. Two exemplary bank arrangements are provided in Figures 1B and 1C.

[0022] 1B shows a data cell array 128B having a total of 32 banks, with a first memory block 150A having 8 bank groups (BG) each having 2 banks, and a second memory block 150B also having 8 bank groups (BG) each having 2 banks, for the existing LPDDR5 standard. The 32 banks are divided into two pseudo channels 152A, 152B. Data cell array 128B can include an interface 154 having a first pair of twelve DQ conductors (DQ[11:0]), two conductors forming a first differential write clock (WCK0), and a first redundant data strobe (RDQS0) in a first group 156, as well as a second pair of twelve DQ conductors (DQ[23:12]), two conductors forming a second differential write clock (WCK1), and two conductors forming a second redundant data strobe (RDQS1) in a second group 158. Groups 156, 158 share the differential clock (CK), seven command and address conductors (CA[7:0]), a chip select conductor (CS), and a reset conductor (all shown in an intermediate group 160). The memory device 104 has a maximum bandwidth of 25.6 Gigabytes per second (GB / s), an input / output (IO) rate of 6400 Megabits per second (Mbps), a maximum CK frequency of 1600 Megahertz (MHz), a maximum WCK frequency of 3200 MHz, a CA rate of 3200 Megatransfers per second (MT / s), and can operate with Pulse Amplitude Modulation (PAM) and / or Non-Return to Zero (NRZ) signaling schemes. It should be appreciated that the interface 154 is configured to receive commands and / or data from a remote source, such as the host 102.

[0023] While data cell array 128B is one possible implementation of the improved memory configuration, other architectures exist, such as data cell array 128C shown in FIG. 1C. Data cell array 128C includes a first memory block 170(0) with 16 banks and a second memory block 170(1) with 16 banks, for a total of 32 banks. The 32 banks are divided into two pseudo channels 172(0), 172(1). The pins / conductors of interface 174 are somewhat different. Specifically, the conductors are mirrored around a central reset conductor 176 that is common to both pseudo channels 172(0), 172(1). Each pseudo channel 172(0), 172(1) includes a respective chip select conductor 178(0), 178(1) and four command and address conductors 180(0), 180(1) (CA0[3:0], CA1[3:0]). In addition, differential clock conductors 182(0), 182(1) (also referred to as CK0_t / c and CK1_t / c) may be provided to each pseudo channel 172(0), 172(1). A first set of data channel conductors 184(0), 184(1) (DQ0[15:8], DQ1[8:15]) may be next. A subdivision of the data channel is a differential write clock conductor pair 186(0), 186(1) (WCK0_t / c, WCK1_t / c) and a differential RDQS conductor pair 188(0), 188(1) (RDQS0_t / c, RDQS1_t / c). A final data channel conductor 190(0), 190(1) (DQ0[7:0], DQ1[0:7]) provides the outer conductor.

[0024] Typically, the locations of the data conductors DQ are spread out and separated by other conductors to reduce crosstalk and other EMI / EMC concerns. Similarly, by pairing the positive and negative differential signals on adjacent conductors, radiation is similarly reduced.

[0025] In practice, the routing and encoding logic 122 or 130 may combine the data signal with a data mask signal, as better shown in Figures 2A-2C. Figure 2A is a signaling chart showing two data conductors used for a single byte (Dx-Dx+7, e.g., D0-D7, or other arrangements such as DQ[48:51]+DQ[64:67]), generally indicated at 200(1)-200(3). Periodically, a data mask signal (Mx-Mx+7, e.g., M0-M7)) is provided, generally indicated at 202(1)-202(2). It should be understood that other arrangements of data and data masks can be made while still encoding a byte onto two conductors. In an exemplary embodiment, the clock signal 206 is 4.8 GHz. In an alternative exemplary embodiment, the clock signal 206 is 6.4 GHz.

[0026] Alternatively, the routing and encoding logic 122 or 130 may combine the data and data mask signals to encode a byte across three conductors as shown in FIG. 2B. The byte is generally shown as 250(1)-250(2) encoded across three conductors. In this encoding scheme, the data mask bits 252(1)-252(2) are encoded in the ninth slot per byte. It should be understood that other arrangements of data and data mask can be made while still encoding a byte onto three conductors. In an exemplary embodiment, the clock signal 206 is 4.8 GHz. In an alternative exemplary embodiment, the clock signal 206 is 6.4 GHz.

[0027] Alternatively, the routing and encoding logic 122 or 130 may combine the data and data mask signals to encode a byte across four conductors as shown in FIG. 2C. The bytes are generally shown as 260(1)-260(2) encoded across four conductors. In this encoding scheme, the data mask bits 262(1)-262(8) are grouped and encoded in byte after 8 bytes. It should be understood that other arrangements of data and data mask can be made while still encoding a byte onto four conductors. In an exemplary embodiment, the clock signal 206 is 4.8 GHz. In an alternative exemplary embodiment, the clock signal 206 is 6.4 GHz.

[0028] It should be understood that the frequencies described in relation to Figures 2A-2C may be maximum frequencies. Clock frequency scaling is widely used in mobile systems, and therefore it may be possible for these maximum frequencies to be scaled to lower frequencies.

[0029] 3A is an exemplary data receiver structure within memory bus interface 118 or 124 for use with the encoding scheme of FIG. 2A. Specifically, pins 300(1)-300(6) may be used to couple to data conductors DQ[0:5] in first group 132. Clock pins 302(1)-302(2) may be used to couple to data clock conductors in first group 132. RDQS pins 304(1)-304(2) may be used to couple to RDQS conductors in first group 132, and pins 300(7)-300(12) may be used to couple to data conductors DQ[6:11] in first group 132. Pins 300(1)-300(12) are coupled to respective receiver / transmitter circuits 306(1)-306(12). The receiver / transmitter circuits 306(1)-306(12) may be coupled in pairs to data registers 308(1)-308(6). The RDQS pins 304(1)-304(2) may be coupled to an RDQS driver 310. Similarly, the clock pins 302(1)-302(2) may be coupled to a clock receiver and four-phase generator 312.

[0030] FIG. 3B is an exemplary data receiver structure within memory bus interface 118 or 124 for use with the encoding scheme of FIG. 2B. Specifically, pins 300(1)-300(6) may be used to couple to data conductors DQ[0:5] in first group 132. Clock pins 302(1)-302(2) may be used to couple to data clock conductors in first group 132. RDQS pins 304(1)-304(2) may be used to couple to RDQS conductors in first group 132, and pins 300(7)-300(12) may be used to couple to data conductors DQ[6:11] in first group 132. Pins 300(1)-300(12) are coupled to respective receiver / transmitter circuits 306(1)-306(12). The receiver / transmitter circuits 306(1)-306(12) may be coupled in sets of three to data registers 350(1)-350(4). The RDQS pins 304(1)-304(2) may be coupled to an RDQS driver 310. Similarly, the clock pins 302(1)-302(2) may be coupled to a clock receiver and four-phase generator 312.

[0031] 4 is a block diagram showing details of how receiver 306 accommodates four-phase data. Specifically, pin 300(1) may be coupled to four delays and comparators 400(1)-400(4) to populate bit register slots 402(1)-402(4). Similarly, pin 300(2) may be coupled to four delays and comparators 400(5)-400(8) to populate bit register slots 402(5)-402(8). When the signals at comparators 400(1)-400(8) exceed a threshold, a logic high (or low) may be output to bit register slots 402(1)-402(8). In this manner, more data may be provided for a given clock signal. For example, two clock cycles (2 WCK) may generate a four-phase data clock where the first rising edge of WCK is WCK_0, the first falling edge of WCK is WCK_90, the second rising edge of WCK is WCK_180, and the second falling edge of WCK is WCK_270.

[0032] A hybrid memory system with improved bandwidth according to aspects disclosed herein may be provided or integrated within any processor-based device, including, but not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.

[0033] In this regard, Figure 5 is a system level block diagram of an exemplary mobile communications device or mobile terminal 500, such as a smartphone, mobile computing device tablet, etc. Although mobile terminals are specifically contemplated as being able to benefit from exemplary aspects of the present disclosure, it should be understood that the present disclosure is not so limited and may be useful in any system having a memory bus that conforms to existing or emerging memory standards.

[0034] Continuing to refer to FIG. 5, the mobile terminal 500 includes an application processor 504 (sometimes referred to as a host or SoC) that communicates with a mass storage element 506 through a universal flash storage (UFS) bus 508. The application processor 504 may also communicate with a DDR memory element 506A via a memory bus 508A in accordance with an exemplary aspect of the present disclosure. The application processor 504 may be further connected to a display 510 through a display serial interface (DSI) bus 512 and to a camera 514 through a camera serial interface (CSI) bus 516. Various audio elements, such as a microphone 518, a speaker 520, and an audio codec 522, may be coupled to the application processor 504 through a serial low-power interchip multimedia bus (SLIMbus) 524. Additionally, the audio elements may communicate with each other through a SOUNDWIRE bus 526. A modem 528 may also be coupled to the SLIMbus 524 and / or the SOUNDWIRE bus 526. The modem 528 may further be connected to the application processor 504 through a peripheral component interconnect (PCI) or PCI Express (PCIe) bus 530 and / or a system power management interface (SPMI) bus 532.

[0035] 5, the SPMI bus 532 may also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 534, a power management integrated circuit (PMIC) 536, a companion IC (sometimes referred to as a bridge chip) 538, and a radio frequency IC (RFIC) 540. It should be appreciated that separate PCI buses 542 and 544 may also couple the application processor 504 to the companion IC 538 and the WLAN IC 534. The application processor 504 may be further connected to sensors 546 through a sensor bus 548. The modem 528 and the RFIC 540 may communicate using a bus 550.

[0036] 5, the RFIC 540 may couple to one or more RFFE elements, such as an antenna tuner 552, a switch 554, and a power amplifier 556, through a radio frequency front end (RFFE) bus 558. Additionally, the RFIC 540 may couple to an envelope tracking power supply (ETPS) 560 through a bus 562, which may communicate with the power amplifier 556. Collectively, the RFFE elements including the RFIC 540 may be considered to be an RFFE system 564. It should be understood that the RFFE bus 558 may be formed from clock and data lines (not shown).

[0037] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, as instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or as a combination of both. The master and slave devices described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. The memories disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0038] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0039] Aspects disclosed herein may be embodied in hardware and instructions stored in the hardware and may reside in, for example, a random access memory (RAM), a flash memory, a read-only memory (ROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0040] It should also be noted that the operational steps described in any of the exemplary aspects herein are set forth to provide examples and explanations. The described operations may be performed in many different orders other than the order shown. Moreover, an operation described in a single operational step may actually be performed in several different steps. In addition, one or more operational steps described in the exemplary aspects may be combined. It should be understood that many different variations may be made to the operational steps shown in the flowchart diagrams, as would be readily apparent to one of ordinary skill in the art. Those skilled in the art will also appreciate that information and signals may be represented using any of a variety of different technologies and techniques.

[0041] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other examples. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0042] The following numbered clauses describe example implementations. 1. An integrated circuit (IC), comprising: A memory bus interface having 32 pins, 24 pins correspond to data conductors, Four pins correspond to the clock conductors, a memory bus interface, the four pins of which correspond to read strobe clock (RDQS) conductors; and routing and encoding logic associated with the memory bus interface and configured to route signals to pins within the memory bus interface. 2. The IC of clause 1, wherein the IC comprises a memory device. 3. The IC of claim 2, wherein the memory bus interface comprises an input / output (IO) block. 4. The IC of any one of clauses 1 to 3, wherein the IC comprises a system on a chip (SoC). 5. The IC of clause 4, wherein the memory bus interface comprises a physical layer (PHY). 6. An IC as described in any one of clauses 1 to 3, wherein the IC comprises a host. 7. 32 pins include a first group and a second group, the first group being: the first six of the twenty-four pins corresponding to data conductors; a first two pins of the four pins corresponding to clock conductors disposed adjacent to the first six pins; a second two pins of the four pins corresponding to the RDQS conductors adjacent to the first two pins; and a second six of the 24 pins corresponding to data conductors adjacent the second two pins. 8. The IC of clause 7, wherein the first two pins are configured to form a differential clock channel. 9. The IC of clause 7, wherein the second two pins are configured to form a differential RDQS channel. 10. The second group the third six of the twenty-four pins corresponding to data conductors; a third two of the four pins corresponding to clock conductors disposed adjacent to the third six pins; four pins corresponding to the RDQS conductors adjacent to the third two pins; and and a fourth six of the twenty-four pins corresponding to data conductors adjacent the fourth two pins. 11. The IC of claim 10, wherein the third two pins are configured to form a differential clock channel. 12. The IC of clause 10, wherein the fourth two pins are configured to form a differential RDQS channel. 13. The IC of clause 10, further comprising a third group of additional pins between the first 6 of the 24 pins and the third 6 of the 24 pins. 14. A third group of additional pins are a first command clock pair of pins; a second command clock pair of pins; a first set of four command and address pins; a second set of four command and address pins; a first chip select pin; a second chip select pin; and a reset pin. 15. The IC of clause 14, wherein the reset pin is centrally located among all pins of the memory bus interface. 16. The IC of clause 15, wherein a first command clock pair of pins is adjacent to the second six pins of the 24 pins. 17. The IC of clause 16, wherein the second command clock pair of pins are adjacent to the third six pins of the 24 pins. 18. The IC of clause 16 or 17, wherein the first set of four command and address pins are adjacent to a first command clock pair of pins. 19. The IC of clause 17, wherein the second set of four command and address pins are adjacent to the second command clock pair of pins. 20. The IC of any one of clauses 1-19, further comprising a clock source, the clock source configured to generate a clock signal having a maximum frequency of 4.8 gigahertz (GHz). 21. The IC of any one of clauses 1-20, further comprising a clock source, the clock source configured to generate a clock signal having a maximum frequency of 6.4 gigahertz (GHz). 22. The IC of any one of clauses 1-21, wherein the routing and encoding logic is configured to encode a byte onto two data conductors. 23. The IC of any one of clauses 1-21, wherein the routing and encoding logic is configured to encode a byte onto three data conductors. 24. The IC of any one of clauses 1-21, wherein the memory bus interface further comprises a command and address (CA) pin, a command clock pin, a chip select pin, and a reset pin. 25. set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, mobile phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, multicopters, 25. The IC of clauses 1-24 integrated into a device selected from the group consisting of: 26. The IC of any one of clauses 1-25, wherein the routing and encoding logic is further configured to transmit a first error correcting code (ECC) parity bit through two of the four pins corresponding to the RDQS conductors and receive a second ECC parity bit through eight of the 24 pins corresponding to the data conductors. 27. The IC of any one of clauses 1-25, wherein the routing and encoding logic is further configured to transmit a first error correcting code (ECC) parity bit through 8 of the 24 pins corresponding to the data conductors and receive a second ECC parity bit through 8 of the 24 pins corresponding to the data conductors. 28. The IC of any one of clauses 1-25, wherein the routing and encoding logic is further configured to transmit a first error correcting code (ECC) parity bit through one of the four pins corresponding to the RDQS conductors and receive a second ECC parity bit through one of the 24 pins corresponding to the data conductors. 29. The IC of any one of clauses 1-25, wherein the routing and encoding logic is further configured to transmit a first error correcting code (ECC) parity bit through one of the 24 pins corresponding to the data conductors and receive a second ECC parity bit through one of the 24 pins corresponding to the data conductors. 30. The IC of any one of clauses 1-21, wherein the routing and encoding logic is configured to encode a byte onto four data conductors. 31. A computing device comprising: A host, A physical layer (PHY) having 32 pins, 24 pins correspond to data conductors, Four pins correspond to the clock conductors, a PHY whose four pins correspond to the read strobe clock (RDQS) conductors; a host comprising routing and encoding logic associated with the PHY and configured to route signals to pins in a memory bus interface; A memory bus, 24 data conductors; Two differential clock channels, a memory bus having two differential RDQS channels; 1. A memory module comprising: and a memory module having an input / output (IO) block having 32 pins corresponding to the conductors of a memory bus. 32. An integrated circuit (IC), 1. A memory bus interface, comprising: a plurality of data pins corresponding to the data conductors; a memory bus interface including a plurality of clock pins corresponding to the clock conductors; and routing and encoding logic associated with the memory bus interface and configured to encode bytes onto a plurality of data conductors associated with a plurality of data pins. 33. The IC of clause 32, wherein the routing and encoding logic is configured to encode a byte onto two data conductors of the plurality of data conductors. 34. The IC of clause 32, wherein the routing and encoding logic is configured to encode a byte onto three data conductors of the plurality of data conductors. 35. The IC of clause 32, wherein the routing and encoding logic is configured to encode a byte onto four data conductors of the plurality of data conductors. 36. The IC of any one of clauses 32-35, wherein the routing and encoding logic is configured to encode data mask inversion (DMI) information on at least one data conductor of the plurality of data conductors. 37. The IC of any one of clauses 32-36, wherein the routing and encoding logic is further configured to transmit a first error correcting code (ECC) parity bit and receive a second ECC parity bit over one data conductor of the plurality of data conductors.

Claims

1. 1. An integrated circuit (IC), comprising: A memory bus interface having 32 pins, 24 pins correspond to data conductors, Four pins correspond to the write clock conductors, a memory bus interface, four pins of which correspond to read strobe clock (RDQS) conductors; routing and encoding logic associated with the memory bus interface and configured to route signals to pins within the memory bus interface, the routing and encoding logic configured to encode bytes onto a plurality of the data conductors; The 32 pins include a first group and a second group, the first group including: the first six of the twenty-four pins corresponding to the data conductors; a first two pins of the four pins corresponding to the write clock conductors located adjacent to the first six pins; second two pins of the four pins corresponding to the RDQS conductors adjacent to the first two pins; a second six pins of the twenty-four pins corresponding to the data conductors adjacent the second two pins; An IC comprising:

2. 2. The IC of claim 1, wherein the IC comprises a memory device, and preferably the memory bus interface comprises an input / output (IO) block.

3. The IC of claim 1 , wherein the IC comprises a system on a chip (SoC), and the memory bus interface preferably comprises a physical layer (PHY).

4. The IC of claim 1 , wherein the IC comprises a host.

5. 2. The IC of claim 1, wherein the first two pins are configured to form a differential clock channel and / or the second two pins are configured to form a differential RDQS channel.

6. The second group comprises: a third six pins of the twenty-four pins corresponding to the data conductors; a third two pins of the four pins corresponding to the clock conductors located adjacent to the third six pins; two fourth pins of the four pins corresponding to the RDQS conductors adjacent to the third two pins; 2. The IC of claim 1, further comprising: a fourth six of said twenty-four pins corresponding to said data conductors adjacent said fourth two pins.

7. 7. The IC of claim 6, wherein the third two pins are configured to form a differential clock channel and / or the fourth two pins are configured to form a differential RDQS channel.

8. a third group of additional pins between the first six of the twenty-four pins and the third six of the twenty-four pins; Said third group of additional pins preferably a first command clock pair of pins; a second command clock pair of pins; a first set of four command and address pins; a second set of four command and address pins; a first chip select pin; a second chip select pin; and a reset pin, wherein the reset pin is preferably centrally located among all pins of the memory bus interface, the first command clock pair of pins is preferably adjacent to the second six pins of the 24 pins, the second command clock pair of pins is preferably adjacent to the third six pins of the 24 pins, and / or the first set of four command and address pins is adjacent to the first command clock pair of pins and the second set of four command and address pins is preferably adjacent to the second command clock pair of pins.

9. The IC of claim 1 , further comprising a clock source, the clock source configured to generate a write clock signal having a maximum frequency of 4.8 gigahertz (GHz) or 6.4 GHz.

10. 2. The IC of claim 1, wherein the routing and encoding logic is configured to encode a byte onto two, three, or four data conductors.

11. 10. The IC of claim 1, wherein the memory bus interface further comprises a command and address (CA) pin, a command clock pin, a chip select pin, and a reset pin.

12. set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, mobile phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, multicopters, 10. The IC of claim 1 integrated into a device selected from the group consisting of:

13. the routing and encoding logic: transmitting a first error correcting code (ECC) parity bit over two of the four pins corresponding to RDQS conductors and receiving a second ECC parity bit over eight of the twenty-four pins corresponding to data conductors; transmitting a first error correction code (ECC) parity bit over eight of the twenty-four pins corresponding to data conductors and receiving a second ECC parity bit over eight of the twenty-four pins corresponding to the data conductors; or Transmitting a first error correcting code (ECC) parity bit through one of the four pins corresponding to an RDQS conductor and receiving a second ECC parity bit through one of the twenty-four pins corresponding to a data conductor.

10. The IC of claim 1, configured to perform any one of the following:

14. 2. The IC of claim 1, wherein the routing and encoding logic is further configured to transmit a first error correcting code (ECC) parity bit over one of the 24 pins corresponding to a data conductor and to receive a second ECC parity bit over the one of the 24 pins corresponding to the data conductor.

15. 1. A computing device comprising: A host, A physical layer (PHY) having 32 pins, 24 pins correspond to data conductors, Four pins correspond to the write clock conductors, Four pins correspond to read strobe clock (RDQS) conductors, the 32 pins comprising a first group and a second group, the first group comprising: the first six of the twenty-four pins corresponding to the data conductors; a first two pins of the four pins corresponding to the write clock conductors located adjacent to the first six pins; second two pins of the four pins corresponding to the RDQS conductors adjacent to the first two pins; a second six pins of the twenty-four pins corresponding to the data conductors adjacent the second two pins; a PHY comprising: a host comprising routing and encoding logic associated with said PHY and configured to route signals to pins in a memory bus interface, said routing and encoding logic configured to encode bytes onto a plurality of said data conductors; A memory bus, 24 data conductors; two differential clock channels; a memory bus comprising two differential RDQS channels; 1. A memory module, comprising: a memory module comprising an input / output (IO) block comprising the 32 pins corresponding to the conductors of the memory bus.

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