Display device and manufacturing method thereof

Abstract

A display device is provided, the display device including a plurality of insulating layers, a light emitting element, and a pixel circuit electrically connected to the light emitting element. The pixel circuit includes a first transistor. The first transistor includes a metal oxide semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region, a first gate disposed on the metal oxide semiconductor pattern and overlapping the channel region, and a metal oxide pattern disposed on the first gate.

Description

[Technical field]

[0001] The present invention relates to a display device and a manufacturing method thereof, and to a display device including oxide transistors and a manufacturing method thereof. [Background technology]

[0002] The display device includes a plurality of pixels and a driving circuit (e.g., a scan driving circuit and a data driving circuit) for controlling the plurality of pixels. Each of the plurality of pixels includes a display element and a pixel circuit for controlling the display element. The pixel circuit includes a plurality of transistors that are organically connected.

[0003] The plurality of transistors may include a silicon semiconductor or a metal oxide semiconductor. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device including oxide transistors with a wider driving voltage range.

[0005] An object of the present invention is to provide a method for manufacturing the display device. [Means for solving the problem]

[0006] According to an embodiment of the present invention, a display device includes a plurality of insulating layers, a light emitting element, and a pixel circuit electrically connected to the light emitting element. The pixel circuit includes a first transistor. The first transistor may include a metal oxide semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region, a first gate disposed on the metal oxide semiconductor pattern and overlapping the channel region, and a metal oxide pattern disposed on the first gate.

[0007] The plurality of insulating layers may include a first insulating layer disposed between the channel region and the first gate, a second insulating layer having a first portion disposed between the first gate and the metal oxide pattern, a second portion disposed on the source region, and a third portion disposed on the drain region, and a third insulating layer disposed on the second insulating layer and the metal oxide pattern.

[0008] The first insulating layer may include a silicon oxide layer, the second insulating layer may include a silicon oxide layer or a silicon oxynitride layer, and the third insulating layer may include a silicon oxynitride layer and a silicon nitride layer disposed on the silicon oxynitride layer.

[0009] The second insulating layer may cover a side surface of the first insulating layer.

[0010] The metal oxide pattern may be electrically connected to the first gate.

[0011] The pixel circuit may further include a conductive pattern disposed over the metal oxide pattern.

[0012] A corresponding one of the plurality of insulating layers may be disposed between the first gate and the conductive pattern, and the first gate and the conductive pattern may define a capacitor.

[0013] The first transistor may control a driving current of the light emitting device based on a charge capacitance of the capacitor.

[0014] The pixel circuit may further include a second transistor, the second transistor may include a metal oxide semiconductor pattern, and the second transistor may provide a data voltage to the capacitor.

[0015] An edge of the metal oxide pattern may be aligned with an edge of the conductive pattern.

[0016] The length of the channel region is 3 μm or less.

[0017] The first transistor may further include a second gate disposed under the metal oxide semiconductor pattern and electrically connected to the first gate.

[0018] The metal oxide pattern may include at least one of indium (In), tin (Sn), zinc (Zn), gallium (Ga), magnesium (Mg), hafnium (Hf), and titanium (Ti).

[0019] The metal oxide pattern has a thickness of 100 Å to 300 Å.

[0020] A manufacturing method of a display device according to one embodiment of the present invention may include the steps of forming a transistor including a metal oxide semiconductor pattern on a base layer, the metal oxide semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region, a first insulating layer disposed on the channel region, and a gate disposed on the first insulating layer, forming a second insulating layer covering the gate, the source region, and the drain region, forming a metal oxide layer on the second insulating layer, etching at least a portion of the metal oxide layer, and forming a third insulating layer on the second insulating layer.

[0021] The method may further include forming a conductive pattern on the metal oxide layer that overlaps the gate.

[0022] In the step of etching at least a portion of the metal oxide layer, the conductive pattern may be used as a mask to form a metal oxide pattern from the metal oxide layer that overlaps the conductive pattern on a plane.

[0023] A periphery of the metal oxide pattern may be aligned with a periphery of the conductive pattern.

[0024] In the step of forming the metal oxide layer, the partial pressure of the oxygen gas relative to the reaction gas may be 50% to 100%.

[0025] A manufacturing method of a display device according to one embodiment of the present invention may include the steps of forming a transistor including a metal oxide semiconductor pattern on a base layer, the metal oxide semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region, a first insulating layer disposed on the base layer and covering the metal oxide semiconductor pattern, and a gate disposed on the first insulating layer, forming a metal oxide layer on the first insulating layer covering the gate, etching at least a portion of the metal oxide layer, and forming a second insulating layer on the base layer. Effect of the Invention

[0026] As described above, in the step of forming the metal oxide pattern, oxygen is implanted onto the insulating layer covering the metal oxide semiconductor pattern. The oxygen is diffused into the source and drain regions of the metal oxide semiconductor pattern, reducing the carriers in the source and drain regions. The resistance of the source and drain regions where the carriers are reduced increases, thereby changing the voltage-current characteristics of the oxide transistor. The driving voltage range of the oxide transistor can be increased.

[0027] The implanted oxygen may diffuse into the channel region, particularly into edge regions of the channel region exposed by the gate. The diffused oxygen removes oxygen vacancies in the edge regions of the channel region. With the oxygen vacancies reduced and hydrogen bound thereto reduced, the carrier concentration in the outer regions of the channel region is not increased. That is, the channel characteristics of the peripheral regions of the channel region may be maintained and the effective length of the channel region may be maintained substantially the same as the length of the channel region. [Brief description of the drawings]

[0028] [Figure 1] 1 is a block diagram of a display device according to an embodiment of the present invention; [Diagram 2] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Diagram 3] 3 is a waveform diagram of a driving signal for driving the pixel shown in FIG. 2. [Figure 4] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention. [Diagram 5] 1 is a graph comparing voltage-current characteristics of an oxide transistor and a silicon transistor. [Figure 6] FIG. 2 is an enlarged cross-sectional view of a first transistor according to one embodiment of the present invention. [Figure 7] 1 is a graph comparing voltage-current characteristics of an oxide transistor according to an embodiment of the present invention and an oxide transistor according to a comparative example. [Figure 8a] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 8b] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 8c] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 8d] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 8e] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 8f] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 9] FIG. 2 is an enlarged cross-sectional view of a first transistor according to one embodiment of the present invention. [Figure 10] FIG. 2 is an enlarged cross-sectional view of a first transistor according to one embodiment of the present invention. [Figure 11a] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 11b] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 11c] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 11d] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 11e] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 11f] 2A to 2C are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] As used herein, when a component (or region, layer, portion, etc.) is referred to as being "on" or "coupled" to another component, it means that it may be directly disposed, coupled, or joined to the other component, or that a third component may be disposed therebetween.

[0030] The same reference numerals refer to the same components. Also, in the drawings, thicknesses, ratios, and dimensions of the components are exaggerated for the purpose of effectively explaining the technical contents. "And / or" includes all combinations of one or more of the components defined by the associated components.

[0031] Terms such as "first" and "second" are used to describe various components, but the components are not limited to these terms. The terms are used only to distinguish one component from another. For example, the first component may be named the second component, and similarly the second component may be named the first component, without departing from the scope of the present invention. A singular surface includes a plural expression unless the context clearly indicates otherwise.

[0032] In addition, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. The terms are relative concepts and are described based on the directions shown in the drawings.

[0033] It should be understood that terms such as "comprise" or "have" specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described above in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms that are defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an overly ideal or formal sense unless expressly defined herein.

[0035] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0036] 1 is a block diagram of a display device DD according to an embodiment of the present invention. The display device DD includes a timing controller TC, a scan driver circuit SDC, a data driver circuit DDC, and a display panel DP. In this embodiment, the display panel DP is described as an emissive display panel. The emissive display panel may include an organic light-emitting display panel or an inorganic light-emitting display panel.

[0037] The timing controller TC receives an input video signal, converts the timing format of the input video signal to match the interface specifications with the scan driver circuit SDC, and generates video data D-RGB. The timing controller TC outputs the video data D-RGB and various control signals DCS and SCS.

[0038] The scan driving circuit SDC receives a scan control signal SCS from the timing controller TC. The scan control signal SCS may include a vertical start signal for starting the operation of the scan driving circuit SDC and a clock signal for determining the output timing of the signal. The scan driving circuit SDC generates a plurality of scan signals and sequentially outputs them to corresponding scan signal lines SL11 to SL1n. In addition, the scan driving circuit SDC generates a plurality of light emitting control signals in response to the scan control signal SCS and outputs the plurality of light emitting control signals to corresponding light emitting signal lines EL1 to ELn.

[0039] 1 shows that a plurality of scan signals and a plurality of emission control signals are output from one scan driving circuit SDC, but the present invention is not limited thereto. In one embodiment of the present invention, the display device DD may include a plurality of scan driving circuits. Also, in one embodiment of the present invention, a driving circuit that generates and outputs a plurality of scan signals and a driving circuit that generates and outputs a plurality of emission control signals may be formed separately.

[0040] The data driving circuit DDC receives a data control signal DCS and video data D-RGB from the timing controller TC. The data driving circuit DDC converts the video data D-RGB into a data signal and outputs the data signal to a number of data lines DL1 to DLm, which will be described later. The data signal is an analog voltage corresponding to the grayscale value of the video data D-RGB.

[0041] The light-emitting display panel DP may include a plurality of groups of scan lines. A first group of scan signal lines SL11 to SL1n is shown in FIG 1 as an example. The light-emitting display panel DP includes light-emitting signal lines EEL1 to ELn, data lines DL1 to DLm, a first voltage line VL1, a second voltage line VL2, a third voltage line VL3, a fourth voltage line VL4, and a plurality of pixels PX.

[0042] The first group of scan signal lines SL1 to SLn may be extended in a first direction DR1 and arranged in a second direction DR2. The data lines DL1 to DLm may cross the first group of scan signal lines SL11 to SL1n.

[0043] The first voltage line VL1 receives the first power supply voltage ELVSS. The second voltage line VL2 receives the second power supply voltage ELVDD. The second power supply voltage ELVDD has a higher level than the first power supply voltage ELVSS. The third voltage line VL3 receives a reference voltage Vref (hereinafter, the first voltage). The fourth voltage line VL4 receives an initialization voltage Vint (hereinafter, the second voltage). The first voltage Vref has a lower level than the second power supply voltage ELVDD. The second voltage Vint has a lower level than the second power supply voltage ELVDD. In this embodiment, the second voltage Vint may have a lower level than the first voltage Vref and the first power supply voltage ELVSS.

[0044] At least one of the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, and the fourth voltage line VL4 includes at least one of a line extended in a first direction DR1 and a line extended in a second direction DR2. The line extended in the first direction DR1 and the line extended in the second direction DR2 of the voltage lines are electrically connected to each other even if they are disposed on different layers among the insulating layers 10 to 40 shown in FIG.

[0045] Although the display device DD according to an embodiment has been described with reference to FIG. 1, the display device DD of the present invention is not limited thereto. Signal lines may be added or omitted depending on the configuration of the pixel driving circuit. In addition, the electrical connection relationship between one pixel PX and a signal line may be changed.

[0046] The pixels PX may include a plurality of groups that generate light of different colors, for example, a red pixel that generates red light, a green pixel that generates green light, and a blue pixel that generates blue light. The light emitting element of the red pixel, the light emitting element of the green pixel, and the light emitting element of the blue pixel may include light emitting layers made of different materials.

[0047] The pixel circuit includes a plurality of transistors and at least one capacitor. At least one of the scan driving circuit SDC and the data driving circuit DDC may include a plurality of transistors formed by the same process as the pixel circuit.

[0048] Fig. 2 is an equivalent circuit diagram of a pixel PXij according to an embodiment of the present invention, and Fig. 3 is a waveform diagram of a driving signal for driving the pixel PXij shown in Fig. 2.

[0049] 2 shows a pixel PXij connected to the ith scan line SL1i of the first group of scan lines SL11 to SL1n (see FIG. 1) and connected to the jth data line DLj of the plurality of data lines DL1 to DLm (see FIG. 1). The pixel PXij is connected to the ith scan line SL2i of the second group of scan lines and connected to the ith scan line SL3i of the third group of scan lines.

[0050] In this embodiment, the pixel circuit includes first to fifth transistors T1 to T5, first to third capacitors C1 to C3, and a light emitting element OLED. In this embodiment, the first to fifth transistors T1 to T5 are described as N-type. However, this is not limited thereto, and at least one of the first to fifth transistors T1 to T5 may be a P-type transistor. In addition, in one embodiment of the present invention, at least one of the first to fifth transistors T1 to T4 may be omitted, or an additional transistor may be further included in the pixel PXij.

[0051] In the present embodiment, each of the first to fifth transistors T1 to T5 includes a gate, but at least one of the transistors includes only one gate. Although the upper gates G2-1, G3-1, G4-1, and G5-1 and the lower gates G2-2, G3-2, G4-2, and G5-2 of the second to fifth transistors T2 to T5 are electrically connected to each other, this is not limited thereto. The lower gates G2-2, G3-2, G4-2, and G5-2 of the second to fifth transistors T2 to T5 may be floating electrodes.

[0052] In this embodiment, the first transistor T1 is a driving transistor, and the second transistor T2 is a switching transistor. A node to which a gate G1-1 (hereinafter, a first upper gate) of the first transistor T1 is connected may be defined as a first node ND1, and a node to which a source S1 of the first transistor T1 is connected may be defined as a second node ND2.

[0053] The light emitting element OLED includes a first electrode electrically connected to the first node ND1, a second electrode receiving the first power supply voltage ELVSS, and a light emitting layer disposed between the first electrode and the second electrode. A detailed description of the light emitting element OLED will be provided later.

[0054] The first transistor T1 is electrically connected between a second power line VL2 receiving a second power voltage ELVDD and a second node ND2. The first transistor T1 includes a source S1 (hereinafter, first source) connected to the second node ND2, a drain D1 (hereinafter, first drain), a channel region (or semiconductor region), and a first upper gate G1-1. The first transistor T1 further includes a gate G1-2 (hereinafter, first lower gate) connected to the second node ND2. The first transistor T1 controls a driving current of the light emitting element OLED based on the charge capacitance of the first capacitor C1.

[0055] The second transistor T2 is electrically connected between the first data line DLj and the first node ND1. The second transistor T2 may include a source S2 (hereinafter, second source) connected to the first node ND1, a drain D2 (hereinafter, second drain) connected to the first data line DLj, a channel, and a gate G2-1 (hereinafter, second upper gate) connected to the i-th scan line SL1i of the first group. The second transistor T2 may further include a gate G2-2 (hereinafter, second lower gate) electrically connected to the second upper gate G2-1. The third to fifth transistors T3 to T5 described later include upper gates G3-1, G4-1, and G5-1 and lower gates G3-2, G4-2, and G5-2 corresponding to the second upper gate G2-1 and the second lower gate G2-2. The second transistor T2 provides a data voltage to the first capacitor C1.

[0056] The third transistor T3 is electrically connected between the first node ND1 and a third voltage line VL3 receiving the first voltage Vref. The third transistor T3 may include a drain D3 (hereinafter, third drain) connected to the first node ND1, a source S3 (hereinafter, third source) connected to the third voltage line VL3, a channel region, and a third upper gate G3-1 connected to the i-th scan line SL2i of the second group.

[0057] The fourth transistor T4 is electrically connected between a first voltage line VL4 receiving a second voltage Vint and a second node ND2. The fourth transistor T4 may include a drain (hereinafter, a fourth drain) connected to the second node ND2, a source S4 (hereinafter, a fourth source) connected to the fourth voltage line VL4, a channel region, and a fourth upper gate G4-1 connected to the i-th scan line SL3i of the third group.

[0058] The fifth transistor T5 is electrically connected between the second voltage line VL2 and the first drain D1 or the first source S1. In this embodiment, the fifth transistor T5 may include a source S5 (hereinafter, the fifth source) connected to the second power line VL2, a drain D5 (hereinafter, the fifth drain) connected to the first drain D1, a channel region, and a fifth upper gate G5-1 connected to the i-th light emission signal line ELi.

[0059] The first capacitor C1 is electrically connected between a first node ND1 and a second node ND2. The first capacitor C1 includes a first electrode E1-1 connected to the first node ND1 and a second electrode E1-2 connected to the second node ND2.

[0060] The second capacitor C2 is electrically connected between the second voltage line VL2 and the second node ND2. The second capacitor C2 includes a first electrode E2-1 connected to the second power line VL2 and a second electrode E2-2 connected to the second node ND2.

[0061] The third capacitor C3 is electrically connected between the first electrode and the second electrode of the light-emitting element OLED. The third capacitor C3 includes a first electrode E3-1 connected to the first electrode of the light-emitting element OLED and a second electrode E3-2 connected to the second electrode of the light-emitting element OLED.

[0062] The operation of pixel PXij will be described in more detail with reference to Figures 2 and 3. The display device DD (see Figure 1) displays an image every frame period. The first group of scan lines, the second group of scan lines, the third group of scan lines, and the light emission signal lines are sequentially scanned during the frame period. Figure 3 shows a part of the frame period.

[0063] 3, each of the signals Ei, GRi, GWi, and GIi has a high level (V-HIGH) during a certain period and a low level V-LOW during a certain period. The first to fifth N-type transistors T1 to T5 are turned on when the corresponding control signal has a high level V-HIGH.

[0064] The non-light emitting period includes an initialization period IP, a compensation period CP, and a writing period WP. During the initialization period IP, the third transistor T3 and the fourth transistor T4 are turned on. The first node ND1 is initialized to a first voltage Vref. The second node ND1 is initialized to a second voltage Vint. The first capacitor C1 is initialized to a difference between the first voltage Vref and the second voltage Vint. The second capacitor C2 is initialized to a difference between the second power supply voltage ELVDD and the second voltage Vint. The third capacitor C3 is initialized to a difference between the first power supply voltage ELVSS and the second voltage Vint.

[0065] During the compensation period CP, the third transistor T3 and the fifth transistor T5 are turned on, and the first capacitor C1 is compensated for with a voltage equivalent to the threshold voltage of the first transistor T1.

[0066] During the write period WP, ​​the second transistor T2 is turned on. The second transistor T2 outputs a voltage (or data voltage) corresponding to the data signal DS. As a result, the first capacitor C1 is charged with a voltage level corresponding to the data signal DS. The first capacitor C1 is charged with the data signal DS, which is compensated for by the threshold of the first transistor T1. Although the threshold of the driving transistor differs for each pixel PX (see FIG. 1), the pixel PXij shown in FIGS. 2 and 3 can supply a current proportional to the data signal DS to the light emitting element OLED regardless of the deviation in the threshold of the driving transistor.

[0067] Next, during the light emitting period, the fifth transistor T5 is turned on. The first transistor T1 provides a current corresponding to the charge capacity stored in the first capacitor C1 to the light emitting element OLED. The light emitting element OLED can emit light with a brightness corresponding to the data signal DS.

[0068] 4 is a cross-sectional view of a display panel DP according to an embodiment of the present invention, showing a cross section of a portion corresponding to a part of the configuration of the pixel PXij shown in FIG.

[0069] 4, the display panel DP may include a base layer BS, a circuit element layer DP-CL disposed on the base layer BD, a display element layer DP-OLED, and an encapsulation layer TFE. The display panel DP may further include a functional layer such as an anti-reflection layer or a refractive index adjustment layer. The circuit element layer DP-CL may include at least a plurality of insulating layers and circuit elements. The insulating layers described below may include organic layers and / or inorganic layers.

[0070] An insulating layer, a semiconductor layer, and a conductive layer are formed by a process such as coating, deposition, etc. Then, the insulating layer, the semiconductor layer, and the conductive layer are selectively patterned by a photolithography and etching process. By such a process, a semiconductor pattern, a conductive pattern, a signal line, etc. are formed. Patterns disposed in the same layer are formed by the same process.

[0071] The base layer BS may include a synthetic resin film. The synthetic resin film includes a thermosetting resin. In particular, the synthetic resin layer is a polyimide-based resin layer, but the material is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene-based resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a ferrylene-based resin. Alternatively, the base layer may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate. The base layer may include a first polyimide layer, a second polyimide layer, and an inorganic layer disposed therebetween.

[0072] At least one inorganic layer is formed on the upper surface of the base layer BS. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in a multilayer (stacked film). The multilayer inorganic layer may constitute a barrier layer BRL and / or a buffer layer BFL, which will be described later. The barrier layer BRL and the buffer layer BFL may be selectively disposed.

[0073] The barrier layer BRL prevents foreign matter from entering from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of these may be provided in a plurality of layers, and the silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0074] A conductive layer (hereinafter, a first conductive layer) is disposed on the barrier layer BRL. The first conductive layer may include a plurality of conductive patterns. A partial pattern of the first conductive layer is shown in FIG. 4. A first lower gate G1-2, a second lower gate G2-2, and a first conductive pattern P1 are shown as examples of the conductive patterns.

[0075] The first conductive pattern defines the second electrode E2-2 of the second capacitor C2 shown in Fig. 2. Although the first lower gate G1-2 and the first conductive pattern P1 are shown separated from each other in Fig. 4, they may be electrically connected to each other. They may be connected to each other via a conductive pattern disposed on another layer, or may have an integral shape on a plane.

[0076] The buffer layer BFL may be disposed on the barrier layer BRL to cover the first lower gate G1-2, the second lower gate P2, and the first conductive pattern P1. The buffer layer BFL improves the bonding strength between the base layer BS and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL includes a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer are alternately stacked.

[0077] A semiconductor layer is disposed on the buffer layer BFL. The semiconductor layer may include a plurality of semiconductor patterns. In the present embodiment, the semiconductor pattern may be a metal oxide pattern SP. The metal oxide semiconductor pattern SP may include a crystalline or amorphous oxide semiconductor. For example, the metal oxide semiconductor pattern SP may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), and these oxides. The oxide semiconductor may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZnO), zinc-indium oxide (ZIO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), or the like.

[0078] The metal oxide semiconductor pattern SP may include a plurality of regions that are distinguished according to whether the metal oxide is reduced or not. The region where the metal oxide is reduced (hereinafter, referred to as the reduced region) has higher conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as the non-reduced region). The reduced region essentially functions as a source region, drain region, or signal transmission region of a transistor. The non-reduced region essentially corresponds to a channel region (or semiconductor region, or non-reduced region) of a transistor. In other words, one part of the semiconductor pattern may be the channel region of the transistor, another part may be the source region or drain region of the transistor, and still another part may be the signal transmission region.

[0079] In effect, the first upper gate G1-1 described later defines the channel region A1 of the first transistor T1, and the second upper gate G2-1 described later defines the channel region A2 of the second transistor T2. The length of the channel region A1 of the first transistor T1 is determined so as to correspond to the width of the first upper gate G1-1, and the length of the channel region A2 of the second transistor T2 is determined so as to correspond to the width of the second upper gate G2-1.

[0080] The source region or drain region may be the source or drain of the transistors T1 to T4 described in Fig. 2. The source or drain of the transistors T1 to T5 may include the source or drain region of the semiconductor pattern described above and a conductive pattern connected thereto. Hereinafter, for convenience of explanation, the source region or drain region of the metal oxide semiconductor pattern SP will be referred to as the source or drain.

[0081] 4, the first transistor T1 includes a metal oxide semiconductor pattern SP including a source S1, a channel region A1, and a drain D1. The source S1 and drain D1 of the first transistor T1 extend in opposite directions from the channel region A1. The source S2, channel region A2, and drain D2 of the second transistor T2 are also formed from semiconductor patterns.

[0082] The above-mentioned first and second lower gates G1-2 and G2-2 have a function of a light-shielding pattern. The first and second lower gates G1-2 and G2-2 are disposed below the channel region A1 of the first transistor T1 and the channel region A2 of the second transistor T2, respectively, and block light incident thereon from the outside. The first and second lower gates G1-2 and G2-2 prevent external light from changing the voltage-current characteristics of the first and second transistors T1 and T2.

[0083] A first insulating layer 10 is disposed on the buffer layer BFL. In this embodiment, the first insulating layer 10 is not formed over the entire display panel DP, but overlaps only a channel region of a transistor or a specific conductive pattern described later. The first insulating layer 10 includes a plurality of insulating patterns. In FIG. 4, a first insulating pattern 10-1, a second insulating pattern 10-2, and a third insulating pattern 10-3 are exemplarily shown. In one embodiment of the present invention, the first insulating layer 10 may not be patterned. Here, the first insulating layer 10 covers the metal oxide semiconductor pattern SP.

[0084] The first insulating pattern 10-1 and the second insulating pattern 10-2 overlap a first upper gate G1-1 and a second upper gate G2-1, respectively, which will be described later. The third insulating pattern 10-3 overlaps a second conductive pattern P2, which will be described later.

[0085] A conductive layer (hereinafter, a second conductive layer) is disposed on the first insulating layer 10. The second conductive layer may include a plurality of conductive patterns overlapping the first insulating layer 10. In FIG. 4, a first upper gate G1-1, a second upper gate G2-1, and a second conductive pattern P2 are shown as examples of the conductive patterns of the second conductive layer. Since the second conductive layer and the first insulating layer 10 are etched through the same process, the conductive pattern of the second conductive layer and the insulating pattern of the first insulating layer 10 may have substantially the same shape. The edges of the conductive patterns of the second conductive layer and the insulating pattern of the first insulating layer 10 that overlap each other are aligned. The first upper gate G1-1 defines the first electrode E1-1 of the first capacitor C1 shown in FIG. 2. In a plan view, the first upper gate G1-1 may extend from the first electrode E1-1 of the first capacitor C1, and thus the first upper gate G1-1 may be defined as a portion of the first electrode E1-1 of the first capacitor C1.

[0086] The second conductive pattern defines a first electrode E2-1 of the second capacitor C2 shown in Figure 2. Although not shown, the second conductive pattern P2 may be electrically connected to a second voltage line VL2.

[0087] A second insulating layer 20 is disposed on the buffer layer BFL to cover the first upper gate G1-1, the second upper gate G2-1, and the second conductive pattern P2. The second insulating layer 20 is an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The second insulating layer 20 may cover the source S1 and drain D1 of the first transistor T1 and the source S2 and drain D2 of the second transistor T2. The second insulating layer 20 may cover each side of the first insulating pattern 10-1, the second insulating pattern 10-2, and the third insulating pattern 10-3.

[0088] A metal oxide pattern MOP is disposed on the second insulating layer 20, the details of which will be described later with reference to FIG.

[0089] A conductive layer (hereinafter, the third conductive layer) is disposed on the second insulating layer 20. The third conductive layer includes a plurality of conductive patterns overlapping the second insulating layer 20. The third conductive layer includes a third conductive pattern P3 overlapping the first upper gate G1-1. The third conductive pattern P3 defines the second electrode E1-2 of the first capacitor C1 shown in FIG. 2. In a plan view, the third conductive pattern P3 extends from the second electrode E1-2 of the first capacitor C1, thereby defining the third conductive pattern P3 as a portion of the second electrode E1-2 of the first capacitor C1.

[0090] In one embodiment of the present invention, even if the third conductive layer includes a conductive pattern, the third conductive pattern P2 overlapping the first upper gate G1-1 may be omitted, that is, the second electrode E1-2 of the first capacitor C1 does not need to overlap the first upper gate G1-1.

[0091] A third insulating layer 30 is disposed on the second insulating layer 20 to cover the third conductive layer P3. In this embodiment, the third insulating layer 30 is an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure.

[0092] A conductive layer (hereinafter, a fourth conductive layer) is disposed on the third insulating layer 30. The fourth conductive layer may include a plurality of conductive patterns. The fourth conductive layer may include a plurality of connecting electrodes. FIG. 4 exemplarily illustrates first to third connecting electrodes CNE1 to CNE3. The first connecting electrode CNE may be connected to the first conductive pattern P1 through a contact hole 113 penetrating the buffer layer BFL and the second and third insulating layers 20 and 30, connected to the first source S1 through a contact hole 115 penetrating the second and third insulating layers 20 and 30, and connected to the third conductive pattern P3 through a contact hole 117 penetrating the third insulating layer 30. The second connecting electrode CNE2 may be connected to the second source S2 through a contact hole 106 penetrating the second and third insulating layers 20 and 30, and the third connecting electrode CNE3 may be connected to the second drain D2 through a contact hole 107 penetrating the second and third insulating layers 20 and 30.

[0093] A fourth insulating layer 40 covering the fourth conductive layer is disposed on the third insulating layer 30. In this embodiment, the fourth insulating layer 40 may be an organic layer and may have a single-layer structure, but is not limited thereto.

[0094] A conductive layer (hereinafter, a fifth conductive layer) is disposed on the fourth insulating layer 40. The fifth conductive layer includes a plurality of conductive patterns. The fifth conductive layer includes a fourth connecting electrode CNE4. The fourth connecting electrode CNE4 is connected to the first connecting electrode CNE1 via a contact hole 203 penetrating the fourth insulating layer 40.

[0095] The fifth conductive layer further includes a data line DLj and a first voltage line VL1. The data line DLj is connected to the third connecting electrode CNE3 through a contact hole 205 penetrating the fourth insulating layer 40. A portion of the first voltage line VL1 overlapping a first electrode AE ​​of the light emitting element OLED, which will be described later, defines a second electrode E3-2 of the third capacitor C3 shown in FIG. 2. A portion of the first electrode AE ​​of the light emitting element OLED defines a first electrode E3-1 of the third capacitor C3 shown in FIG. 2.

[0096] A fifth insulating layer 50 covering the fourth conductive layer is disposed on the fourth insulating layer 40. In this embodiment, the fifth insulating layer 50 may be an organic layer and may have a single-layer structure, but is not limited thereto.

[0097] A first electrode AE ​​of the light-emitting element OLED is disposed on the fifth insulating layer 50. The first electrode AE ​​is an anode. A pixel defining film PDL is disposed on the fifth insulating layer 50. The first electrode AE ​​is connected to a fourth connecting electrode CNE4 through a contact hole 301 penetrating the fifth insulating layer 50.

[0098] The opening OP of the pixel definition film PDL exposes at least a portion of the first electrode AE. The opening OP of the pixel definition film PDL defines a light-emitting area PXA. For example, a plurality of pixels PX (see FIG. 1) may be arranged in a regular pattern on the plane of the display panel DP (see FIG. 1). The area in which the plurality of pixels PX are arranged is defined as a pixel area, and one pixel area PXA may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA. The non-light-emitting area NPXA may surround the light-emitting area PXA.

[0099] The hole control layer HCL may be disposed in common to the light emitting region PXA and the light emitting element region NPXA. A common layer such as the hole control layer HCL may be formed in common to a plurality of pixels PX. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0100] The light emitting layer EML is disposed on the hole control layer HCL. The light emitting layer EML may be disposed only in an area corresponding to the opening OP. The light emitting layer EML may be formed separately for each of the plurality of pixels PX.

[0101] In this embodiment, a patterned light emitting layer EML is shown as an example, but the light emitting layer EML may be disposed in common to a plurality of pixels PX. The commonly disposed light emitting layer EML may generate white light or blue light. The light emitting layer EML may have a multi-layer structure.

[0102] An electronic control layer ECL may be disposed on the light emitting layer EML. The electronic control layer ECL may include an electron transport layer and an electron injection layer. A second electrode CE may be disposed on the electronic control layer ECL. The electronic control layer ECL and the second electrode CE may be disposed in common to a plurality of pixels PX.

[0103] A thin film encapsulation layer TFE is disposed on the second electrode CE. The thin film encapsulation layer TFE is disposed in common to a plurality of pixels PX. In this embodiment, the thin film encapsulation layer TFE directly covers the second electrode CE. In one embodiment of the present invention, a capping layer may be further disposed to directly cover the second electrode CE. In one embodiment of the present invention, the stacked structure of the light emitting element OLED may have a structure that is inverted from the structure shown in FIG. 4.

[0104] The thin film encapsulation layer TFE includes at least an inorganic layer or an organic layer. In one embodiment of the present invention, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer disposed therebetween. In one embodiment of the present invention, the thin film encapsulation layer may include a plurality of inorganic layers and a plurality of organic layers that are alternately stacked.

[0105] Fig. 5 is a graph comparing voltage-current characteristics of an oxide transistor and a silicon transistor. Fig. 6 is an enlarged cross-sectional view of a first transistor T1 according to an embodiment of the present invention. Fig. 7 is a graph comparing voltage-current characteristics of an oxide transistor according to an embodiment of the present invention and an oxide transistor according to a comparative example.

[0106] The fifth graph G1 shows the voltage-current characteristic of a P-type silicon transistor. The second graph G2 shows the voltage-current characteristic of an N-type oxide transistor. According to the first graph G1 and the second graph G2, it can be seen that the range DA2 of the gate voltage Vg (hereinafter, the driving voltage range) of the oxide transistor having the driving current Ids of 1 nA to 500 nA is narrower than the range DA1 of the gate voltage Vg of the silicon transistor having the driving current Ids of 1 nA to 500 nA. If the driving voltage range is narrow, it may be necessary to precisely control the gray scale voltage to express a plurality of gray scales. On the other hand, the oxide transistor has an advantage of reducing leakage current compared to the silicon transistor.

[0107] As will be described later, the driving voltage range of the first transistor T1 can be further widened by controlling the resistance of the source S1 and drain D1 of the first transistor T1, which will be described in more detail with reference to Figures 6 and 7.

[0108] 6, the buffer layer BFL includes a silicon nitride layer BFL1 and a silicon oxide layer BFL2. The first insulating pattern 10-1 includes a silicon oxide layer. The first upper gate G1-1 and the third conductive pattern P3 have a single layer or multi-layer (lamination) structure made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0109] The second insulating layer 20 may include a silicon oxide layer or a silicon oxynitride layer. The third insulating layer 30 may include a silicon oxynitride layer 31 and a silicon nitride layer 32 disposed on the silicon oxynitride layer 31.

[0110] According to the present embodiment, a metal oxide pattern MOP may be disposed between the third conductive pattern P3 and the second insulating layer 20. The thickness of the metal oxide pattern MOP is 100 Å to 300 Å. The metal oxide pattern MOP may include any one of oxides of indium (In), tin (Sn), zinc (Zn), gallium (Ga), magnesium (Mg), hafnium (Hf), and titanium (Ti), or a mixture of any one of metals of indium (In), tin (Sn), zinc (Zn), gallium (Ga), magnesium (Mg), hafnium (Hf), and titanium (Ti) and any one of these oxides.

[0111] The metal oxide pattern MOP may be formed by a sputtering method or a metal organic chemical vapor deposition (MOCVD) method, which uses oxygen gas and supplies oxygen to the second insulating layer 20 disposed below. In this sense, the metal oxide pattern MOP may be defined as an oxygen supplying pattern. The oxygen supplied to the second insulating layer 20 is diffused to the lower side of the second insulating layer 20 during a subsequent heat treatment process and moves to the oxide semiconductor pattern. The first upper gate G1-1 is disposed above the channel region A1 and may block oxygen diffusing toward the channel region A1. Accordingly, the amount of oxygen supplied to the channel region A1 is less than the amount of oxygen supplied to the source S1 and the drain D1.

[0112] Hydrogen is supplied to the source S1 and the drain D1 during the process of forming the second insulating layer 20 and the third insulating layer 30. In particular, the process of forming the silicon nitride layer 32 maintains a high hydrogen partial pressure, so that a large amount of oxygen is provided to the oxide semiconductor pattern.

[0113] Hydrogen impinges on the carriers, reducing the resistance of the metal oxide pattern, especially the source S1 and drain D1. The first upper gate G1-1 is disposed above the channel region A1, blocking hydrogen diffusing toward the channel region A1, so that the channel region A1 maintains semiconducting properties compared to the source S1 and drain D1.

[0114] The resistance of the source S1 and the drain D1 is determined by the amount of hydrogen and oxygen supplied to the source S1 and the drain D1 during the above-mentioned process. The oxygen supplied to the source S1 and the drain D1 reduces the oxygen deficiency in the source S1 and the drain D1 and inhibits the combination of the oxygen deficiency with hydrogen, thereby preventing the resistance of the source S1 and the drain D1 from decreasing.

[0115] During the process of forming the metal oxide pattern MOP, even if the first upper gate G1-1 covers the channel region A1, oxygen diffuses from the boundary region between the channel region A1 and the source region S1 or between the channel region A1 and the drain D1 toward the edge region of the channel region A1. Even if hydrogen diffuses from the boundary region between the channel region A1 and the source region S1 or between the channel region A1 and the drain D1 toward the peripheral region of the channel region A1 during the process of forming the silicon nitride layer 32 of the third insulating layer 30 described above, the oxygen deficiency is eliminated by the oxygen already supplied, so that hydrogen is prevented from bonding to the channel region A1. As a result, the effective length of the channel region A1 is prevented from becoming smaller than the length of the channel region A1.

[0116] The length of the channel region A1 is less than 3 μm, and the channel region A1 has a short channel characteristic. According to the above-mentioned principle, the effective length of the channel region A1 is maintained substantially the same as the length of the channel region A1 corresponding to the width of the first upper gate G1-1.

[0117] A first graph G10 of FIG. 7 shows a voltage-current curve of a transistor in which the metal oxide pattern MOP of FIG. 6 is not formed, and a second graph G20 of FIG. 7 shows a voltage-current curve of the first transistor T1 of FIG. 6. The sheet resistance of the source S1 and drain D1 of the transistor in which the metal oxide pattern MOP is not formed is 217.75 Ω / □ (or Ω / sq), and the sheet resistance of the source S1 and drain D1 of the first transistor T1 of FIG. 6 is measured to be 513.32 Ω / □. The driving voltage V of the transistor in which the metal oxide pattern MOP is not formed GSThe range of DA10 is 1.92V, whereas the driving voltage V of the first transistor T1 in FIG. GS The range of the DA20 was measured to be 2.1V.

[0118] As described with reference to FIG. 6, it can be seen from FIG. 7 that oxygen is injected during the formation of the metal oxide pattern MOP, thereby increasing the resistance of the source S1 and drain D1 of the first transistor T1 and widening the driving voltage range of the first transistor T1.

[0119] 8a to 8f are cross-sectional views showing a manufacturing process of a display panel DP according to an embodiment of the present invention. Detailed description of the same configuration as that described with reference to FIGS.

[0120] As shown in FIG. 8a, a first transistor T1 is formed on the base layer BS. The first transistor T1 includes a first lower gate G1-2, a metal oxide semiconductor pattern SP, a first insulating pattern 10-1, and a first upper gate G1-1 as described with reference to FIG. 4. The second transistor T2 may be formed by the same process as the process for forming the first transistor T1. The first conductive pattern P1 of the second capacitor C2 may be formed by the same process as the first lower gate G1-2, and the second conductive pattern P2 of the second capacitor C2 may be formed by the same process as the first upper gate G1-1.

[0121] A second insulating layer 20 is formed on the base layer BS to cover the first upper gate G1-1, the first source S1, and the first drain D1. For example, an inorganic material may be deposited using a plasma enhanced chemical vapor deposition (PECVD) method.

[0122] Next, as shown in FIG. 8b, a metal oxide layer MOL is formed on the second insulating layer 20. The metal oxide layer MOL may be formed using a sputtering method or an MOCVD method. In the step of forming the metal oxide layer MOL, the partial pressure of oxygen gas with respect to the reaction gas may be 50% to 100%. The reaction gas may further include silane gas, fluorinated silane gas, nitrogen dioxide, etc.

[0123] In the deposition process of the metal oxide layer MOL, oxygen (eg, oxygen radicals, oxygen atoms, or oxygen ions) may be supplied to the second insulating layer 20 by oxygen plasma, and then the oxygen may be diffused into the metal oxide layer semiconductor pattern SP by a heat treatment process.

[0124] Next, as shown in FIG. 8c, a conductive pattern P3 is formed on the metal oxide layer MOL. After the conductive layer is formed, the conductive layer is patterned by a photolithography process and an etching process. In one embodiment of the present invention, the process of forming the conductive pattern P3 overlapping the first upper gate G1-1 may be omitted.

[0125] Next, as shown in FIG. 8d, the metal oxide layer MOL is patterned using the conductive pattern P3 as a mask. The metal oxide layer MOL may be patterned through a wet etching process. A metal oxide pattern MOP aligned with the conductive pattern P3 may be formed from the metal oxide layer MOL. The edge of the conductive pattern P3 may be aligned with the edge of the metal oxide pattern MOP.

[0126] If the conductive pattern P3 is not formed, the metal oxide layer MOL may be patterned using a separate mask pattern, which may be a photoresist pattern.

[0127] If the conductive pattern P3 is not formed, the metal oxide layer MOL may be completely removed. Since oxygen has already been supplied to the second insulating layer 20 in the step of forming the metal oxide layer MOL, even if the metal oxide layer MOL is completely removed, the resistance of the first source S1 and the first drain D1 can be controlled as described with reference to Fig. 6. On the other hand, if the metal oxide pattern MOP remains, oxygen will further diffuse from the metal oxide pattern MOP to the metal oxide semiconductor pattern SP during a subsequent process.

[0128] 8e, a third insulating layer 30 is formed on the second insulating layer 20. A silicon oxynitride layer and a silicon nitride layer are sequentially formed using a PECVD method, as shown in FIG.

[0129] 8f, a light emitting element OLED is formed on the third insulating layer 30. Contact holes 106, 107, 113, 115, and 117 are formed by photolithography and etching processes. Next, a metal layer is formed and then patterned to form first to third connecting electrodes CNE1, CNE2, and CNE3.

[0130] Next, the process of forming the insulating layer and the process of forming the conductive pattern are repeated. A fourth insulating layer 40 is formed, and then the data line DLj, the first voltage line VL1, and the fourth connecting electrode CNE4 are formed. A fifth insulating layer 50 is formed on the fourth insulating layer 40. Next, a light emitting element OLED is formed on the fifth insulating layer 50.

[0131] 9 is an enlarged cross-sectional view of a first transistor T1 according to an embodiment of the present invention. In the following, detailed description of the same configuration as the first transistor T1 described with reference to FIG.

[0132] According to this embodiment, unlike the illustration of Fig. 6, the third conductive pattern P3 is omitted. The metal oxide pattern MOP is formed by patterning the metal oxide layer using an additional mask pattern.

[0133] The metal oxide pattern MOP may be a floating pattern or may correspond to the second electrode E1-2 of the first capacitor C1 like the third conductive pattern P3. The metal oxide pattern MOP is reduced in the process of forming the third insulating layer 30 to reduce its resistance and may function as an electrode.

[0134] 10 is an enlarged cross-sectional view of a first transistor according to an embodiment of the present invention. FIGs. 11a to 11f are cross-sectional views showing a manufacturing process of a display panel according to an embodiment of the present invention. Hereinafter, detailed description of the same configuration as the first transistor T1 described with reference to FIGs. 1 to 9 will be omitted.

[0135] 10, the metal oxide pattern MOP may be disposed on an upper surface of the first upper gate G1-1. The metal oxide pattern MOP may contact an upper surface of the first upper gate G1-1. The second insulating layer 20 may cover the metal oxide pattern MOP in an area overlapping the first upper gate G1-1. The third conductive pattern P3 may be disposed on the second insulating layer 20.

[0136] 11a, a metal oxide semiconductor pattern SP is formed on the base layer BS. Next, a first insulating layer 10 and a metal layer G1-P are formed on the buffer layer BFL.

[0137] As shown in FIG. 11b, a first upper gate G1-1 is formed from the metal layer G1-P by a photolithography process and an etching process.

[0138] 11c, a metal oxide layer MOL covering the first upper gate G1-1 is formed on the first insulating layer 10. In the process of forming the metal oxide layer MOL, oxygen is supplied to the first insulating layer 10, and oxygen may be injected into the region of the metal oxide semiconductor pattern SP exposed from the first upper gate G1-1 by a heat treatment process.

[0139] 11d, a metal oxide pattern MOP is formed from the metal oxide layer MOL by photolithography and etching processes. According to an embodiment of the present invention, the metal oxide layer MOL may be entirely removed.

[0140] As shown in Fig. 11e, a first insulating pattern 10-1 is formed from the first insulating layer 10 by an etching process. In the etching process of Fig. 11e, the first upper gate G1-1 may be used as a mask. In one embodiment of the present invention, the patterning process of the first insulating layer 10 may be omitted. Here, the first insulating pattern 10-1 may cover the entire metal oxide semiconductor pattern SP.

[0141] As shown in Fig. 11f, a third insulating layer 30 is formed on the second insulating layer 20. A silicon oxynitride layer 31 and a silicon nitride layer 32 are sequentially formed using a PECVD method. Although the manufacturing process of the display panel has been described with reference to the first transistor T1 in Figs. 11a to 11f, subsequent processes may be added. The subsequent processes are the same as those described with reference to Figs. 8e and 8f, and therefore will not be described in detail.

[0142] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or those having ordinary knowledge in the art that the present invention may be modified and changed in various ways without departing from the spirit and technical scope of the present invention as set forth in the claims below.

[0143] Therefore, the technical scope of the present invention should be determined not by the contents described in the detailed description of the specification, but by the claims. [Industrial Applicability]

[0144] Display devices indispensably include thin film transistors as pixel driving circuits. Improvements in the performance of thin film transistors are useful for improving the display quality of display devices. Oxide transistors, which have a wider driving voltage range, are likely to be applied to display devices.

Claims

1. a plurality of insulating layers; A light-emitting element; a pixel circuit electrically connected to the light emitting device; The pixel circuit includes a first transistor, The first transistor is a metal oxide semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region; a first gate disposed on the metal oxide semiconductor pattern and overlapping the channel region in a plan view; a metal oxide pattern disposed over the first gate.

2. The plurality of insulating layers include a first insulating layer disposed between the channel region and the first gate; a second insulating layer having a first portion disposed between the first gate and the metal oxide pattern, a second portion disposed over the source region, and a third portion disposed over the drain region; The display device of claim 1 , further comprising: a third insulating layer disposed on the second insulating layer and the metal oxide pattern.

3. the first insulating layer includes a silicon oxide layer; the second insulating layer includes a silicon oxide layer or a silicon oxynitride layer; The display device according to claim 2 , wherein the third insulating layer includes a silicon oxynitride layer and a silicon nitride layer disposed on the silicon oxynitride layer.

4. The display device according to claim 2 , wherein the second insulating layer covers a side surface of the first insulating layer.

5. The display device of claim 1 , wherein the metal oxide pattern is electrically connected to the first gate.

6. The display device of claim 1 , wherein the pixel circuit further comprises a conductive pattern disposed over the metal oxide pattern.

7. a corresponding insulating layer of the plurality of insulating layers is disposed between the first gate and the conductive pattern; 7. The display of claim 6, wherein the first gate and the conductive pattern define a capacitor.

8. The display device according to claim 7 , wherein the first transistor controls a drive current for the light-emitting element based on a charge capacity of the capacitor.

9. The pixel circuit further includes a second transistor, the second transistor includes a metal oxide semiconductor pattern; The display device of claim 7 , wherein the second transistor provides a data voltage to the capacitor.

10. The display device of claim 6 , wherein a periphery of the metal oxide pattern is aligned with a periphery of the conductive pattern.

11. 2. The display device according to claim 1, wherein the length of the channel region is 3 [mu]m or less.

12. The display device of claim 1 , wherein the first transistor further comprises a second gate, the second gate being disposed under the metal oxide semiconductor pattern and electrically connected to the first gate.

13. The display device of claim 1 , wherein the metal oxide pattern includes at least one of indium (In), tin (Sn), zinc (Zn), gallium (Ga), magnesium (Mg), hafnium (Hf), and titanium (Ti).

14. 2. The display device of claim 1, wherein the metal oxide pattern has a thickness of 100 to 300 Å.

15. forming a transistor on a base layer, the transistor including a metal oxide semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region, a first insulating layer disposed on the channel region, and a gate disposed on the first insulating layer; forming a second insulating layer covering the gate, the source region, and the drain region; forming a metal oxide layer on the second insulating layer; Etching at least a portion of the metal oxide layer; forming a third insulating layer on the second insulating layer.

16. The method of claim 15, further comprising forming a conductive pattern on the metal oxide layer so as to overlap the gate.

17. In the step of etching at least a portion of the metal oxide layer, the conductive pattern is used as a mask; The method for manufacturing a display device according to claim 16 , wherein a metal oxide pattern is formed from the metal oxide layer so as to overlap the conductive pattern in a plan view.

18. The method of claim 17 , wherein an edge of the metal oxide pattern is aligned with an edge of the conductive pattern.

19. 16. The method of claim 15, wherein in the step of forming the metal oxide layer, a partial pressure of the oxygen gas relative to the reactive gas is 50% to 100%.

20. forming a transistor including a metal oxide semiconductor pattern on a base layer, the metal oxide semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region; a first insulating layer disposed on the base layer and covering the metal oxide semiconductor pattern; and a gate disposed on the first insulating layer; forming a metal oxide layer over the first insulating layer covering the gate; Etching at least a portion of the metal oxide layer; forming a second insulating layer on the base layer.

Images