Time-of-Flight Sensors and Electronic Devices

Abstract

An indirect time-of-flight sensor having a pixel array including a plurality of pixels and a readout circuit configured to read out charge collected at each of three or more taps, each pixel having the three or more taps.

Description

[Technical field]

[0001] The present disclosure relates generally to the field of time-of-flight imaging, and more particularly to devices, sensors, and methods for capturing time-of-flight images. [Background technology]

[0002] A Time-of-Flight (ToF) camera is a range imaging camera system that determines the range of an object by measuring the time of flight of a light signal between the camera and the object for each point in the image. Typically, a ToF camera has an illumination section (LED or VCSEL, Vertical-Cavity Surface-Emitting Laser) that illuminates the scene with modulated light. An array of pixels in the ToF camera collects the light reflected from the scene and measures the phase shift, which provides information about the travel time of the light and therefore information about the distance.

[0003] Currently, acquisition of optical signals at short distances is typically covered by indirect time-of-flight (iToF) systems, while acquisition at medium to long distances is typically covered by direct time-of-flight (dToF) systems.

[0004] A pixel of a ToF camera typically includes one or more photosensitive elements (e.g., photodiodes). The photoconductor converts the incoming light into an electric current. Typically, in the field of time-of-flight, the pixels included in the ToF image are, for example, current-assisted photonic demodulator (CAPD) pixels, gate-controlled iToF, etc. A switch (e.g., transfer gate) connected to the photodiode directs the current to one or more memory elements (e.g., capacitors) that function as storage elements to accumulate and / or store the electric charge. The TOF sensor unit pixel is usually controlled by a modulation signal coming from one or more mixed drivers.

[0005] A typical ToF camera pixel generates a charge that represents the correlation between the illuminated light and the backscattered light. To enable the correlation between the illuminated light and the backscattered light, each pixel is controlled by a common modulation input coming from one or more mixing drivers. The modulation input to the pixel is typically synchronized with the illumination block modulation.

[0006] Current iToF systems using 2-tap sensors produce correlation with unambiguous range inversely proportional to the modulation frequency. When using a lower modulation frequency for longer distance measurements, the maximum phase shift remains the same (2K). This leads to lower depth resolution and higher depth noise in the distance measurements.

[0007] It is therefore generally desirable to provide techniques for improving depth image determination in iToF cameras.

[0008] By increasing the number of taps in the sensor, a larger phase shift can be measured for a given depth range, i.e., allowing a higher effective modulation frequency and therefore reduced depth noise.

[0009] The maximum phase shift in an n-tap system, where n>2, is (n-1)π, compared to 2π for a 2-tap system.

[0010] Although the current 2-tap system has some mismatch, the actual measurement technique (with 4 measurement phases) has an inherent cancellation of the mismatch between the taps and the readout stage. Directly extending the existing pixel structure from 2 to N taps may result in some measurement errors, since the N-tap measurement technique does not have this cancellation. In order to reduce the mismatch between the taps, some pixel features need to be predicted. Summary of the Invention

[0011] According to a first aspect, the present disclosure provides a time-of-flight sensor comprising a pixel array including a plurality of pixels, each pixel having three or more taps, and a readout circuit configured to read out charge collected at each of the three or more taps.

[0012] According to a second aspect, the present disclosure provides an electronic device comprising an indirect time-of-flight sensor comprising a pixel array including a plurality of pixels, each pixel having three or more taps, and a readout circuit configured to read out charge collected at each of the three or more taps.

[0013] Further aspects are set out in the dependent claims, the following description and the drawings. [Brief description of the drawings]

[0014] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which: [Figure 1] 1 illustrates a schematic of the basic working principle of an indirect time-of-flight (iToF) imaging system that can be used for depth sensing. [Diagram 2] 1 illustrates a schematic diagram of one embodiment of a basic N-tap sensor included in an N-tap system. [Diagram 3] 1 illustrates a schematic diagram of an embodiment of an N-tap current-assisted photonic demodulator (CAPD) based pixel in top view. [Figure 4] 1 illustrates an embodiment of a circuit diagram for an N-tap CAPD-based ToF pixel having more than two taps (N>2), here N=9 CAPD taps. [Diagram 5] FIG. 13 shows a timing diagram for the control of mixing elements GD1-GD9 of an N-tap CAPD based pixel during exposure. [Figure 6] FIG. 11 is a timing diagram during exposure relating to control of mixing gates GD1 to GD8 of an N-tap CAPD-based pixel and control of GD9 as an overflow collector OFC. [Figure 7]7a and 7b show schematic diagrams in a top view and a cross-sectional view, respectively, of an embodiment of a first type of CAPD-based pixel including N-CAPD elements forming a CAPD-based pixel, respectively. [Figure 8] 8a illustrates, in top view, a schematic representation of an embodiment of a second type of CAPD-based pixel comprising N isolated CAPD-based unit cell elements forming a CAPD-based pixel, and FIG. 8b illustrates, in cross-sectional view, a schematic representation of an embodiment of a CAPD-based pixel comprising N isolated CAPD-based unit cell elements as described in relation to FIG. 8a. [Figure 9] 1 illustrates generally one embodiment of a first or second type CAPD based pixel, where the N-tap CAPD based pixel operates as one 16-tap pixel or four 4-tap pixels. [Figure 10a] FIG. 10 is a timing diagram during exposure for controlling the N-tap CAPD-based pixel of FIG. 9 operating as a 16-tap pixel. [Figure 10b] FIG. 10 is a timing diagram for controlling the N-tap CAPD-based pixel described in FIG. 9, where GD16 acts as an overflow collector OFC. [Figure 11a] FIG. 10 shows a timing diagram for controlling the N-tap CAPD-based pixel of FIG. 9 operating as four 4-tap pixels during exposure. [Figure 11b] FIG. 10 shows a timing diagram for the control of the N-tap CAPD-based pixel described in FIG. 9, where GD6, GD8, GD14 and GD16 are operating as overflow collectors OFC. [Figure 12] 1 illustrates an embodiment of an implementation layout of a basic trans-transfer gate (TG) based N-tap pixel, where the number of trans-transfer gates is N=8. [Figure 13] 13 illustrates an embodiment of the TG-based N-tap pixel schematic of FIG. 12; [Figure 14] 13 shows a timing diagram for the TG-based N-tap pixel 120 of FIG. 12 during integration. [Figure 15] 1 illustrates a schematic diagram of an embodiment of a TG-based N-tap pixel with a memory node in a top view. [Figure 16] FIG. 16 illustrates an embodiment of a schematic diagram of a TG-based N-tap pixel with memory nodes of FIG. 15, where the number of transfer gates is N=8. [Figure 17] FIG. 15 shows a readout timing diagram of a TG-based N-tap pixel with the memory node of FIG. 15, where the number of transfer gates is N=8, the readout stage is R=4, and the last transfer gate TG7 acts as an overflow gate OFG). [Figure 18] One embodiment of a cascaded TG-based N-tap pixel is shown in top view, with S=2, N1=4, N2=2, and R=8. [Figure 19] 19 illustrates an embodiment of the cascaded TG-based N-tap pixel schematic of FIG. 18; [Figure 20] FIG. 19 shows a timing diagram during integration of the cascaded TG-based N-tap pixel of FIG. 18, where the transfer gate TG3B acts as an overflow gate OFG. [Figure 21] 1 illustrates a schematic diagram of an embodiment of a cascaded TG-based N-tap pixel, where N=16, S=3, N1=4, N2=2, N3=2, and R=16. [Figure 22] FIG. 22 diagrammatically illustrates one embodiment of the cascaded TG-based N-tap pixel schematic of FIG. 21; [Diagram 23] 1 shows a schematic of a cascaded TG-based NTAP pixel with memory nodes, where S = 2, N1 = 4, N2 = 2, and R = 4. [Figure 24] 24 illustrates an embodiment of a schematic diagram of a cascaded TG-based N-tap pixel with memory nodes of FIG. 23. [Diagram 25]FIG. 24 shows a timing diagram during integration of a cascaded TG-based N-tap pixel with memory nodes of FIG. 23, where the transfer gate TX3B acts as an overflow gate OFG. [Figure 26] FIG. 24 shows a readout timing diagram of a cascaded TG-based N-tap pixel with the memory nodes of FIG. 23, where the second transfer gate TX3B acts as an overflow gate OFG. [Figure 27] 1 illustrates a schematic top view of one embodiment of a TG-based NTAP pixel with cycling memory nodes. [Figure 28] 28 illustrates an embodiment of a schematic diagram of a cascaded TG-based N-tap pixel with cycling memory nodes of FIG. 27. [Figure 29] FIG. 27 shows a timing diagram for memory cycle operation of a TG-based N-tap pixel with cycling memory nodes, where the transfer gate TG7 acts as an overflow gate OFG. [Diagram 30] 28 diagrammatically illustrates one embodiment of a conceptual representation for rotating charge in a TG-based N-tap pixel with cycling memory nodes of FIG. 27. [Diagram 31] 1 illustrates a schematic diagram of an embodiment of a cascaded TG-based NTAP pixel with cycling memory nodes in a top view. [Diagram 32] 32 illustrates an embodiment of a schematic diagram of a cascaded TG-based N-tap pixel with cycling memory nodes of FIG. 31 . [Diagram 33] 32 shows a timing diagram during integration of a cascaded TG-based N-tap pixel with memory nodes of FIG. 31, where the transfer gate TX3B acts as an overflow gate OFG. [Diagram 34] FIG. 32 shows a timing diagram for memory cycle operation of a cascaded TG-based N-tap pixel with cycling memory nodes, where the transfer gate TX3B acts as an overflow gate OFG. [Diagram 35]1 shows a schematic diagram of an embodiment of a cascaded TG-based N-tap pixel with cycling memory nodes and no central light collection area, where S=2, N1=4, N2=2, and R=4. [Diagram 36] 36 illustrates an embodiment of a schematic diagram 360 of a TG-based N-tap pixel with cycling memory nodes without a central light collection region of FIG. 35. [Figure 37] FIG. 36 shows a timing diagram during integration of a cascaded TG-based N-tap pixel with cycling memory nodes and no central light collecting area of ​​FIG. 35, where the transfer gate TX3B acts as an overflow gate OFG. [Figure 38] FIG. 35 shows a timing diagram for memory cycle operation of a cascaded TG-based N-tap pixel with cycling memory nodes without a central light collecting region, where transfer gate TX3B operates as an overflow gate OFG. [Figure 39] 1 illustrates a schematic diagram of an embodiment of a cascaded TG-based N-tap pixel with cycle memory nodes, where S=2, N1=4, N2=2, and R=4. [Diagram 40] 40 is a schematic diagram of an embodiment of a TG-based N-tap pixel schematic 400 with cycling memory nodes and a first stage CAPD modulation circuit of FIG. 39; [Diagram 41] FIG. 40 shows a timing diagram during integration of a cascaded TG-based N-tap pixel with cycling memory nodes and the first-stage CAPD modulation circuit of FIG. 39, where the transfer gate TX3B acts as an overflow gate OFG. [Diagram 42] FIG. 39 shows a timing diagram of the memory cycle operation of the cascaded TG-based N-tap pixel with cycling memory nodes and a first-stage CAPD modulation circuit, where the transfer gate TX3B acts as an overflow gate OFG. [Diagram 43]Figure 1 shows a schematic diagram in top view of one embodiment of a cascaded TG-based N-tap pixel with a cycling memory node, as well as a first-stage CAPD modulator and a second-stage photogate, where S = 2, N1 = 4, N2 = 2, and R = 4. [Diagram 44] FIG. 44 diagrammatically illustrates one embodiment of the cycling memory node of FIG. 43 and a schematic diagram of a TG-based N-tap pixel with a first-stage CAPD modulator and photogate. [Diagram 45] FIG. 44 shows a timing diagram during cycling memory nodes and integration of a cascaded TG-based N-tap pixel with a first-stage CAPD modulation circuit and photogate of FIG. 43, where the transfer gate TX3B acts as an overflow gate OFG. [Diagram 46] FIG. 44 shows a timing diagram for the memory cycle operation of a cascaded TG-based N-tap pixel having a cycling memory node and a first-stage CAPD modulation circuit and a photogate of FIG. 43, where the transfer gate TX3B acts as an overflow gate OFG. [Figure 47] 1 illustrates a schematic diagram of an embodiment of an iToF device that can implement a process for performing depth measurements using N-tap pixels. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Before describing the embodiments in detail with reference to FIGS. 1 to 47, a general description will be given.

[0016] As mentioned at the beginning, an indirect time-of-flight (iToF) camera has an illumination unit that illuminates an area of ​​interest with modulated light and a pixel array that includes a number of pixel units that collect light reflected from the same area of ​​interest. The pixel units are typically based on semiconductor technology. In semiconductors, the excitation of electrons from the valence band to the conduction band creates free charge carriers such as electron-hole pairs. This excitation leaves holes in the valence band that behave as positive charges, and electron-hole pairs are created.

[0017] Current iToF systems include image sensors with so-called "2-tap" type pixels, which are known to introduce mismatching between taps and through the readout stage, resulting in depth measurements with low accuracy and low signal-to-noise ratio (SNR). While there are operating modes to overcome this, they limit the possible frame rate, introduce motion artifacts, and require heavy post-processing. Thus, it is recognized that in some cases, an "N-tap" operating mode may be more appropriate. A "2-tap" iToF sensor may not be appropriate since current "2-tap" iToF sensors may not support an N-tap operating mode. N-tap operation may refer to the use of multiple taps (e.g., 7, 8, 9 or more, or less) instead of 2 taps, as is known for iToF, so that an iToF sensor may be comparable to a dToF sensor in terms of SNR under high ambient light. However, N-tap is not limited to the iToF case, as the principles of the present disclosure may be applied to dToF sensors or dToF readout circuits that are detected based on a modulated signal or taps, for example by detecting pulsed light. It is also recognized that reduced dark current, reduced tap mismatch, reduced mismatch associated with the readout, reduced pixel size, reduced light collection area, optimized charge transfer, etc. are desirable.

[0018] As a result, some embodiments relate to an indirect time-of-flight sensor that includes a pixel array including a plurality of pixels, each pixel having three or more taps, and a readout circuit configured to read out the charge collected at each of the three or more taps.

[0019] The indirect time-of-flight sensor iToF may be an imaging sensor having an N-tap pixel, where N indicates the number of taps provided in the pixel of the iToF sensor. The iToF sensor may also include additional circuitry. For example, the circuitry of the iToF sensor may include electronic components such as switching elements (gates, transistors, etc.), resistors, memory elements (capacitors, RAM, ROM, etc.), pixel circuits, storage devices, etc.

[0020] A tap may be any structure or configuration of the camera sensor that each pixel of the camera sensor uses to output data. For example, a tap may be a node where photocharges are collected. A pixel may be any single cell of the iToF sensor. When light is captured by the iToF sensor, a photosensor (e.g., a photodiode) in each pixel generates a charge. A signal corresponding to the charge accumulated in the pixel of the iToF sensor is transferred by readout electronics from the pixel to a processor for post-processing of the image.

[0021] The readout circuit may include a vertical scanner that provides clocks for normal pixel operations such as reset, select, etc. for the reset and readout phases. The readout circuit may further include a guide driver that provides special clocks required for N-tap operations. The readout circuit may further include an analog front end and ADC for digitization and subsequent readout. The readout circuit may further include a control unit that ensures synchronization across the vertical scanner, guide driver, and analog front end and ADC, including an illuminator. The illuminator may be a laser, a vertical cavity surface emitting laser (VCSEL), a light emitting diode (LED), etc. In some embodiments, the tap of each pixel may be configured to collect the charge generated by the light collection region. The light collection region may be a pinned photodiode (PPD), a partially pinned photodiode, a photogate (PG), etc.

[0022] In some embodiments, each pixel may include a mixing element, each mixing element corresponding to one of the taps. The mixing elements may be implemented, for example, as a mixing gate.

[0023] In some embodiments, each pixel is a current-assisted optical demodulator (CAPD)-based pixel. A CAPD-based pixel may include an N-CAPD tap, a reset transistor, a shutter transistor, an amplifier, and a select transistor. For example, a CAPD-based pixel may include nine taps, without limiting the disclosure in that respect. Alternatively, a CAPD-based pixel may include more than nine taps, or less than nine taps.

[0024] In some embodiments, one of the mixing elements can act as an overflow collector with a pulse duration longer than that of the remaining mixing elements of the mixing element, allowing less ambient light to be collected while keeping the amount of collected active light the same, thus improving the signal-to-noise ratio. The first purpose of the overflow collector is to protect the OFC from collecting charge from environmental light damage outside the integration period, e.g., during readout. The second purpose of the OFC can be to discard a portion of the incident reflected light corresponding to the unwanted range (range gate).

[0025] In some embodiments, each pixel may be formed by a CAPD element, which may include multiple mixing elements corresponding to multiple taps.

[0026] In some embodiments, each pixel may be formed by an isolated CAPD element, which is separated by an isolation element (eg, an implant), which may result in high resolution.

[0027] The isolated CAPD element may be configured to operate as either a 16-tap pixel or four 4-tap pixels, without limiting the disclosure in that respect. Alternatively, different, not necessarily symmetric configurations may be possible. The isolated CAPD element may be configured to operate as a single N-tap pixel, or as K (i.e., a plurality of) M-tap pixels, with K × M = N, or other configurations that are not necessarily symmetric. Such CAPD-based pixels may be readily adapted.

[0028] In some embodiments, the light collecting area may be a central light collecting area.

[0029] In some embodiments, each pixel may include a transfer gate, with each transfer gate corresponding to a respective tap.

[0030] In some embodiments, each pixel may be a transfer gate (TG) based pixel.

[0031] In some embodiments, each pixel may be a cascaded TG-based pixel.

[0032] In some embodiments, the readout circuitry may be configured to sequentially open the transfer gates of each tap of the pixel (high conductance state) for a predetermined period of time to obtain the depth measurement.

[0033] In some embodiments, one of the transfer gates may operate as an overflow gate with a pulse duration longer than the pulse duration of the remaining of the transfer gates to filter out ambient light.

[0034] In some embodiments, each transfer gate of a TG-based pixel can connect a central light collecting region to a respective floating diffusion (FD) region.

[0035] In some embodiments, the TG-based pixel may further include a memory node for intermediate charge storage. The TG-based pixel may include a source line node for intermediate charge storage. By performing intermediate charge storage of charge, dark current (DC) may be reduced, the memory node typically generates less DC than FD, generated noise may be reduced, and some readout stages may be shared, resulting in a relaxation of routing requirements, and ADC counts and pixel areas may be reduced. Thus, intermediate storage can save space in readout stages, output line routing, etc.

[0036] The TG-based pixel further comprises a floating diffusion region, a plurality of memory nodes connected thereto, and a respective plurality of second transfer gates, the plurality of memory nodes being connected to the floating diffusion region via the plurality of second transfer gates. The TG-based pixel may include at least one floating diffusion region. The plurality of memory nodes may be two or more memory nodes, and the respective plurality of second transfer gates may be two or more second transfer gates.

[0037] In some embodiments, the transfer gate is a first transfer gate, and the TG-based pixel further comprises a floating diffusion region, two or more memory nodes, and two or more respective second transfer gates, where the two or more memory nodes are connected to the floating diffusion region via the two or more second transfer gates. For example, the TG-based pixel may comprise at least one floating diffusion region, two or more respective memory nodes, and two or more respective second transfer gates, where each floating diffusion region may be connected to two respective memory nodes via two respective second transfer gates. In an exemplary configuration, the TG-based pixel may include four floating diffusion regions, where each floating diffusion region may be connected to two respective memory nodes via two respective second transfer gates.

[0038] In some embodiments, the TG-based pixel may further include a memory shift gate configured to transfer charge from one of the memory nodes to another of the memory nodes, the two memory nodes being adjacent to each other. Such transfer of charge from one memory node to the next memory node acts as a cycling memory function that can reduce mismatch between taps by making some of the exposure of each signal on each tap, and can result in reducing the readout area since only one readout structure / FD is required depending on the implementation. Furthermore, by utilizing only one readout structure, depending on the implementation, the readout-related tap mismatch can be reduced, improving the trade-off relationship between mismatch and speed (fps).

[0039] Note that other implementations for realizing memory cycles are also possible, such as CCD-like MEMs (1.5-phase / 2-phase / ,,,). For example, a CCD-like MEM structure may allow utilizing all taps as signal integrators, but due to the larger area requirements for CCD-memories compared to MS gates, the saturation charge (QSAT) of each tap may be reduced, i.e., less space may be available for each MEM node.

[0040] In some embodiments, a memory shift gate may be placed between two memory nodes to perform a cycle memory function.

[0041] In some embodiments, the cascaded TG-based pixel may further include a common gate representing the first modulation stage. In such a cascaded TG-based pixel, the demodulation of the incident light to the N taps may be divided into multiple steps or modulation stages into a first modulation stage, a second modulation stage, a third modulation stage, etc. By implementing multiple stages, the number of taps / modulators directly connected to the central light collecting region can be reduced. Thus, a smaller area is required for the central collecting region, which can result in faster charge transfer from the central collecting region to the mixing element.

[0042] In some embodiments, a common gate can connect the central light collecting region to each floating diffusion region through a respective transfer gate, which represents a second modulation stage. This can result in a smaller collector area and therefore a higher modulation electric field (E-field) for the same applied potential, e.g., higher modulation frequency FMOD, better demodulation contrast CMOD, and the built-in E-field can be better oriented depending on the configuration, resulting in further FMOD / CMOD improvement. For example, cases where the modulation electric field is reduced due to a large distance from the far end of the modulation region / charge collecting region can be addressed by reducing the number of modulators directly connected to the first modulation region / charge collecting region and by implementing multiple modulation stages as described herein.

[0043] In some embodiments, the cascaded TG-based pixels may further include a first common gate representing a first modulation stage. In some embodiments, the cascaded TG-based pixels may further include a second common gate representing a second modulation stage, the second common gate connecting the first common gate to a plurality of respective transfer gates. For example, the second common gate may connect the first common gate to two respective transfer gates, without limiting the disclosure in this respect. Alternatively, the second common gate may connect the first common gate to more than two respective transfer gates.

[0044] In some embodiments, the cascaded TG-based pixels may further comprise a memory node for intermediate charge storage.

[0045] The G-based pixel may further include a floating diffusion region, a plurality of memory nodes, and a plurality of respective second transfer gates, the plurality of memory nodes being connected to the floating diffusion region via the respective plurality of second transfer gates. The TG-based pixel may include at least one floating diffusion region. The plurality of memory nodes may be two or more memory nodes, and the respective plurality of second transfer gates may be two or more second transfer gates.

[0046] In some embodiments, the transfer gate may be a first transfer gate, and the TG-based pixel may further include a floating diffusion region, two or more memory nodes, and two or more respective second transfer gates, with the two or more memory nodes connected to the floating diffusion region via the two or more respective second transfer gates, without limiting the present disclosure in that respect. For example, the TG-based pixel may include one or more floating diffusion regions, two or more memory nodes, and two or more respective second transfer gates, with each floating diffusion region connected to two or more respective memory nodes via two or more respective second transfer gates. The memory nodes may operate as memory nodes, which may provide dark current reduction, noise reduction, relaxed routing requirements, ADC counting, pixel area with shared readout stages.

[0047] In some embodiments, the cascaded TG-based pixel may further comprise a memory shift gate configured to transfer charge from one of the two memory nodes to another of the two memory nodes, the two memory nodes being adjacent to each other. The memory nodes may operate as cycling memory nodes, which may result in reducing the mismatch between the taps by making a portion of the exposure of each signal on each tap, and since one readout structure / FD is required, it is noted that by utilizing only one readout structure, the readout-related tap-mismatch may be reduced, allowing for an improved trade-off between mismatch and speed (fps), i.e., low mismatch and flexible readout, depending on the implementation. Other implementations for realizing memory cycling are also possible, e.g., CCD-like MEMs (1.5 phase / 2 phase / ,,,), etc. For example, a CCD-like MEMs structure may allow utilizing all taps as signal integrators, but due to the larger area requirements for CCD-memories compared to MS gates, the QSAT of each tap may be reduced, i.e., less space may be available for each MEMs node.

[0048] In some embodiments, the light collecting region may be an intermediate collecting region including multiple central light collecting regions, each of which is connected to a respective CAPD modulation circuit. That is, the first modulation stage is implemented as CAPD by including a CAPD modulation circuit in the light collecting region, which results in a low FPN for the first modulation stage and can be reconfigured depending on the configuration, e.g., without cycling, thus avoiding complex subsequent gate transfers.

[0049] In some embodiments, each pixel is a cascaded TG-based pixel that may include a common gate (CG0-3) configured to generate charge and direct the charge directly to a first transfer gate (TG0A-3B).

[0050] In some embodiments, each pixel may be a cascaded TG-based pixel (350) that does not have a central light collecting region. By eliminating the central light collector region and directing the charge to the first modulation step directly through an auxiliary electrode such as a common gate, reduced pixel area may be achieved and charge transfer optimization may be performed. Because all parts are now controlled by electronically applied potentials, faster modulation may be performed due to the reduced total electron path length and due to the elimination of the central region with an electric field that is difficult to control.

[0051] In some embodiments, each pixel may be a cascaded TG-based pixel that includes a CAPD modulator and two respective photogates representing the first modulation stage. The CAPD modulation circuit does not require a central collector to operate, and the photogates may function together as a photodiode and a transfer gate. This allows for a faster second modulation stage, potentially resulting in a higher fmod / cmod.

[0052] Such ToF sensors, as described herein, can provide more accurate depth information due to improved charge transfer speeds by reducing tap-to-tap mismatch, reducing noise, improving signal-to-noise ratio, and providing faster readout.

[0053] The embodiments also disclose an electronic device comprising an indirect time-of-flight sensor according to claim 1. The electronic device may for example be an imaging sensor of an imaging camera, in particular a sensor of a ToF camera. For example, the electronic device may be an imaging sensor with N-tap pixels, where N indicates the number of taps provided on the pixels of the imaging sensor. The electronic device may also comprise additional circuits. For example, the circuit of the electronic device may include electronic components such as switching elements (gates, transistors, etc.), resistors, memory elements (capacitors, RAM, ROM, etc.), pixel circuits, storage devices, input means (mouse, keyboard, camera, etc.), output means (displays (e.g. liquid crystals, (organic) light emitting diodes, etc.), loudspeakers, etc.), (wireless) interfaces, as generally known for electronic devices (computers, smartphones, etc.). Furthermore, it may include sensors for sensing still or video image data (image sensors, camera sensors, video sensors, etc.), for sensing fingerprints, for sensing environmental parameters (e.g. radar, humidity, light, temperature), etc.

[0054] (Operation principle of indirect time-of-flight imaging system (iToF)) FIG. 1 shows a schematic of the basic working principle of an indirect time-of-flight (iToF) imaging system that can be used for depth sensing. The iToF imaging system 1 includes an iToF camera with an image sensor 2 with a matrix of pixels, and a processor (CPU) 5. A scene 7 is actively illuminated with amplitude-modulated infrared light 8 at a predefined wavelength, for example by several light pulses of at least one predefined modulation frequency 4 generated by a timing generator 6, using an illumination device 10. The amplitude-modulated infrared light 8 is reflected from objects in the scene 7. A lens 3 collects the reflected light 9 and forms an image of the objects in the scene 7 on the image sensor 2. In indirect time-of-flight (iToF), the CPU 5 determines for each pixel the phase delay between the modulated signal 8 and the reflected light 9.

[0055] While in the embodiment of FIG. 1 the timing generator 6 and the imaging sensor 2 of the iToF system 1 are depicted separately, in the case of an N-tap system these two functions are implemented on the same block (dashed rectangle) forming an N-tap three-dimensional (3D) sensor such as N-tap sensor 20 in FIG. 2 below.

[0056] (N tap sensor) FIG. 2 illustrates a schematic of one embodiment of a basic N-tap sensor included in an N-tap system.

[0057] The N-tap system comprises an N-tap sensor 20 with an N-tap pixel array 21 and its main connections, namely vertical scanner 22, guide driver 23, analog front end and ADC 24 and control unit 25. The vertical scanner 22 provides clocks for normal pixel operations such as reset, select, for reset and readout phases. The guide driver 23 provides special clocks required for N-tap operation. The pixel outputs are connected to the analog front end and ADC 24 for digitization and subsequent readout. The control unit 25 ensures synchronization across the vertical scanner 22, guide driver 23 and analog front end as well as ADC 24, including the illumination device (see 10 in FIG. 1).

[0058] In the embodiment of FIG. 2, the N-tap system is similar to the normal iToF system (see 1 in FIG. 1), but utilizes a different pixel array, control unit and timing diagram. The emitter, such as the illumination device 10 in FIG. 1, may be a laser, a vertical cavity surface emitting laser (VCSEL), a light emitting diode (LED), etc. Although the vertical scanner 22 and the guide driver 23 are depicted separately, it is possible to combine the functions of these two on the same block. The N-tap sensor 20 is an N-tap three-dimensional (3D) sensor, which realizes the functions of the timing generator 6 and the imaging sensor 2 of the iToF system 1 in FIG. 1.

[0059] In the embodiment of Figure 2, the N-tap system 20 comprises an N-tap sensor having an N-tap pixel array 21, which may be implemented, for example, as a CAPD modulator-based N-tap pixel array as shown in Figures 3-11b below, as a gate modulator-based N-tap pixel array as shown in Figures 12-38 below, or as a cascaded CAPD gate pixel array as shown in Figures 39-46 below. The N-tap pixel array 21 of the N-tap system 20 includes a plurality of N-tap pixels. The LSR signal is used to represent the light output signal of the illuminator.

[0060] (CAPD-based pixels) FIG. 3 illustrates a schematic top view of one embodiment of an N-tap current-assisted photonic demodulator (CAPD) based pixel.

[0061] The N-tap pixel 30 comprises a number of CAPD taps, i.e., N=9 CAPD taps, a number of reset transistors RST, a number of amplifiers AMP, a number of selection transistors SEL and a number of shutters SH. Each of the nine CAPD taps GD1-GD9 is formed by a p+ region represented by a dotted octagon and an n+ region represented by a pattern filling the diagonal of the octagon, as shown in GD1 of FIG. 3. The transistors are represented by rectangles with vertical and horizontal stripe patterns, while the nodes between the transistors are represented by white octagons. During exposure, each CAPD tap GD1-GD9 is clocked sequentially as shown in FIG. 5. After exposure, the shutter transistor SH connected to the respective CAPD tap is closed (low conductive state). The storage nodes connected to the shutter transistors SH are read out line by line by toggling the corresponding selection transistor SEL clock and associated analog stages, where the read out timing is the same as for a normal iToF sensor and is not shown in FIG. 5.

[0062] In the embodiment of FIG. 3, the N-tap pixel 30 has a size of about 15 μm×15 μm, with N=9, but this is not a limitation of this embodiment. Alternatively, other pixel sizes, geometries, and N implementations are possible. Each CAPD tap GD1-GD9 of FIG. 3 is connected to a respective reset transistor RST, a respective amplifier AMP, a respective selection transistor SEL, and a respective shutter SH, as shown in FIG. 4 below. In the embodiment of FIG. 3, GD1-GD9 are used as CAPD mixing elements (e.g., mixing gates), and each mixing element GD1-GD9 is associated with a respective tap of the pixel. Also, one of the CAPD mixing elements GD1-GD9 may be used as an overflow collector OFC at different timings. An example of such timing is shown in FIG. 6, where GD9 is operating as an overflow collector OFC. In the embodiment of FIG. 3, the mixing elements are implemented as mixing gates.

[0063] FIG. 4 shows a schematic of an embodiment of a circuit diagram of an N-tap CAPD-based ToF pixel having more than two taps (N>2), here N=9 CAPD taps. The circuit diagram 40 of the 9-tap CAPD-based ToF pixel comprises a plurality of photodiodes, i.e., nine photodiodes 41-49, which collect incident photons and generate a photocurrent. Each of the plurality of photodiodes is connected to a respective mixing gate GD1-GD9, which is associated with a respective tap of the pixel. Each of the nine photodiodes 41-49 includes a capacitor, and each photodiode 41-49 is connected to a respective reset transistor RST[1]-RST[9] and a respective shutter SH[1]-SH[9], where the shutter is used as a switch to allow the charge generated by the respective photodiode to be accumulated or not. The collected charge is transferred to a source follower consisting of an amplifier AMP and a select transistor SEL, and is connected to a readout line V outThe amplified signals are read out on the pixel electrodes 114. The mixing gates GD1 to GD9 are controlled according to a timing diagram as shown in Figure 5. Respective reset transistors RST[1] to RST[9] are provided to reset the pixels.

[0064] In the embodiment of Fig. 4, GD1-GD9 are used as CAPD mixing elements, but this is not a limitation of the embodiment. Alternatively, one of the CAPD mixing elements GD1-GD9, for example GD9, is used as an overflow collector OFC to collect all unwanted charges. A photodiode 49 is connected to the overflow collector OFC, where the CAPD mixing gates GD1-GD8 and the overflow collector OFC, here GD9, are controlled according to a timing diagram as shown in Fig. 6.

[0065] It should be noted that although the embodiment of Figure 4 shows a 9-tap (N = 9) CAPD-based ToF pixel, in alternative embodiments other numbers of taps in the N-tap pixel may be foreseen, for example there may be CAPD-based pixels with N = 3, 4, 5, 6, 7, 8, 10, 11, 12 or more taps.

[0066] FIG. 5 is a timing diagram during exposure for the control of the mixing elements GD1-GD9 of the N-tap CAPD-based pixel described in FIG. 3. A laser pulse for illuminating a scene is activated for a predefined illumination period. As shown, RST[i] signals 500, where i=1,,,9 are activated for a predefined period Δt, here Δt=t2-t1. SH[i] signals 501 (i=1,,,,9) are activated at activation time t1, concurrent with RST[i] signal 500, and remain active until deactivation is required. By activating SH[i] signal 501, the charge generated by each photodiode 41-49 can be accumulated. The CAPD-based mixing elements GD1-GD9 of the 9-tap CAPD-based pixel are controlled by respective control signals, also called "demodulation signals" or "mix signals". According to this specific timing diagram of FIG. 5, each of the mixing elements GD1-GD9 of the pixel is activated one after the other for a predefined activation period Δt'. As described above, the control signals 502 to 510 are applied to the mixing gates GD1 to GD9, respectively, to activate the mixing elements GD1 to GD9 for a predetermined activation period Δt′. 12 At , the activation period Δt′ of the mixing gate GD1 starts again, and the above process is carried out again.

[0067] The LSR signal shows an example of a light output from a lighting device (see 10 in FIG. 1). The pulse width, amplitude, phase, frequency, and waveform shown in the embodiment of FIG. 5 are not limiting. Alternatively, different pulse widths, amplitudes, phases, frequencies, and waveforms can be used.

[0068] Regarding the timing diagrams in FIG. 5 and all following timing diagrams, please note that they only show the relative positions of the pulses.

[0069] FIG. 6 shows a timing diagram for the control of the mixing elements GD1-GD8 of the N-tap CAPD based pixel described in FIG. 3 and the control of GD9 as overflow collector OFC. As shown in the figure, the signal 600 of RST[1-8] is active for a predefined period, here Δt=t2-t1. The signal 601 of SH[1-8] is activated at activation time t1, simultaneous with the signal 600, and remains active until deactivation is required. The signal 602 of RST[9] and the signal 603 of SH[9] are always active. As mentioned above, the control signal 604 of GD1 is activated at time t4 for a predefined period Δt', here Δt'=t5-t4. The control signals 604-611 are applied to the mixing gates GD1-GD8, respectively, to activate the respective mixing gates GD1-GD8 for a predefined activation period Δt', as mentioned above. At time t when the activation cycle of GD1 starts, the control signal 612 of GD9 used as the overflow collector OFC becomes active again at time t 12 It is inactive until time t 12 6, the control signal 612 remains active for a predefined period of time Δt″. At the point t 13 At t′, the activation period Δt of the mixing element GD1 starts again and the above process is performed again. The described process, also called “sub-integration periods”, is repeated multiple times to achieve measurements over a given integration period.

[0070] 6, the OFC pulse duration, i.e., the activation period of the control signal 612, is larger than the pulses of the other GDs, so that the LSR pulses are further apart in time, which may allow for higher optical peak power while maintaining eye-safe operation. Because of the higher peak power, less integration time is required on the CAPD-based taps GD1-8 to reach the same signal level, so less ambient light is collected, and therefore the signal-to-noise ratio (SNR) may be improved.

[0071] Two different types of CAPD-based pixels 30 described in Figure 3 are shown in Figures 7a-8b. For example, the first type includes N-CAPD elements forming a pixel, as shown in Figures 7a and 7b, and the second type includes N separate CAPD-based unit cell elements forming a pixel, as shown in Figures 8a and 8b.

[0072] FIG. 7a shows a schematic diagram of an embodiment of a first type of CAPD based pixel in a top view including N-CAPD elements forming a CAPD based pixel 70. The N-tap pixel 70 includes a light collecting region 77, a plurality of CAPD elements, i.e., 9 CAPD elements, N=9, a plurality of reset transistors RST, a plurality of amplifiers AMP, a plurality of selection transistors SEL and a plurality of shutters SH. The plurality of transistors RST, AMP, SEL, SH are arranged around the CAPD elements GD1-GD9 and on an isolation region separating the CAPD elements GD1-GD9. Each CAPD element is associated with a respective tap of the CAPD based pixel 70 and is formed by a p+ region represented by a dotted octagon and an n+ region represented by an octagon with a diagonal fill pattern, as shown in GD1 of FIG. 7a. The plurality of transistors are represented by rectangles with vertical and horizontal stripe patterns, while the nodes between the plurality of transistors are represented by white octagons. In the top view of CAPD-based pixel 70, a horizontal dashed line 71 is drawn, which starts on one side of the pixel where CAPD tap GD4 is located and ends on the other side of the pixel where CAPD tap GD6 is located, indicating a cut line cutting the pixel and CAPD taps GD4-GD6 down the middle. A cross-sectional view of CAPD-based pixel 70 is described with respect to FIG. 7b.

[0073] In the embodiment of FIG. 7a, the CAPD-based pixel 70 has a size of about 15 μm×15 μm and N=9, although the embodiment is not limited in this respect. Alternatively, other pixel sizes, geometries, and N implementations are possible. In the embodiment of FIG. 7a, GD1-GD9 are used as CAPD mixing gates, with each mixing gate GD1-GD9 associated with a respective tap of the pixel. Alternatively, one of the CAPD mixing gates GD1-GD9 may operate as an overflow collector OFC by adjusting the timing for one GD of each pixel, as shown in FIG. 10b and FIG. 11b. The CAPD-based pixel 70 of FIG. 7a may achieve an improved bandwidth device, but may require a more complex layout.

[0074] Figure 7b shows a schematic cross-sectional view of one embodiment of the CAPD-based pixel 70 described with respect to Figure 7a. In the cross-sectional view 72 of the CAPD-based pixel 70 of Figure 7a, a first type of CAPD-based pixel 70 has an n+ region 74 and a p+ region 75 inside a lightly doped substrate, two transistors 73 and two isolated implants 76. The n+ region 74 (diagonal fill pattern) and the p+ region 75 (dot pattern, located on the same side of the CAPD based pixel 70, e.g., at the top of the pixel. The n+ region 74 and the p+ region 75 form a mixing element, where the mixing element taps GD4-GD6, where each mixing gate GD4-GD6 is associated with a respective tap of the CAPD based pixel 70. The two transistors 73 are shutters SH located on the isolation region formed around the CAPD mixing gates GD1-GD9, and the two isolation implants 76 are part of the isolation region formed around the CAPD mixing elements GD1-GD9. The isolation region formed around the CAPD mixing elements GD1-GD9 can be adapted to completely isolate each pixel from its neighbors, both optically and electrically. This can be achieved by deep P-wells, trench regions, etc.

[0075] An electric field is set up to move the electrons to a collector tap, typically a reverse-biased diode. Modulation is achieved by alternating the direction of the voltage applied between the mix taps. This modulated electric field applied within the substrate allows electrons generated deep within the substrate to be collected onto the desired tap. The voltage used for demodulation controls the field strength and therefore the drift velocity of the generated electrons.

[0076] FIG. 8a shows, in a top view, a schematic diagram of an embodiment of a second type of CAPD-based pixel including N isolated CAPD-based unit cell elements forming a CAPD-based pixel 80. The N-tap pixel 80 includes a plurality of CAPD unit cell elements 86, i.e., N=9, 9 CAPD unit cell elements 86, a plurality of reset transistors RST, a plurality of amplifiers AMP, a plurality of select transistors SEL, and a plurality of shutters SH. The plurality of transistors RST, AMP, SEL, and SH are located on one side of each isolated CAPD unit cell element GD1-GD9. The plurality of transistors RST, AMP, SEL, and SH are located on a p-well implant forming a simple pixel transistor layout. Each isolated CAPD unit cell element GD1-GD9 is associated with a respective tap of the CAPD-based pixel 80 and is formed by a p+ region shown as an octagonal dotted line and an n+ region shown as an octagonal diagonal fill pattern as shown in GD1 of FIG. 7a. The transistors are represented by rectangles with vertical and horizontal stripe patterns, while the nodes between the transistors are represented by white octagons. A top view of CAPD-based pixel 80 includes a horizontal dashed line 81 indicating a cut line beginning on one side of the pixel where CAPD unit cell element GD4 is located and ending on the other side of the pixel where CAPD unit cell element GD6 is located, the cut line cutting through the pixel and CAPD unit cell elements GD4-GD6. A cross-sectional view of CAPD-based pixel 80 is described with respect to FIG. 8b.

[0077] In the embodiment of FIG. 8a, the second type CAPD-based pixel 80 including N isolated CAPD-based unit cell elements has a size of about 15 μm×15 μm, with N=9, although the embodiment is not limited in this respect. Alternatively, other pixel sizes, geometries, and N implementations are possible. In the embodiment of FIG. 8a, GD1-GD9 are used as CAPD mixing elements, with each mixing element GD1-GD9 associated with a respective tap of the pixel. Alternatively, one of the CAPD mixing elements GD1-GD9 may be operated as an overflow collector OFC by adjusting the timing for one GD in each pixel, as shown in FIG. 10b and FIG. 11b.

[0078] FIG. 8b shows, in a cross-sectional view, a schematic of an embodiment of a CAPD-based pixel 80 including N isolated CAPD-based unit cell elements as described with respect to FIG. 8a. In the cross-sectional view 82 of the CAPD-based pixel 80 of FIG. 8a, the second type of CAPD-based pixel 80 has a low-doped substrate, i.e., n+ region 83 and p+ region 84 inside the light collection region 87, and a p-well implant 85 formed between the N isolated CAPD-based unit cell elements GD4-GD6. The n+ region 83 (diagonal fill pattern) and the p+ region 84 (dot pattern) are located on the same side of the CAPD-based pixel 80, e.g., at the top of the pixel. The n+ region 83 and the p+ region 84 form a mixing element, where the mixing element taps GD4-GD6, where each mixing element GD4-GD6 is associated with a respective tap of the CAPD-based pixel 80.

[0079] FIG. 9 shows a schematic diagram of an embodiment of a first or second type CAPD-based pixel, where an N-tap CAPD-based pixel 90 operates as one 16-tap pixel or four 4-tap pixels. The N-tap CAPD-based pixel 90 is a CAPD-based pixel with N=16 mixing elements, and thus 16 taps. In the embodiment of FIG. 9, the N-tap CAPD-based pixel 90 has the configuration of the CAPD-based pixel 80 described in connection with FIG. 8a, which includes N isolated CAPD-based unit cell elements. Each of the N isolated CAPD elements operates as one 16-tap pixel or four 4-tap pixels depending on the configuration of the guide driver 23. The N-tap CAPD-based pixel 90 operating as a 16-tap CAPD-based pixel is represented by dashed line 91, and the N-tap CAPD-based pixel 90 operating as four 4-tap (4×4) CAPD-based pixels is represented by dashed line 92. The guide driver 23 provides the special clocks required for N-tap operation, and depending on the configuration of these clocks, causes the N-tap CAPD based pixel 90 to operate as a 16-tap CAPD based pixel or as a 4×4-tap CAPD based pixel. Configurations with different N are also possible.

[0080] In the embodiment of FIG. 9, the N-tap CAPD-based pixel 90 operates as one 16-tap pixel or four 4-tap pixels, without limiting the embodiment in that respect. Alternatively, different, not necessarily symmetrical configurations may be possible. The separated CAPD elements may be configured to operate as a single N-tap pixel, or as K (i.e., a plurality of) M-tap pixels with K×M=N, or other configurations that are not necessarily symmetrical. Such CAPD-based pixels may be easily adapted. Based on the configuration of the guide driver 23, higher resolution but smaller N formats can be supported.

[0081] FIG. 10(a) is a timing diagram during exposure for the control of the N-tap CAPD-based pixel of FIG. 9 operating as a 16-tap pixel. The N-tap CAPD-based pixel 90 is a CAPD-based pixel with N=16 mixing elements and thus 16 taps. A laser pulse for illuminating a scene is activated for a predefined illumination period. As shown in the figure, a RST[i] signal 1000 (where i=1,,,,,16) is activated for a predefined period t. A SH[i] signal 1001 (where i=1,,,,,16) is activated simultaneously with the RST[i] signal 1000 and remains active until deactivation is required. According to this particular timing diagram of FIG. 10a, each of the mixing elements GD1 to GD16 of the pixel is activated one after the other for a predefined activation period Δt′. The control signals 1002-1017 are applied to the mixing elements GD1-GD16, respectively, as described above, to activate the respective mixing elements GD1-GD16 for a predetermined activation period Δt'. At the end of the activation period Δt' of the mixing element GD16, the activation period Δt' of the mixing element GD1 starts again, and the above-mentioned process is carried out once again. The described process, also called a "sub-integration period", is repeated multiple times to achieve a measurement over a predetermined integration period. The pulse width, amplitude, phase, frequency, and waveform shown in the embodiment of FIG. 10a are not limiting. Alternatively, different pulse widths, amplitudes, phases, frequencies, and waveforms can be used.

[0082] FIG. 10(b) is a timing diagram for controlling the N-tap CAPD based pixel described in FIG. 9, with GD16 acting as an overflow collector OFC. As shown, signal 1018 on RST[1-15] is activated for a predetermined period Δt. Signal 1019 on SH[1-15] is activated simultaneously with signal 1018 and remains active until deactivation is required. Signal 1020 on RST

[16] and signal 1021 on SH

[16] are always active. As shown, control signal 1022 on GD1 is activated for a predetermined period Δt'. Control signals 1022-1036 are applied to mixing gates GD1-GD15, respectively, to activate the respective mixing elements GD1-GD15 for a predetermined activation period Δt' as described above. At the time when the activation period of GD1 starts, the control signal 1037 of GD16, which is used as the overflow collector OFC, is deactivated until the time when the activation period of GD15 ends. As shown in the embodiment of FIG. 10b, the control signal 1037 remains active for a predetermined period Δt″. At the time when the activation period Δt″ of GD16 ends, the activation period Δt′ of the mixing element GD1 starts again and the above process is carried out once again. The described process, also called “sub-integration periods”, is repeated multiple times to achieve a measurement over a predetermined integration period.

[0083] FIG. 11a shows a timing diagram during exposure for the control of the N-tap CAPD-based pixel of FIG. 9 operating as four 4-tap pixels. The N-tap CAPD-based pixel 90 is a CAPD-based pixel with N=16 mixing gates and therefore 16 taps. Laser pulses for illuminating the scene are activated for a predefined illumination period. As shown, RST[i] signals 1100, where i=1,,,16, and each RST[i] is activated for a predefined period Δt. SH[i] signals 1101 (i=1,,,,16) are activated simultaneously with each SH[i] RST[i] signal 1000 and remain active until deactivation is required. According to this particular timing diagram of Fig. 11, the mixing elements GD1-GD16 of the pixel are controlled as four groups, where the first group includes mixing elements GD1, GD2, GD5 and GD6, the second group includes mixing elements GD3, GD4, GD7 and GD8, the third group includes mixing elements GD9, GD10, GD13 and GD14, and the fourth group includes GD11, GD12, GD15 and GD16. The first mixing elements of each group, here GD1, GD3, GD9 and GD11, are activated simultaneously, and in each group, each mixing element is activated one after the other for a predetermined activation period Δt'. The control signals 1102-1105 are applied to the mixing elements GD1, GD2, GD5 and GD6, respectively, to activate them for a predetermined activation period Δt', as described above. As described above, the control signals 1106-1109 are applied to the mixing elements GD3, GD4, GD7, and GD8, respectively, to activate them for a predetermined activation period Δt'. As described above, the control signals 1110-1113 are applied to the mixing elements GD9, GD10, GD13, and GD14, respectively, to activate them for a predetermined activation period Δt'. As described above, the control signals 1114-1117 are applied to the mixing elements GD11, GD12, GD15, and GD16, respectively, to activate them for a predetermined activation period Δt'.At the end of the activation period Δt' of the fourth mixing element of each group, here GD6, GD8, GD14, GD16, the activation period Δt' of the first mixing gate of each group, here GD1, GD3, GD9, GD11, starts again, and the above-mentioned process is carried out again. The pulse width, amplitude, phase, frequency, and waveform shown in the embodiment of FIG. 11a are not limiting. Alternatively, different pulse widths, amplitudes, phases, frequencies, and waveforms can be used.

[0084] FIG. 11(b) shows a timing diagram for the control of the N-tap CAPD based pixel described in FIG. 9. Here, GD6, GD8, GD14 and GD16 are operating as overflow collectors OFC. As shown, signal 1118 of RST[1-5, 7, 9-13, 15] is activated for a predetermined period of time Δt. Signal 1119 of SH[1-5, 7, 9-13, 15] is activated simultaneously with signal 1118 and remains active until it needs to be deactivated. Signal 1120 of RST[6, 8, 14, 16] and signal 1121 of SH[6, 8, 14, 16] are always active until they need to be deactivated. As shown, the control signals 1122, 1126, 1129, and 1133 of GD1, GD3, GD9, and GD11 activate GD1, GD3, GD9, and GD11, respectively, for a predefined period Δt'. The control signals 1122-1124 are applied to the mixing elements GD1, GD2, and GD5, respectively, as described above, to activate them for a predetermined activation period Δt'. The control signals 1126-1128 are applied to the mixing elements GD3, GD4, and GD7, respectively, as described above, to activate them for a predetermined activation period Δt'. The control signals 1130-1132 are applied to the mixing elements GD9, GD10, and GD13, respectively, to activate them for a predetermined activation period Δt', as described above. As described above, the control signals 1134 to 1136 are applied to the mixing elements GD11, GD12, and GD15, respectively, to activate them for a predetermined activation period Δt′.

[0085] At the time when the activation period of GD1, GD3, GD9 and GD11 starts, the control signals 1125, 1129, 1133 and 1137 of GD6, GD8, GD14 and GD16 are inactivated until the time when the activation period of GD5, GD7, GD13 and GD15 ends, respectively. As shown in the embodiment of FIG. 11b, the control signals 1125, 1129, 1133 and 1137 remain activated for a predetermined period Δt″. At the time when the activation period Δt″ of GD6, GD8, GD14 and GD16 ends, the activation period Δt′ of the mixing gates GD1, GD3, GD9 and GD11 starts again and the above process is carried out once again. The described process, also called “sub-integration period”, is repeated multiple times to achieve the measurement over the predetermined integration period.

[0086] Without limiting these embodiments, the embodiments of Figures 3, 4, 7a, 7b, 8a, 8b, and 9 do not include capacitors and transistors for full well capacitance improvement. Alternatively, the implementations of Figures 3, 4, 7a, 7b, 8a, 8b, and 9 may include capacitors and transistors for full well capacitance improvement.

[0087] (Basic Transfer Gate (TG) based N-tap pixel) FIG. 12 illustrates generally one embodiment of a basic trans-transfer gate (TG) based N-tap pixel implementation layout, where the number of trans-transfer gates is N=8.

[0088] The TG based N-tap pixel 120 has a central light collecting region 121, here N=8 transfer gates, connecting the central light collecting region 121 to N floating diffusions FD, N=8. Each of the floating diffusions FD is connected to a reset transistor RST, here RST0-RST7. For each floating diffusion FD there is an associated readout stage, namely an amplifier AMP and a selection transistor SEL. A number of n+ regions, represented by white octagons, connect a number of amplifiers AMPO-AMP7 to a number of selection transistors SEL1-SEL8 and a number of reset transistors RST0-RST7. The floating diffusion FD connecting the TG to the RST transistors accumulates the modulation charge. The light collecting region 121 is a pinned photodiode PPD.

[0089] In the embodiment of FIG. 12, the light collecting region 121 is a pinned photodiode PPD, without limiting the present embodiment in that respect. Alternatively, the light collecting region 121 may be a photogate or a partially pinned photodiode, etc. By sequentially opening each of the transfer gates TG0-TG7, depth information from the incoming modulated light can be extracted. It should be noted that one or more of the transfer gates TG0-TG7 may operate as overflow gates OFG to allow ambient light to escape. If one or more of the transfer gates TG0-TG7 operate as overflow gates OFG, the number of RST transistors and readout stages AMP and SEL may be reduced by one for each transfer gate TG that permanently operates as an overflow gate OFG.

[0090] 12, the TG-based N-tap pixel is an 8-tap pixel (N=8), without limiting the embodiment in that respect. Alternatively, the TG-based N-tap pixel may be a pixel having any number N, e.g., N=3, 4, 5, 6, 8, 9, 10, 11, 12, or more.

[0091] FIG. 13 shows a schematic of one embodiment of the schematic diagram of the TG-based N-tap pixel of FIG. 12, where the number of transfer gates is N=8. The central light collecting region 121 is a pinned photodiode PPD, which collects the generated photocarriers and generates a photocurrent. The light collecting region 121 is a central photodiode connected to transfer gates TG0-TG7, each of which is associated with a respective tap of the TG-based N-tap pixel and is connected to a respective reset transistor RST0-RST7, to a respective amplifier AMPO-AMP7, and to a respective select transistor SELO-SEL7. By opening one of the transfer gates TG0-TG7, the charge generated by the light collecting region 121 is transferred to the floating diffusion and from the respective amplifier AMPO to AMP7. A signal representing this charge is transferred to the respective select transistor SELO-SEL7, which reads out the amplified signal on the readout line. After integration, the floating diffusion signal is read out line by line by toggling the analog stage associated with the corresponding SEL clock. Reset transistors RST0-RST7 are provided to reset the pixel. The floating diffusion level is reset via the reset transistors RST0-RST7 to prepare the pixel for the next integration period.

[0092] Note that when one or more of the transfer gates TG0-TG7 operate as overflow gates OFG, the light collecting region 121 is also connected to the overflow gates OFG. The transfer gates TG0-TG7 including the overflow gates OFG are controlled according to a timing diagram such as FIG. 14, where the readout timing is not shown, as in the normal gate-iToF sensor. As in the 2-tap iToF case, the received signal will contain both a phase shift configured by the control unit and an additional phase shift induced by the time of flight.

[0093] FIG. 14 shows a timing diagram for the TG-based N-tap pixel 120 of FIG. 12 during integration. A laser pulse with an LSR signal 1400 to illuminate a scene is activated for a predetermined illumination period. The transfer gates TG0-TG7 of the 7-tap (N=8) N-tap pixel are controlled by respective control signals 1401-1408. According to this particular timing diagram of FIG. 14, each of the transfer gates TG0-TG7 of the TG-based N-tap pixel 120 of FIG. 12 are activated one after the other for a predetermined activation time window. In the embodiment of FIG. 14, since the transfer gate TG7 is operating as an overflow gate OFG, the control signal 1408 for the transfer gate TG7 deactivates the transfer gate TG7 for a predetermined time period equal to the period during which the rest of the transfer gates TG0-TG6 are active. The overflow gate OFG, here TG7, is activated again after the last transfer gate TG6 is closed. The described process, also called a "sub-integration period", is repeated multiple times to achieve measurements over a predetermined integration period.

[0094] In the embodiment of FIG. 14, the pulse duration of the overflow gate OFG, here TG7, is greater than the duration of the remaining pulses of the transfer gates TG0-TG6, thereby spacing the LSR pulses further apart in time. LSR signal 1400 of the LSR pulses shows an example of the light output from a lighting device (see 10 in FIG. 1). The spacing of the pulse durations of the overflow gates OFG in time allows for higher optical peak power while maintaining eye-safe operation, resulting in shorter integration times on the taps to reach the same signal level, and therefore less ambient light is collected, thereby achieving an improved signal-to-noise ratio (SNR).

[0095] (TG-based N-tap pixel with memory node) 15 shows a schematic top view of one embodiment of a TG-based N-tap pixel with a memory node. The TG-based N-tap pixel 150 is the basic TG-based N-tap pixel 120 of FIG. 12 with an additional memory node MEM, which may be implemented via a gate element or a PPD, etc. The additional memory node MEM is used for intermediate charge storage.

[0096] The TG-based N-tap pixel 150 has a central light collecting region 151, and N=8 first transfer gates TG0-TG7 connect the central light collecting region 151 to multiple MEM nodes. Each of the first transfer gates TG0-TG7 connects the light collecting region 151, which is a pinned photodiode PPD, to a respective memory node MEM0-MEM7. Each memory node MEM0-MEM7 is implemented as an intermediate storage node. Each memory node MEM0-MEM7 is then connected to a floating diffusion region FD (white octagon) via a respective second transfer gate TX0-TX7. Thus, multiple MEM nodes are connected to the same floating diffusion region FD.

[0097] In the embodiment of FIG. 15, two memory nodes MEM are connected to the same floating diffusion region FD, i.e., memory nodes MEM0 and MEM1 are connected to floating diffusion region FD01, memory nodes MEM2 and MEM3 are connected to floating diffusion region FD23, memory nodes MEM4 and MEM5 are connected to floating diffusion region FD45, and memory nodes MEM6 and MEM7 are connected to floating diffusion region FD67. The floating diffusion region FD01 is connected on one side by two second transfer gates TX0, TX1, and on the other side by a reset transistor RST01. The floating diffusion region FD23 is connected on one side by two second transfer gates TX2, TX3, and on the other side by a reset transistor RST23. The floating diffusion region FD45 is connected on one side by two second transfer gates TX4 and TX5, and on the other side by a reset transistor RST45. The floating diffusion region FD67 is connected on one side with two second transfer gates TX6 and TX7 and on the other side with a reset transistor RST67. Similarly, each of the floating diffusion regions FD01, FD23, FD45, FD67 is connected to an associated readout stage, i.e., an amplifier AMP and a select transistor SEL. As mentioned before, a shared readout stage is connected to every two MEM nodes, resulting in N / 2 = 4 readout stages, R = 4.

[0098] In the embodiment of FIG. 15, the light collecting region 151 is a pinned photodiode PPD, without limiting the present embodiment in that respect. Alternatively, the light collecting region 151 is a photogate or a partially pinned photodiode, etc. In the embodiment of FIG. 15, the TG-based N-tap pixel with memory node is an 8-tap pixel (N=8), without limiting the present embodiment in that respect. Alternatively, the TG-based N-tap pixel may be a pixel having any number N, for example, N=3, 4, 5, 6, 8, 9, 10, 11, 12 or more. It should be noted that one or more of the transfer gates TG0-TG7 may operate as an overflow gate OFG to allow ambient light to escape. If one or more of the transfer gates TG0-TG7 operate as an overflow gate OFG, the number of RST transistors and readout stages AMP and SEL may be reduced by one for each transfer gate TG that permanently operates as an overflow gate OFG. During the readout period, the transfer gates TG0 to TG7, including the overflow gate OFG, are controlled according to a timing diagram as shown in Figure 17. Here, the integration period timing is not shown, similar to Figure 14.

[0099] 15, the first transfer gates TG0 to TG7, the second transfer gates TX0 to TX7, and the overflow gate OFG may be implemented as, for example, transistors, and the memories MEM0 to MEM7 may be implemented as, for example, capacitors. By operating the transfer gates TG0 to TG7, depth information can be extracted from the incoming modulated light.

[0100] FIG. 16 shows diagrammatically one embodiment of a schematic diagram 160 of a TG-based N-tap pixel with memory nodes of FIG. 15, where the number of transfer gates is N=8. A central light collecting region 151, which is a pinned photodiode PPD, collects incident photons and generates a photocurrent. The central light collecting region 151 is connected to first transfer gates TG0-TG7, each of which is associated with a respective tap of the TG-based N-tap pixel. By opening one of the transfer gates TG0-TG7, the charge generated by the central light collecting region 151 is transferred onto the respective memory MEM0-MEM7 and stored there. That is, during integration, all the charge is stored in the memory node MEM. At this point, the second transfer gates TX0-TX7 are closed. As a first step, the floating diffusion region FD is reset and their levels are read out. This readout gives the noise level of the reset transistor RST on the floating diffusion region FD. As a next step, the charge is transferred from the R MEM node to the floating diffusion region FD via the second transfer gates TX0-TX7. The floating diffusion level is then read out again. The RST noise level can then be subtracted from the actual signal level to obtain a reset noise-free signal. This process of reading out the reset and signal levels is repeated N / R times until all the MEM node charges are read out. To reset the pixel, reset transistors RST01, RST23, RST45, RST67 are provided. The floating diffusion level is reset via the reset transistors RST01, RST23, RST45, RST67 to prepare the pixel for the next integration period.

[0101] In the embodiment of FIG. 16, N=8, R=4, and therefore R MEM nodes are equal to four MEM nodes. For example, the charges stored in MEM0, MEM2, MEM4 and MEM6 are transferred to the floating diffusion regions FD01, FD23, FD45, FD67 via the second transfer gates TX0, TX2, TX4 and TX6, respectively. By opening the second transfer gates TX0, TX2, TX4 and TX6, respectively, the charges collected on the memory nodes MEM0, MEM2, MEM4 and MEM6 are transferred to the amplifiers AMP0, AMP2, AMP4 and AMP6. The signals representing the charges in FD01, FD23, FD45, FD67 are transferred to the select transistors SEL01, SEL23, SEL45, SEL67, and the amplified signals are read out on the readout lines. Reset transistors RST01, RST23, RST45, RST67 are provided to reset the pixels.

[0102] FIG. 17 shows a readout timing diagram of a TG-based N-tap pixel with the memory nodes of FIG. 15. Here, the number of transfer gates is N=8, the readout stage is R=4, and the last transfer gate TG7 operates as an overflow gate OFG. During readout, signal 1700 represents the control signals of the first transfer gates TG0-TG6, and signal 1701 represents the control signal of the first transfer gate TG7 operating as an overflow gate OFG. Similarly, signals 1702-1709 represent the control signals of the memory nodes MEM0-MEM7, respectively, signals 1710-1716 represent the control signals of the second transfer gates TG0-TG7, respectively, signals 1718-1721 represent the control signals of the reset transistors RST01-RST67, respectively, and signals 1722-1725 represent the control signals of the select transistors SEL01-SEL67, respectively. An alternative timing for signals 1722-1725 is to keep the SEL01-SEL67 signals high during the entire readout procedure for that pixel as long as the output lines are still sampled at the correct time (i.e., within the time frame where SEL is high in the current timing diagram).

[0103] In the embodiments of Figures 15, 16, and 17, the operation of a TG-based N-tap pixel with memory nodes is described, where each first transfer gate TG0-TG7 is driven separately, without limiting the present embodiment in that respect. In alternative embodiments, the N-taps can be driven in groups of two, e.g., TG0 and TG1 together, TG2 and TG3 together, etc. Then, MEM0 and MEM1, MEM2 and MEM3, etc., can be binned together onto the same floating diffusion region FD for readout, e.g., for low signal conditions where binning improves SNR or reduces average mismatch due to different storage channels.

[0104] (Cascaded TG-based N-tap pixel) 18 is a schematic diagram illustrating an embodiment of a cascaded TG-based N-tap pixel in a top view. In the cascaded TG-based N-tap pixel 180, the number of taps is 8, N=8 taps, the number of readout stages is 8, R=8 readout stages, the number of modulation stages is 2, S=2 modulation stages, N1=4, N2=2, where N x is the number of gates on each stage's x input.

[0105] The cascaded TG-based N-tap pixel 180 has a central light collecting region 181 with 8 taps, N=8. The 8 taps are connected to the light collecting region 181 through 12 modulation gates. The modulation circuit gates are separated in two stages. The first stage consists of N1=4 modulation gates. The second stage consists of N1×N2=8 modulation gates, totaling 12 modulation gates. The cascaded TG-based N-tap pixel 180 has four common gates CG0-CG3 that connect the central light collecting region 181 to eight transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B. Each transfer gate TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B is associated with a respective tap of the pixel. Here, common gate CG0 is directly connected to transfer gate TG0A, common gate CG1 is directly connected to transfer gate TG1A, common gate CG2 is directly connected to transfer gate TG2A, and common gate CG3 is directly connected to transfer gate TG3A, TG3B. Each transfer gate TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B is connected to a respective reset transistor RST, here RST0A, RST0B, RST1A, RST1B, RST2A, RST2B, RST3A, RST3B, via a floating diffusion region FD. For each floating diffusion region FD there is an associated readout stage, namely an amplifier AMP and a select transistor SEL. A plurality of n+ regions FD represented by white octagons connect the plurality of select transistors SELOA, SELOB, SEL1A, SEL1B, SEL2A, SEL2A, SEL2B, SEL3A, and SEL3B to the plurality of amplifiers AMP0A, AMP0B, AMP1A, AMP1B, AMP2A, AMP2B, AMP3A, and AMP3B, respectively.

[0106] In the embodiment of FIG. 18, the common gates CG0-CG3 and the transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B are modulators connected to a first modulation region / charge collection region, here the central light collection region 181, and the common gates CG0-CG3 are directly connected to the first modulation region / charge collection region, as described above. The light collection region 181 is a pinned photodiode PPD, without limiting the embodiment in that respect. Alternatively, the light collection region 181 is a photogate or a partially pinned photodiode, etc. The cascaded TG-based N-tap pixel 180 of FIG. 18 has two modulation stages, without limiting the embodiment in that respect. One skilled in the art can select any suitable number of modulation stages. The cascaded TG-based N-tap pixel 180 of FIG. 18 is an 8-tap pixel (N=8), without limiting the embodiment in that respect.

[0107] Alternatively, the cascaded TG-based N-tap pixels may be pixels having any number N, such as N = 3, 4, 5, 6, 8, 9, 10, 11, 12 or more. The number of modulation stages is two for S = 2 modulation stages in the embodiment of Figure 18, and is not intended to limit the embodiment in this respect. The number of modulation stages may be any integer value.

[0108] In the embodiment of Fig. 18, the cascaded TG-based N-tap pixel 180 with N = 8 taps has a light collection area 181 with N1 = 4 taps that needs to be supported instead of N = 8 taps, because the demodulation of the incoming light is performed in multiple modulation stages, here two modulation stages S = 2. By connecting fewer modulators to the light collection area 181, the collection area can be reduced and therefore the modulation field created by the modulator CG can be improved.

[0109] FIG. 19 illustrates in schematic form one embodiment of the schematic of the cascaded TG-based N-tap pixel of FIG. 18. The schematic of pixel 180 illustrates the readout circuitry of pixel 180. A central light collecting region 181, here a pinned photodiode PPD, collects incident photons and generates a photocurrent. The central light collecting region 181 is directly connected to common gates CG0-CG3 which are directly connected to transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B as described above. The generated photocurrent is transferred from the light collecting region 181 to the common gates CG0-CG3 and then to the transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B. By opening one of the transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B, the charges generated by the light collecting region 181 are transferred to the floating diffusion region FD and the respective amplifiers AMPOA, AMPOB, AMP1A, AMP1B, AMP2A, AMP2A, AMP2B, AMP3A, AMP3B. Signals representing these charges are transferred to the respective select transistors SEL0A, SEL0B, SEL1A, SEL1B, SEL2A, SEL2B, SEL3A, SEL3B to read out the amplified signals on the readout lines. After integration, the floating diffusion signals are read out line by line by toggling the analog stages associated with the corresponding SEL clocks. To reset the pixels, reset transistors RST0A, RST0B, RST1A, RST1B, RST2A, RST2B, RST3A, RST3B are provided. The floating diffusion levels are reset via reset transistors RST0A, RST0B, RST1A, RST1B, RST2A, RST2B, RST3A, and RST3B to prepare the pixel for the next integration period.

[0110] In the embodiment of Fig. 18 and Fig. 19, the generated photocurrent is transferred from the light collecting area 181 to the common gates CG0-CG3 and then to the transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B, such that the demodulation of the incoming light is split into multiple modulation stages. By implementing multiple modulation stages, the number of taps, i.e., modulators, e.g., transfer gates, directly connected to the central light collecting area, and therefore the size of the central light collecting area, can be reduced. One or more of the transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B may operate as an overflow gate OFG. As shown in Fig. 20, the common gates CG0-CG3 and the transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B, including the overflow gate OFG, are controlled according to a timing diagram.

[0111] FIG. 20 shows a timing diagram during integration of the cascaded TG-based N-tap pixel of FIG. 18, where the transfer gate TG3B operates as an overflow gate OFG. A laser pulse with an LSR signal 2000 for illuminating a scene is activated for a predetermined illumination period. The common gates CG0-CG3 are controlled by control signals 2001-2004, respectively. According to this particular timing diagram of FIG. 20, each of the common gates CG0-CG3 of the cascaded TG-based N-tap pixel of FIG. 18 opens one after the other for a predetermined activation time window, as shown by the control signals 2001-2004. As shown by the control signals 2005, 2007, 2009, 2011 for the transfer gates TG0A, TG1A, TG2A, TG3A, the transfer gates TG0A, TG1A, TG2A, TG3A open in sequence for a predetermined activation time window with a window length that is four times the activation time window for CG0, CG1, CG2, CG3, respectively. Each transfer gate TG0A, TG1A, TG2A, TG3A opens simultaneously with a respective common gate CG0-CG3. The common gates CG0-CG3 open in sequence, with the common gate CG0 opening again at the time the activation period of the common gate CG3 ends. As shown by the control signals 2006, 2008, 2010 for the transfer gates TG0B, TG1B, TG2B, the transfer gates TG0B, TG1B, TG2B open in sequence for a predetermined activation time window with a window length that is four times the activation time window for the previous stage CG on period. Each transfer gate TG0B, TG1B, TG2B opens at the same time that each common gate CG0-CG2 opens for the second time. Since the transfer gate TG3B acts as an overflow gate OFG, it opens at the same time that the common gate CG3 opens for the second time. Both the common gate CG3 and the transfer gate TG3B remain open as needed. After the signal charges have passed through all the stages, they end up in their respective storage nodes.

[0112] 20, transfer gate TG3B operates as an overflow gate OFG without limiting this embodiment. Alternatively, any other transfer gate may operate as an overflow gate OFG, or one or more transfer gates may operate as an overflow gate OFG, or none of the transfer gates may operate as an overflow gate OFG, etc.

[0113] 21 shows a schematic diagram of one embodiment of a cascaded TG-based N-tap pixel, where N=16, S=3, N1=4, N2=2, N3=2, and R=16.

[0114] In the cascaded TG-based N-tap pixel 210, the number of taps is 16, N = 16 taps, the number of readout stages is 16, R = 16 readout stages, the number of modulation stages is three, S = 3 modulation stages and the number of gates at each stage (x - 1) output is N x The numbers are N1 = 4, N2 = 2 and N3 = 2.

[0115] The cascaded TG-based N-tap pixel 210 has a central light collecting region 211 with 16 taps, N=16. The 16 taps are divided into three groups, N1, N2, and N3, each group associated with a respective modulation stage X. The first group has 4 taps, N1=4, the second group has 2 taps per output of the previous stage, N2=2, and the third group has 2 taps per output of the previous stage, N3=2. The cascaded TG-based N-tap pixel 210 has four first common gates CG0-CG3, i.e., a first group N1=4, that connect the central light collecting region 211 to eight second common gates CG0A, CG0B, CG1A, CG1B, CG2A, CG2B, CG3A, CG3B. That is, each first common gate CG0-CG3 is connected to two second common gates, i.e., a second group N2=2. Each second common gate CG0A, CG0B, CG1A, CG1B, CG2A, CG2B, CG3A, CG3B is connected to two transfer gates, third group N3=2. That is, each second common gate CG0A, CG0B, CG1A, CG1B, CG2A, CG2B, CG3A, CG3B is connected to two respective transfer gates TG0AA and TG0AB, TG0BA and TG0BB, TG1AA and TG1AB, TG1BA and TG1BB, TG2AA and TG2AB, TG2BA and TG2BB, TG3AA and TG3AB, TG3BA and TG3BB. Each transfer gate TG0AA, TG0AB, TG0BA, TG0BB, TG1AA, TG1AB, TG1BA, TG1BB, TG2AA, TG2AB, TG2BA, TG2BB, TG3AA, TG3AB, TG3BA, TG3BB is associated with a respective tap of the pixel.Each transfer gate TG0A, TG0AA, TG0B, TG1AB, TG1AB, TG1AB, TG2AB, TG2AB, TG2BA, TG3AB, TG3BA, TG3BA, TG3BB is connected to a respective reset transistor RST0AA, RST0AB, RST0BA, T0BA, RST1AA, RST1AB, RST1BA, RST1BAB, T2AA, RST2BA, T2BB, RST3AA, RST3BA, RST3BA, RST3BB via a floating diffusion region FD. Similarly, each transfer gate TG is also connected to a respective read stage, i.e., a respective amplifier AMP, via a floating diffusion region FD. These respective amplifiers AMP are connected to respective select transistors SEL via n_regions. Here, the read stages in the layout are omitted, but FIG. 22 shows these read stages.

[0116] In the embodiment of FIG. 21, the light collecting region 211 is a pinned photodiode PPD. This embodiment is not limited in this respect. Alternatively, the light collecting region 211 may be a photogate or a partially pinned photodiode, etc. The cascaded TG-based N-tap pixel 210 of FIG. 21 has three modulation stages, this embodiment is not limited in this respect. Those skilled in the art may select any suitable number of modulation stages. The cascaded TG-based N-tap pixel 210 of FIG. 21 is a 16-tap pixel (N=16), this embodiment is not limited in this respect. Alternatively, the cascaded TG-based N-tap pixel may be a pixel having any number of N taps. The number of modulation stages is three, S=3, in the embodiment of FIG. 21, this embodiment is not limited in this respect. The number of modulation stages may be any integer value.

[0117] FIG. 22 diagrammatically illustrates one embodiment of the schematic diagram of the cascaded TG-based N-tap pixel of FIG. 21. The schematic diagram of pixel 210 illustrates the readout circuitry of pixel 210. The central light collecting area 211, here a pinned photodiode PPD, collects incident photons and generates a photocurrent. The central light collecting area 211 is directly connected to the first common gates CG0-CG3 which are directly connected to the second common gates CG0A, CG0B, CG1A, CG1B, CG2A, CG2B, CG3A, CG3B as described above. The generated photocurrent is transferred from the light collecting area 211 to the first common gate CG, which is a first modulation step, then to the second common gate CG, which is a second modulation step, and then to the transfer gate TG, which is a third modulation step. Each of the first common gate CG, the second common gate CG, and the transfer gate TG operates as a modulation circuit for the incident light. By opening one of the transfer gates TG, the charge generated by the light collecting region 211 is transferred to the floating diffusion region FD and the respective amplifier AMP. A signal representing this charge is transferred to the respective select transistor SEL to read out the amplified signal on the readout line. A reset transistor RST is provided to reset the pixel. The floating diffusion level is reset via the reset transistor RST to prepare the pixel for the next integration period.

[0118] In the embodiment of Figures 21 and 22, the first modulation step can occur very fast due to the small modulation area. After the first modulation step by the first common gate CG, the signal is further modulated by the second common gate CG and the transfer gate TG before being transferred to the respective floating diffusion area FD. The operating frequency (or pulse width) of the first modulation step f1 is determined by the FMOD or pulse width of the optical signal. The subsequent modulation stages S x For each operating frequency f x is determined by: f x = f (x-1) / N (x-1) Here, N x is the number of taps and x is the modulation step. Thus, subsequent stages can have a slower charge transfer than previous stages.

[0119] (Cascaded TG-based NTAP pixels with memory nodes) Figure 23 is a schematic diagram of a cascaded TG-based NTAP pixel with memory nodes, where S = 2, N1 = 4, N2 = 2, and R = 4.

[0120] In the cascaded TG-based NTAP pixel 230, the number of taps is 8, N = 8 taps, the number of readout stages is 4, R = 4 readout stages, the number of modulation stages is 2, S = 2 modulation stages, N1 = 4, N2 = 2, where N x is the number of gates on each stage x connected to each output of the previous stage.

[0121] The cascaded TG-based N-tap pixel 230 has a central light collecting area 231 with eight taps (N=8). The eight taps are divided into two groups (N1, N2), each group associated with a respective modulation stage x. The first group has four gates, N1=4, and the second group has two gates, N2=2. The cascaded TG-based N-tap pixel 230 has four common gates CG0-CG3 that connect the central light collecting area 231, which is a pinned photodiode PPD, to eight first transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B. Each first transfer gate TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B is associated with a respective tap of the pixel. Here, the common gate CG0 is directly connected to the first transfer gates TG0A and TG0B, the common gate CG1 is directly connected to the first transfer gates TG1A and TG1B, the common gate CG2 is directly connected to the first transfer gates TG2An and TG2B, and the common gate CG3 is directly connected to the first transfer gates TG3A and TG3B. Each first transfer gate TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B is connected to a respective memory node MEM0A, MEM0B, MEM1A, MEM1B, MEM2A, MEM2B, MEM2B, MEM3A, MEM3B. Each memory node MEM is implemented as an intermediate storage node. Then, each memory node MEM is connected to a floating diffusion region FD (white octagon) via a respective second transfer gate TX0A, TX0B, TX1A, TX1B, TX2A, TX2B, TX3A, TX3B. Therefore, the two memory nodes MEM are connected to the same floating diffusion region FD.

[0122] In the embodiment of FIG. 23, the two second transfer gates TX are connected to the same floating diffusion region FD, i.e. the second transfer gates TX1A and TX0B are connected to the floating diffusion region FD01, the second transfer gates TX2B and TX3A are connected to the floating diffusion region FD23, the second transfer gates TX0A and TX3B are connected to the floating diffusion region FD03, and the second transfer gates TX1B and TX2A are connected to the floating diffusion region FD12. A reset transistor RST01 is also connected to the floating diffusion region FD01. A reset transistor RST23 is also connected to the floating diffusion region FD23. The floating diffusion region FD03 is also connected to the reset transistor RST03. A reset transistor RST12 is also connected to the floating diffusion region FD12. Similarly, each of the floating diffusion regions FD01, FD03, FD12, FD23 is connected to an associated readout stage, i.e. an amplifier AMP and a selection transistor SEL. As mentioned above, every second transfer gate TX, and therefore every second first transfer gate TG, is connected to a shared read stage, resulting in N / 2=4 read stages, R=4.

[0123] In the embodiment of FIG. 23, the light collecting region 231 is a pinned photodiode PPD, without limiting the present embodiment in this respect. Alternatively, the light collecting region 231 may be a photogate or a partially pinned photodiode, etc. In the embodiment of FIG. 23, the cascaded TG-based N-tap pixel with memory node is an 8-tap pixel (N=8), without limiting the present embodiment in this respect. Alternatively, the cascaded TG-based N-tap pixel may be a pixel having any number N, such as N=3, 4, 5, 6, 8, 9, 10, 11, 12 or more. The number of modulation stages is two in the embodiment of FIG. 23, with S=2 modulation stages, without limiting the present embodiment in this respect. The number of modulation stages may be any integer value.

[0124] In the embodiment of Fig. 23, one or more of the first transfer gates TG can operate as overflow gates OFG to filter out ambient light. When one or more of the first transfer gates TG operate as overflow gates OFG, the number of RST transistors and readout stages AMP and SEL can be reduced by one for each first transfer gate TG that permanently operates as an overflow gate OFG. The first transfer gates TG including the overflow gates OFG are controlled according to the timing diagrams as shown in Fig. 25 during the integration period and as shown in Fig. 26 during the readout period.

[0125] In the embodiment of Fig. 23, the first transfer gate TG, the second transfer gate TX and the overflow gate OFG may be implemented, for example, as transistors, and the memory node MEM may be implemented, for example, as a capacitor. By operating the first transfer gate TG, depth information from the incoming modulated light can be extracted.

[0126] FIG. 24 shows in schematic form one embodiment of a schematic diagram of a cascaded TG-based N-tap pixel with memory nodes of FIG. 23. A central light collecting region 231, here a pinned photodiode PPD, collects incident photons and generates a photocurrent. The central light collecting region 231 is directly connected to common gates CG0-CG3 which are directly connected to first transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B as described above. The generated photocurrent is transferred from the light collecting region 231 to the common gates CG0-CG3 and then to the first transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B. By opening one of the first transfer gates TG0A, TG0B, TG1 A, TG1B, TG2A, TG2B, TG3A, TG3B, the charge generated by the light collecting region 231 is transferred onto the respective memory MEM0A, MEM0B, MEM1A, MEM1B, MEM2A, MEM2B, MEM3A, MEM3B, where it is stored. That is, during integration, all the charge is stored in the memory node MEM. At this point, the second transfer gates TX0A, TX0B, TX1A, TX1B, TX2A, TX2B, TX3A, TX3B are closed. As a first step, the floating diffusion region FD is reset and their levels are read out. This reading gives the noise level of the reset transistor RST on the floating diffusion region FD. As a next step, the charge is transferred from the R MEM node to the floating diffusion region FD via the second transfer gate TX. After that, the floating diffusion level is read out again. The RST noise level can then be subtracted from the actual signal level to obtain the reset noise free signal. This process of reading out the reset and signal levels is repeated N / R times until all MEM node charges are read out. Reset transistors RST01, RST23, RST03, and RST12 are provided to reset the pixel. The floating diffusion level is reset via reset transistors RST01, RST23, RST03, and RST12 to prepare the pixel for the next integration period.

[0127] FIG. 25 shows a timing diagram during integration of the cascaded TG-based N-tap pixel with memory nodes of FIG. 23, where the transfer gate TX3B acts as an overflow gate OFG. A laser pulse with an LSR signal 2500 for illuminating a scene is activated for a predetermined illumination period. The common gates CG0-CG3 are controlled by control signals 2501-2504, respectively. According to this particular timing diagram of FIG. 23, each of the common gates CG0-CG3 of the cascaded TG-based N-tap pixel with memory nodes of FIG. 23 opens one after the other for a predetermined activation time window, as indicated by the control signals 2501-2504. As shown by the control signals 2505, 2507, 2509, 2511 of the transfer gates TG0A, TG1A, TG2A, TG3A, respectively, the first transfer gates TG0A, TG1A, TG2A, TG3A open one after the other for a predetermined activation time window whose window length is four times the previous stage CG on period. Each first transfer gate TG0A, TG1A, TG2A, TG3A opens simultaneously with the respective common gates CG0-CG3. The common gates CG0-CG3 open one after the other, and the common gate CG0 opens again at the time when the activation period of the common gate CG3 ends. As shown by the control signals 2506, 2508, 2510 of the first transfer gates TG0B, TG1B, TG2B, respectively, the transfer gates TG0B, TG1B, TG2B open one after the other for a predetermined activation time window whose window length is four times the previous stage CG on period. Each of the first transfer gates TG0B, TG1B, TG2B opens at the same time that the respective common gates CG0-CG2 open for the second time. Since the first transfer gate TG3B operates as an overflow gate OFG, the first transfer gate TG3B (see control signal 2512 in FIG. 25) opens at the same time that the common gate CG3 opens for the second time. Both the common gate CG3 and the first transfer gate TG3B remain open as necessary. After the signal charges have passed through all the stages, they end up in their respective storage nodes.Signal 2514 represents the control signal for memory node MEM[0A-3A, 0B-3B] which is constantly open during integration, signal 2515 represents the control signal for a second transfer gate TX[0A-3A, 0B-2B] which is constantly closed during integration, signal 2516 represents the control signal for a second transfer gate TX[3B] which is constantly open during integration, signal 2517 represents the control signal for a reset transistor RST[0A-3A, 0B-2B] which is constantly closed during integration, and signal 2518 represents the control signal for a reset transistor RST[3B] which is constantly open during integration.

[0128] 25, the second transfer gate TX3B operates as an overflow gate OFG, without limiting the embodiment in that respect. Alternatively, any other transfer gate may operate as an overflow gate OFG, or one or more transfer gates may operate as an overflow gate OFG, or none of the transfer gates may operate as an overflow gate OFG, etc.

[0129] Figure 26 shows a readout timing diagram for a cascaded TG-based N-tap pixel with the memory node of Figure 23, where the second transfer gate TX3B acts as an overflow gate OFG. During readout, signal 2600 represents the control signal for the common gate CG[i] (CG0 to CG3), which is closed during readout, and signal 2601 represents the control signal for the first transfer gate TG[i], which is closed during readout. Similarly, signals 2602 to 2608 represent control signals for memory nodes MEM[0A to 3A, 0B to 2B], respectively, signal 2609 represents a control signal for memory node MEM[3B], signals 2610 to 2616 represent control signals for second transfer gates TX[0A to 3A, 0B to 2B], respectively, signal 2617 represents a control signal for a second transfer gate TX[3B] operating as an overflow gate OFG, signals 2618 to 2620 represent control signals for reset transistors RST01, RST12, and RST23, signal 2621 represents a control signal for a reset transistor RST03 corresponding to the overflow gate OFG, signals 2622 to 2624 represent control signals for selection transistors SEL01, SEL12, and SEL23, respectively, and signal 2625 represents a control signal for a selection transistor SEL03 corresponding to the overflow gate OFG. Optionally, SEL03 can be clocked in a similar manner to the other control lines to improve symmetry of operation.

[0130] (TG-based N-tap pixel with cycling memory node) FIG. 27 illustrates a schematic top view of one embodiment of a TG-based N-tap pixel with cycling memory nodes.

[0131] A TG-based N-tap pixel 270 with circular memory nodes has a central light collecting region 271, N=8 first transfer gates TG0-TG7 that connect the central light collecting region 271 to source line nodes MEM, i.e. MEM0-MEM7. Each of the first transfer gates TG0-TG7 connects the light collecting region 271, which is a pinned photodiode PPD, to a respective memory node MEM0-MEM7. Each memory node MEM0-MEM7 is implemented as an intermediate storage node. Each memory node MEM0-MEM7 is then connected to a floating diffusion region FD (white octagon) via a respective second transfer gate TX0-TX7. Thus, multiple memory nodes MEM are connected to the same floating diffusion region FD. For example, here, two memory nodes MEM are connected to the same floating diffusion region FD, that is, memory nodes MEM0 and MEM1 are connected to the floating diffusion region FD01, memory nodes MEM2 and MEM3 are connected to the floating diffusion region FD23, memory nodes MEM4 and MEM5 are connected to the floating diffusion region FD45, and memory nodes MEM6 and MEM7 are connected to the floating diffusion region FD67. The floating diffusion region FD01 is connected on one side by two second transfer gates TX0, TX1, and on the other side by a reset transistor RST01. The floating diffusion region FD23 is connected on one side by two second transfer gates TX2, TX3, and on the other side by a reset transistor RST23. The floating diffusion region FD45 is connected on one side by two second transfer gates TX4 and TX5, and on the other side by a reset transistor RST45. The floating diffusion region FD67 is connected on one side by two second transfer gates TX6 and TX7 and on the other side by a reset transistor RST67. Similarly, each of the floating diffusion regions FD01, FD23, FD45, FD67 is connected to an associated read stage, i.e. an amplifier AMP connected to a select transistor SEL. As before, a shared read stage is connected to every two memory nodes MEM, resulting in N / 2 = 4 read stages, R = 4.

[0132] In the embodiment of FIG. 27, the TG-based N-tap pixel 270 is a TG-based N-tap pixel with a circulating memory node MEM. The function of transferring charge from one memory node MEM to the next memory node MEM is realized by inserting a memory shift gate MS between adjacent memory nodes MEM. For example, here, a memory shift gate MS0 is inserted between memory nodes MEM0 and MEM1. For example, charge is transferred from MEM0 to MEM1 and vice versa. Similarly, a memory shift gate MSI is inserted between memory nodes MEM1 and MEM2. For example, charge is transferred from MEM1 to MEM2 and vice versa. A memory shift gate MS2 is inserted between memory nodes MEM2 and MEM3. Charge is transferred from MEM2 to MEM3 and vice versa. A memory shift gate MS3 is inserted between memory nodes MEM3 and MEM4. For example, charge is transferred from MEM3 to MEM4 and vice versa. A memory shift gate MS4 is inserted between memory nodes MEM4 and MEM5, such as charge transferred from MEM4 to MEM5 and vice versa. A memory shift gate MS5 is inserted between memory nodes MEM5 and MEM6, such as charge transferred from MEM5 to MEM6 and vice versa. A memory shift gate MS6 is inserted between memory nodes MEM6 and MEM7, such as charge transferred from MEM6 to MEM7 and vice versa. A memory shift gate MS7 is inserted between memory nodes MEM7 and MEM0, such as charge transferred from MEM7 to MEM0 and vice versa. A representation of the above rotating charges in the TG-based N-tap pixel 270 of FIG. 27 with one memory node counterclockwise is shown with respect to FIG. 30 according to the timing diagram for the memory cycle operation of FIG. 29.

[0133] In the embodiment of FIG. 27, the light collecting region 271 is a pinned photodiode PPD. This embodiment is not limited in this respect. Alternatively, the light collecting region 271 may be a photogate or a partially pinned photodiode, etc. In the embodiment of FIG. 27, the TG-based N-tap pixel with a circular memory node is an 8-tap pixel (N=8), which is not limited in this respect. Alternatively, the TG-based N-tap pixel may be a pixel having any number N, for example, N=3, 4, 5, 6, 8, 9, 10, 11, 12 or more. Note that one or more of the transfer gates TG0-TG7 may act as an overflow gate OFG to allow ambient light to escape. If one or more of the transfer gates TG0-TG7 are the only ones that permanently act as overflow gates OFG, the number of RST transistors and readout stages AMP and SEL may be reduced by one for each transfer gate TG that permanently acts as an overflow gate OFG, provided that no other taps share the same readout circuit. During memory cycling, the transfer gates TG0 to TG7 including the overflow gate OFG are controlled according to a timing diagram as shown in Fig. 29. Here, the read timing is not shown, similar to the timing in Fig. 17, and the integration timing is not shown, similar to Fig. 14.

[0134] 27, the first transfer gates TG0 to TG7, the second transfer gates TX0 to TX7, and the overflow gate OFG may be implemented, for example, as transistors, and the memories MEM0 to MEM7 may be implemented, for example, as capacitors. By operating the transfer gates TG0 to TG7, depth information can be extracted from the incoming modulated light.

[0135] FIG. 28 shows an embodiment of a schematic diagram 280 of a TG-based N-tap pixel with cycling memory nodes of FIG. 27, where the number of taps is N=8 and the number of readout stages is R=4. The central light collecting region 271 is a pinned photodiode PPD, which collects incident photons and generates a photocurrent. The central light collecting region 271 is connected to first trans-transfer gates TG0-TG7, each of which is associated with a respective tap of the TG-based N-tap pixel. By opening one of the transfer gates TG0-TG7, the charge generated by the central light collecting region 271 is transferred onto a respective memory MEM0-MEM7 and stored there. The charge is transferred from one memory node MEM to the next through memory shift gates MS located between adjacent memory nodes MEM. The function of charge transfer between memory nodes MEM through memory shift gates MS is represented by the diagonal dashed lines connecting memory nodes MEM to memory shift gates MS, and during integration, all the charge is stored in memory node MEM. During readout, the second transfer gates TX0-TX7 are closed. As a first step, the floating diffusion region FD is reset and their levels are read out. This readout gives the noise level of the reset transistor RST on the floating diffusion region FD. As a next step, charges are transferred from the R MEM node to the floating diffusion region FD via the second transfer gates TX0-TX7. The floating diffusion level is then read out again. The RST noise level can then be subtracted from the actual signal level and a reset noise-free signal can be obtained. This process of reading out the reset and signal levels is repeated N / R times until all MEM node charges have been read out. To reset the pixel, reset transistors RST01, RST23, RST45, RST67 are provided. The floating diffusion levels are reset via the reset transistors RST01, RST23, RST45, RST67 to prepare the pixel for the next integration period.

[0136] In the embodiment of FIG. 28, N=8, R=4, and therefore R MEM nodes are equal to four MEM nodes. For example, the charges stored in MEM0, MEM2, MEM4 and MEM6 are transferred to the floating diffusion regions FD01, FD23, FD45, FD67 via the second transfer gates TX0, TX2, TX4 and TX6, respectively. By opening the second transfer gates TX0, TX2, TX4 and TX6, respectively, the charges collected on the memory nodes MEM0, MEM2, MEM4 and MEM6 are transferred to the amplifiers AMP0, AMP2, AMP4 and AMP6. Signals representing the charges in FD01, FD23, FD45, FD67 are transferred to the select transistors SEL01, SEL23, SEL45, SEL67, and the amplified signals are read out on the readout lines. Reset transistors RST01, RST23, RST45, RST67 are provided to reset the pixels. As mentioned above, charge is transferred from one memory node MEM to the next memory node MEM via a memory shift gate MS located between adjacent memory nodes MEM, which can result in a mismatch between the tap reductions.

[0137] FIG. 29 shows a timing diagram for memory cycling operation of a TG-based N-tap pixel with cycling memory nodes of FIG. 27, where transfer gate TG7 operates as an overflow gate OFG. In this embodiment, the timing diagram shows the function of cycling charge from one memory node MEM to the next memory node MEM. Signal 2900 represents the control signal for the first transfer gate TG0, signal 2901 represents the control signal for the first transfer gate TG[0-6], and signal 2902 represents the control signal for the first transfer gate TG7 operating as an overflow gate OFG in the embodiment of FIG. 29. As indicated by control signals 2903-2910, memory nodes MEM6-MEM0 close one after the other for a predetermined time. Charge is transferred to MS0 via memory shift MS7, which opens one after the other as indicated by respective control signals 2911-2917. After all seven signals, i.e. TG[0-6], have been shifted one MEM node counterclockwise, for example TG0 takes over the role of the overflow gate OFG function and no longer contains any signals.

[0138] 29, without limiting the present embodiment in that respect, the first transfer gate TG7 operates as the overflow gate OFG. Alternatively, any other transfer gate TG may operate as the overflow gate OFG, or none of the transfer gates TG of pixel 270 may operate as the overflow gate OFG.

[0139] FIG. 30 diagrammatically illustrates one embodiment of a conceptual representation 300 of rotating charge in a TG-based N-tap pixel with cycling memory nodes of FIG. 27, where one node rotates counterclockwise according to the timing diagram of FIG. 29.

[0140] During the integration period, as a first step, all memory nodes MEM and the central light collecting region 271 are reset. As a second step, tap 7 associated with the first and second transfer gates TG7, TX7 and their respective reset transistors RST are assigned to operate as overflow gates OFG. As a third step, the first and second transfer gates TG7, TX7 and their respective reset transistors RST are opened (turned on) to eliminate ambient light until the next sub-integration. As a fourth step, the overflow gate OFG is closed (turned off) and sequentially toggles with each other so that the first transfer gate TG captures depth information. As a fifth step, all transfer gates including the overflow gate are turned off, and as a sixth step, all charges are rotated counterclockwise as shown in FIG. 29 above. As a seventh step, taps are assigned to operate as overflow gates OFG associated with the first and second transfer gates TG, TX and their respective reset transistors RST counterclockwise adjacent to the current overflow gate OFG and therefore no longer contain a signal. As an eighth step, the timing controls for the first and second transfer gates TG and TX, respectively, and the respective reset transistors RST are updated so that the signals stored on each MEM on each tap have a consistent delay relative to the laser pulse. As a ninth step, steps 3-8 are repeated seven times for a total of eight sub-exposures. Optionally, steps 2-9 may be repeated for any integer amount of time.

[0141] In the embodiment of Figures 27-30, the exposure time of each signal is divided evenly across each tap so that mismatches associated with the collection and storage nodes of the pixel can be reduced. The readout timing is the same as the readout timing of pixel 150 with respect to Figure 15. Optionally, the mismatches associated with the readout portion can be reduced by sequentially transferring the signals from each intermediate storage node to a common readout node. This may trade mismatches and accuracy for readout speed (fps).

[0142] Note that other implementations for realizing memory cycles are also possible, such as CCD-like MEM (1.5-phase / 2-phase / ,,,). For example, a CCD-like MEM structure may allow utilizing all taps as signal integrators, but due to the larger area requirements for CCD-memory compared to MS gates, the QSAT of each tap may be reduced, i.e., less space may be available for each MEM node.

[0143] (Cascaded TG-based NTAP pixels with cycling memory nodes) FIG. 31 illustrates a schematic top view of one embodiment of a cascaded TG-based N-tap pixel with cycling memory nodes, where S=2, N1=4, N2=2, and R=4.

[0144] In the cascaded TG-based N-tap pixel 310, the number of taps is eight, N = 8 taps, the number of readout stages is four, R = 4 readout stages, the number of modulation stages is two, S = 2 modulation stages, N1 = 4, N2 = 2, where N x is the number of taps on each stage x connected to the output of each previous stage.

[0145] The cascaded TG-based N-tap pixel 310 has a central light collecting area 311 with 8 taps, N=8. The 8 taps are divided into two groups (N1, N2), each group associated with a respective modulation stage x. The first group has 4 taps, N1=4, and the second group has 2 taps, N2=2, connected to each output of the first stage. The cascaded TG-based N-tap pixel 310 has four common gates CG0-CG3 that connect the central light collecting area 311, which is a pinned photodiode PPD, to eight first transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B. Each first transfer gate TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B is associated with a respective tap of the pixel. Here, the common gate CG0 is directly connected to the first transfer gates TG0A and TG0B, the common gate CG1 is directly connected to the first transfer gates TG1A and TG1B, the common gate CG2 is directly connected to the first transfer gates TG2A and TG2B, and the common gate CG3 is directly connected to the first transfer gates TG3A and TG3B. Each first transfer gate TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B is connected to a respective memory node MEM0A, MEM0B, MEM1A, MEM1B, MEM2A, MEM2B, MEM2B, MEM3A, MEM3B. Each memory node MEM is implemented as an intermediate storage node. In the embodiment of FIG. 31, the N-tap pixel 310 is a cascaded TG-based N-tap pixel with a circulating memory node MEM. The ability to transfer charge from one memory node MEM to the next is achieved by inserting memory shift gates MS between adjacent memory nodes MEM, as described above with respect to Figure 27. Each memory node MEM is then connected to a floating diffusion region FD (white octagon) via a respective second transfer gate TX0A, TX0B, TX1A, TX1B, TX2A, TX2B, TX3A, TX3B. Thus, two memory nodes MEM are connected to the same floating diffusion region FD.

[0146] In the embodiment of FIG. 31, the two second transfer gates TX are connected to the same floating diffusion region FD, as similarly described with reference to FIG. 23 above. Each floating diffusion region FD01, FD03, FD12, FD23 is also connected to a respective reset transistor RST01, RST03, RST12, RST23, also as described with reference to FIG. 23. Similarly, each floating diffusion region FD01, FD03, FD12, FD23 is connected to an associated readout stage, i.e. an amplifier AMP connected to a select transistor SEL. Every two second transfer gates TX, and therefore every two first transfer gates TG, are connected to a shared readout stage, resulting in N / 2=4 readout stages, R=4. A timing diagram of the memory cycle operation of the N-tap pixel 310 is shown in FIG. 33.

[0147] In the embodiment of FIG. 31, the light collecting region 311 is a pinned photodiode PPD. This embodiment is not limited in this respect. Alternatively, the light collecting region 311 may be a photogate or a partially pinned photodiode, etc. In the embodiment of FIG. 31, the cascaded TG-based N-tap pixel with memory node is an 8-tap pixel (N=8), this embodiment is not limited in this respect. Alternatively, the cascaded TG-based N-tap pixel may be a pixel having any number N, such as N=3, 4, 5, 6, 8, 9, 10, 11, 12 or more. The number of modulation stages is two, S=2 modulation stages, in the embodiment of FIG. 31, this embodiment is not limited in this respect. The number of modulation stages may be any integer value.

[0148] In the embodiment of Figure 31, one or more of the first transfer gates TG can operate as overflow gates OFG to filter out ambient light. Note that when one or more of the first transfer gates TG operate as overflow gates OFG, the number of RST transistors and readout stages AMP and SEL can be reduced by one for each first transfer gate TG that permanently operates as an overflow gate OFG if no other taps share its readout stage.

[0149] In the embodiment of Fig. 31, the first transfer gate TG, the second transfer gate TX and the overflow gate OFG may be implemented, for example, as transistors, and the memory node MEM may be implemented, for example, as a capacitor. By operating the first transfer gate TG, depth information from the incoming modulated light can be extracted.

[0150] FIG. 32 shows an embodiment of a schematic diagram 320 of a TG-based N-tap pixel with cycling memory nodes of FIG. 31, where the number of taps is N=8 and the number of readout stages is R=4. The schematic diagram of pixel 310 shows the readout circuitry of pixel 310. The central light collecting area 231, here a pinned photodiode PPD, collects incident photons and generates a photocurrent. The central light collecting area 231 is directly connected to common gates CG0-CG3 which are directly connected to first transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B as described above. The generated photocurrent is transferred from the light collecting area 231 to the common gates CG0-CG3 and then to the first transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B. By opening one of the first transfer gates TG0A, TG0B, TG1A, TG1B, TG2A, TG2B, TG3A, TG3B, the charge generated by the light collecting region 231 is transferred onto the respective memory MEM0A, MEM0B, MEM1A, MEM1B, MEM2A, MEM2B, MEM3A, MEM3B where it is stored. That is, during integration, all the charge is stored in the memory node MEM. The charge is transferred from one memory node MEM to the next through the memory shift gate MS located between the adjacent memory nodes MEM. The charge transfer function between the memory nodes MEM through the memory shift gate MS is represented by the diagonal dashed lines connecting the memory nodes MEM to the memory shift gate MS, and during the memory cycling operation, the second transfer gates TX0A, TX0B, TX1A, TX1B, TX2A, TX2B, TX3A, TX3B are closed. The integration process of this embodiment is the same as the integration process described in the embodiment with respect to Figures 24 and 28 above.

[0151] In the embodiment of FIG. 28, N=8, R=4, and therefore R MEM nodes are equal to four MEM nodes. For example, the charges stored in MEM0, MEM2, MEM4 and MEM6 are transferred to the floating diffusion regions FD01, FD23, FD45, FD67 via the second transfer gates TX0, TX2, TX4 and TX6, respectively. By opening the second transfer gates TX0, TX2, TX4 and TX6, respectively, the charges collected on the memory nodes MEM0, MEM2, MEM4 and MEM6 are transferred to the amplifiers AMP0, AMP2, AMP4 and AMP6. Signals representing the charges in FD01, FD23, FD45, FD67 are transferred to the select transistors SEL01, SEL23, SEL45, SEL67, and the amplified signals are read out on the readout lines. Reset transistors RST01, RST23, RST45, RST67 are provided to reset the pixels. As mentioned above, charge is transferred from one memory node MEM to the next memory node MEM via a memory shift gate MS located between adjacent memory nodes MEM, which can result in a mismatch between the tap reductions.

[0152] FIG. 33 shows a timing diagram during integration of the cascaded TG-based N-tap pixel with memory nodes of FIG. 31, where the transfer gate TX3B acts as an overflow gate OFG. A laser pulse with an LSR signal 3300 for illuminating a scene is activated for a predetermined illumination period. The common gates CG0-CG3 are controlled by control signals 3301-3304, respectively. According to this particular timing diagram of FIG. 33, each of the common gates CG0-CG3 of the cascaded TG-based N-tap pixel with cycling memory nodes 310 of FIG. 33 opens one after the other for a predetermined activation time window, as the control signals 3301-3304 are shown. As shown in the control signals 3305, 3307, 3309, 3311 for the transfer gates TG0A, TG1A, TG2A, TG2A, TG3A, respectively, the first transfer gates TG0A, TG1A, TG2A, TG2A, TG3A open one after the other for a predetermined activation time window whose window length is four times the previous stage CG on period. Each first transfer gate TG0A, TG1A, TG2A, TG3A opens simultaneously with a respective common gate CG0-CG3. The common gates CG0-CG3 open one after the other, with the common gate CG0 opening again at the time when the activation period of the common gate CG3 ends. As shown in the control signals 3306, 3308, 3310 for the first transfer gates TG0B, TG1B, TG2B, respectively, the transfer gates TG0B, TG1B, TG2B open one after the other for a predetermined activation time window whose window length is four times the previous stage CG on period. Each of the first transfer gates TG0B, TG1B, TG2B opens at the same time that the respective common gates CG0-CG2 open for the second time. Since the first transfer gate TG3B operates as an overflow gate OFG, the first transfer gate TG3B (see control signal 3312 in FIG. 33) opens at the same time that the common gate CG3 opens for the second time. Both the common gate CG3 and the first transfer gate TG3B remain open as necessary. After the signal charges have passed through all stages, they end up in their respective storage nodes.Signal 3314 represents the control signal of the memory node MEM[0A-3A, 0B-3B] which is constantly open during integration, signal 3315 represents the control signal of the memory shift MS[0A-3A, 0B-3B], signal 3316 represents the control signal of the second transfer gate TX[0A-3A, 0B-2B] which is constantly closed during integration, signal 3317 represents the control signal of the second transfer gate TX[3B] which is constantly closed during integration, signal 3318 represents the control signal of the reset transistor RST[0A-3A, 0B-2B] which is constantly closed during integration, and signal 3319 represents the control signal of the reset transistor RST[3B] which is constantly open during integration.

[0153] 33, the second transfer gate TX3B operates as an overflow gate OFG, without limiting the embodiment in that respect. Alternatively, any other transfer gate may operate as an overflow gate OFG, or one or more transfer gates may operate as an overflow gate OFG, or none of the transfer gates may operate as an overflow gate OFG, etc.

[0154] Note that in the embodiment of Figure 33, multiple sub-exposures can be used and the accumulated charge can be shifted to adjacent MEM nodes before the next sub-exposure begins. The readout timing diagram for the cascaded TG-based N-tap pixel with cycling memory nodes of Figure 31 is identical to the readout timing diagram for pixel 150 (see Figure 15).

[0155] FIG. 34 shows a timing diagram for a memory cycle operation of the cascaded TG-based N-tap pixel with cycling memory nodes of FIG. 31, where the transfer gate TX3B operates as an overflow gate OFG. This timing diagram is an example of the memory cycle described with respect to FIGS. 33 and 34 above. In this embodiment, the timing diagram shows the function of cycling charge from one memory node MEM to the next memory node MEM. Signal 3400 represents the control signal for the common gate CG0, signal 3401 represents the control signal for the common gate CG[l-2], and signal 3402 represents the control signal for the common gate CG3. Signal 3403 represents the control signal for the first transfer gate TG0A, signal 3404 represents the control signal for the first transfer gate TG[0B-3A], and signal 3405 represents the control signal for the first transfer gate TG3B, which operate as the overflow gate OFG in the embodiment of FIG. 31. As shown by control signals 3406-3413, memory nodes MEM3B-MEM0A open one after the other for a predetermined time. Charge is transferred to MS0A via memory shift MS3B, which opens one after the other as shown by respective control signals 3414-3421. Signal 3422 represents the control signal for the second transfer gate TX0A, signal 3423 represents the control signal for the second transfer gate TX[0B-3A], and signal 3424 represents the control signal for the second transfer gate TX3B. Signal 3425 represents the control signal for the reset transistor RST03, signal 3426 represents the control signal for the reset transistor RST[01,12,23], and signal 3427 represents the control signal for the select transistor SEL[0A-3A]. In the timing diagram of FIG. 34 for a memory cycle operation for pixel 310 of FIG. 31, tap 3B is operated as an overflow gate OFG before the cycle. After all seven signals, i.e. TG[0A-3A], have been shifted one MEM node counterclockwise, for example TG0A takes over the role of the overflow gate OFG function and no longer contains any signal.

[0156] (TG-based N-tap pixel without a central photo-acquisition area) 35 shows a schematic top view of one embodiment of a cascaded TG-based N-tap pixel without a central light collection region, where S=2, N1=4, N2=2, and R=4.

[0157] The cascaded TG-based N-tap pixel 350 of Figure 35 is formed like the cascaded TG-based N-tap pixel with circular memory nodes (see 310 of Figure 31), with the central light collection area omitted. In the cascaded TG-based N-tap pixel 350, the number of taps is eight, N = 8 taps, the number of readout stages is four, R = 4 readout stages, the number of modulation stages is two, S = 2 modulation stages, N1 = 4, N2 = 2, where N x is the number of taps on each stage x connected to the output of each previous stage. The eight taps are divided into two groups (N1, N2), each group associated with a different modulation stage x. The first group has four gates, N1 = 4, the second group has two gates, N2 = 2.

[0158] The cascaded TG-based N-tap pixel 350 of FIG. 35 has four common gates CG0-CG3 that are directly connected to the first transfer gates TG[0A-3B], as described in more detail in FIG. 31 above. The cascaded TG-based N-tap pixel 350 of FIG. 35 does not have a central light collection area for collecting charge. In this way, the charge is directly guided to the first modulation step via the auxiliary electrodes, i.e., the common gates CG0-CG3. Each first transfer gate TG[0A-3B] is connected to a respective memory node MEM[0A-3B], each memory node MEM being implemented as an intermediate storage node, as described in more detail in FIG. 31 above. The function of transferring charge from one memory node MEM to the next memory node MEM is realized by inserting a memory shift gate MS between adjacent memory nodes MEM, as described in more detail in FIG. 31 above. Each memory node MEM is then connected to a floating diffusion region FD (white octagon) via a respective second transfer gate TX[0A-3B]. Therefore, the two memory nodes MEM are connected to the same floating diffusion region FD.

[0159] In the embodiment of Figure 35, the auxiliary gates are realized by surface or buried gate elements such as common gates CG0-CG3. Four auxiliary gates are used as a first stage modulator technique to replace the central light collecting region, reduce the pixel area, and reduce the total electron path length.

[0160] Figure 36 illustrates generally one embodiment of a schematic 360 of a TG-based N-tap pixel with a circular memory node and no central light collection region, where the number of taps is N = 8 and the number of readout stages is R = 4. The schematic 360 of Figure 36 and its functionality is the same as the schematic 320 of Figure 32, without the central light collection region.

[0161] FIG. 37 shows a timing diagram during integration of a cascaded TG-based N-tap pixel with cycling memory nodes and no central light collection region of FIG. 35, where the transfer gate TX3B operates as an overflow gate OFG, and FIG. 38 shows a timing diagram for memory cycle operation of a cascaded TG-based N-tap pixel with cycling memory nodes and no central light collection region of FIG. 35, where the transfer gate TX3B operates as an overflow gate OFG. The operation, schematic, and timing diagram of the cascaded TG-based N-tap pixel with memory nodes and no central light collection region of FIG. 35 is the same as that of the cascaded TG-based N-tap pixel with cycling memory nodes of FIG. 31 (see FIGS. 32, 33, and 34). The timing and levels of the signals described with respect to FIGS. 32, 33, and 34, and therefore with respect to FIGS. 36, 37, and 38, respectively, are not intended to limit the disclosure in that respect. Timing may be updated to optimize charge collection. For example, the use of intermediate bias levels can be implemented for improved charge collection.

[0162] (Cascaded TG-based N-tap pixel with first-stage CAPD modulation circuit) 39 shows a schematic of one embodiment of a cascaded TG-based N-tap pixel with cycle memory nodes, where S = 2, N1 = 4, N2 = 2, and R = 4. With the first stage CAPD modulation circuit located at the pixel boundary, a mirrored pixel arrangement can be used to avoid contention for first stage modulation circuit bias between adjacent pixels.

[0163] In the cascaded TG-based N-tap pixel 390, the number of taps is 8, N = 8 taps, the number of readout stages is 4, R = 4 readout stages, the number of modulation stages is 2, S = 2 modulation stages, N1 = 4, N2 = 2, where N xis the number of taps on each stage x. The eight taps are divided into two groups (N1, N2), each group associated with a respective modulation stage x. The first modulation stage has four mixing elements, N1 = 4, and the second modulation stage has two mixing elements, N2 = 2.

[0164] The cascaded TG-based N-tap pixel 390 has N1=4 CAPD modulation circuits in the first modulation stage, i.e., MIX0 to MIX3. Each CAPD modulation circuit in MIX0 to MIX3 directs charge to their associated N1=4 first collector regions, i.e., CC0 to CC3. Each of the first collector regions CC0 to CC3 can be a pinned photodiode (PPD), a p-type pinned photodiode (PPPD), a photogate (PG), etc. The central collector region CC0 to CC3 acts as an intermediate node through which the charge passes to the next modulation stage, i.e., the second modulation stage. The second modulation stage has N2=2 modulators associated with each CAPD modulator in the first modulation stage. The second modulation step modulation circuit is the first transfer gate TG0A-TG3B, MIX0 and CC0 are directly connected to the first transfer gate TG0A and TG0B, MIX1 and CC1 are directly connected to the first transfer gate TG1A and TG1B, MIX2 and CC2 are directly connected to the first transfer gate TG2A and TG2B, and MIX3 and CC3 are directly connected to the first transfer gate TG3A and TG3B. When the charge passes through the second step modulation circuit TG0A-TG3B, the operation on the charge is similar to the pixel structure with cycle memory nodes of Figures 27, 31 and 35 described in detail above.

[0165] Each first transfer gate TG[0A-3B] is connected to a respective memory node MEM[0A-3B], and each memory node MEM is implemented as an intermediate storage node, as described in more detail in FIG. 31 above. The function of transferring charge from one memory node MEM to the next memory node MEM is realized by inserting a memory shift gate MS between adjacent memory nodes MEM, as described in more detail in FIG. 31 above. Each memory node MEM is then connected to a floating diffusion region FD (white octagon) via a respective second transfer gate TX[0A-3B]. Thus, two memory nodes MEM are connected to the same floating diffusion region FD.

[0166] In the embodiment of Figure 39, there are two modulation stages, S = 2, and this embodiment is not limited in this respect. Alternatively, more than two modulation stages can be formed, in which case the second modulation circuit and higher stage modulation circuits include, for example, TG, vertical gate (VG), etc.

[0167] Figure 40 diagrammatically illustrates one embodiment of a schematic diagram 400 of a TG-based N-tap pixel with cycling memory nodes and first stage CAPD modulation circuits of Figure 39. As illustrated in Figure 39, the first collector regions CC0-CC3 pass charge from the first stage modulation circuit to the second stage modulation circuit, i.e., the CAPD modulation circuits MIX0-MIX3 form the transfer gates TG0A-TG3B.

[0168] FIG. 41 shows a timing diagram during integration of a cascaded TG-based N-tap pixel with a cycling memory node and the first stage CAPD modulator of FIG. 39, where the transfer gate TX3B acts as an overflow gate OFG, and FIG. 42 shows a timing diagram for the memory cycle node operation of a cascaded TG-based N-tap pixel with a cycling memory node and the first stage CAPD modulator of FIG. 39, where the transfer gate TX3B acts as an overflow gate OFG. The operation, schematic and timing diagrams for the cascaded TG-based N-tap pixel with cycling memory nodes and the first stage CAPD modulation circuit of FIG. 39 are the same as those for the cascaded TG-based N-tap pixel with cycling memory nodes of FIG. 31 (see FIGS. 32, 33 and 34), with the common gate CG0 to CG3 of FIGS. 31, 32, 33 and 34 being replaced by CAPD modulation circuits MIX0-MIX3 in the embodiments of FIGS. 39, 40, 41 and 42. The timing and levels of the signals described with respect to FIGS. 32, 33 and 34, and therefore with respect to FIGS. 40, 41 and 42, respectively, are not intended to limit the disclosure in that respect. Timing may be updated to optimize charge collection. For example, the use of intermediate bias levels may be implemented for improved charge collection.

[0169] (Cascaded TG-based NTAP pixel with first-stage CAPD and photogate) 43 shows a schematic top view of one embodiment of a cascaded TG-based N-tap pixel with a cycling memory node, a first stage CAPD modulation circuit and a photogate, where S=2, N1=4, N2=2, and R=4. If the first stage CAPD modulation circuit is placed at the pixel boundary, a mirrored pixel arrangement can be used to avoid conflicts regarding first stage modulation circuit bias between adjacent pixels.

[0170] In the cascaded TG-based N-tap pixel 430, the number of taps is 8, N = 8 taps, the number of readout stages is 4, R = 4 readout stages, the number of modulation stages is 2, S = 2 modulation stages, N1 = 4, N2 = 2, where N x is the number of taps on each stage connected to each output of the previous stage. The eight taps are divided into two groups (N1, N2), each group associated with a respective modulation stage x. The first modulation stage has four mixing elements, N1 = 4, and the second modulation stage has two gates, N2 = 2, connected to each output of the previous stage.

[0171] The cascaded TG-based N-tap pixel 430 has N1=4 CAPD modulators in the first modulation stage, i.e., MIX0-MIX3, which do not require a central collector to operate as the CAPD modulators MIX0-MIX3 of FIG. 39. The CAPD modulation circuits MIX0-MIX3 direct charge to photogates PG0A-PG3B. Each CAPD modulation circuit MIX directs charge to two respective photogates PG. For example, CAPD modulator MIX0 directs charge to photogates PG0A and PG0B, CAPD modulator MIX1 directs charge to photogates PG1A and PG1B, CAPD modulator MIX2 directs charge to photogates PG2A and PG2B, and CAPD modulator MIX3 directs charge to photogates PG3A and PG3B.

[0172] In the embodiment of Figure 43, the first collector region CC and CAPD modulation circuit MIX of Figure 39 are replaced by CAPD modulation circuits MIX0 to MIX3, and the photogates PG0A to PG3B, which do not need to operate the central collector of Figure 43, function as pinned photodiodes (PPDs) and the first transfer gates TG0A to TG3B of Figure 39, as a result of which the speed of the second modulation stage, i.e., the modulation stage of the photogates PG0A to PG3B, can be improved.

[0173] Figure 44 diagrammatically illustrates one embodiment of a schematic diagram 440 of a TG-based N-tap pixel with cycling memory nodes and first stage CAPD modulators and photogates of Figure 43. As described in Figure 43, charge passage from the first stage modulation circuit to the second stage modulation circuit, i.e., charge passage to the CAPD modulation circuits MIX0-MIX3 photogates PG0A-PG3B, is formed.

[0174] FIG. 45 shows a timing diagram during integration of the cascaded TG-based N-tap pixel with cycling memory node and first stage CAPD modulator and photogate of FIG. 43, where transfer gate TX3B acts as overflow gate OFG, and FIG. 46 shows a timing diagram for memory cycle operation of the cascaded TG-based N-tap pixel with cycling memory node and first stage CAPD modulator and photogate of FIG. 43, where transfer gate TX3B acts as overflow gate OFG. The operation, schematic and timing diagrams of the cascaded TG-based N-tap pixel with cycling memory node and first stage CAPD modulator and photogates of FIG. 43 are the same as for the cascaded TG-based N-tap pixel with cycling memory node and first stage CAPD modulator of FIG. 39 (see FIGS. 40, 41 and 42), with the first collector region CC and transfer gates TG0A-TG3B to TG3B of FIG. 39, FIG. 40, FIG. 41 and FIG. 42 being replaced by photogates PG0A-PG3B in the embodiments of FIG. 43, FIG. 44, FIG. 45 and FIG. 46. The timing and levels of the signals described with respect to FIG. 40, 41 and 42, and therefore with respect to FIG. 44, 45 and 46, respectively, are not intended to limit the disclosure in that respect. Timing may be updated to optimize charge collection. For example, the use of intermediate bias levels may be implemented for improved charge collection.

[0175] (implementation) FIG. 47 illustrates in schematic form an embodiment of an iToF device that can implement a process of performing depth measurement using N-tap pixels. The electronic device 470 can further implement all other processes of a standard iToF / SpotToF system. The electronic device 470 comprises a CPU 471 as a processor. The electronic device 470 further comprises an iToF sensor 476 connected to the processor 471. The processor 471 can, for example, implement performing depth measurement of the N-tap pixels. The electronic device 470 further comprises a user interface 477 connected to the processor 471. The user interface 477 serves as a man-machine interface and allows interaction between an administrator and the electronic system. For example, an administrator can configure the system using the user interface 477. The electronic device 470 further comprises a Bluetooth interface 474, a WLAN interface 475, and an Ethernet interface 478. These units 474, 475, and 478 serve as I / O interfaces for data communication with Windows. For example, a video camera with an Ethernet, WLAN or Bluetooth connection may be coupled to the processor 471 via these interfaces 474, 475 and 478. The electronic device 470 further comprises a data storage 472 and a data memory 473 (here a RAM). The data storage 472 is arranged as a long-term storage, for example for recording iToF sensor data obtained from the iToF sensor 476, etc., for storing parameters for one or more use cases. The data memory 473 is arranged to temporarily store or cache data or computer instructions for processing by the processor 471.

[0176] It should be noted that the above descriptions are merely example configurations, and alternative configurations may be implemented using additional or other sensors, storage devices, interfaces, etc.

[0177] It should be understood that the above-described embodiments describe methods with exemplary ordering of method steps. However, the particular ordering of method steps is provided for illustrative purposes only and should not be construed as binding.

[0178] It should also be noted that the division of the electronic device of FIG. 47 into units is done for illustrative purposes only, and the present disclosure is not limited to any particular division of functionality in particular units. For example, at least a portion of the circuitry may be realized by a respectively programmed processor, a field programmable gate array (FPGA), dedicated circuitry, etc. All units and entities described herein and claimed in the appended claims may be implemented, for example, as integrated circuit logic on a chip, unless otherwise noted, and the functionality provided by such units and entities may be implemented by software, unless otherwise noted.

[0179] In so far as the embodiments of the disclosure described above are implemented, at least in part, using software-controlled data processing apparatus, it will be understood that computer programs providing such software control, and the transmission, storage, or other media on which such computer programs are provided, are contemplated as aspects of the present disclosure.

[0180] The present technology can also be configured as follows. (1) a pixel array (21) including a plurality of pixels (30; 70; 80; 90; 120; 150; 180; 210; 230; 270; 310; 350; 390; 430), each pixel having three or more taps (GD1-9; GD1-16; TG0-7; TG0A-3B; TG0AA-3BB); a readout circuit (22, 24, 25) configured to read out the charge collected at each of the three or more taps; Equipped with An indirect time-of-flight sensor (20). (2) the tap of each pixel is configured to collect charge generated by a light collecting region (77; 87; 121; 151; 181; 211; 231; 271; 311; 351); An indirect time-of-flight sensor (20) as described in (1). (3) Each pixel (30; 70; 80) includes a mixing element (GD1-9), each mixing element corresponding to one of the taps. An indirect time-of-flight sensor (20) according to (1) or (2). (4) Each pixel (30; 70; 80) is a current-assisted optical demodulator (CAPD)-based pixel. An indirect time-of-flight sensor (20) as described in (3). (5) one of the mixing elements (GD1-9) operates as an overflow collector (OFC) having a pulse duration longer than the pulse durations of the remaining mixing gates of the mixing gates (GD1-9); An indirect time-of-flight sensor (20) as described in (4). (6) Each pixel (70) is formed by a CAPD element. An indirect time-of-flight sensor (20) as described in (4). (7) Each pixel (80) is formed by separate CAPD elements (86), said separate CAPD elements (86) being separated by p-wells (85). An indirect time-of-flight sensor (20) as described in (4). (8) Each of the separate CAPD elements (86) is configured to operate as either a 16-tap pixel (91) or four 4-tap pixels (92). An indirect time-of-flight sensor (20) as described in (7). (9) The light collecting area is a central light collecting area (121; 151; 181; 211; 231; 271; 311). An indirect time-of-flight sensor (20) as described in (2). (10) Each pixel (120; 150; 180; 210; 230; 270; 310) includes a transfer gate (TG0-7; TG0A-3B; TG0AA-3BB), each of which corresponds to a respective tap. An indirect time-of-flight sensor (20) as described in (9). (11) Each pixel is a TG-based pixel (120; 150; 270). An indirect time-of-flight sensor (20) as described in (10). (12) Each pixel is a cascaded TG-based pixel (180; 210; 230; 310). An indirect time-of-flight sensor (20) as described in (10). (13) The readout circuit (22, 23, 24, 25) is configured to sequentially open the transfer gates (TG1-8; TG0-7; TG0A-3B) of the taps of each of the pixels (120; 150; 180; 210; 230; 270; 310) for a predetermined period of time to obtain a depth measurement. An indirect time-of-flight sensor (20) as described in (10). (14) One of the transfer gates (TG1-8; TG0-7; TG1A-3B) operates as an overflow gate (OFG) having a pulse duration longer than the pulse durations of the remaining transfer gates of the transfer gates (TG1-8; TG0-7; TG0A-3B). An indirect time-of-flight sensor (20) as described in (10). (15) Each of the transfer gates (TG0-7) of the TG-based pixels (120; 150; 270) connects the central light collection region (121) to a respective floating diffusion region (FD). An indirect time-of-flight sensor (20) as described in (11). (16) The TG-based pixel (150; 270) further comprises a memory node (MEM0-7) for intermediate charge storage. An indirect time-of-flight sensor (20) as described in (11). (17) The transfer gate is a first transfer gate (TG0-3), The TG-based pixel (150; 270) further includes a floating diffusion region (FD01), a plurality of memory nodes (MEM0, MEM1) respectively connected to a plurality of second transfer gates (TX0, TX1), and a memory node (MEM0, MEM1) connected to the floating diffusion region (FD01) via the plurality of second transfer gates (TX0, TX1). An indirect time-of-flight sensor (20) as described in (11). (18) The transfer gate is a first transfer gate (TG0-3), and the TG-based pixel (150; 270) further includes a floating diffusion region (FD01), two or more memory nodes (MEM0, MEM1), and two or more respective second transfer gates (TX0, TX1), the two or more memory nodes (MEM0, MEM1) being connected to the floating diffusion region (FD01) via the two or more second transfer gates (TX0, TX1). An indirect time-of-flight sensor (20) as described in (17). (19) The TG-based pixel (270) further includes a memory shift gate (MS0) configured to transfer charge from one memory node (MEM0) of two memory nodes (MEM0, MEM1) to another memory node (MEM1) of the memory nodes (MEM0, MEM1), the two memory nodes (MEM0, MEM1) being adjacent to each other. An indirect time-of-flight sensor (20) as described in (18). (20) The memory shift gate (MS0-7) is located between the two memory nodes (MEM0, MEM1). An indirect time-of-flight sensor (20) as described in (19). (21) The cascaded TG-based pixels (180; 230; 310; 350) further include a common gate (CG0-3) representing a first modulation stage. An indirect time-of-flight sensor (20) as described in (12). (22) The common gate (CG0-3) connects the central light collecting region (181) to each floating diffusion region (FD) via a respective transfer gate (TG0A-3B), the respective transfer gate (TG0A-3B) representing a second modulation stage. An indirect time-of-flight sensor (20) as described in (21). (23) The cascaded TG-based pixel (210) further includes a first common gate (CG0-3) representing a first modulation stage. An indirect time-of-flight sensor (20) as described in (12). (24) The cascaded TG-based pixel (210) further comprises a second common gate (CG0A) representing a second modulation stage, the second common gate (CG0A) connecting the first common gate (CG0) to two respective transfer gates (TG0AA, TG0AB). An indirect time-of-flight sensor (20) as described in (23). (25) The cascaded TG-based pixel (230) further includes a memory node (MEM0A-1A) for intermediate charge storage. An indirect time-of-flight sensor (20) as described in (21). (26) The transfer gate is a first transfer gate (TG0A-3B), and the TG-based pixel (230) further includes a floating diffusion region (FD01), a plurality of memory nodes (MEM0B, MEM1A), and a plurality of respective second transfer gates (TX0B, TX1A), the plurality of memory nodes (MEM0B, MEM1A) being connected to the floating diffusion region (FD01) via the respective plurality of second transfer gates (TX0B, TX1A). An indirect time-of-flight sensor (20) as described in (22). (27) The transfer gate is a first transfer gate (TG0A-3B), and the TG-based pixel (230) further includes a floating diffusion region (FD01), two or more memory nodes (MEM0B, MEM1A), and two or more respective second transfer gates (TX0B, TX1A), the two or more memory nodes (MEM0B, MEM1A) being connected to the floating diffusion region (FD01) via the two or more second transfer gates (TX0B, TX1A). An indirect time-of-flight sensor (20) as described in (22). (28) The cascaded TG-based pixel (310) further includes a memory shift gate (MS0B) configured to transfer charge from one memory node (MEM0B) of two memory nodes (MEM0B, MEM1A) to another memory node (MEM1A) of the memory nodes (MEM0B, MEM1A), the two memory nodes (MEM0B, MEM1A) being adjacent to each other. An indirect time-of-flight sensor (20) as described in (27). (29) The light collecting area is an intermediate light collecting area including a plurality of central light collecting areas (CCO-3), each of the central light collecting areas (CCO-3) being connected to a respective CAPD modulation circuit (MIX0-3). An indirect time-of-flight sensor (20) as described in (2). (30) Each pixel is a cascaded TG-based pixel (350), the cascaded TG-based pixel (350) including a common gate (CG0-3) configured to generate charge and direct the charge directly to a first transfer gate (TG0A-3B). An indirect time-of-flight sensor (20) according to any one of (1) to (29). (31) Each pixel is a cascaded TG-based pixel (350) without a central light-collecting area. An indirect time-of-flight sensor (20) according to any one of (1) to (30). (32) Each pixel is a cascaded TG-based pixel (430) including a CAPD modulation circuit (MIX0) and two respective photogates (PG0A, PG0B) representing a first modulation stage. An indirect time-of-flight sensor (20) according to any one of (1) to (31). (33) An electronic device comprising the indirect time-of-flight sensor according to (1).

Claims

1. a pixel array including a plurality of pixels, each pixel having three or more taps; a readout circuit configured to read out the charge collected at each of the three or more taps; and Equipped with Indirect time-of-flight sensor.

2. The tap of each pixel is configured to collect charge generated by the light collection region.

2. The indirect time-of-flight sensor of claim 1.

3. Each pixel includes a mixing element, each mixing element corresponding to one of the taps.

2. The indirect time-of-flight sensor of claim 1.

4. Each pixel is a current-assisted optical demodulator (CAPD)-based pixel.

4. An indirect time-of-flight sensor as defined in claim 3.

5. One of the mixing elements acts as an overflow collector having a pulse duration longer than the pulse durations of the remaining mixing gates of the mixing gates.

5. An indirect time-of-flight sensor as defined in claim 4.

6. Each pixel is formed by a CAPD element.

5. An indirect time-of-flight sensor as defined in claim 4.

7. Each pixel is formed by separate CAPD elements, the separate CAPD elements being separated by p-wells.

5. An indirect time-of-flight sensor as defined in claim 4.

8. Each of the separate CAPD elements is configured to operate as either a 16-tap pixel or four 4-tap pixels.

8. An indirect time-of-flight sensor as defined in claim 7.

9. The light collecting area is a central light collecting area.

3. The indirect time-of-flight sensor of claim 2.

10. Each pixel includes a transfer gate, and each transfer gate corresponds to a respective tap.

10. The indirect time-of-flight sensor of claim 9.

11. Each pixel is a TG-based pixel.

11. The indirect time-of-flight sensor of claim 10.

12. Each pixel is a cascaded TG-based pixel 11. The indirect time-of-flight sensor of claim 10.

13. The readout circuit is configured to sequentially open the transfer gates of the taps of each of the pixels for a predetermined period of time to obtain a depth measurement.

11. The indirect time-of-flight sensor of claim 10.

14. One of the transfer gates acts as an overflow gate having a pulse duration longer than the pulse durations of the remaining ones of the transfer gates.

11. The indirect time-of-flight sensor of claim 10.

15. Each of the transfer gates of the TG-based pixels connects the central light collection region to a respective floating diffusion region.

12. An indirect time-of-flight sensor as defined in claim 11.

16. The TG-based pixel further comprises a memory node for intermediate charge storage.

12. An indirect time-of-flight sensor as defined in claim 11.

17. the transfer gate is a first transfer gate; The TG-based pixel further includes a floating diffusion region, a plurality of memory nodes each connected to a plurality of second transfer gates, and a memory node connected to the floating diffusion region via the plurality of second transfer gates.

12. An indirect time-of-flight sensor as defined in claim 11.

18. The transfer gate is a first transfer gate, and the TG-based pixel further includes a floating diffusion region, two or more memory nodes, and two or more respective second transfer gates, the two or more memory nodes being connected to the floating diffusion region via the two or more second transfer gates.

20. The indirect time-of-flight sensor of claim 17.

19. The TG-based pixel further includes a memory shift gate configured to transfer charge from one of two memory nodes to another of the memory nodes, the two memory nodes being adjacent to each other.

20. The indirect time-of-flight sensor of claim 18.

20. The memory shift gate is located between the two memory nodes.

20. The indirect time-of-flight sensor of claim 19.

21. The cascaded TG-based pixels further include a common gate representing a first modulation stage.

13. An indirect time-of-flight sensor as defined in claim 12.

22. The common gate connects the central light collecting region to each floating diffusion region through a respective transfer gate, the respective transfer gate representing a second modulation stage.

22. The indirect time-of-flight sensor of claim 21.

23. The cascaded TG-based pixels further include a first common gate representing a first modulation stage.

13. An indirect time-of-flight sensor as defined in claim 12.

24. The cascaded TG-based pixel further comprises a second common gate representing a second modulation stage, the second common gate connecting the first common gate to two respective transfer gates.

24. An indirect time-of-flight sensor as defined in claim 23.

25. The cascaded TG-based pixels further include a memory node for intermediate charge storage.

22. The indirect time-of-flight sensor of claim 21.

26. The transfer gate is a first transfer gate, and the TG-based pixel further includes a floating diffusion region, a plurality of memory nodes, and a plurality of respective second transfer gates, the plurality of memory nodes being connected to the floating diffusion region via the respective plurality of second transfer gates.

23. An indirect time-of-flight sensor as defined in claim 22.

27. The transfer gate is a first transfer gate, and the TG-based pixel further includes a floating diffusion region, two or more memory nodes, and two or more respective second transfer gates, the two or more memory nodes being connected to the floating diffusion region via the two or more second transfer gates.

23. An indirect time-of-flight sensor as defined in claim 22.

28. The cascaded TG-based pixel further includes a memory shift gate configured to transfer charge from one of the two memory nodes to another of the two memory nodes, the two memory nodes being adjacent to each other.

28. An indirect time-of-flight sensor as defined in claim 27.

29. The light collecting area is an intermediate light collecting area including a plurality of central light collecting areas, each of the central light collecting areas being connected to a respective CAPD modulation circuit.

3. The indirect time-of-flight sensor of claim 2.

30. Each pixel is a cascaded TG-based pixel, the cascaded TG-based pixel including a common gate configured to generate charge and direct the charge directly to a first transfer gate.

2. The indirect time-of-flight sensor of claim 1.

31. Each pixel is a cascaded TG-based pixel with no central light-collecting area 2. The indirect time-of-flight sensor of claim 1.

32. Each pixel is a cascaded TG-based pixel that includes a CAPD modulation circuit and two respective photogates (PG0A, PG0B) that represent the first modulation stage.

2. The indirect time-of-flight sensor of claim 1.

33. 13. An electronic device comprising an indirect time-of-flight sensor according to claim 1.

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