Tool security system

Abstract

To provide a system, method and circuit for providing tool access security in a device.SOLUTION: The device includes a bus master, a memory protection unit (MPU), and a protection agent circuit. The bus master stores a request message received from a tool interface in a first region of memory locations. Each request message encapsulates a tool-related command. The memory protection unit prevents the bus master from accessing a memory location outside a first range of memory locations. The protection agent circuit accesses the first range of memory locations, identifies one or more request messages, and transmits each request message to one of a plurality of component circuits based on the component circuit identified by the request message.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates generally to the field of processors and central processing units (CPUs), and more particularly to external tools used to access integrated circuits during development and troubleshooting. [Background technology]

[0002] External software development and debugging tools are configured to be coupled to specialized hardware interfaces on an Integrated Circuit (IC) device, such as a Microcontroller Unit (MCU), Microprocessor Unit (MPU) or System-on-Chip (SoC).

[0003] Some examples of circuits, devices and / or methods are described below, by way of example only, and in this context reference is made to the accompanying drawings, in which: [Brief description of the drawings]

[0004] [Figure 1] FIG. 2 is a block diagram of an example architecture in which a protection agent restricts access by a tool to a range of memory locations in accordance with various described aspects. [Diagram 2] FIG. 2 is a block diagram of an example architecture in which a protection agent restricts access by a tool to a range of memory locations in accordance with various described aspects. [Diagram 3] 1 is a flow diagram outlining an exemplary method of processing requests from a tool in accordance with various described aspects. [Figure 4] 1 is a flow diagram outlining an exemplary method of processing requests from a tool in accordance with various described aspects. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] The present disclosure is described with reference to the accompanying drawings. In the various drawings, similar components may be represented by similar reference numerals. The drawings are not drawn to scale and are provided merely to illustrate the disclosure. Some aspects of the disclosure are described below with reference to example applications for explanation. Numerous specific details, relationships and methods are described to aid in understanding the disclosure. The present disclosure is not limited to the illustrated order of steps or events, as some steps (acts) may occur in different orders and / or concurrently with other steps or events. Moreover, not all illustrated steps or events are required to implement a methodology in accordance with the selected disclosure.

[0006] Integrated circuits contain many components that are not easily accessible by external means during normal operation. Specialized tools have been developed to facilitate programming, development, and debugging of integrated circuits. A tool is a device that includes a user interface, such as a host computer, through which a user may enter tool-related commands and read results. Tools often include specialized hardware interfaces that are configured to mechanically and electrically couple to the integrated circuit through special tool ports. A tool-enabled integrated circuit includes paths and connections through which the tool may access circuits such as memory, registers, and specialized tool circuitry (e.g., breakpoint units, trace units, and overlay units).

[0007] Examples of tool ports include Joint Test Action Group (JTAG, IEEE), Device Access Port (DAP, Infineon) and Serial-Wire Debug (SWD, ARM). Each tool type communicates with the IC according to a specific protocol over a tool interface, which may convert tool commands into serial communication over multiple interface pins of the tool port. Tools may be used to debug, measure, calibrate or flash integrated circuits.

[0008] The specialized user and hardware interfaces of the tool may provide some level of security against unauthorized access to the integrated circuit via the tool. For example, the user interface may include password protection and / or challenge / response authentication measures. However, once the tool gains access to the integrated circuit, any tool-enabled circuitry or memory may be accessed. The memory may store instructions and data used in implementing different software components (e.g., applications or functions) of the device. As used herein, device components include any hardware or memory specifically associated with a given application or function supported by device 100. If different device components are supplied by different vendors, then the user of the tool will have access to potentially sensitive information of the different vendors. Additionally, tool commands are not encrypted, meaning that any key exchanges occur over unencrypted channels and can be intercepted.

[0009] Described herein are systems, circuits, and methods for providing fine-grained tool access to integrated circuit memory. The systems, circuits, and methods disclosed herein also support authentication and encryption of tool commands for added security.

[0010] Fine-grained tools for memory access 1 shows an integrated circuit device 100 including a processor 105, tool interface hardware 110, a bus master 120, and a memory 130. Memory 130 includes a range 132 of memory locations allocated to a first device component A, a range 134 of memory locations allocated to a second device component B, and a range 136 of memory locations allocated for storing messages received from and sent to tool interface hardware 110. In some examples, the ranges of memory locations 132, 134, 136 do not overlap.

[0011] Device components A and B may be associated with different applications of device 100, may be supplied by different vendors, or may be characterized as A or B based on some other criteria. A separate component circuit is provided for each device component. Component circuit 160 is configured to execute tool-related commands associated with component A and may access (e.g., read or write) memory locations in memory range 132. Component circuit 170 is configured to execute tool-related commands associated with component B and may access (e.g., read or write) memory locations in memory range 134. In one example, the component circuit comprises a set of hardware components or processor 105 of device 100 that executes computer-executable instructions stored (e.g., in computer-readable medium or memory 130) to perform operations associated with a particular device component A or B.

[0012] The host computer provides two tool user interfaces: a tool A user interface used to interact with software component A and a tool B user interface used to interact with software component B. Each tool user interface receives tool-related commands from the user for a given component (e.g., a read or write command for a particular memory location, an interrupt, etc.). Based on which tool user interface generated the tool-related command, the tool access server converts the tool-related command into a request message that is addressed or indicated (e.g., via a destination indicator in a header or control element) as intended for tool A or tool B. The tool access server provides the request message to the device 100 via specialized tool interface hardware 110. A protocol exists between the tools and each device component that can encapsulate tool commands into request messages.

[0013] Bus master 120 receives the request message and stores the request message in message memory range 136. To prevent free access to device memory by bus master 120, memory protection unit (MPU) 125 prevents the bus master from accessing any memory location outside message memory range 136. In this way, bus master 120 cannot execute a command that accesses a memory location outside range 136. In one example, MPU 125 is programmable with a base address and a range and includes a hardware comparator that is used to compare the destination address of a command with the programmed range. When the destination address is not within the range, the read or write operation of the command is prevented from being executed by the hardware.

[0014] In the illustrated example, there is a single message memory range 136, but in other examples there may be multiple memory ranges used to store request messages. For example, a different message memory range may be allocated for each component circuit. MPU 125 may be able to enforce access restrictions outside any of these multiple different ranges.

[0015] Protection agent circuitry 140 sets the range of allowed memory addresses for MPU 125 to correspond to message memory range 136. Protection agent circuitry 140 may thus control the size of the message memory range based on loading.

[0016] The protection agent circuit 140 accesses the message memory area 136 and transmits or routes the request messages stored in the message memory area 136 to the respective component circuits indicated in the respective request messages. In one example, the protection agent circuit 140 is configured to forward or route the request messages based on the message header and does not need to read or interpret the commands in the payload of the request messages. This means that even if the message payload is encrypted, the protection agent circuit 140 can still route the message to the appropriate component circuit.

[0017] In some examples, the protection agent circuit 140 has rights to access the message memory range 136 and the respective queues (not shown) for the component circuits. In these examples, the protection agent circuit 140 reads the request message header and copies the message to the queue associated with the indicated component circuit. In one example, the protection agent circuit 140 comprises a set of hardware components of the device 100 or a processor 105 that executes computer-executable instructions stored (e.g., in a computer-readable medium or memory 130) to perform the operations disclosed herein as being performed by the protection agent circuit.

[0018] Protection agent circuitry 140 may be configured to periodically check message memory range 136 for a request message. In another example, tool interface hardware 110 or bus master 120 triggers protection agent circuitry when a request message is stored. For example, tool interface hardware 110 or bus master 120 may generate an interrupt when a request message is received or stored within the message memory range. The interrupt causes protection agent circuitry 140 to check the message memory range for the message.

[0019] Each component circuit 160, 170 receives request messages from the protection agent circuit 140 (eg, via a queue) and, based on the message, executes encapsulated tool-related commands, including accessing associated memory ranges.

[0020] 2 illustrates an example device 200 that includes a protection agent circuit 240 that restricts tool access to specific areas of memory. The device includes a processor 205, tool interface hardware 210, a bus master 220, an MPU 225, a memory 230, and component circuits 260, 270. After executing the tool-related commands of the request message, the component circuits 260, 270 encapsulate the results in a response message. The component circuits store the response message in message memory range 236. The component that generated the response message may be referenced in the response message (e.g., in a header or control element).

[0021] Under control of tool interface HW 210, bus master 220 retrieves the message memory range containing the response message for the tool access server, which routes the retrieved response message to the associated tool user interface.

[0022] Encryption and Authentication In addition to providing fine-grained access to device memory, encryption and / or authentication of tool-related messages may be provided by the illustrated system. Referring to FIG. 1, the tool user interfaces may encrypt the payload of request messages with respective encryption keys known to the corresponding component circuits. For example, the tool A user interface and component circuit 160 may share a key that is different from the key shared by the tool B user interface and component circuit 170. The encrypted messages are stored in message memory range 136 and routed by the protection agent circuit 140 to the component circuit 160 or 170. The access protection circuit decrypts the request messages for execution. As can be seen in FIG. 2, the component circuits may encrypt response messages, which are stored in the message memory range and sent to the tool user interfaces via the bus master and the tool hardware interface. In this way, tool-related messages are encrypted end-to-end and the protection agent circuit cannot decode the payload of the messages it routes.

[0023] In addition to or instead of encryption on a per-component basis, the disclosed system may provide an authentication service in which the source of the request message (e.g., a particular tool user interface) provides an authentication certificate or other credentials to the protection agent circuit upon initial connection. Once the source is authenticated, a session key identifying the source may be shared between the source and the component circuit. The session key may be generated using a random number generator. The payload of the request message may include this session key or may be encrypted based on the session key to indicate that the source has been properly authenticated. The request message header may not be encrypted and / or may be without a session key in one example to simplify the operation of the protection agent circuit.

[0024] In addition to authenticating the source of the message, the component circuitry may enforce a level of authorization associated with the authenticated message source. For example, some tools for component A may only be authorized to read memory, while other tools for component A may be authorized to reset, write, interrupt, etc. This functionality is supported because the component circuitry can determine the identity of the tool sending a request message through a session key associated with the request message payload. In this manner, execution of interrupts or other potentially damaging tool-related commands may be prevented when the source of the command cannot be authenticated or permission to perform the command is not granted.

[0025] An additional feature supported by the protection agent circuitry is a security shutdown when an attack notification is received from any device component. As shown in FIG. 2 by the bold line, an attack notification may be generated by a component circuit (e.g., 260) that detects more than a threshold number of improperly encrypted or unauthenticated messages. In response to the attack notification, the protection agent circuitry may block tool access HW 210 from accessing the IC or may control MPU 225 to block access to any memory locations in memory 230. When an attack is suspected, this prevents the execution of any potentially damaging commands.

[0026] One benefit of the disclosed architecture is that the same physical architecture and components can be used regardless of whether encryption and / or authentication is provided. This provides flexibility when configuring tool access and allows upgrades to encryption and authentication as needed.

[0027] Below are several flow diagrams outlining example methods. In this specification and the appended claims, the term "determining" used in describing a method step or function with reference to any entity (e.g., a parameter, a variable, etc.) should be interpreted broadly. For example, "determining" should be interpreted to include, for example, receiving and analyzing a communication that encodes the entity or a value of the entity. "Determining" should be interpreted to include accessing and reading a memory (e.g., a lookup table, a register, a device memory, a remote memory, etc.) that stores the entity or a value for the entity. "Determining" should be interpreted to include calculating or deriving the entity or a value of the entity based on other quantities or entities. "Determining" should be interpreted to include any method of estimating or identifying the entity or a value of the entity.

[0028] As used herein, the term identifying, when used with reference to any entity or value of an entity, should be interpreted broadly to include any manner of determining the entity or the value of the entity. For example, the term identifying should be interpreted to include, for example, receiving and parsing a communication that encodes the entity or the value of the entity. The term identifying should be interpreted to include accessing a memory (e.g., a device queue, a lookup table, a register, a device memory, a remote memory, etc.) that stores the entity or a value for the entity, and reading the memory.

[0029] As used herein, the term indicate, when used in reference to any entity (e.g., a parameter or setting) or value of an entity, should be interpreted broadly to include any manner of explicitly or implicitly conveying the entity or value of the entity. For example, a bit in a transmitted message may be used to explicitly encode an indicated value, or may encode an index or other indicator that maps to a value indicated by a previous configuration. The absence of a field in a message may implicitly indicate a value of the entity based on a previous configuration.

[0030] 3 is a flow diagram outlining an example method 300 for processing messages encapsulating tool-related commands. At 310, the method includes a bus master (e.g., bus master 120 of FIG. 1, bus master 220 of FIG. 2) receiving request messages from a tool interface. Each request message encapsulates a tool-related command. The tool-related commands may include requests to read from a memory or register, requests to write to a memory or register, interrupts, etc. Each request message is generated by a tool user interface associated with a component circuit. At 320, the method includes the bus master storing the request messages within a first range of memory locations.

[0031] At 330, the method includes a protection agent circuit (e.g., 140 of FIG. 1 , 240 of FIG. 2 ) accessing a first range of memory locations and identifying one or more request messages. In one example, the method includes periodically accessing the first range of memory according to a polling schedule, and in another example, the method includes accessing the first range of memory in response to an interrupt signal.

[0032] At 340, the method includes the protection agent circuit sending each request message to one of the plurality of component circuits based on the component circuit identified by the request message.

[0033] In one example, the method further includes configuring the bus master with the protection agent circuitry to prevent the bus master from accessing memory locations outside the first range of memory locations.

[0034] FIG. 4 is a flow diagram outlining an example method 400 that may be performed, for example, by a protection agent circuit (e.g., 140 of FIG. 1 , 240 of FIG. 2 ). The method includes configuring the bus master at 410 to prevent the bus master from accessing memory locations outside of a first range of memory locations. In one example, the configuration is performed by setting a range of addresses in a hardware-based memory protection unit that are excluded from access by the bus master. The method includes accessing the first range of memory locations and identifying one or more request messages at 420. In some examples, the method includes periodically accessing the first range of memory locations according to a polling schedule. In some examples, the method includes accessing the first range of memory locations in response to an interrupt. The method includes sending each request message to one of a plurality of component circuits at 430 based on a component circuit identified in a header of the request message. In some examples, the method includes copying the request message to a queue associated with each indicated component circuit.

[0035] example Example 1 is a device including a bus master, a memory protection unit, and a protection agent circuit. The bus master is configured to store, within a first range of memory locations, request messages received from a tool interface of the device, each request message encapsulating a tool-related command. The memory protection unit is configured to prevent the bus master from accessing memory locations outside the first range of memory locations. The protection agent circuit is configured to access the first range of memory locations, identify one or more request messages, and send each request message to one of a plurality of component circuits based on a component circuit identified by the request message.

[0036] Example 2 includes the subject matter of example 1, and includes or omits optional elements, wherein the protection agent circuitry is configured to control the range of memory locations protected by the memory protection unit.

[0037] Example 3 includes the subject matter of Example 1 and includes or omits optional elements, wherein the bus master is configured to access a first range of memory locations, identify one or more response messages, and provide the one or more response messages to a tool interface of the device.

[0038] Example 4 includes the subject matter of example 1, and includes or omits optional elements, wherein the protection agent circuitry periodically accesses the first range of the memory according to a polling schedule.

[0039] Example 5 includes the subject matter of example 1, and includes or omits optional elements, wherein the protection agent circuitry accesses the first range of memory in response to an interrupt signal.

[0040] Example 6 includes the subject matter of Example 1, including or omitting optional elements, and further includes a plurality of component circuits, each component circuit configured to receive a request message from the protection agent circuit, execute a tool-related command encapsulated by the request message by accessing a respective range of memory locations assigned to the component circuit, generate a response message encapsulating a result of the tool-related command, and store the response message within a first range of memory addresses.

[0041] Example 7 includes the subject matter of example 1, and includes or omits optional elements, where each request message is encrypted using a key known by the component circuit identified in the request message.

[0042] Example 8 includes the subject matter of example 1, and includes or omits optional elements, where each request message is encrypted with a session key indicating an authenticated identity of the source of the request message.

[0043] Example 9 includes the subject matter of example 1 and includes or omits optional elements, wherein each component circuit is configured to decrypt a received request message using a key known by a tool associated with the component circuit, or to encrypt a response message using a key known by a tool associated with the component circuit.

[0044] Example 10 includes the subject matter of example 1 and includes or omits optional elements, wherein the protection agent circuit is configured to control the memory protection unit to prevent bus masters from accessing any memory locations in response to the attack notification signal.

[0045] Example 11 is a method, the method including receiving, by a bus master, request messages from a tool interface, each request message encapsulating a tool-related command, and storing the request messages within a first range of memory locations. The method includes accessing, by a protection agent circuit, the first range of memory locations to identify one or more request messages, and sending each request message to one of a plurality of component circuits based on a component circuit identified by the request message.

[0046] Example 12 includes the subject matter of Example 11 and includes or omits optional elements, wherein the method includes configuring the bus master with a protection agent circuit to prevent the bus master from accessing memory locations outside a first range of memory locations.

[0047] Example 13 includes the subject matter of Example 12 and includes or omits optional elements, wherein the method includes, in response to receiving the attack notification signal, configuring the bus master with the protection agent circuitry to prevent the bus master from accessing any memory locations.

[0048] Example 14 includes the subject matter of example 11, including or omitting optional elements, and including periodically accessing the first range of the memory according to a polling schedule.

[0049] Example 15 includes the subject matter of example 11, including or omitting optional elements, and including accessing the first range of memory in response to an interrupt signal.

[0050] Example 16 includes the subject matter of example 11 and includes or omits optional elements, wherein each request message is encrypted using a key known to a component circuit identified in a header of the request message, or using a session key indicating an authenticated source of the request message.

[0051] Example 17 is a computer-readable medium storing computer-executable instructions that, when executed by a processor, cause the processor to perform corresponding operations including configuring a bus master to prevent the bus master from accessing memory locations outside a first range of memory locations, accessing the first range of memory locations to identify one or more request messages, and sending each request message to one of a plurality of component circuits based on a component circuit identified in a header of the request message.

[0052] Example 18 includes the subject matter of Example 17 and includes or omits optional elements, wherein the instructions include instructions for causing the processor to configure the bus master to prevent the bus master from accessing any memory location in response to receiving the attack notification signal.

[0053] Example 19 includes the subject matter of example 17, including or omitting optional elements, wherein the instructions include instructions for causing the processor to periodically access the first range of the memory according to a polling schedule.

[0054] Example 20 includes the subject matter of example 17, including or omitting optional elements, and wherein the instructions include instructions for causing the processor to access the first range of the memory in response to an interrupt signal.

[0055] It can be seen from the above discussion that limiting access of bus masters receiving tool-related request messages to ranges of memory reserved for storing messages and for use by a security agent to retrieve messages from ranges of memory and route them to appropriate components within the device provides protection against unauthorized access of device components by external tools.

[0056] While the present invention has been illustrated and described with respect to one or more embodiments, substitutions and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, circuitry, systems, etc.), the terms used to describe such components (including references to "means") are intended to correspond to any component or structure that performs the particular function (e.g., is functionally equivalent) of the described component, unless otherwise specified, even if not structurally equivalent to the disclosed structures that perform the functions in the exemplary embodiments of the invention illustrated herein.

[0057] Examples may include subject matter, e.g., methods, means for performing steps (acts) or blocks of the methods, at least one machine-readable medium containing instructions that, when executed by a machine, cause the machine to provide security management per application group in accordance with the embodiments and examples described herein.

[0058] The various illustrated logic, logic blocks, modules, circuitry, and circuits described in connection with the embodiments disclosed herein may be implemented or performed by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic circuit, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively the processor may be any conventional processor, controller, microcontroller, or state machine.

[0059] In this disclosure, like reference numerals are used to refer to like elements throughout, and illustrated structures and devices are not necessarily drawn to scale. As used herein, terms such as "module," "component," "system," "circuit," "circuitry," "element," "slice," and the like are intended to relate to computer-related entities, hardware, software (e.g., at run-time), and / or firmware. For example, a circuit or similar term can be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and / or a computer having a processing device. Illustratively, an application running on a server and the server can also be a circuit. One or more circuits can be present within a process, and a circuit can be localized to one computer and / or distributed among two or more computers. In this specification, a set of elements or other circuits can be described, and the term "set" can be interpreted as "one or more."

[0060] As another example, a circuit or similar term can be a device having a particular function provided by mechanical components operated by electrical or electronic circuitry, the electrical or electronic circuitry being operable by software or firmware applications executed by one or more processors. The one or more processors can be internal or external to the device and can execute at least a portion of the software or firmware applications. As yet another example, a circuit can be a device that provides a particular function through electronic components without mechanical components, the electronic components can include field gates, logic components, hardware encoded logic, register transfer logic, one or more processors executing software and / or firmware that at least partially provide the functionality of the electronic components.

[0061] The use of exemplary terms is intended to present concepts in a concrete manner. Terms used herein are intended to describe specific examples only and are not intended to limit the examples. In this specification, singular articles are intended to include the plural unless the context clearly dictates otherwise. It is further understood that the terms "comprises", "comprising", "includes" and / or "comprising" as used herein identify the stated features, integers, steps, operations, elements and / or components and do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. The term "or" as used herein includes all element options related to the term "or". For example, A or B should be interpreted as including A only, B only, and both A and B. Furthermore, the phrase "one or more" followed by A, B, or C should be interpreted as including A, B, C, AB, AC, BC, and ABC.

Claims

1. 1. A device comprising a bus master, a memory protection unit and a protection agent circuit, the bus master is configured to store within a first range of memory locations request messages received from a tool interface of the device, each request message encapsulating a tool-related command; the memory protection unit is configured to prevent the bus master from accessing memory locations outside the first range of memory locations; The protection agent circuit includes: Accessing the first range of memory locations and identifying one or more request messages; configured to send respective request messages to one of a plurality of component circuits based on the component circuit identified by the request messages. device.

2. the protection agent circuitry is configured to control a range of memory locations that are protected by the memory protection unit; The device of claim 1 .

3. The bus master: Accessing the first range of memory locations and identifying one or more response messages; configured to provide the one or more response messages to the tool interface of the device. The device of claim 1 .

4. the protection agent circuitry periodically accesses the first range of memory according to a polling schedule; The device of claim 1 .

5. the protection agent circuitry is responsive to an interrupt signal to access the first range of memory. The device of claim 1 .

6. The device further comprises the plurality of component circuits, each component circuit comprising: receiving a request message from the protection agent circuit; execute the tool-related command encapsulated by the request message by accessing respective ranges of memory locations allocated to the component circuit; generating a response message encapsulating a result of the tool-related command; configured to store the response message within the first range of memory addresses. The device of claim 1 .

7. each request message is encrypted using a key known by the component circuit identified in said request message; The device of claim 1 .

8. each request message is encrypted with a session key indicating an authenticated identity of the source of said request message; The device of claim 1 .

9. each component circuit is configured to decrypt a received request message using a key known by a tool associated with that component circuit, or to encrypt a response message using a key known by a tool associated with that component circuit; The device of claim 1 .

10. the protection agent circuitry is configured to, in response to an attack notification signal, control the memory protection unit to prevent the bus master from accessing any memory location. The device of claim 1 .

11. The bus master receiving request messages from a tool interface, each request message encapsulating a tool-related command; storing the request message within a first range of memory locations; The protection agent circuit is accessing the first range of memory locations and identifying one or more request messages; sending a respective request message to one of a plurality of component circuits based on the component circuit identified by the request message; The method includes:

12. The method includes configuring the bus master with the protection agent circuitry to prevent the bus master from accessing memory locations outside the first range of memory locations; The method of claim 11.

13. The method includes configuring the bus master, in response to receiving an attack notification signal, with the protection agent circuitry to prevent the bus master from accessing any memory locations; The method of claim 12.

14. The method includes periodically accessing the first range of memory according to a polling schedule; The method of claim 11.

15. The method includes the step of accessing the first range of memory in response to an interrupt signal; The method of claim 11.

16. each request message is encrypted using a key known to the component circuits identified in a header of the request message or using a session key indicating an authenticated source of the request message; The method of claim 11.

17. 1. A computer-readable medium storing computer-executable instructions that, when executed by a processor, cause the processor to perform corresponding operations, the operations including: configuring the bus master to prevent the bus master from accessing memory locations outside a first range of memory locations; accessing the first range of memory locations to identify one or more request messages; sending each request message to one of a plurality of component circuits based on the component circuit identified in a header of the request message; 11. A computer readable medium comprising:

18. the instructions include instructions for causing the processor to configure the bus master to prevent the bus master from accessing any memory location in response to receiving an attack notification signal; 20. The computer-readable medium of claim 17.

19. the instructions include instructions for causing the processor to periodically access the first range of memory according to a polling schedule; 20. The computer-readable medium of claim 17.

20. the instructions include instructions for causing the processor to access the first range of memory in response to an interrupt signal; 20. The computer-readable medium of claim 17.

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