Semiconductor circuit, memory system, and information processor

Abstract

To suppress mounting area of a circuit.SOLUTION: A semiconductor circuit includes a semiconductor substrate, a first T coil including a first inductive element and a second inductive element connected in series, and a second T coil including a third inductive element and a fourth inductive element connected in series. The first T coil and the second T coil are provided so as to be separated from the semiconductor substrate. A part of the first T coil is provided at a first position in the vertical direction from a surface of the semiconductor substrate. A part of the second T coil is provided at a second position in the vertical direction from the surface and so as to be superposed with a part of the first T coil when viewed in the vertical direction. In the vertical direction, a first distance from the semiconductor substrate to the first position is different from a second distance from the semiconductor substrate to the second position. The semiconductor circuit is configured so that a first signal having a first polarity of a differential signal is applied to the first T coil. The semiconductor circuit is configured so that a second signal having a second polarity differing from the first polarity of a the differential signal is applied to the second T coil.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor circuit, a memory system, and an information processing device. [Background technology]

[0002] In order to improve the quality of signal transmission and reception, semiconductor circuits having various configurations using various circuit elements have been researched and developed. Among such semiconductor circuits, an on-chip coil provided above a semiconductor substrate is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2016-517628 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a semiconductor circuit, a memory system, and an information processing device that reduce the mounting area of ​​a circuit. [Means for solving the problem]

[0005] The semiconductor circuit according to the embodiment includes a semiconductor substrate, a first T coil including a first induction element and a second induction element connected in series, and a second T coil including a third induction element and a fourth induction element connected in series. The first T coil is provided at a distance from the semiconductor substrate. The second T coil is provided at a distance from the semiconductor substrate. A part of the first T coil is provided at a first position in a vertical direction from a surface of the semiconductor substrate. A part of the second T coil is provided at a second position in the vertical direction from the surface so as to overlap with a part of the first T coil when viewed in the vertical direction. In the vertical direction, a first distance from the semiconductor substrate to the first position is different from a second distance from the semiconductor substrate to the second position. The first T coil is configured to receive a first signal having a first polarity of a differential signal. The second T coil is configured to receive a second signal having a second polarity different from the first polarity of the differential signal. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an overall configuration of a system including a semiconductor circuit according to a first embodiment. [Diagram 2] FIG. 2 is a schematic diagram showing a configuration example of a receiver including a receiving circuit according to the first embodiment; [Diagram 3] FIG. 2 is a circuit diagram showing a configuration example of a receiving circuit according to the first embodiment. [Figure 4] FIG. 2 is a plan view for explaining an example of a layout of a T coil according to the first embodiment. [Diagram 5] FIG. 4 is a plan view for explaining another example of the layout of the T coil according to the first embodiment. [Figure 6] FIG. 2 is a plan view for explaining the layout of a T coil pair according to the first embodiment. [Figure 7] 3 is a cross-sectional view for explaining the layout of a T coil pair according to the first embodiment. FIG. [Figure 8] 4 is a plan view for explaining the direction of a signal current flowing through a T coil pair according to the first embodiment. FIG. [Figure 9] FIG. 11 is a plan view for explaining an example of a layout of a T coil according to the second embodiment. [Figure 10]FIG. 11 is a plan view for explaining another example of the layout of the T coil according to the second embodiment. [Figure 11] FIG. 11 is a plan view for explaining the layout of a T coil pair according to the second embodiment. [Figure 12] 13 is a cross-sectional view for explaining the layout of a T coil pair according to the second embodiment. FIG. [Figure 13] 13 is a plan view for explaining the direction of a signal current flowing through a T coil pair according to the second embodiment. FIG. [Figure 14] FIG. 4 is a circuit diagram showing a configuration example of a termination circuit and a receiving circuit according to a first modified example. [Figure 15] FIG. 13 is a schematic diagram showing a configuration example of a transmitter according to a second modified example. [Figure 16] FIG. 11 is a circuit diagram showing a configuration example of a transmission circuit and a termination circuit according to a second modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the description, components having substantially the same functions and configurations are given the same reference numerals. The embodiments described below are merely examples of technical ideas. The materials, shapes, structures, arrangements, etc. of the components are not specified in the embodiments. Various modifications can be made to the embodiments.

[0008] <1> First embodiment A semiconductor circuit according to a first embodiment will be described. In the first embodiment, a receiver circuit will be used as an example of the semiconductor circuit according to the first embodiment. An example of a system including the receiver circuit will be described below.

[0009] <1-1> Configuration <1-1-1> Overall configuration of information processing system FIG. 1 is a block diagram showing the overall configuration of a system including a circuit according to a first embodiment.

[0010] 1, the information processing system 9 includes a host device 40 and a memory system 500. The memory system 500 writes data, reads data, and erases data in the memory system 500 based on a request from the host device 40. The internal configuration of the memory system 500 will be described later.

[0011] The host device 40 includes a processor 41, a RAM 42, and an interface circuit 43. The host device 40 is an example of an information processing device.

[0012] The processor (hereinafter also referred to as the host processor) 41 controls various processes and operations of the host device 40.

[0013] The host processor 41 can issue (generate and transfer) commands (hereinafter referred to as host commands) for requesting (instructing, instructing) various processes and operations for the memory system 500. The host processor 41 can generate data according to the host commands. The generated data includes information (e.g., addresses), parameters, and data to be written to the memory system 500, which are used in the processes and operations of the memory system 500.

[0014] The RAM 42 functions as a work area (work memory) for various data processing by the host processor 41. The RAM 42 temporarily stores programs (an example of software) and data (results of calculation processing, data during calculation processing, and parameters) used in various processing by the host processor 41.

[0015] The interface circuit (also called a host interface (host I / F) circuit) 43 communicates with the memory system 500 based on a certain interface standard and / or communication protocol. The interface circuit 43 has a transmitter TXh for transmitting data and a receiver RXh for receiving data in a physical layer (PHY layer).

[0016] The host command to the memory system 500 is based on the interface standard of the interface circuit 43. For example, examples of the interface standard (or communication protocol) used in the interface circuit 43 include the SAS standard, the SATA standard, and the PCI Express standard. TM Standard (hereafter referred to as PCIe TM (also referred to as standard), NVMexpress TM Standard (hereinafter referred to as NVMe TM standard), or the Universal Flash Storage (UFS) standard. Note that an interface standard conforming to any of these standards or another interface standard may be used for the interface circuit 43.

[0017] In addition to the above configuration, the host device 40 may further include a storage device (not shown) such as a hard disc drive (HDD).

[0018] For example, examples of the host device 40 or the information processing system 9 include a personal computer, a smartphone, a feature phone, a mobile terminal (eg, a tablet terminal), a game machine, an in-vehicle terminal, a router, and a base station.

[0019] <1-1-2> Memory system configuration The memory system 500 includes a memory controller 50 and a NAND flash memory 60 .

[0020] Based on a request from the host device 40, the memory controller 50 instructs (commands) the NAND flash memory 60 to perform various processes and operations such as writing data, reading data, and erasing data.

[0021] The memory controller 50 includes a processor 51 , a RAM 52 , a buffer circuit 53 , and interface circuits 54 and 55 .

[0022] The processor 51 can instruct (command) various processes or operations to the NAND flash memory 60. For example, the processor 51 can generate commands indicating instructions to the NAND flash memory 60 (hereinafter, also referred to as controller commands).

[0023] The RAM 52 functions as a work area for various processes and operations of the processor 51 in the memory controller 50. The RAM 52 temporarily stores programs and data (results of calculation processes, data and parameters during calculation processes) used in various processes by the processor 51. The RAM 52 may be a memory area provided in the processor 51.

[0024] The buffer circuit 53 temporarily stores data transferred between the memory controller 50 and the host device 40, and data transferred between the memory controller 50 and the NAND flash memory 60.

[0025] The interface circuit (also called a host interface (host I / F) circuit) 54 transfers data between the host device 40 and the memory controller 50 based on a certain interface standard. The interface standard (and communication protocol) of the interface circuit 54 is the same standard (or a standard that complies with) as the interface standard of the interface circuit 43 of the host device 40. For example, the interface circuit 54 communicates with the interface circuit 43 by serial transmission (serial communication).

[0026] The interface circuit (also referred to as a memory interface (memory I / F) circuit) 55 performs communication (e.g., data transfer) between the memory controller 50 and the NAND flash memory 60 based on the NAND interface standard. The interface circuit 55 performs, for example, parallel transmission communication (parallel communication) with the NAND flash memory 60. The interface circuit 55 includes a transmitter TXm and a receiver RXm in a physical layer (PHY layer).

[0027] When the memory controller 50 commands the NAND flash memory 60 to perform a certain operation, the memory controller 50 sends a data set including a command and an address (hereinafter also referred to as a memory command set) to the NAND flash memory 60. Note that when the memory controller 50 commands the NAND flash memory 60 to write data, the memory command set further includes write data.

[0028] It should be noted that in addition to the above components, the memory controller 50 may also include other components, such as an ECC circuit (not shown) for detecting and correcting errors in data.

[0029] The NAND flash memory 60 is a non-volatile semiconductor memory device. The NAND flash memory 60 can store data in a substantially non-volatile manner. The NAND flash memory 60 writes data sent from the memory controller 50 into a memory cell array (not shown). The NAND flash memory 60 reads data requested by the memory controller 50 from the memory cell array. Hereinafter, the NAND flash memory 60 is also simply referred to as the flash memory 60.

[0030] The flash memory 60 communicates with the memory controller 50. The communication between the flash memory 60 and the memory controller 50 is supported by the NAND interface standard.

[0031] For example, the memory system 500 is a SSD (Slid State Drive), a UFS (Universal Flash Storage) device, a memory card, a USB (Universal Serial Bus) memory, etc. Instead of the flash memory 60, other non-volatile or volatile memory devices may be used in the memory system 500.

[0032] In the memory system 500, the interface circuit 54 of the memory controller 50 includes a transmitter TX and a receiver RX in the physical layer (PHY layer).

[0033] Regarding communication (signal transmission) between the host device 40 and the memory system 500, the transmitter TX of the interface circuit 54 transmits various signals (e.g., data) to the receiver RXh of the interface circuit 43. Regarding communication between the host device 40 and the memory system 500, the receiver RX of the interface circuit 54 receives various signals from the transmitter TXh of the interface circuit 43. For example, in the memory system 500, the memory controller 50 can perform various processes on the data received by the receiver RX.

[0034] For example, the transmitter TX and the receiver RX are used for relatively high-speed data transfer of 10 Gbps or more (for example, data transfer of 100 Gbps class).

[0035] The semiconductor circuit according to the first embodiment is, for example, a receiving circuit 100. The receiving circuit 100 according to the first embodiment is provided in a receiver RX of a memory controller 50.

[0036] The receiving circuit 100 of the first embodiment may be provided in the receiver RXh of the interface circuit 43 of the host device 40.

[0037] <1-1-3> Receiver configuration FIG. 2 is a schematic diagram showing a configuration example of a receiver including the receiving circuit of the first embodiment.

[0038] As shown in FIG. 2, the receiver RX includes a termination circuit 900, a plurality of receiving circuits 100, a sampler 901, and a digital signal processing circuit 902.

[0039] The termination circuit 900 is connected to a receiving terminal (receiving node) 999 of the memory controller 50. The termination circuit 900 includes a resistive element, a capacitive element, a current source and / or a voltage source, etc. The termination circuit 900 ensures impedance matching of the signal line on the input side of the receiver RX. As a result, the termination circuit 900 suppresses reflections occurring on the signal line on the input side of the receiver RX.

[0040] A plurality of receiving circuits 100 are connected to a termination circuit 900. The plurality of receiving circuits 100 are connected in series between the termination circuit 900 and a sampler 901.

[0041] The first-stage receiving circuit 100 of the multiple receiving circuits 100 receives a signal supplied to a receiving terminal 999 via a termination circuit 900. The last-stage receiving circuit 100 of the multiple receiving circuits 100 supplies the received signal to a sampler 901. Each receiving circuit 100 can amplify the received signal. Each receiving circuit 100 receives a differential signal, processes the signal internally, and outputs a differential signal.

[0042] The sampler 901 samples the signal from the receiving circuit 100 at a timing synchronized with a certain clock. The sampler 901 supplies the sampled signal (hereinafter, referred to as a sampling signal) to a digital signal processing circuit 902.

[0043] The digital signal processing circuit 902 performs digital signal processing on the sampling signal. For example, the digital signal processing circuit 902 performs analog-to-digital conversion on the sampling signal. The digital signal processing circuit 902 supplies the signal after the digital signal processing to a downstream circuit.

[0044] <1-1-4> Receiving circuit configuration FIG. 3 is a circuit diagram showing a configuration example of the receiving circuit according to the first embodiment.

[0045] As shown in FIG. 3, the receiving circuit 100 of the first embodiment includes two input terminals ITp and ITn, two output terminals OTp and OTn, a plurality of transistors TR1 and TR2, a plurality of inductive elements 111, 112, 121 and 122, a plurality of resistive elements 113 and 123, a plurality of current sources 115 and 125, an RC network circuit 130, and a plurality of power supply lines 140 and 141.

[0046] The receiver circuit 100 of the first embodiment is a differential input / output type receiver circuit. The input terminal ITp is configured to receive a positive signal Vip. The input terminal ITn is configured to receive a negative signal Vin. The output terminal OTp is configured to output a positive signal Vop. The output terminal OTn is configured to output a negative signal Von.

[0047] The transistors TR1 and TR2 function as a signal input section in the receiving circuit 100. The transistors TR1 and TR2 receive signals (signal voltage, input signal, input voltage) Vip and Vin that are complementary to each other. As a result, differential signals Vip and Vin are input to the receiving circuit 100. The transistors TR1 and TR2 are, for example, field effect transistors such as MOS transistors.

[0048] One end of the current path of the transistor TR1 is electrically connected to a node ND1a. The other end of the current path of the transistor TR1 is electrically connected to a node ND2a. The gate of the transistor TR1 is electrically connected to a positive input terminal ITp of the receiving circuit 100. The gate of the transistor TR1 receives a positive signal Vip from the preceding termination circuit 900 or the receiving circuit 100.

[0049] One end of the current path of the transistor TR2 is electrically connected to a node ND1b. The other end of the current path of the transistor TR2 is electrically connected to a node ND2b. The gate of the transistor TR2 is electrically connected to a negative-positive input terminal ITn of the receiver circuit 100. The gate of the transistor TR2 receives a negative-positive signal Vin from the previous termination circuit 900 or the receiver circuit 100. The signals Vin and Vip are complementary to each other.

[0050] An input node of the current source 115 is electrically connected to a node ND2a. An output node of the current source 115 is electrically connected to a power supply line 141 on the low potential side of the receiving circuit 100. A ground voltage VGND is applied to the power supply line 141. Hereinafter, the power supply line 141 is referred to as a ground line 141. The ground voltage VGND is a reference potential when the receiving circuit 100 operates.

[0051] An input node of the current source 125 is electrically connected to the node ND2b. An output node of the current source 125 is electrically connected to the ground line 141.

[0052] The RC network circuit 130 is electrically connected between the node ND2a and the node ND2b. The RC network circuit 130 includes a plurality of resistive elements 131 and a plurality of capacitive elements 132. The RC network circuit 130 has a circuit network in which the plurality of resistive elements 131 and the plurality of capacitive elements 132 are electrically connected in series and / or in parallel.

[0053] Each of the inductive elements 111, 112, 121 and 122 is, for example, an on-chip coil.

[0054] One end of the inductive element 111 is electrically connected to the node ND1a. The other end of the inductive element 111 is electrically connected to the node ND3a. The polarity of the mutual induction of the inductive element 111 is on the node ND1a side of the inductive element 111 (the one end side of the inductive element 111).

[0055] One end of the inductive element 112 is electrically connected to the node ND3a. The other end of the inductive element 112 is electrically connected to the node ND4a. The polarity of the mutual induction of the inductive element 112 is on the node ND3a side of the inductive element 112 (the one end side of the inductive element 112).

[0056] One end of the inductive element 121 is electrically connected to the node ND1b. The other end of the inductive element 121 is electrically connected to the node ND3b. The polarity of the mutual induction of the inductive element 121 is on the node ND1b side of the inductive element 121 (the one end side of the inductive element 121).

[0057] One end of the inductive element 122 is electrically connected to the node ND3b. The other end of the inductive element 122 is electrically connected to the node ND4b. The polarity of the mutual induction of the inductive element 122 is on the node ND3b side of the inductive element 122 (the one end side of the inductive element 122).

[0058] One end of the resistive element 113 is electrically connected to the node ND4a. The other end of the resistive element 113 is electrically connected to a power supply line 140 on the high potential side of the receiving circuit 100. A power supply voltage VDD is applied to the power supply line 140.

[0059] One end of the resistor element 123 is electrically connected to the node ND4b. The other end of the resistor element 123 is electrically connected to the power supply line 140.

[0060] The positive output terminal OTp of the receiving circuit 100 is electrically connected to a node ND3b between the other end of the inductive element 121 and one end of the inductive element 122. The negative output terminal OTn of the receiving circuit 100 is electrically connected to a node ND3a between the other end of the inductive element 111 and one end of the inductive element 112. The receiving circuit 100 outputs a positive signal (signal voltage, output signal, output voltage) Vop from the output terminal OTp. The receiving circuit 100 outputs a negative signal Von from the output terminal OTn. The signals Vop and Von are complementary to each other. As a result, the differential signals Vop and Von are sent from the receiving circuit 100 to the subsequent receiving circuit 100 or the sampler 901.

[0061] A configuration in which two inductive elements are connected in series, such as the inductive element 111 and the inductive element 112, is also called a T coil. Hereinafter, the inductive element 111 and the inductive element 112 are called a T coil TC1, and the inductive element 121 and the inductive element 122 are called a T coil TC2. In addition, a pair of the T coil TC1 and the T coil TC2 is called a T coil pair TCP.

[0062] <1-1-5> Layout of T coil pair The layout of the T coil pair according to the first embodiment will be described below with reference to Fig. 4 to Fig. 7. First, the T coil TC1 alone will be described, then the T coil TC2 alone will be described, and finally, the T coil pair TCP, i.e., the combination of the T coil TC1 and the T coil TC2 will be described.

[0063] In the drawings referred to in this specification, the plane defined by the X and Y directions corresponds to a plane parallel to the surface of the semiconductor substrate. The Z direction corresponds to a vertical direction to the surface of the semiconductor substrate. The left-right direction of the paper is the X direction, the direction from the left side of the paper to the right side of the paper is the positive X direction, and the direction from the right side of the paper to the left side of the paper is the negative X direction. The up-down direction of the paper is the Y direction, the direction from the bottom of the paper to the top of the paper is the positive Y direction, and the direction from the top of the paper to the bottom of the paper is the negative Y direction.

[0064] FIG. 4 is a plan view for explaining an example of the layout of the T coil according to the first embodiment. As shown in FIG. 4, the T coil TC1 is, for example, a two-turn planar coil having a rectangular ring shape. The rectangular ring shape can also be rephrased as a rectangle shape. The T coil TC1 includes wiring portions LP101 to LP111. The wiring portions LP101 to LP105 and the wiring portions LP107 to LP111 are provided in a first wiring layer above a semiconductor substrate. The wiring portion LP106 is provided in a second wiring layer that is above the first wiring layer. That is, the first wiring layer is a wiring layer different from the second wiring layer. The wiring portions LP101 to LP106 correspond to the inductive element 111. The wiring portions LP108 to LP111 correspond to the inductive element 112. The wiring portions LP105 to LP106 may be considered to correspond to the inductive element 112 instead of the inductive element 111.

[0065] The wiring portion LP101 is provided extending in the X direction. One end of the wiring portion LP101 on the negative X direction side is connected to the node ND1a. The other end of the wiring portion LP101 on the positive X direction side is connected to one end of the wiring portion LP102 on the positive Y direction side. The wiring portion LP102 is provided extending in the Y direction. The other end of the wiring portion LP102 on the negative Y direction side is connected to one end of the wiring portion LP103 on the positive X direction side. The wiring portion LP103 is provided extending in the X direction. The other end of the wiring portion LP103 on the negative X direction side is connected to one end of the wiring portion LP104 on the negative Y direction side.

[0066] The wiring portion LP104 is provided extending in the Y direction. The other end of the wiring portion LP104 on the positive Y direction side is connected to one end of the wiring portion LP105 on the negative X direction side. The other end of the wiring portion LP104 does not contact the wiring portion LP101. The wiring portion LP105 is provided extending in the X direction. The other end of the wiring portion LP105 on the positive X direction side does not contact the wiring portion LP102. The wiring portion LP105 is provided side by side with the wiring portion LP101 in the Y direction. The wiring portion LP106 is provided extending in the X direction in a layer (second wiring layer) above the layer (first wiring layer) in which the wiring portions LP101 to LP105 and the wiring portions LP107 to LP111 are provided. One end of the wiring portion LP106 on the negative X direction side is connected to the other end of the wiring portion LP105 on the positive X direction side via a via plug. The other end of the wiring part LP106 on the positive X-direction side is connected to one end of the wiring part LP107 on the negative X-direction side and one end of the wiring part LP108 on the positive Y-direction side through via plugs.

[0067] The wiring portion LP107 is provided extending in the X direction. One end of the wiring portion LP107 on the negative X direction side is not in contact with the wiring portion LP102. The other end of the wiring portion LP107 on the positive X direction side is connected to the node ND3a. The wiring portion LP108 is provided extending in the Y direction. The other end of the wiring portion LP108 on the negative Y direction side is connected to one end of the wiring portion LP109 on the positive X direction side. The wiring portion LP108 is provided side by side with the wiring portion LP102 in the X direction. The wiring portion LP109 is provided extending in the X direction. The other end of the wiring portion LP109 on the negative X direction side is connected to one end of the wiring portion LP110 on the negative Y direction side. The wiring portion LP109 is provided side by side with the wiring portion LP103 in the Y direction.

[0068] The wiring portion LP110 is provided extending in the Y direction. The other end of the wiring portion LP110 on the positive Y direction side is connected to one end of the wiring portion LP111 on the positive X direction side. The other end of the wiring portion LP110 is not in contact with the wiring portion LP101. The wiring portion LP110 is provided side by side with the wiring portion LP104 in the X direction. The wiring portion LP111 is provided extending in the X direction. One end of the wiring portion LP111 is not in contact with either the wiring portions LP104 or LP105. The other end of the wiring portion LP111 on the negative X direction side is connected to the node ND4a.

[0069] In the T-coil TC1 configured as above, an inductive element 112 is provided around the inductive element 111.

[0070] FIG. 5 is a plan view for explaining another example of the layout of the T coil according to the first embodiment. As shown in FIG. 5, the T coil TC2 is, for example, a two-turn planar coil having a rectangular ring shape. The rectangular ring shape can also be rephrased as a rectangle shape. The T coil TC2 includes wiring portions LP201 to LP211. The wiring portions LP201 to LP205 and the wiring portions LP207 to LP211 are provided in the second wiring layer. The wiring portion LP206 is provided in the first wiring layer. The wiring portions LP201 to LP206 correspond to the inductive element 121. The wiring portions LP208 to LP211 correspond to the inductive element 122. The wiring portions LP205 to LP206 may be considered to correspond to the inductive element 122 instead of the inductive element 121.

[0071] The wiring portion LP201 is provided extending in the X direction. One end of the wiring portion LP201 on the negative X direction side is connected to the node ND1b. The other end of the wiring portion LP201 on the positive X direction side is connected to one end of the wiring portion LP202 on the negative Y direction side. The wiring portion LP202 is provided extending in the Y direction. The other end of the wiring portion LP202 on the positive Y direction side is connected to one end of the wiring portion LP203 on the positive X direction side. The wiring portion LP203 is provided extending in the X direction. The other end of the wiring portion LP203 on the negative X direction side is connected to one end of the wiring portion LP204 on the positive Y direction side.

[0072] The wiring portion LP204 is provided extending in the Y direction. The other end of the wiring portion LP204 on the negative Y direction side is connected to one end of the wiring portion LP205 on the negative X direction side. The other end of the wiring portion LP204 does not contact the wiring portion LP201. The wiring portion LP205 is provided extending in the X direction. The other end of the wiring portion LP205 on the positive X direction side does not contact the wiring portion LP202. The wiring portion LP205 is provided side by side with the wiring portion LP201 in the Y direction. The wiring portion LP206 is provided extending in the X direction in a layer (first wiring layer) lower than the layer (second wiring layer) in which the wiring portions LP201 to LP205 and the wiring portions LP207 to LP211 are provided. One end of the wiring portion LP206 on the negative X direction side is connected to the other end of the wiring portion LP205 on the positive X direction side via a via plug. The other end of the wiring part LP206 on the positive X-direction side is connected to one end of the wiring part LP207 on the negative X-direction side and one end of the wiring part LP208 on the negative Y-direction side through via plugs.

[0073] The wiring portion LP207 is provided extending in the X direction. One end of the wiring portion LP207 on the negative X direction side is not in contact with the wiring portion LP202. The other end of the wiring portion LP207 on the positive X direction side is connected to the node ND3b. The wiring portion LP208 is provided extending in the Y direction. The other end of the wiring portion LP208 on the positive Y direction side is connected to one end of the wiring portion LP209 on the positive X direction side. The wiring portion LP208 is provided side by side with the wiring portion LP202 in the X direction. The wiring portion LP209 is provided extending in the X direction. The other end of the wiring portion LP209 on the negative X direction side is connected to one end of the wiring portion LP210 on the positive Y direction side. The wiring portion LP209 is provided side by side with the wiring portion LP203 in the Y direction.

[0074] The wiring portion LP210 is provided extending in the Y direction. The other end of the wiring portion LP210 on the negative Y direction side is connected to one end of the wiring portion LP211 on the positive X direction side. The other end of the wiring portion LP210 is not in contact with the wiring portion LP201. The wiring portion LP210 is provided side by side with the wiring portion LP204 in the X direction. The wiring portion LP211 is provided extending in the X direction. One end of the wiring portion LP211 is not in contact with either the wiring portion LP204 or LP205. The other end of the wiring portion LP211 on the negative X direction side is connected to the node ND4b.

[0075] In the T coil TC2 configured as above, an inductive element 122 is provided so as to surround the inductive element 121.

[0076] 6 is a plan view for explaining the layout of the T coil pair according to the first embodiment. The T coil TC1 provided mainly in the first wiring layer and the T coil TC2 provided mainly in the second wiring layer are arranged so as to overlap each other in the XY plane view and not to be short-circuited with each other.

[0077] More specifically, a part of the wiring portion LP102 and a part of the wiring portion LP202 overlap in the XY planar view. A part of the wiring portion LP104 and a part of the wiring portion LP204 overlap in the XY planar view. A part of the wiring portion LP108 and a part of the wiring portion LP208 overlap in the XY planar view. A part of the wiring portion LP110 and a part of the wiring portion LP210 overlap in the XY planar view. In addition, the wiring portion LP101, the wiring portion LP105, the wiring portion LP209, and the wiring portion LP203 are arranged in sequence in the Y direction in the XY planar view. The wiring portion LP103, the wiring portion LP109, the wiring portion LP205, and the wiring portion LP201 are arranged in sequence in the Y direction in the XY planar view.

[0078] Fig. 7 is a cross-sectional view for explaining the layout of the T coil pair according to the first embodiment. Fig. 7 shows a cross-sectional structure of a portion corresponding to line VII-VII in Fig. 6. A first wiring layer is provided above a semiconductor substrate, and a second wiring layer is provided above the first wiring layer. The semiconductor substrate and the first wiring layer, and the first wiring layer and the second wiring layer are insulated from each other by an interlayer insulating film (not shown).

[0079] In the region shown in Fig. 7, the first wiring layer is provided with wiring portions LP102, LP104, LP108, and LP110. In the region shown in Fig. 7, the second wiring layer is provided with wiring portions LP202, LP204, LP208, and LP210. The wiring portion LP202 is provided above the wiring portion LP102 in the Z direction. The wiring portion LP204 is provided above the wiring portion LP104 in the Z direction. The wiring portion LP208 is provided above the wiring portion LP108 in the Z direction. The wiring portion LP210 is provided above the wiring portion LP110 in the Z direction.

[0080] FIG. 8 is a plan view for explaining the direction of the signal current flowing through the T coil pair according to the first embodiment. With reference to FIG. 8, the direction of the signal current flowing through the T coil TC1 and the T coil TC2 will be described with an example. In FIG. 8, the direction of the signal current flowing through the T coil TC1 and the T coil TC2 is indicated by arrows. The direction of the signal current flowing through the T coil TC1 is indicated by a dashed arrow, and the direction of the signal current flowing through the T coil TC2 is indicated by a solid arrow. Here, a case where the signal current flows from the node ND1a of the T coil TC1 to the node ND4a will be described as an example. In this case, since the signal applied to the receiving circuit 100 is a differential signal, the signal current flows in the T coil TC2 in the opposite direction to that of the T coil TC1. That is, in the T coil TC2, the signal current flows from the node ND4b to the node ND1b.

[0081] In the T coil TC1, the signal current flows from node ND1a to node ND4a. Considering each wiring section, the signal current flows from one end to the other end in each of the wiring sections LP101 to LP111. In the T coil TC2, the signal current flows from node ND4b to node ND1b. Considering each wiring section, the signal current flows from the other end to one end in each of the wiring sections LP201 to LP211.

[0082] Here, the direction of the signal current when the wiring parts are arranged overlapping or side by side in the XY plane view will be described. In each of the wiring parts LP102 and LP202, the signal current flows from the plus Y direction side to the minus Y direction side in FIG. 8. In each of the wiring parts LP104 and LP204, the signal current flows from the minus Y direction side to the plus Y direction side in FIG. 8. In each of the wiring parts LP108 and LP208, the signal current flows from the plus Y direction side to the minus Y direction side in FIG. 8. In each of the wiring parts LP110 and LP210, the signal current flows from the minus Y direction side to the plus Y direction side in FIG. 8. In each of the wiring parts LP101, the wiring part LP105, the wiring part LP209, and the wiring part LP203, the signal current flows from the minus X direction side to the plus X direction side in FIG. 8. In each of the wiring portion LP103, the wiring portion LP109, the wiring portion LP205, and the wiring portion LP201, the signal current flows from the positive X direction to the negative X direction in Fig. 8. Thus, in the T coil pair TCP according to the first embodiment, the signal current flows in the same direction in the locations where the wiring portions overlap or are arranged side by side in the XY plane view.

[0083] <1-2> Effects According to the semiconductor circuit of the first embodiment described above, the mounting area of ​​the circuit can be reduced. The effects of the semiconductor circuit of the first embodiment will be described in detail below.

[0084] The semiconductor circuit according to the first embodiment includes a T coil pair. The T coil pair to which a differential signal is applied is implemented by, for example, symmetrically laying out a T coil to which a positive polarity signal is applied and a T coil to which a negative polarity signal is applied. It is desirable for the area of ​​the T coil pair to be small.

[0085] The T coil pair TCP according to the first embodiment is laid out so that the T coil TC1 to which a positive polarity signal is applied and the T coil TC2 to which a negative polarity signal is applied overlap in the XY plane. This allows the semiconductor circuit according to the first embodiment to reduce the mounting area compared to a layout in which the T coils are arranged side by side.

[0086] Furthermore, in the T coil pair TCP according to the first embodiment, the T coils TC1 and TC2 are mounted overlapping each other in the XY plane so that the signal currents are oriented in the same direction when a differential signal is applied. As a result, when a differential signal is applied, the overlapping T coils are inductively coupled to each other so as to strengthen their inductance. Therefore, the T coil pair TCP according to the first embodiment can increase the inductance per unit area compared to a layout in which the T coils are not overlapped. In the semiconductor circuit according to the first embodiment, the inductance per unit area of ​​the T coil pair is increased, so that the mounting area can be reduced when a T coil pair with the same inductance is laid out.

[0087] Moreover, the semiconductor circuit according to the first embodiment can improve the performance of the T coil pair in exchange for reducing the mounting area. For example, the semiconductor circuit according to the first embodiment can realize a T coil pair with a smaller resistance component by utilizing the area secured by laying out the T coils in an overlapping manner in the XY plane view and laying out the T coil pair using wiring with a larger width. If the resistance component of the T coil pair is reduced, for example, the semiconductor circuit according to the first embodiment can widen the band.

[0088] <2> Second embodiment The configuration of the semiconductor circuit according to the second embodiment is different from that of the semiconductor circuit according to the first embodiment in the shape of the T coil pair. The following describes the semiconductor circuit according to the second embodiment and the differences from the first embodiment.

[0089] The semiconductor circuit according to the second embodiment has the same circuit diagram description as the semiconductor circuit according to the first embodiment, but has a different layout. In the second embodiment, the inductive element 111 and the inductive element 112 are called T coil TC1a, and the inductive element 121 and the inductive element 122 are called T coil TC2a. Moreover, the pair of the T coil TC1a and the T coil TC2a is called a T coil pair TCPa.

[0090] <2-1> Configuration <2-1-1> Layout of T coil pair FIG. 9 is a plan view for explaining an example of the layout of the T coil according to the second embodiment. As shown in FIG. 9, the T coil TC1a is, for example, a two-turn planar coil having an octagonal ring shape. The octagonal ring shape can also be rephrased as an octagonal shape. The T coil TC1a includes wiring portions LP301 to LP317. The wiring portions LP301 to LP309 and the wiring portions LP311 to LP317 are provided in a first wiring layer. The wiring portion LP310 is provided in a second wiring layer. The wiring portions LP301 to LP310 correspond to the inductive element 111. The wiring portions LP312 to LP317 correspond to the inductive element 112. The wiring portions LP309 to LP310 may be considered to correspond to the inductive element 112 instead of the inductive element 111.

[0091] In the XY plane, the direction when the X axis is rotated clockwise, for example, by 45 degrees, is defined as direction A, and the direction when the X axis is rotated counterclockwise, for example, by 45 degrees is defined as direction B. Additionally, the direction from the upper left to the lower right of the paper is defined as the positive A direction, and the direction from the lower right to the upper left of the paper is defined as the negative A direction. The direction from the lower left to the upper right of the paper is defined as the positive B direction, and the direction from the upper right to the lower left of the paper is defined as the negative B direction.

[0092] The wiring part LP301 is provided extending in the X direction. One end of the wiring part LP301 on the negative X direction side is connected to the node ND1a. The other end of the wiring part LP301 on the positive X direction side is connected to one end of the wiring part LP302 on the negative A direction side. The wiring part LP302 is provided extending in the A direction. The other end of the wiring part LP302 on the positive A direction side is connected to one end of the wiring part LP303 on the positive Y direction side. The wiring part LP303 is provided extending in the Y direction. The other end of the wiring part LP303 on the negative Y direction side is connected to one end of the wiring part LP304 on the positive B direction side.

[0093] The wiring portion LP304 is provided extending in the B direction. The other end of the wiring portion LP304 on the negative B direction side is connected to one end of the wiring portion LP305 on the positive X direction side. The wiring portion LP305 is provided extending in the X direction. The other end of the wiring portion LP305 on the negative X direction side is connected to one end of the wiring portion LP306 on the positive A direction side. The wiring portion LP306 is provided extending in the A direction. The other end of the wiring portion LP306 on the negative A direction side is connected to one end of the wiring portion LP307 on the negative Y direction side.

[0094] The wiring portion LP307 is provided so as to extend in the Y direction. The other end of the wiring portion LP307 on the positive Y direction side is connected to one end of the wiring portion LP308 on the negative B direction side. The wiring portion LP308 is provided so as to extend in the B direction. The other end of the wiring portion LP308 on the positive B direction side is connected to one end of the wiring portion LP309 on the negative X direction side. The other end of the wiring portion LP308 is not in contact with the wiring portion LP301. The wiring portion LP309 is provided so as to extend in the X direction. The other end of the wiring portion LP309 on the positive X direction side is connected to one end of the wiring portion LP310 on the negative X direction side via a via plug. The other end of the wiring portion LP309 is not in contact with the wiring portions LP302 and LP303. The wiring portion LP309 is provided so as to be aligned with the wiring portion LP301 in the Y direction.

[0095] The wiring portion LP310 is provided extending in the X direction. The other end of the wiring portion LP310 on the positive X direction side is connected to one end of the wiring portion LP311 on the negative X direction side and one end of the wiring portion LP312 on the positive Y direction side through via plugs. The wiring portion LP311 is provided extending in the X direction. The other end of the wiring portion LP311 on the positive X direction side is connected to the node ND3a. One end of the wiring portion LP311 is not in contact with the wiring portions LP302 and LP303. The wiring portion LP312 is provided extending in the Y direction. The other end of the wiring portion LP312 on the negative Y direction side is connected to one end of the wiring portion LP313 on the positive B direction side. The wiring portion LP312 is provided side by side with the wiring portion LP303 in the X direction.

[0096] The wiring portion LP313 is provided extending in the B direction. The other end of the wiring portion LP313 on the negative B direction side is connected to one end of the wiring portion LP314 on the positive X direction side. The wiring portion LP313 is provided side by side with the wiring portion LP304 in the A direction. The wiring portion LP314 is provided extending in the X direction. The other end of the wiring portion LP314 on the negative X direction side is connected to one end of the wiring portion LP315 on the positive A direction side. The wiring portion LP314 is provided side by side with the wiring portion LP305 in the Y direction. The wiring portion LP315 is provided extending in the A direction. The other end of the wiring portion LP315 on the negative A direction side is connected to one end of the wiring portion LP316 on the negative Y direction side. The wiring portion LP315 is provided side by side with the wiring portion LP306 in the B direction.

[0097] The wiring portion LP316 is provided extending in the Y direction. The other end of the wiring portion LP316 on the positive Y direction side is connected to one end of the wiring portion LP317 on the positive X direction side. The other end of the wiring portion LP316 does not contact the wiring portion LP301. The wiring portion LP316 is provided side by side with the wiring portion LP307 in the X direction. The wiring portion LP317 is provided extending in the X direction. The other end of the wiring portion LP317 on the negative X direction side is connected to the node ND4a. One end of the wiring portion LP317 does not contact the wiring portion LP308.

[0098] In the T coil TC1a configured as above, an inductive element 112 is provided around the inductive element 111.

[0099] FIG. 10 is a plan view for explaining another example of the layout of the T coil according to the second embodiment. As shown in FIG. 10, the T coil TC2a is, for example, a two-turn planar coil having an octagonal ring shape. The octagonal ring shape can also be rephrased as an octagonal shape. The T coil TC2a includes wiring portions LP401 to LP417. The wiring portions LP401 to LP409 and the wiring portions LP411 to LP417 are provided in the second wiring layer. The wiring portion LP410 is provided in the first wiring layer. The wiring portions LP401 to LP410 correspond to the inductive element 121. The wiring portions LP412 to LP417 correspond to the inductive element 122. The wiring portions LP409 to LP410 may be considered to correspond to the inductive element 122 instead of the inductive element 121.

[0100] The wiring portion LP401 is provided extending in the X direction. One end of the wiring portion LP401 on the negative X direction side is connected to the node ND1b. The other end of the wiring portion LP401 on the positive X direction side is connected to one end of the wiring portion LP402 on the negative B direction side. The wiring portion LP402 is provided extending in the B direction. The other end of the wiring portion LP402 on the positive B direction side is connected to one end of the wiring portion LP403 on the negative Y direction side. The wiring portion LP403 is provided extending in the Y direction. The other end of the wiring portion LP403 on the positive Y direction side is connected to one end of the wiring portion LP404 on the positive A direction side.

[0101] The wiring portion LP404 is provided extending in the A direction. The other end of the wiring portion LP404 on the negative A direction side is connected to one end of the wiring portion LP405 on the positive X direction side. The wiring portion LP405 is provided extending in the X direction. The other end of the wiring portion LP405 on the negative X direction side is connected to one end of the wiring portion LP406 on the positive B direction side. The wiring portion LP406 is provided extending in the B direction. The other end of the wiring portion LP406 on the negative B direction side is connected to one end of the wiring portion LP407 on the positive Y direction side.

[0102] The wiring portion LP407 is provided so as to extend in the Y direction. The other end of the wiring portion LP407 on the negative Y direction side is connected to one end of the wiring portion LP408 on the negative A direction side. The wiring portion LP408 is provided so as to extend in the A direction. The other end of the wiring portion LP408 on the positive A direction side is connected to one end of the wiring portion LP409 on the negative X direction side. The other end of the wiring portion LP408 is not in contact with the wiring portion LP401. The wiring portion LP409 is provided so as to extend in the X direction. The other end of the wiring portion LP409 on the positive X direction side is connected to one end of the wiring portion LP410 on the negative X direction side via a via plug. The other end of the wiring portion LP409 is not in contact with the wiring portions LP402 and LP403. The wiring portion LP409 is provided so as to be aligned with the wiring portion LP401 in the Y direction.

[0103] The wiring portion LP410 is provided extending in the X direction. The other end of the wiring portion LP410 on the positive X direction side is connected to one end of the wiring portion LP411 on the negative X direction side and one end of the wiring portion LP412 on the negative Y direction side via a via plug. The wiring portion LP411 is provided extending in the X direction. The other end of the wiring portion LP411 on the positive X direction side is connected to the node ND3b. One end of the wiring portion LP411 is not in contact with the wiring portions LP402 and LP403. The wiring portion LP412 is provided extending in the Y direction. The other end of the wiring portion LP412 on the positive Y direction side is connected to one end of the wiring portion LP413 on the positive A direction side. The wiring portion LP412 is provided side by side with the wiring portion LP403 in the X direction.

[0104] The wiring portion LP413 is provided extending in the A direction. The other end of the wiring portion LP413 on the negative A direction side is connected to one end of the wiring portion LP414 on the positive X direction side. The wiring portion LP413 is provided side by side with the wiring portion LP404 in the B direction. The wiring portion LP414 is provided extending in the X direction. The other end of the wiring portion LP414 on the negative X direction side is connected to one end of the wiring portion LP415 on the positive B direction side. The wiring portion LP414 is provided side by side with the wiring portion LP405 in the Y direction. The wiring portion LP415 is provided extending in the B direction. The other end of the wiring portion LP415 on the negative B direction side is connected to one end of the wiring portion LP416 on the positive Y direction side. The wiring portion LP415 is provided side by side with the wiring portion LP406 in the A direction.

[0105] The wiring portion LP416 is provided extending in the Y direction. The other end of the wiring portion LP416 on the negative Y direction side is connected to one end of the wiring portion LP417 on the positive X direction side. The other end of the wiring portion LP416 does not contact the wiring portion LP401. The wiring portion LP416 is provided side by side with the wiring portion LP407 in the X direction. The wiring portion LP417 is provided extending in the X direction. The other end of the wiring portion LP417 on the negative X direction side is connected to the node ND4b. One end of the wiring portion LP417 does not contact the wiring portion LP408.

[0106] In the T coil TC2a configured as above, an inductive element 122 is provided around the inductive element 121.

[0107] 11 is a plan view for explaining the layout of the T coil pair according to the second embodiment. The T coil TC1a provided mainly in the first wiring layer and the T coil TC2a provided mainly in the second wiring layer are arranged so as to overlap each other in the XY plane view and not to be short-circuited with each other.

[0108] For example, a part of the wiring portion LP303 and a part of the wiring portion LP403 overlap in the XY planar view. A part of the wiring portion LP307 and a part of the wiring portion LP407 overlap in the XY planar view. A part of the wiring portion LP312 and a part of the wiring portion LP412 overlap in the XY planar view. A part of the wiring portion LP316 and a part of the wiring portion LP416 overlap in the XY planar view. The wiring portion LP301, the wiring portion LP309, the wiring portion LP414, and the wiring portion LP405 are arranged in sequence in the Y direction in the XY planar view. The wiring portion LP305, the wiring portion LP314, the wiring portion LP409, and the wiring portion LP401 are arranged in sequence in the Y direction in the XY planar view.

[0109] Fig. 12 is a cross-sectional view for explaining the layout of the T coil pair according to the second embodiment. Fig. 12 shows a cross-sectional structure of a portion corresponding to line XII-XII in Fig. 11. A first wiring layer is provided above a semiconductor substrate, and a second wiring layer is provided above the first wiring layer. The semiconductor substrate and the first wiring layer, and the first wiring layer and the second wiring layer are insulated from each other by an interlayer insulating film (not shown).

[0110] In the region shown in FIG. 12, the first wiring layer is provided with wiring portions LP303, LP307, LP312, and LP316. In the region shown in FIG. 12, the second wiring layer is provided with wiring portions LP403, LP407, LP412, and LP416. The wiring portion LP403 is provided above the wiring portion LP303 in the Z direction. The wiring portion LP407 is provided above the wiring portion LP307 in the Z direction. The wiring portion LP412 is provided above the wiring portion LP312 in the Z direction. The wiring portion LP416 is provided above the wiring portion LP316 in the Z direction.

[0111] FIG. 13 is a plan view for explaining the direction of the signal current flowing through the T coil pair according to the second embodiment. With reference to FIG. 13, the direction of the signal current flowing through the T coil TC1a and the T coil TC2a will be described with an example. In FIG. 13, the direction of the signal current flowing through the T coil TC1a and the T coil TC2a is indicated by arrows. The direction of the signal current flowing through the T coil TC1a is indicated by a dashed arrow, and the direction of the signal current flowing through the T coil TC2a is indicated by a solid arrow. Here, a case where the signal current flows from the node ND1a of the T coil TC1a to the node ND4a will be described as an example. In this case, since the signal applied to the receiving circuit 100 is a differential signal, the signal current flows in the T coil TC2a in the opposite direction to that of the T coil TC1a. That is, in the T coil TC2a, the signal current flows from the node ND4b to the node ND1b.

[0112] In the T coil TC1a, the signal current flows from node ND1a to node ND4a. In each of the wiring parts, the signal current flows from one end to the other end in each of the wiring parts LP301 to LP317. In the T coil TC2a, the signal current flows from node ND4b to node ND1b. In each of the wiring parts, the signal current flows from the other end to one end in each of the wiring parts LP401 to LP417.

[0113] Here, the direction of the signal current when the wiring parts are arranged overlapping or side by side in the XY plane view will be described with some examples. In each of the wiring parts LP303 and LP403, the signal current flows from the plus Y direction side to the minus Y direction side in FIG. 13. In each of the wiring parts LP307 and LP407, the signal current flows from the minus Y direction side to the plus Y direction side in FIG. 13. In each of the wiring parts LP312 and LP412, the signal current flows from the plus Y direction side to the minus Y direction side in FIG. 13. In each of the wiring parts LP316 and LP416, the signal current flows from the minus Y direction side to the plus Y direction side in FIG. 13. In each of the wiring parts LP301, the wiring part LP309, the wiring part LP414, and the wiring part LP405, the signal current flows from the minus X direction side to the plus X direction side in FIG. 13. In each of the wiring portion LP305, the wiring portion LP314, the wiring portion LP409, and the wiring portion LP401, the signal current flows from the positive X direction to the negative X direction in Fig. 13. Thus, in the T coils TC1a and TC2a according to the second embodiment, the signal current flows in the same direction at the locations where the wiring portions overlap or are arranged side by side in the XY plane view.

[0114] <2-2> Effects According to the semiconductor circuit of the second embodiment described above, the mounting area of ​​the circuit can be reduced, similarly to the semiconductor circuit of the first embodiment.

[0115] The shape of the T coil is different between the first embodiment and the second embodiment. Specifically, it is a square ring shape in the first embodiment, and an octagonal ring shape in the second embodiment. In the semiconductor circuit according to the second embodiment, even if it is an octagonal ring shape, the mounting area can be reduced in the same manner as the semiconductor circuit according to the first embodiment by laying out the T coils overlapping each other in the XY plane view. In addition, in the semiconductor circuit according to the second embodiment, like the semiconductor circuit according to the first embodiment, when a differential signal is applied to the T coil pair, the T coils overlapping each other in the XY plane view are inductively coupled so as to reinforce their inductances. Therefore, like the semiconductor circuit according to the first embodiment, the semiconductor circuit according to the second embodiment can increase the inductance per unit area and reduce the mounting area.

[0116] <3> Modifications etc. In the above embodiment, a receiving circuit has been described as an example of the semiconductor circuit according to the embodiment. The semiconductor circuit according to the embodiment may be a circuit other than the receiving circuit, for example, a termination circuit of a receiver.

[0117] Fig. 14 is a circuit diagram showing a configuration example of a termination circuit and a receiving circuit according to Modification 1. As shown in Fig. 14, a termination circuit 900 includes two input terminals ITpa and ITna, two output terminals OTpa and OTna, a plurality of inductive elements 911, 912, 921 and 922, a plurality of diodes 913, 914, 923 and 924, a resistive element 930, and a plurality of power supply lines 940 and 941.

[0118] The termination circuit 900 of the first modification is a differential input / output type termination circuit. The input terminal ITpa is configured to receive a positive polarity signal. The input terminal ITna is configured to receive a negative polarity positive signal. The output terminal OTpa is configured to output a positive polarity signal. The output terminal OTna is configured to output a negative polarity positive signal.

[0119] Each of the inductive elements 911, 912, 921, and 922 is, for example, an on-chip coil.

[0120] One end of the inductive element 911 is electrically connected to the input terminal ITpa. The other end of the inductive element 911 is electrically connected to the node ND5a. The polarity of the mutual induction of the inductive element 911 is on the node ND5a side of the inductive element 911 (the other end side of the inductive element 911).

[0121] One end of the inductive element 912 is electrically connected to the node ND5a. The other end of the inductive element 912 is electrically connected to the output terminal OTpa. The polarity of the mutual induction of the inductive element 912 is on the output terminal OTpa side of the inductive element 912 (the other end side of the inductive element 912).

[0122] One end of the inductive element 921 is electrically connected to the input terminal ITna. The other end of the inductive element 921 is electrically connected to the node ND5b. The polarity of the mutual induction of the inductive element 921 is on the node ND5b side of the inductive element 921 (the other end side of the inductive element 921).

[0123] One end of the inductive element 922 is electrically connected to the node ND5b. The other end of the inductive element 922 is electrically connected to the output terminal OTna. The polarity of the mutual induction of the inductive element 922 is on the output terminal OTna side of the inductive element 922 (the other end side of the inductive element 922).

[0124] The anode of the diode 913 is electrically connected to the node ND5a. The cathode of the diode 913 is electrically connected to a power supply line 940 on the high potential side of the termination circuit 900. A power supply voltage VDD is applied to the power supply line 940.

[0125] An anode of the diode 914 is electrically connected to a power supply line 941 on the low potential side of the termination circuit 900. A ground voltage VGND is applied to the power supply line 941. The ground voltage VGND is a reference potential when the termination circuit 900 operates. An anode of the diode 914 is electrically connected to a node ND5a.

[0126] The anode of the diode 923 is electrically connected to the node ND5b. The cathode of the diode 923 is electrically connected to the power supply line 940.

[0127] The anode of the diode 924 is electrically connected to the power supply line 941. The cathode of the diode 924 is electrically connected to the node ND5b.

[0128] One end of the resistive element 930 is electrically connected to the output terminal OTpa, and the other end of the resistive element 930 is electrically connected to the output terminal OTna.

[0129] An output terminal OTpa of the termination circuit 900 is electrically connected to an input terminal ITp of the reception circuit 100. An output terminal OTna of the termination circuit 900 is electrically connected to an input terminal ITn of the reception circuit 100. As a result, a differential signal applied to the input terminals ITpa and ITna of the termination circuit 900 is sent to the input terminals ITp and ITn of the reception circuit 100 via the internal circuitry of the termination circuit 900.

[0130] Hereinafter, the inductive elements 911 and 912 will be referred to as T coil TC1b, and the inductive elements 921 and 922 will be referred to as T coil TC2b. In addition, the pair of T coils TC1b and TC2b will be referred to as T coil pair TCPb.

[0131] By laying out the T coil pair TCPb of the first modified example in the same manner as the T coil pair of the first or second embodiment, the termination circuit 900 of the first modified example can obtain the same effect as the first or second embodiment.

[0132] In the first modification, the T coil pair is included in the termination circuit of the receiver. The termination circuit including the T coil pair may be incorporated in a circuit other than the receiver, for example, may be used in a transmitter.

[0133] 15 is a schematic diagram showing a configuration example of a transmitter according to Modification 2. As shown in FIG.

[0134] The termination circuit 900a is connected to the transmission terminal (transmission node) 888 of the memory controller 50. The termination circuit 900a ensures impedance matching of the signal line on the output side of the transmitter TX. As a result, the termination circuit 900a suppresses reflections that occur in the signal line on the output side of the transmitter TX.

[0135] The transmission circuit 800 amplifies a signal input from outside the transmission circuit 800, and outputs the amplified signal to a transmission terminal (transmission node) 888 via a termination circuit 900a.

[0136] Fig. 16 is a circuit diagram showing a configuration example of a transmission circuit and a termination circuit according to a second modification. As shown in Fig. 16, the termination circuit 900a according to the second modification has a configuration in which the input terminal ITpa is replaced with an input terminal ITpc, the input terminal ITna is replaced with an input terminal ITnc, the output terminal OTpa is replaced with an output terminal OTpc, the output terminal OTna is replaced with an output terminal OTnc, and the resistive element 930 is removed, compared to the termination circuit 900 according to the first modification. The other configurations of the termination circuit 900a according to the second modification are the same as those of the termination circuit 900 according to the first modification. In addition, the transmission circuit 800 includes an output terminal OTpb and an output terminal OTnb.

[0137] The output terminal OTpb of the transmission circuit 800 is a terminal that outputs a positive polarity signal.The output terminal OTnb of the transmission circuit 800 is a terminal that outputs a negative polarity signal.

[0138] The output terminal OTpb of the transmission circuit 800 is electrically connected to the input terminal ITpc of the termination circuit 900a. The output terminal OTnb of the transmission circuit 800 is electrically connected to the input terminal ITnc of the termination circuit 900a. As a result, the differential signal output by the transmission circuit 800 passes through the internal circuitry of the termination circuit 900a and is output from the output terminals OTpc and OTnc of the termination circuit 900a.

[0139] By laying out the T coil pair TCPb of the second modified example in the same manner as the T coil pair of the first or second embodiment, the termination circuit 900a of the second modified example can obtain the same effect as the first or second embodiment.

[0140] In this specification, "one end of a current path of a transistor" corresponds to the source or drain of a MOS transistor, and "the other end of a current path of a transistor" corresponds to the drain or source of a MOS transistor.

[0141] In this specification, "connection" refers to being electrically connected, and does not exclude, for example, the interposition of another element. Furthermore, "electrically connected" may be performed through an insulator as long as it is possible for the device to function in the same manner as an electrically connected device.

[0142] Note that a part or the whole of the first or second embodiment can be described as, but is not limited to, the following supplementary notes.

[0143] [Appendix 1] A semiconductor substrate; a first T coil provided at a distance from the semiconductor substrate and including a first inductive element and a second inductive element connected in series; a second T coil provided at a distance from the semiconductor substrate and including a third inductive element and a fourth inductive element connected in series; Equipped with a portion of the first T coil is provided at a first position in a vertical direction from a surface of the semiconductor substrate; a portion of the second T coil is provided so as to overlap a portion of the first T coil as viewed in the vertical direction at a second position in the vertical direction from the surface; a first distance from the semiconductor substrate to the first position and a second distance from the semiconductor substrate to the second position are different in the vertical direction; A first signal having a first polarity of a differential signal is applied to the first T coil, A semiconductor circuit configured such that a second signal having a second polarity different from the first polarity of the differential signal is applied to the second T coil.

[0144] [Appendix 2] the surface of the semiconductor substrate is parallel to a plane defined by a first direction and a second direction intersecting the first direction; The first T coil is A first portion having one end and another end and extending in the first direction; a second portion having one end connected to the other end of the first portion and the other end and extending in the second direction; a third portion having one end connected to the other end of the second portion and the other end, the third portion extending in the first direction; a fourth portion having one end connected to the other end of the third portion and the other end, extending in the second direction and not in contact with the first portion; a fifth portion having one end connected to the other end of the fourth portion and the other end, extending in the first direction parallel to the first portion and not in contact with the second portion; a sixth portion having one end electrically connected to the other end of the fifth portion and the other end, extending in the first direction and provided at a position different from that of the second portion; a seventh portion having one end electrically connected to the other end of the sixth portion and the other end, the seventh portion extending in the second direction in parallel to the second portion; an eighth portion having one end connected to the other end of the seventh portion and the other end, the eighth portion extending in the first direction in parallel with the third portion; a ninth portion having one end connected to the other end of the eighth portion and the other end, extending in the second direction in parallel with the fourth portion and not in contact with the first portion; a tenth portion having one end connected to the other end of the ninth portion and the other end, extending in the first direction parallel to the first portion and not in contact with the fourth portion; Including, 2. The semiconductor circuit of claim 1.

[0145] [Appendix 3] The second T coil is an eleventh portion having one end and the other end and extending in the first direction; a twelfth portion having one end connected to the other end of the eleventh portion and the other end and extending in the second direction; a thirteenth portion having one end connected to the other end of the twelfth portion and the other end and extending in the first direction; a 14th portion having one end connected to the other end of the 13th portion and the other end, extending in the second direction, and provided so as not to contact the 11th portion; a 15th portion having one end connected to the other end of the 14th portion and the other end, extending in the first direction in parallel with the 11th portion and not in contact with the 12th portion; a 16th portion having one end electrically connected to the other end of the 15th portion and the other end, extending in the first direction, and provided at a position different from that of the 12th portion; a 17th portion having one end electrically connected to the other end of the 16th portion and the other end, the 17th portion extending in the second direction in parallel with the 12th portion; an 18th portion having one end connected to the other end of the 17th portion and the other end, and extending in the first direction in parallel to the 13th portion; a 19th portion having one end connected to the other end of the 18th portion and the other end, extending in the second direction in parallel with the 14th portion and provided so as not to contact the 11th portion; a 20th portion having one end connected to the other end of the 19th portion and the other end, extending in the first direction in parallel with the 11th portion and not in contact with the 14th portion; 3. The semiconductor circuit of claim 2,

[0146] [Appendix 4] a portion of the twelfth portion is provided above a portion of the second portion; a portion of the fourteenth portion is provided above a portion of the fourth portion; a part of the seventeenth portion is provided above a part of the seventh portion; A part of the 19th portion is provided above a part of the 9th portion. 4. The semiconductor circuit of claim 3.

[0147] [Appendix 5] the first portion, the fifth portion, the thirteenth portion, and the eighteenth portion are arranged side by side in the second direction, The third portion, the eighth portion, the eleventh portion, and the fifteenth portion are arranged side by side in the second direction. 4. The semiconductor circuit of claim 3.

[0148] [Appendix 6] a direction of the current of the first signal flowing through the second portion is equal to a direction of the current of the second signal flowing through the twelfth portion; a direction of a current of the first signal flowing through the fourth portion is equal to a direction of a current of the second signal flowing through the fourteenth portion; a direction of a current of the first signal flowing through the seventh portion is equal to a direction of a current of the second signal flowing through the seventeenth portion; A direction of the current of the first signal flowing through the 9th portion is equal to a direction of the current of the second signal flowing through the 19th portion. 4. The semiconductor circuit of claim 3.

[0149] [Appendix 7] a current of the first signal flowing through the first portion, a current of the first signal flowing through the fifth portion, a current of the second signal flowing through the thirteenth portion, and a current of the second signal flowing through the eighteenth portion are all in the same direction; the current of the first signal flowing through the third portion, the current of the first signal flowing through the eighth portion, the current of the second signal flowing through the eleventh portion, and the current of the second signal flowing through the fifteenth portion are all in the same direction; 4. The semiconductor circuit of claim 3.

[0150] [Appendix 8] the surface of the semiconductor substrate is parallel to a plane defined by a first direction and a second direction intersecting the first direction; a third direction is a direction that is included in the plane defined by the first direction and the second direction and is different from the first direction and the second direction; When a direction that is included in the plane defined by the first direction and the second direction and is different from the first direction, the second direction, and the third direction is defined as a fourth direction, The first T coil is A first portion having one end and another end and extending in the first direction; a second portion having one end connected to the other end of the first portion and the other end and extending in the third direction; a third portion having one end connected to the other end of the second portion and the other end and extending in the second direction; a fourth portion having one end connected to the other end of the third portion and the other end and extending in the fourth direction; a fifth portion having one end connected to the other end of the fourth portion and the other end and extending in the first direction; a sixth portion having one end connected to the other end of the fifth portion and the other end and extending in the third direction; a seventh portion having one end connected to the other end of the sixth portion and the other end and extending in the second direction; an eighth portion having one end connected to the other end of the seventh portion and the other end, extending in the fourth direction and not in contact with the first portion; a ninth portion having one end connected to the other end of the eighth portion and the other end, extending in the first direction parallel to the first portion, and provided so as not to contact the second portion and the third portion; a tenth portion having one end electrically connected to the other end of the ninth portion and the other end, extending in the first direction, and provided at a position different from the second portion and the third portion; an eleventh portion having one end electrically connected to the other end of the tenth portion and the other end, the eleventh portion extending in the second direction in parallel with the third portion; a twelfth portion having one end connected to the other end of the eleventh portion and the other end, the twelfth portion extending in the fourth direction parallel to the fourth portion; a thirteenth portion having one end connected to the other end of the twelfth portion and the other end, the thirteenth portion extending in the first direction in parallel with the fifth portion; a 14th portion having one end connected to the other end of the 13th portion and the other end, and extending in the third direction in parallel to the 6th portion; a fifteenth portion having one end connected to the other end of the fourteenth portion and the other end, extending in the second direction in parallel with the seventh portion and not in contact with the first portion; a 16th portion having one end connected to the other end of the 15th portion and the other end, extending in the first direction in parallel with the first portion and not in contact with the 8th portion; Including, 2. The semiconductor circuit of claim 1.

[0151] [Appendix 9] The second T coil is a 17th portion having one end and the other end and extending in the first direction; an 18th portion having one end connected to the other end of the 17th portion and the other end and extending in the fourth direction; a 19th portion having one end connected to the other end of the 18th portion and the other end and extending in the second direction; a 20th portion having one end connected to the other end of the 19th portion and the other end and extending in the third direction; a 21st portion having one end connected to the other end of the 20th portion and the other end and extending in the first direction; a 22nd portion having one end connected to the other end of the 21st portion and the other end and extending in the fourth direction; a 23rd portion having one end connected to the other end of the 22nd portion and the other end and extending in the second direction; a 24th portion having one end connected to the other end of the 23rd portion and the other end, extending in the third direction, and provided so as not to contact the 17th portion; a 25th portion having one end connected to the other end of the 24th portion and the other end, extending in the first direction in parallel with the 17th portion, and provided so as not to contact the 18th portion and the 19th portion; a 26th portion having one end electrically connected to the other end of the 25th portion and the other end, extending in the first direction, and provided at a position different from the 18th portion and the 19th portion; a 27th portion having one end electrically connected to the other end of the 26th portion and the other end, the 27th portion extending in the second direction in parallel with the 19th portion; a 28th portion having one end connected to the other end of the 27th portion and the other end, and extending in the third direction in parallel with the 20th portion; a 29th portion having one end connected to the other end of the 28th portion and the other end, and extending in the first direction in parallel with the 21st portion; a 30th portion having one end connected to the other end of the 29th portion and the other end, and extending in the fourth direction in parallel to the 22nd portion; a 31st portion having one end connected to the other end of the 30th portion and the other end, extending in the second direction in parallel with the 23rd portion and provided so as not to contact the 17th portion; a 32nd portion having one end connected to the other end of the 31st portion and the other end, extending in the first direction in parallel with the 17th portion and provided so as not to contact the 24th portion; Including, 9. The semiconductor circuit of claim 8.

[0152] [Appendix 10] a part of the 19th portion is provided above a part of the 3rd portion, a part of the 23rd portion is provided above a part of the 7th portion, a part of the 27th portion is provided above a part of the 12th portion; A part of the 31st portion is provided above a part of the 16th portion. 10. The semiconductor circuit of claim 9.

[0153] [Appendix 11] the first portion, the ninth portion, the twenty-first portion, and the twenty-ninth portion are arranged side by side in the second direction, The fifth portion, the fourteenth portion, the seventeenth portion, and the twenty-fifth portion are arranged side by side in the second direction. 10. The semiconductor circuit of claim 9.

[0154] [Appendix 12] a direction of the current of the first signal flowing through the third portion is equal to a direction of the current of the second signal flowing through the nineteenth portion; a direction of a current of the first signal flowing through the seventh portion is equal to a direction of a current of the second signal flowing through the twenty-third portion; a direction of a current of the first signal flowing through the 12th portion is equal to a direction of a current of the second signal flowing through the 27th portion; The direction of the current of the first signal flowing through the 16th portion is equal to the direction of the current of the second signal flowing through the 31st portion. 10. The semiconductor circuit of claim 9.

[0155] [Appendix 13] the directions of the current of the first signal flowing through the first portion, the current of the first signal flowing through the 9th portion, the current of the second signal flowing through the 21st portion, and the current of the second signal flowing through the 29th portion are equal to each other; the current of the first signal flowing through the 5th portion, the current of the first signal flowing through the 14th portion, the current of the second signal flowing through the 17th portion, and the current of the second signal flowing through the 25th portion are all in the same direction; 10. The semiconductor circuit of claim 9.

[0156] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0157] 9...information processing system, 40...host device, 41...processor, 43...interface circuit, 50...memory controller, 51...processor, 52...RAM, 53...buffer circuit, 54...interface circuit, 55...interface circuit, 60...NAND flash memory, 100...receiving circuit, 111,112,121,122,911,912,921,922...inductive element, 113,123,131,930...resistive element, 115,125...current source, 130...RC network circuit, 132...capacitive element, 140,141,940,941...power supply line, 500...memory system, 800...transmitting circuit, 888...transmitting terminal, 900,900a... Termination circuit, 901...sampler, 902...digital signal processing circuit, 913, 914, 923, 924...diodes, 999...receiving terminal, ITn, ITna, ITnc, ITp, ITpa, ITpc...input terminal, LP101 to LP111, LP201 to LP211, LP301 to LP317, LP401 to LP417...wiring section, OTn, OTna, OTnb, OTnc, OTp, OTpa, OTpb, OTpc...output terminal, RX, RXh, RXm...receivers, TC1, TC1a, TC1b, TC2, TC2a, TC2b...T coil, TCP, TCPa, TCPb...T coil pair, TR1, TR2...transistor, TX, TXh, TXm...transmitters.

Claims

1. A semiconductor substrate; a first T coil provided at a distance from the semiconductor substrate and including a first inductive element and a second inductive element connected in series; a second T coil provided at a distance from the semiconductor substrate and including a third inductive element and a fourth inductive element connected in series; Equipped with a portion of the first T coil is provided at a first position in a vertical direction from a surface of the semiconductor substrate, a portion of the second T coil is provided so as to overlap a portion of the first T coil as viewed in the vertical direction at a second position in the vertical direction from the surface, a first distance from the semiconductor substrate to the first position and a second distance from the semiconductor substrate to the second position are different in the vertical direction; A first signal having a first polarity of a differential signal is applied to the first T coil, A semiconductor circuit configured such that a second signal having a second polarity different from the first polarity of the differential signal is applied to the second T coil.

2. The semiconductor circuit according to claim 1 , wherein each of the first T coil and the second T coil has a square or octagonal ring shape.

3. A direction of a current of the first signal flowing through the first T coil; The direction of the current of the second signal flowing through the second T coil is The semiconductor circuit according to claim 1 , wherein a portion of the first T coil and a portion of the second T coil that overlap each other in the vertical direction are aligned.

4. the surface of the semiconductor substrate is parallel to a plane defined by a first direction and a second direction intersecting the first direction; The first T coil is a first portion having one end and another end and extending in the first direction; a second portion having one end connected to the other end of the first portion and an other end, the second portion extending in the second direction; a third portion having one end connected to the other end of the second portion and the other end, the third portion extending in the first direction; a fourth portion having one end connected to the other end of the third portion and the other end, extending in the second direction and not in contact with the first portion; a fifth portion having one end connected to the other end of the fourth portion and the other end, extending in the first direction in parallel with the first portion and not in contact with the second portion; a sixth portion having one end electrically connected to the other end of the fifth portion and the other end, extending in the first direction and provided at a position different from that of the second portion; a seventh portion having one end electrically connected to the other end of the sixth portion and the other end, the seventh portion extending in the second direction in parallel with the second portion; an eighth portion having one end connected to the other end of the seventh portion and the other end, the eighth portion extending in the first direction in parallel with the third portion; a ninth portion having one end connected to the other end of the eighth portion and the other end, extending in the second direction in parallel with the fourth portion and not in contact with the first portion; a tenth portion having one end connected to the other end of the ninth portion and the other end, extending in the first direction in parallel with the first portion and not in contact with the fourth portion; Including, The semiconductor circuit according to claim 1 .

5. The second T coil is an eleventh portion having one end and the other end and extending in the first direction; a twelfth portion having one end connected to the other end of the eleventh portion and the other end and extending in the second direction; a thirteenth portion having one end connected to the other end of the twelfth portion and the other end and extending in the first direction; a 14th portion having one end connected to the other end of the 13th portion and the other end, extending in the second direction, and provided so as not to contact the 11th portion; a 15th portion having one end connected to the other end of the 14th portion and the other end, extending in the first direction in parallel with the 11th portion and not in contact with the 12th portion; a sixteenth portion having one end electrically connected to the other end of the fifteenth portion and the other end, extending in the first direction and provided at a position different from that of the twelfth portion; a seventeenth portion having one end electrically connected to the other end of the sixteenth portion and the other end, the seventeenth portion extending in the second direction in parallel with the twelfth portion; an eighteenth portion having one end connected to the other end of the seventeenth portion and the other end, the eighteenth portion extending in the first direction in parallel with the thirteenth portion; a 19th portion having one end connected to the other end of the 18th portion and the other end, extending in the second direction in parallel with the 14th portion, and provided so as not to contact the 11th portion; a 20th portion having one end connected to the other end of the 19th portion and the other end, extending in the first direction in parallel with the 11th portion, and provided so as not to contact the 14th portion; The semiconductor circuit of claim 4 .

6. the surface of the semiconductor substrate is parallel to a plane defined by a first direction and a second direction intersecting the first direction; a third direction is a direction that is included in the plane defined by the first direction and the second direction and is different from the first direction and the second direction; When a direction that is included in the plane defined by the first direction and the second direction and is different from the first direction, the second direction, and the third direction is defined as a fourth direction, The first T coil is a first portion having one end and another end and extending in the first direction; a second portion having one end connected to the other end of the first portion and the other end, the second portion extending in the third direction; a third portion having one end connected to the other end of the second portion and the other end, the third portion extending in the second direction; a fourth portion having one end connected to the other end of the third portion and the other end and extending in the fourth direction; a fifth portion having one end connected to the other end of the fourth portion and the other end, the fifth portion extending in the first direction; a sixth portion having one end connected to the other end of the fifth portion and the other end, the sixth portion extending in the third direction; a seventh portion having one end connected to the other end of the sixth portion and the other end and extending in the second direction; an eighth portion having one end connected to the other end of the seventh portion and the other end, extending in the fourth direction and not in contact with the first portion; a ninth portion having one end connected to the other end of the eighth portion and the other end, extending in the first direction in parallel with the first portion, and provided so as not to contact the second portion and the third portion; a tenth portion having one end electrically connected to the other end of the ninth portion and the other end, extending in the first direction, and provided at a position different from the second portion and the third portion; an eleventh portion having one end electrically connected to the other end of the tenth portion and the other end, the eleventh portion extending in the second direction in parallel with the third portion; a twelfth portion having one end connected to the other end of the eleventh portion and the other end, the twelfth portion extending in the fourth direction in parallel with the fourth portion; a thirteenth portion having one end connected to the other end of the twelfth portion and the other end, the thirteenth portion extending in the first direction in parallel with the fifth portion; a fourteenth portion having one end connected to the other end of the thirteenth portion and the other end, the fourteenth portion extending in the third direction in parallel with the sixth portion; a fifteenth portion having one end connected to the other end of the fourteenth portion and the other end, extending in the second direction in parallel with the seventh portion and not in contact with the first portion; a sixteenth portion having one end connected to the other end of the fifteenth portion and the other end, extending in the first direction in parallel with the first portion and not in contact with the eighth portion; Including, The semiconductor circuit according to claim 1 .

7. The second T coil is a seventeenth portion having one end and another end and extending in the first direction; an eighteenth portion having one end connected to the other end of the seventeenth portion and the other end and extending in the fourth direction; a 19th portion having one end connected to the other end of the 18th portion and the other end and extending in the second direction; a 20th portion having one end connected to the other end of the 19th portion and the other end and extending in the third direction; a 21st portion having one end connected to the other end of the 20th portion and the other end and extending in the first direction; a 22nd portion having one end connected to the other end of the 21st portion and the other end and extending in the fourth direction; a 23rd portion having one end connected to the other end of the 22nd portion and the other end and extending in the second direction; a 24th portion having one end connected to the other end of the 23rd portion and the other end, extending in the third direction, and provided so as not to contact the 17th portion; a 25th portion having one end connected to the other end of the 24th portion and the other end, extending in the first direction in parallel with the 17th portion, and provided so as not to contact the 18th portion and the 19th portion; a 26th portion having one end electrically connected to the other end of the 25th portion and the other end, extending in the first direction, and provided at a position different from the 18th portion and the 19th portion; a 27th portion having one end electrically connected to the other end of the 26th portion and the other end, the 27th portion extending in the second direction in parallel with the 19th portion; a 28th portion having one end connected to the other end of the 27th portion and the other end, the 28th portion extending in the third direction in parallel with the 20th portion; a 29th portion having one end connected to the other end of the 28th portion and the other end, and extending in the first direction in parallel with the 21st portion; a 30th portion having one end connected to the other end of the 29th portion and the other end, the 30th portion extending in the fourth direction in parallel with the 22nd portion; a 31st portion having one end connected to the other end of the 30th portion and the other end, extending in the second direction in parallel with the 23rd portion, and provided so as not to contact the 17th portion; a 32nd portion having one end connected to the other end of the 31st portion and the other end, extending in the first direction in parallel with the 17th portion, and provided so as not to contact the 24th portion; Including, 7. The semiconductor circuit according to claim 6.

8. A memory device; a memory controller including an interface circuit including the semiconductor circuit according to claim 1, the memory controller controlling an operation of the memory device based on communication via the interface circuit; A memory system comprising:

9. An interface circuit including the semiconductor circuit according to any one of claims 1 to 7; a processor for controlling an external device connected via the interface circuit; An information processing device comprising:

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