Computing unit and information processing device

Abstract

To save electric consumption through Power Gating with a fine particle size.SOLUTION: A computing unit comprises a control part configured to: predict second computation precision of a third processing element 123 after predetermined cycles at first timing based upon first data of a first processing element 123 and second data of a second processing element 123 predetermined cycles before the third processing element 123; power on a second circuit corresponding to second computation precision by the third processing element 123 when it is necessary at the first timing to change the first computation precision corresponding a the first circuit operating with the third processing element 123 based upon the result of the prediction; compute the second arithmetic precision by the second circuit of the third processing element 123 at second timing the predetermined cycles after the first timing; and power off the first circuit of the third processing element 123 at third timing after the second timing.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a computing unit and an information processing device. [Background technology]

[0002] In high performance computing, power consumption can be high. Power supply is limited, and power consumption can limit performance.

[0003] In high-performance computing, a systolic array configuration is often used to place arithmetic units at high density to speed up matrix multiplication.

[0004] In addition, in the fields of artificial intelligence (AI) and machine learning, low-precision calculations are being used to improve calculation efficiency, and there is a movement to incorporate them into high-performance computing as well. The power consumption of low-precision calculation units can be significantly reduced compared to high-precision calculation units.

[0005] The power gating technique is known as a technology for reducing power consumption. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2020 / 008643 Summary of the Invention [Problem to be solved by the invention]

[0007] However, with power gating, power to blocks that are not in use is cut off, and when the power is resumed, a waiting time may be required until the power supply stabilizes.

[0008] One aspect is to achieve low power consumption by performing fine-grained power gating. [Means for solving the problem]

[0009] In one aspect, a computing unit has a plurality of processing elements including a first processing element, a second processing element, and a third processing element, and performs systolic array type matrix operations, and is further equipped with a control unit that, at a first timing, predicts a second calculation precision after a predetermined cycle in the third processing element based on first data of the first processing element and second data of the second processing element that are a predetermined cycle before the third processing element, and, when it is necessary to change the first calculation precision corresponding to a first circuit operating in the third processing element based on a result of the prediction at the first timing, turns on a power supply to a second circuit corresponding to the second calculation precision in the third processing element, and, at a second timing that is the predetermined cycle after the first timing, executes a calculation of the second calculation precision in the second circuit of the third processing element, and, at a third timing after the second timing, turns off a power supply to the first circuit in the third processing element. Effect of the Invention

[0010] On the one hand, fine-grained power gating can be used to achieve low power consumption. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram illustrating an example of a hardware configuration of an information processing device according to a first embodiment. [Diagram 2] 2 is a block diagram illustrating a schematic configuration example of a systolic array type matrix operation accelerator illustrated in FIG. 1. [Diagram 3] 3 is a block diagram illustrating a first configuration example of a processing element (PE) illustrated in FIG. 2. [Figure 4] 1A to 1D are diagrams illustrating systolic arrays and matrix operations. [Diagram 5]3 is a block diagram illustrating a third configuration example of the PE illustrated in FIG. 2. [Figure 6] 3 is a diagram illustrating an example of the operation of the accelerator illustrated in FIG. 2. [Figure 7] 7(a) to 7(c) are diagrams illustrating the states of each PE during operation of the accelerator shown in FIG. [Figure 8] FIG. 4 is a diagram illustrating estimation of calculation accuracy in the first embodiment. [Figure 9] 5 is a flowchart illustrating a process of determining which arithmetic unit to use in the first embodiment. [Figure 10] FIG. 11 is a block diagram illustrating a schematic configuration example of a PE in a modified example of the first embodiment. [Figure 11] 10A is a diagram illustrating details of the 64-bit to 16-bit bit width converter illustrated in FIG. 10, and FIG. 10B is a diagram illustrating details of the 64-bit to 32-bit bit width converter illustrated in FIG. [Figure 12] FIG. 11 is a block diagram illustrating a configuration example of a PE in a second embodiment. [Figure 13] FIG. 11 is a diagram illustrating estimation of calculation accuracy in the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] [A] Embodiment An embodiment will be described below with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude the application of various modified examples and techniques not specified in the embodiment. In other words, the present embodiment can be implemented with various modifications within the scope of the gist of the embodiment. In addition, each figure does not intend to include only the components shown in the figure, but can include other functions, etc.

[0013] [A-1] First embodiment FIG. 1 is a block diagram illustrating an example of a hardware configuration of an information processing device 1 according to the first embodiment.

[0014] The information processing device 1 includes a central processing unit (CPU) 11, an accelerator 12, a memory 13, an auxiliary storage device 14, a communication interface 15, and an input / output interface 16.

[0015] The CPU 11 is, for example, a processing device that performs various controls and calculations, and realizes various functions by executing an Operating System (OS) and programs read by the memory 13.

[0016] The programs for implementing various functions may be provided in a form recorded on a computer-readable recording medium, such as a flexible disk, a CD (CD-ROM, CD-R, CD-RW, etc.), a DVD (DVD-ROM, DVD-RAM, DVD-R, DVD+R, DVD-RW, DVD+RW, HD DVD, etc.), a Blu-ray disk, a magnetic disk, an optical disk, a magneto-optical disk, etc. Then, the computer (CPU 11 in this embodiment) may read the program from the above-mentioned recording medium via a reading device (not shown), transfer it to an internal recording device or an external recording device, and store it for use. Also, the program may be recorded in a storage device (recording medium), such as a magnetic disk, an optical disk, a magneto-optical disk, etc., and provided to the computer from the storage device via a communication path.

[0017] When implementing various functions, a program stored in an internal storage device (memory 13 in this embodiment) may be executed by a computer (CPU 11 in this embodiment). Also, a program recorded on a recording medium may be read and executed by a computer.

[0018] For example, the CPU 11 controls the operation of the entire information processing device 1. The device for controlling the operation of the entire information processing device 1 is not limited to the CPU 11, and may be, for example, any one of an MPU, a DSP, an ASIC, a PLD, and an FPGA. The device for controlling the operation of the entire information processing device 1 may be a combination of two or more of a CPU, an MPU, a DSP, an ASIC, a PLD, and an FPGA. Note that MPU is an abbreviation for Micro Processing Unit, DSP is an abbreviation for Digital Signal Processor, and ASIC is an abbreviation for Application Specific Integrated Circuit. Also, PLD is an abbreviation for Programmable Logic Device, and FPGA is an abbreviation for Field Programmable Gate Array.

[0019] The accelerator 12 is an example of a computing unit, and assists the CPU 11 by performing systolic array type matrix operations in order to increase the processing power of the information processing device 1. The accelerator 12 will be described in detail later with reference to FIG. 2 and subsequent figures.

[0020] The memory 13 is illustratively a storage device including a Read Only Memory (ROM) and a Random Access Memory (RAM). The RAM may be, for example, a Dynamic RAM (DRAM). Programs such as a Basic Input / Output System (BIOS) may be written in the ROM of the memory 13. The software programs in the memory 13 may be appropriately read and executed by the CPU 11. The RAM of the memory 13 may be used as a primary recording memory or a working memory.

[0021] The auxiliary storage device 14 is, for example, a device that stores data in a readable and writable manner, and may be, for example, a hard disk drive (HDD), a solid state drive (SSD), or a storage class memory (SCM).

[0022] The communication interface 15 is an interface device for connecting the information processing device 1 to a network and communicating with an external device (not shown) via the network. As the communication interface 15, for example, various interface cards compatible with network standards such as a wired local area network (LAN), a wireless LAN, or a wireless wide area network (WWAN) can be used.

[0023] The input / output interface 16 is configured to allow the recording medium 160 to be attached thereto. The input / output interface 16 is configured to allow the information recorded on the recording medium 160 to be read when the recording medium 160 is attached thereto. In this example, the recording medium 160 is portable. For example, the recording medium 160 is a flexible disk, an optical disk, a magnetic disk, a magneto-optical disk, a semiconductor memory, or the like.

[0024] FIG. 2 is a block diagram showing a schematic configuration example of the systolic array type matrix operation accelerator 12 shown in FIG.

[0025] The accelerator 12 includes a plurality of PEs 120, a control unit 121, three RAMs 122, and a Direct Memory Access (DMA) controller 124.

[0026] The control unit 121 controls the entire accelerator 12 .

[0027] Of the three RAMs 122, the RAMs 122 on the upper and left sides of FIG. 2 input data to the multiple PEs 120. In addition, of the three RAMs 122, the RAM 122 on the lower side of FIG.

[0028] The PE 120 performs matrix multiplication C=A×B. A, B, and C are each N×N (N is a natural number) matrices. N is determined at the time of design and may be, for example, 128. The results of the multiply-and-add calculations that propagate matrix data and partial sums to the right and down are accumulated within the PE 120. N×N multiplications and additions are performed simultaneously, resulting in high calculation efficiency.

[0029] The DMA controller 124 transfers data received from the output side RAM 122 directly to the memory 13 without going through the CPU 11 .

[0030] FIG. 3 is a block diagram showing a first example of the configuration of the PE 120 shown in FIG.

[0031] The PE 120 includes input blocks 21a and 21b, output blocks 21c and 21d, a multiplier 22, an adder 23, and an accelerator block (ACC) 24. One PE 120 performs one multiply-accumulate operation and accumulates the multiply-accumulate result inside.

[0032] The input blocks 21a and 21b receive input from the RAM 122 or the PE 120 at the previous stage.

[0033] The multiplier 22 multiplies the input data from the input blocks 21a and 21b.

[0034] The adder 23 adds the output from the multiplier 22 and the output from the ACC 24 .

[0035] The ACC 24 outputs the output from the adder 23 to the RAM 122. The ACC 24 also receives an input from the RAM 122.

[0036] The output blocks 21c and 21d receive data input from the input blocks 21a and 21b, respectively, and output the data to the PE 120 or the RAM 122 in the subsequent stage.

[0037] FIGS. 4(a) to 4(d) are diagrams illustrating a systolic array and a matrix operation.

[0038] In cycle=0 shown in FIG. 4(a), 0,0 and b 0,0 is entered, and a 0,0 and b 0,0 is stored in ACC24.

[0039] In cycle=1 shown in FIG. 4(b), 0,1 and b 1,0 is entered and a 0,0 b 0,0 +a 0,1 b 1,0 is stored in ACC24, and a 0,0 and b 0,1 is entered and a 0,0 b 0,1 is stored in ACC24, and a 1,0 and b 0,0 is entered and a 1,0 b 0,0 is stored in ACC24.

[0040] In cycle=2 shown in FIG. 4(c), 0,1 and b 1,1 is entered and a 0,0 b 0,1 +a 0,1 b 1,1 is stored in ACC24, and a 1,1 and b 1,0 is entered and a 1,0 b 0,0 +a 1,1 b 1,0 is stored in ACC24, and a 1,0 and b 0,1 is entered and a 1,0 b 0,1 is stored and entered into ACC24.

[0041] In cycle=3 shown in FIG. 4(d), 1,1 and b 1,1 is entered and 1,0 b 0,1+ a 1,1 b1,1 is stored in ACC24.

[0042] The calculation contents in (a) to (d) of FIG. 4 are expressed as the following determinant:

number

[0043] FIG. 5 is a block diagram showing a schematic diagram of a PE 123 as a third configuration example of the PE 120 shown in FIG.

[0044] The PE 123 includes input blocks 21a and 21b, output blocks 21c and 21d, and, for example, three sets of arithmetic circuits for each data type.

[0045] The three sets of arithmetic circuits are, for example, for FP64, FP32, and FP16, and each includes a multiplier 22, an adder 23, and an ACC 24.

[0046] The PE 123 cuts off the power of unused blocks to reduce power consumption. For example, when performing matrix multiplication in FP32, the PE 123 cuts off the power of FP16 and FP64 blocks (see the shaded area in Figure 5).

[0047] When changing data types to FP64 or FP16, you need to wait a few cycles for them to stabilize.

[0048] Therefore, in this embodiment, the necessary calculation precision is predicted for each PE 123 of the systolic array, and the calculation precision of the arithmetic unit is selected several cycles in advance based on the prediction result, and power gating control is performed.

[0049] In the systolic array, the values ​​of a and b are propagated, and the operation accuracy is predicted from the required operation accuracy information of the data propagated several cycles later.

[0050] By predicting the accuracy several cycles later and controlling power gating, the number of cycles required for stabilization can be hidden. The required calculation accuracy for each data is estimated from the range of the exponent value, for example.

[0051] FIG. 6 is a diagram for explaining an example of the operation of the accelerator 12 shown in FIG.

[0052] At clock=t, the required calculation precision of axx is calculated as shown by symbol A1, and the required calculation precision of bxx is calculated as shown by symbol A2. As shown by symbol A3, the calculation precision two cycles later is predicted from the required calculation precision of axx and bxx and the value of Acc24, and if it is determined that a change from FP32 to FP64 is necessary, the FP64 block is powered on.

[0053] At clock=t+1, as shown by reference symbol A4, an operation is performed in FP32, and the FP64 block is waited for to stabilize.

[0054] At clock=t+2, as indicated by reference symbol A5, the value of ACC24 is converted to FP64, and the multiply-and-accumulate operation acc+=axx*bxx is performed in FP64.

[0055] At clock=t+3, as indicated by reference symbol A6, the power to the FP32 circuit is turned off.

[0056] 7(a) to 7(c) are diagrams illustrating the states of the PEs 123 during operation of the accelerator 12 shown in FIG.

[0057] At clock=t, t+1 in Figure 7(a), FP32 is powered on, FP16 is powered off (see the shaded area), and FP64 is powered on and waiting for stability (see the shaded area).

[0058] At clock=t+2 in FIG. 7(b), in addition to FP32, FP64 is powered on and operates stably.

[0059] At clock=t+3 in FIG. 7(c), the power to FP32 is turned off (see the shaded area).

[0060] FIG. 8 is a diagram for explaining the estimation of the calculation accuracy in the first embodiment.

[0061] Assume that axx and bxx are within the representable range, and the calculation result of axx*bxx+acc does not overflow or underflow.

[0062] Let e_a be the exponent (axx), e_b be the exponent (bxx), and e_acc be the exponent (acc). Let s_a be the sign (axx), s_b be the sign (bxx), and s_acc be the sign (acc). Let the exponent of the multiplication result be e_x and the sign be s_x. e_x=e_a+e_b or e_a+e_b+1. s_x=xor(s_a,s_b).

[0063] The data type is determined in the order of FP16 and FP32, and if all the conditions in the table shown by symbol B1 are satisfied, it is determined that the operation will be performed with that data type.

[0064] That is, the range that the input can represent is -e min ≦e_a≦e max And -e min ≦e_b≦e max The range that the multiplication result can represent is -e min ≦e_x≦e max The condition for the addition result to not overflow or underflow is that when s_x=s_acc=0, e_x <e max ,e_acc <e max Then, when s_x=s_acc=1, e min <e_x, e min <e_accとなり、s_x≠s_accのときe_x≠e_accとなる。

[0065] Considering the carry of the hidden bit, e_x0=e_a+e_b when there is no carry, and e_x1=e_a+e_b+1 when there is a carry. In this case, the range that can be expressed by the multiplication result is -e min ≦e_x0 and e_x1≦e max The condition for the addition result not to overflow or underflow is that when s_x=s_acc=0, e_x1 <e max Then, when s_x=s_acc=1, e min <e_x0となり、s_x≠s_accのときe_x0≠e_accまたは e_x1≠e_accとなる。

[0066] As shown in symbol B2, for FP16, e min =-14, e max = 15, and for FP32 e min =-126, e max =127.

[0067] The process of determining which arithmetic unit to use in the first embodiment will be described with reference to the flow chart (steps S1 to S5) shown in FIG.

[0068] The control unit 121 shown in FIG. 1 determines whether it is possible to express in FP16 (step S1).

[0069] If it is possible to express it in FP16 (see the Yes route of step S1), the control unit 121 determines that FP16 is to be used (step S2), and the process of determining the arithmetic unit to be used ends.

[0070] On the other hand, if the image cannot be represented in FP16 (see the No route from step S1), the control unit 121 determines whether the image can be represented in FP32 (step S3).

[0071] If it is possible to express it in FP32 (see the Yes route of step S3), the control unit 121 determines to use FP32 (step S4), and the process of determining the arithmetic unit to be used ends.

[0072] On the other hand, if the data cannot be represented in FP32 (see the No route in step S3), the control unit 121 determines that FP64 is to be used (step S5), and the process of determining the arithmetic unit to be used ends.

[0073] FIG. 10 is a block diagram illustrating a schematic configuration example of a PE 123b in a modification of the first embodiment.

[0074] The PE 123a includes input blocks 21a and 21b, output blocks 21c and 21d, a PE control unit 2, an FP64 circuit 2a, an FP32 circuit 2b, an FP16 circuit 2c, and a RAM 122.

[0075] The PE control unit 2 controls the ON / OFF and operation of each of the circuits 2a to 2c.

[0076] The FP64 circuit 2a includes a multiplier 22, an adder 23, an ACC 24, a converter 25a (FP64→FP32), and a selector (SEL) 26.

[0077] The FP32 circuit 2b includes a multiplier 22, an adder 23, an ACC 24, a converter 25b (FP32→FP64), a converter 25c (FP32→FP16), a SEL 26, and a bit width converter 27a (b_sel32).

[0078] The FP16 circuit 2c includes a multiplier 22, an adder 23, an ACC 24, a converter 25d (FP16→FP32), a SEL 26, and a bit width converter 27a (b_sel16).

[0079] In the FP64 circuit 2a, the multiplier 22 multiplies the 64-bit inputs from the input blocks 21a and 21b. The adder 23 adds the multiplication result by the multiplier 22 and the output by the SEL 26. The ACC 24 stores the addition result by the adder 23, and outputs the stored result to the PE control unit 2, the RAM 122, the SEL 26, and the FP32 circuit 2b. The converter 25a converts the output from the ACC 24 of the FP32 circuit 2b for the FP64 circuit 2a. Based on the control from the PE control unit 2, the SEL 26 selects either the output of the ACC 24 of the FP64 circuit 2a or the output of the ACC 24 of the FP32 circuit 2b via the converter 25a, and inputs it to the adder 23.

[0080] In the FP32 circuit 2b, the multiplier 22 converts the 64-bit input from the input blocks 21a and 21b into 32-bit and multiplies it. The adder 23 adds the multiplication result by the multiplier 22 and the output by the SEL 26. The ACC 24 stores the addition result by the adder 23 and outputs the stored result to the PE control unit 2, the RAM 122, the SEL 26, the FP64 circuit 2a, and the FP16 circuit 2c. The converters 25b and 25c convert the respective outputs from the ACC 24 of the FP64 circuit 2a and the FP16 circuit 2c to the FP32 circuit 2b. Based on the control from the PE control unit 2, the SEL 26 selects one of the output of the ACC 24 of the FP32 circuit 2b, the output of the ACC 24 of the FP64 circuit 2a via the converter 25b, and the output of the ACC 24 of the FP16 circuit 2c via the converter 25c, and inputs it to the adder 23.

[0081] In the FP16 circuit 2c, the multiplier 22 converts the 64-bit input from the input blocks 21a and 21b into 16-bit input and multiplies the result. The adder 23 adds the multiplication result by the multiplier 22 and the output by the SEL 26. The ACC 24 stores the addition result by the adder 23 and outputs the stored result to the PE control unit 2, the RAM 122, the SEL 26, and the FP32 circuit 2b. The converter 25d converts the output from the ACC 24 of the FP32 circuit 2b for the FP16 circuit 2c. Based on the control from the PE control unit 2, the SEL 26 selects either the output of the ACC 24 of the FP16 circuit 2c or the output of the ACC 24 of the FP32 circuit 2b via the converter 25d and inputs it to the adder 23.

[0082] FIG. 11(a) is a diagram illustrating details of the 64-bit to 16-bit bit width converter 27b shown in FIG. 10, and FIG. 11(b) is a diagram illustrating details of the 64-bit to 32-bit bit width converter 27a shown in FIG. 10.

[0083] As shown in (a) of Figure 11, a 64-bit bit string before conversion has 1 sign bit (s), 11 exponent bits (e), and 52 mantissa bits (m). When converted from 64 bits to 16 bits, the sign bit remains as it is, the lower 5 bits of the exponent remain, and the upper 10 bits of the mantissa remain.

[0084] As shown in (b) of Fig. 11, the 64-bit bit string before conversion has 1 sign bit (s), 11 exponent bits (e), and 52 mantissa bits (m). When converted from 64 bits to 32 bits, the sign bit remains as it is, the lower 8 bits of the exponent remain, and the upper 32 bits of the mantissa remain.

[0085] [A-2] Second embodiment In AI accelerators, etc., double precision is sometimes used in the addition part to ensure accuracy during the calculation.

[0086] FIG. 12 is a block diagram illustrating a schematic configuration example of the PE 123a in the second embodiment.

[0087] The PE 123a shown in Fig. 12 has a configuration similar to that of the PE 123 shown in Fig. 5, but the adder 23 and ACC 24 for FP32 are double-precision FP64, and the adder 23 and ACC 24 for FP16 are double-precision FP64.

[0088] FIG. 13 is a diagram for explaining the estimation of the calculation accuracy in the second embodiment.

[0089] Assume that axx and bxx are within the representable range, and the calculation result of axx*bxx+acc does not overflow or underflow.

[0090] Let e_a be the exponent part (axx), e_b be the exponent part (bxx), e_acc be the exponent part (acc), s_a be the sign (axx), s_b be the sign (bxx), s_acc be the sign (acc), and the exponent part of the multiplication result be e_x=e_a+e_b and the sign be s_x=xor(s_a, s_b).

[0091] The data type is determined in the order of FP16 and FP32, and if all the conditions in the table shown by symbol C1 are satisfied, it is determined that the operation is to be performed in that data type. In the second embodiment, unlike the first embodiment, the input range of the multiplier 22 and the range after the output of the multiplier are divided into e1 and e2.

[0092] That is, the range that the input can represent is -e1 min ≦e_a≦e1 max And -e1 min ≦e_b≦e1 max The range that the multiplication result can represent is -e2 min ≦e_x≦e2 max The condition for the addition result to not overflow or underflow is that when s_x=s_acc=0, e_x <e2 max ,e_acc <e2 max Then, when s_x=s_acc=1, e2 min <e_x, e2 min <e_accとなり、s_x≠s_accのときe_x≠e_accとなる。

[0093] Considering the carry of the hidden bit, e_x0=e_a+e_b when there is no carry, and e_x1=e_a+e_b+1 when there is a carry. In this case, the range that can be expressed by the multiplication result is -e2 min ≦e_x0 and e_x1≦e2 max The condition for the addition result not to overflow or underflow is that when s_x=s_acc=0, e_x1 <e2 max Then, when s_x=s_acc=1, e2 min <e_x0となり、s_x≠s_accのとき、e_x0≠e_accまたは e_x1≠e_accとなる。

[0094] As shown in symbol C2, e1 for FP16 min =-14, e1 max =15, e2 min =-126, e2 max = 127, and e1 for FP32 min =-126, e1 max =127, e2 min =-1022, e2 max =1023.

[0095] [B] Effect According to the arithmetic unit and the information processing device in the above-described embodiment, for example, the following advantageous effects can be obtained.

[0096] The control unit 121 predicts the second arithmetic precision of the third PE 123 after a predetermined cycle based on the first data of the first PE 123 and the second data of the second PE 123, which are a predetermined number of cycles before the third PE 123, at a first timing. When it is necessary to change the first arithmetic precision corresponding to the first circuit operating in the third PE 123 based on the result of the prediction at the first timing, the control unit 121 turns on the power of the second circuit corresponding to the second arithmetic precision in the third PE 123. At a second timing that is a predetermined number of cycles after the first timing, the control unit 121 executes an arithmetic operation of the second arithmetic precision in the second circuit of the third PE 123, and at a third timing that is after the second timing, turns off the power of the first circuit in the third PE 123.

[0097] This allows fine-grained power gating to achieve low power consumption. The power consumption is highest for FP64, followed by FP32 and then FP16. In addition, dynamic control of calculation precision according to the matrix data values ​​allows calculations to be performed without failure, and overflow or underflow does not occur.

[0098] The control unit 121 powers on the second circuit when the first data or the second data is not within the range that can be expressed, or when the value obtained by adding the product of the first data and the second data to the output data of ACC24 in the circuit running in the third PE 123 overflows or underflows.

[0099] This makes it possible to appropriately select a circuit having the arithmetic accuracy to output a normal arithmetic result.

[0100] The control unit 121 performs the addition operation in the second circuit of the third PE 123 with double precision, which is the second operation precision.

[0101] As a result, the calculation accuracy of the multiplier 22 is lowered to reduce power consumption, and then the calculation accuracy of the adder 23 is increased, thereby making it possible to improve the calculation accuracy with low power consumption.

[0102] [C] Other The disclosed technology is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present embodiment. Each configuration and each process of the present embodiment can be selected as necessary, or can be combined as appropriate.

[0103] [D] Notes The following supplementary notes are further disclosed regarding the above embodiment.

[0104] (Appendix 1) A computing unit having a plurality of processing elements including a first processing element, a second processing element, and a third processing element, and performing a systolic array type matrix operation, At a first timing, based on first data of the first processing element and second data of the second processing element, which are a predetermined number of cycles before the third processing element, predicting a second calculation accuracy after the predetermined number of cycles in the third processing element; at the first timing, when it is necessary to change a first arithmetic precision corresponding to a first circuit operating in the third processing element based on a result of the prediction, powering on a second circuit corresponding to the second arithmetic precision in the third processing element; executing an operation of the second arithmetic precision in the second circuit of the third processing element at a second timing that is the predetermined number of cycles after the first timing; At a third timing after the second timing, powering off the first circuit in the third processing element; A computing unit having a control unit.

[0105] (Appendix 2) the control unit powers on the second circuit when the first data or the second data is not within a range that can be expressed, or when a value obtained by adding output data of an accelerator in a circuit operating in the third processing element to a product of the first data and the second data overflows or underflows. 2. A computing unit as defined in claim 1.

[0106] (Appendix 3) the control unit performs an addition operation in the second circuit of the third processing element with double precision, which is the second arithmetic precision; 3. A computing device according to claim 1 or 2.

[0107] (Appendix 4) A processor; a computing unit having a plurality of processing elements including a first processing element, a second processing element, and a third processing element, the computing unit executing a systolic array type matrix operation to assist the processor; Equipped with The computing unit includes: At a first timing, based on first data of the first processing element and second data of the second processing element, which are a predetermined number of cycles before the third processing element, predicting a second calculation accuracy after the predetermined number of cycles in the third processing element; at the first timing, when it is necessary to change a first arithmetic precision corresponding to a first circuit operating in the third processing element based on a result of the prediction, powering on a second circuit corresponding to the second arithmetic precision in the third processing element; executing an operation of the second arithmetic precision in the second circuit of the third processing element at a second timing that is the predetermined number of cycles after the first timing; At a third timing after the second timing, powering off the first circuit in the third processing element; Information processing device.

[0108] (Appendix 5) the computing unit powers on the second circuit when the first data or the second data is not within a range that can be expressed, or when a value obtained by adding output data of an accelerator in a circuit operating in the third processing element to a product of the first data and the second data overflows or underflows. 5. The information processing device according to claim 4.

[0109] (Appendix 6) The arithmetic unit performs an addition operation in the second circuit of the third processing element with double precision, which is the second arithmetic precision. 6. The information processing device according to claim 4 or 5. [Explanation of symbols]

[0110] 1: Information processing equipment 2:PE control section 2a:FP64 circuit 2b: FP32 circuit 2c: FP16 circuit 11: CPU 12: Accelerator 13: Memory 14: Auxiliary storage device 15: Communication interface 16: Input / Output Interface 21a, 21b: Input block 21c, 21d: Output block 22: Multiplier 23: Adder 24 :ACC 24a: Multiplexer 25a~25d: Converter 26 :SEL 27a, 27b: Bit width converter 120, 120a, 123, 123a:PE 121: Control unit 122: RAM 124: DMA controller 160: Recording media

Claims

1. A computing unit having a plurality of processing elements including a first processing element, a second processing element, and a third processing element, and performing a systolic array type matrix operation, predicting, at a first timing, a second calculation accuracy after a predetermined cycle in the third processing element based on first data of the first processing element and second data of the second processing element, the second calculation accuracy after a predetermined cycle in the third processing element; at the first timing, when it is necessary to change a first arithmetic precision corresponding to a first circuit operating in the third processing element based on a result of the prediction, powering on a second circuit corresponding to the second arithmetic precision in the third processing element; executing an operation of the second arithmetic precision in the second circuit of the third processing element at a second timing that is the predetermined number of cycles after the first timing; At a third timing after the second timing, powering off the first circuit in the third processing element; A computing unit having a control unit.

2. the control unit powers on the second circuit when the first data or the second data is not within a range that can be expressed, or when a value obtained by adding output data of an accelerator in a circuit operating in the third processing element to a product of the first data and the second data overflows or underflows. The computing unit according to claim 1 .

3. the control unit performs an addition operation in the second circuit of the third processing element with double precision, which is the second arithmetic precision; 3. The computing unit according to claim 1 or 2.

4. A processor; a computing unit having a plurality of processing elements including a first processing element, a second processing element, and a third processing element, the computing unit executing a systolic array type matrix operation to assist the processor; Equipped with The computing unit includes: predicting, at a first timing, a second calculation accuracy after a predetermined cycle in the third processing element based on first data of the first processing element and second data of the second processing element, the second calculation accuracy after a predetermined cycle in the third processing element; at the first timing, when it is necessary to change a first arithmetic precision corresponding to a first circuit operating in the third processing element based on a result of the prediction, powering on a second circuit corresponding to the second arithmetic precision in the third processing element; executing an operation of the second arithmetic precision in the second circuit of the third processing element at a second timing that is the predetermined number of cycles after the first timing; At a third timing after the second timing, powering off the first circuit in the third processing element; Information processing device.

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