Data transfer control device and information processing apparatus

The data transfer control device enhances performance by managing descriptor storage and reading to mitigate speculative read failures and errors, ensuring efficient data transfer without increasing circuit complexity.

JP2025006189APending Publication Date: 2025-01-17FUJITSU LTD
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Patent Information

Application Number
JP2023106833
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2023-06-29
Publication Date
2025-01-17

AI Technical Summary

Technical Problem

Data transfer performance degradation occurs in information processing devices due to non-contiguous storage of descriptors, leading to speculative read failures and increased processing time, especially when small data transfers are frequent, which can degrade the performance of the controller modules (CMs) despite the time required for descriptor reading becoming significant.

Method used

A data transfer control device that includes a control unit to manage descriptor storage and reading, discarding non-consecutive descriptors and performing speculative reads only when necessary, while also handling errors to maintain performance and prevent circuit scale increases.

Benefits of technology

Improves information processing device performance by reducing speculative read failures and maintaining efficiency even when descriptors are not stored consecutively, without increasing circuit complexity.

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Abstract

To improve performance of a device while suppressing increase of circuit scale even when DSCs (descriptors) are not continuously stored in a memory.SOLUTION: A control device which executes data transmission between devices by DMA (Direct Memory Access) on the basis of DSCs writes data with a size corresponding to a prescribed number of DSCs including a first DSC stored in a first address of a memory and one or more DSCs stored in the memory from the first address into a buffer and determines whether the first DSC and following DSCs are continuously stored in the memory or not on the basis of the data and, if they are not continuously stored, discards data following the last second DSC of the one or more DSCs continuous from the first DSC, out of the data from the buffer and writes data with a size corresponding to a prescribed number of DSCs including a third DSC stored in a second address of the memory indicated by the second DSC, from the second address into the buffer.SELECTED DRAWING: Figure 6
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Citation Information

Patent Citations

  • Method for direct memory access block movement using descriptor prefetch, direct memory access device, and data processing system

    JP2008171426A